WO2015101067A1 - Dispositif de lecture/écriture rfid et système rfid - Google Patents

Dispositif de lecture/écriture rfid et système rfid Download PDF

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Publication number
WO2015101067A1
WO2015101067A1 PCT/CN2014/086713 CN2014086713W WO2015101067A1 WO 2015101067 A1 WO2015101067 A1 WO 2015101067A1 CN 2014086713 W CN2014086713 W CN 2014086713W WO 2015101067 A1 WO2015101067 A1 WO 2015101067A1
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WO
WIPO (PCT)
Prior art keywords
reader
signal
radio frequency
writer
card
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Application number
PCT/CN2014/086713
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English (en)
Chinese (zh)
Inventor
李勇
周小果
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深圳市吉芯微半导体有限公司
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Application filed by 深圳市吉芯微半导体有限公司 filed Critical 深圳市吉芯微半导体有限公司
Publication of WO2015101067A1 publication Critical patent/WO2015101067A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
    • G06K7/10009—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves

Definitions

  • the invention belongs to the technical field of radio frequency identification, and particularly relates to an RF reader and a radio frequency identification system.
  • RF readers are widely used in financial card mobile payment, resident health card reading and writing and identification, public transport card reading and writing and identification, resident ID card reading and writing and identification, product management, logistics management and other fields of wireless intelligent reading.
  • the writing device can realize intelligent reading and recognition of the contact IC card or the non-contact IC card.
  • the radio frequency reader includes: an antenna, a radio frequency processing circuit, a field programmable gate array chip, a processor circuit, a local display circuit, and a peripheral interface circuit.
  • the antenna is used to form a resonant circuit with the coil as an antenna in the IC card, generating a carrier having a certain resonant frequency, and using the carrier to realize bidirectional communication of data;
  • the RF processing circuit is used for processing the UHF signal of the front end;
  • the programmable gate array chip is used to implement the baseband data encoding and decoding specified in the radio frequency protocol;
  • the processor circuit is used to implement some operation interfaces such as instruction jump control and return data display;
  • the peripheral interface circuit is used for connecting a computer, a mobile phone, Peripherals such as memory cards; local display circuits are used to implement local display of transmitted data.
  • the above-mentioned radio frequency reader/writer provided by the prior art has the following disadvantages: 1.
  • the processor circuit receives an operation command issued by a read/write application terminal having an upper layer application software through a peripheral interface circuit, and the read/write application terminal is connected through a dedicated data interface.
  • the processor circuits are discrete independent chips, which make the RF readers large in size, heavy in weight, high in power consumption and cost, and inconvenient to carry RF readers.
  • the purpose of the embodiments of the present invention is to provide an RF reader for solving the problem that the existing RF reader uses a dedicated data interface to connect peripherals, resulting in low adaptability of the RF reader, and existing
  • the low integration of RF readers leads to the problem of large size, heavy weight, high power consumption and high cost of RF readers, which is not convenient for carrying RFID readers.
  • An RF reader/writer includes:
  • a radio frequency processing circuit configured to send a command sequence for performing an underlying operation on the IC card via the antenna, and process the high frequency signal carrying the response data sent by the IC card via the antenna to obtain a response signal;
  • a card reader integrated chip wherein the card reader integrated chip is connected to the read/write application terminal through an audio communication interface, and the card reader integrated chip is configured to decode the read/write application terminal by using a command issued by the audio communication interface Obtaining an identifiable digital signal, parsing the digital signal into a command sequence, sending the signal to the radio frequency processing circuit, and processing the response signal obtained by the radio frequency processing circuit to obtain response data, and then passing the audio
  • the communication interface is transmitted back to the read/write application terminal.
  • Another object of the embodiments of the present invention is to provide a radio frequency identification system including a read/write application terminal and a radio frequency reader/writer, and the radio frequency reader/writer is an RF reader/writer as described above.
  • the radio frequency reader/writer provided by the embodiment of the invention is connected to the reading and writing application terminal through the audio communication interface, and integrates the functional units for processing the interaction signal between the radio frequency processing circuit and the read/write application terminal into a single card reader.
  • the integrated chip because the audio communication interface standard is mature and unified, using it to realize data transmission can improve the adaptability of the RF reader and improve the versatility, which is conducive to the promotion of the product.
  • the single chip integration is realized, which greatly reduces the The size, weight, power consumption and cost of the RF reader improve the portability of the RF reader.
  • FIG. 1 is a structural diagram of a radio frequency reader provided by the prior art
  • FIG. 2 is a structural diagram of the radio frequency processing circuit of FIG. 1;
  • FIG. 3 is a structural diagram of an RF reader/writer according to an embodiment of the present invention.
  • FIG. 4 is a structural diagram of the reader integrated chip of FIG. 3;
  • FIG. 5 is a diagram showing an example of signal waveforms after the voltage comparator performs binarization processing according to an embodiment of the present invention
  • FIG. 6 is a structural diagram of the low power control unit of FIG. 4.
  • the present invention proposes an RF reader, which is connected to the reading and writing application terminal through an audio communication interface, and will be used for the RF processing circuit and the reading and writing application terminal.
  • the functional units for processing the interaction signals are integrated into a single card reader integrated chip.
  • FIG. 3 shows the structure of the radio frequency reader/writer provided by the embodiment of the present invention. For the convenience of description, only parts related to the embodiment of the present invention are shown.
  • the radio frequency reader/writer provided by the embodiment of the present invention includes: an antenna 3; a radio frequency processing circuit 1 for issuing a command sequence for performing an underlying operation on the IC card via the antenna 3, and transmitting the IC card through the antenna 3
  • the high frequency signal carrying the response data is processed to obtain a response signal
  • the card reader integrated chip 2 is connected to the read and write application terminal through the audio communication interface, and the card reader integrated chip 2 is used for reading and writing applications.
  • the terminal decodes the command sent by the audio communication interface to obtain the identifiable digital signal, parses the digital signal into a command sequence, sends the signal to the RF processing circuit 1, and processes the response signal obtained by the RF processing circuit 1 to obtain the response data. It is transmitted back to the read/write application terminal through the audio communication interface.
  • the read/write application terminal refers to various terminal devices installed with an upper layer card reading application software and having an audio communication interface, and may be, for example, a computer, a mobile phone, a PDA, or the like.
  • the RF processing circuit 1 and the card reader integrated chip 2 can be in a standard small volume package form to further reduce the size of the RF reader.
  • the standard small form factor package can be a TSSOP package, a QFN package, or the like.
  • the RF processing circuit 1 can be integrated or independent of the reader/writer integrated chip 2, and the RF processing circuit 1 can complete the ISO/IEC 14443 standard and the Type A/B standard. Identification and reading and writing of IC cards of ISO/IEC15693 standard, ISO/IEC18092 standard, ISO/IEC21481 standard, and Sony Felica standard.
  • the radio frequency reader/writer may further include: a non-contact IC card chip (not shown) connected to the antenna 3, and the non-contact IC card chip may be in accordance with the ISO/IEC 14443 standard, the Type A/B standard, IC card chip of ISO/IEC15693 standard or Sony Felica standard. In this way, the RF reader can directly read and write the built-in non-contact IC card chip.
  • FIG. 4 shows the structure of the reader/writer integrated chip 2 of FIG.
  • the reader/writer integrated chip 2 may include: a control register 204; a communication interface unit 201 connected to the radio frequency processing circuit 1; an audio communication interface 202 connected to the read/write application terminal; and a processor 203 for the radio frequency processing circuit 1
  • the response signal input by the communication interface unit 201 is processed to obtain response data, and the value of the control register 204 is configured.
  • the voltage comparator 206 is configured to perform binarization processing on the command sent by the read/write application terminal through the audio communication interface 202. And extracting the binarized transition edge; the audio signal processing unit 205 is configured to calculate a time interval between adjacent edge edges extracted by the voltage comparator 206, and respectively compare each time interval with the control register 204.
  • the values are compared to obtain a plurality of valid data, and the plurality of valid data are processed correspondingly and sent to the processor 203, and sent by the processor 203 to the radio frequency processing circuit 1 through the communication interface unit 201, and is also used for the processor 203.
  • the obtained response data is processed correspondingly, and the corresponding processed response data is transmitted back to the read/write application terminal through the audio communication interface 202;
  • the system bus 207, the control register 204, the communication interface unit 201, the processor 203, the control register 204, and the audio signal processing unit 205 are all mounted on the system bus 207 and interacted through the system bus 207.
  • the corresponding processing of the audio signal processing unit 205 refers to: performing synchronous despreading, carrier synchronization and demodulation, frame synchronization, decoding verification, and the like on the signal received through the audio communication interface 202;
  • the signal of the terminal is encoded, spread, and processed by filtering.
  • the processor 203 can be a central processing unit, or a digital signal processor, or a combination of a central processing unit and a digital signal processor.
  • the central processing unit or digital signal processor can be, but is not limited to, an 8-bit, 16-bit or 32-bit kernel.
  • the communication interface unit 201 can be, but is not limited to, a universal asynchronous transceiver (Universal) Asynchronous Receiver/Transmitter, UART) interface, Universal Serial Bus (Universal Serial Bus, USB) interface, Serial Peripheral Interface (SPI), parallel interface, I2C bus interface, etc.
  • the audio communication interface 202 includes three signal lines and one ground line.
  • the three signal lines are the left channel signal line, the right channel signal line and the microphone signal line.
  • One of the left channel signal line or the right channel signal line is used to implement signal transmission from the read/write application terminal to the reader/writer integrated chip 2; the other of the left channel signal line or the right channel signal line is used for charging Or realize the signal transmission of the read/write application terminal to the reader/writer integrated chip 2; the microphone signal line is used for realizing the signal transmission of the reader integrated chip 2 to the read/write application terminal.
  • the value of the control register 204 may include a carrier frequency and a modulation mode identification bit, a threshold configuration value Lx, a minimum effective value Lmin, and a maximum effective value Lmax, and Lmin ⁇ Lx ⁇ Lmax.
  • Voltage comparator The signal waveform diagram after the binarization processing is performed, for example, as shown in FIG. 5, assuming that the time interval between the nth (n is a positive integer) adjacent transition edges is Ln, the audio signal processing unit 205 can determine the current transmission.
  • Ln ⁇ Lmin or Ln>Lmax it indicates that the current transmission is an interference signal and discards the processing; in the non-data transmission state, Lmin ⁇ Ln ⁇ Lx indicates that the current transmission is a carrier signal, and in the data transmission state, the current transmission is indicated.
  • the data bit is the same as the value of the previous bit data; in the non-data transfer state, Lx ⁇ Ln ⁇ Lmax indicates that the current data transfer start bit is switched to the data transfer state, and the data transfer state indicates that the currently transmitted data bit is before. The value of one bit of data is different.
  • the bit data is combined into a valid data word and switched to a non-data transfer state, and an interrupt signal is generated to notify the processor 203 to proceed to the next step. Processing.
  • the radio frequency reader can be powered by an external power source, or powered by a self-contained rechargeable battery, or by a combined power supply of an external power source and a rechargeable battery.
  • the reader integrated chip 2 may further include: a battery protection circuit 208 for short circuit protection, over current protection, over charge protection and/or over discharge protection of the rechargeable battery; battery management Unit 209, configured to implement a rechargeable battery
  • the charge and discharge management of 208, and the current state of charge of the rechargeable battery 208 is sent to the processor 203 in real time, so that the processor 203 can perform subsequent actions according to the same, for example, if the current state of charge has reached a certain value, the external power source can be The power supply is switched to the rechargeable battery 208 for power supply.
  • the rechargeable battery 208 is a lithium battery.
  • the short circuit protection is to detect the short circuit of the positive/negative voltage output pin of the rechargeable battery, and perform a protection action when a short circuit is detected;
  • the overcurrent protection means that when a large current flows through the load is detected Controlling the rechargeable battery to stop discharging to the load to protect the rechargeable battery; overcharge protection When detecting that the voltage of the rechargeable battery rises to the charging threshold, the control stops charging the rechargeable battery; over-discharge protection refers to when the rechargeable battery is in a discharged state If it is detected that the voltage of the rechargeable battery falls to the discharge threshold, the control rechargeable battery stops supplying power to the load.
  • the reader/writer integrated chip 2 may further include: a voltage conversion unit 210, configured to convert the voltage output by the external power source or the rechargeable battery 208 into a voltage required for the operation of each power component, and output the corresponding voltage to the corresponding a power consumption portion; a detecting unit 211 connected to the power supply circuit of each power consumption portion, configured to detect whether the power supply voltage of the phase application power portion is abnormal, and send the detection result to the processor 203, so that the processor 203 responds in time. To protect the device from operating safely.
  • the reader/writer integrated chip 2 may further include: a peripheral interface unit 212.
  • the peripheral interface unit 212 may be a peripheral interface unit that connects peripheral communication or control devices such as a liquid crystal display, a touch screen, or a smart card, or may be a memory controller that can generate an external memory (eg, external data memory) interface timing.
  • the peripheral interface unit 212 is a peripheral interface unit, the peripheral interface unit can be, but is not limited to, including: UART interface, USB interface, ISO/IEC7816 standard interface, SPI, parallel interface, I2C bus interface, SWP/eSWP interface or NFC-WI interface.
  • the peripheral interface unit is an ISO/IEC7816 standard interface
  • the ISO/IEC7816 standard interface can be connected to various contact chip cards, such as: E-SAM card, P-SAM card, various contact memory cards, password cards. Or smart chip card, etc.
  • the peripheral interface unit is a parallel interface
  • the parallel interface may select whether to filter the input interference signal. This filter function does not work when the passthrough is set, otherwise the interference signal with a stable duration of less than n clock cycles is filtered out.
  • the reader/writer integrated chip 2 may further include: a random number generator 215 for generating a random number of one or more bits; and an encryption and decryption unit 213 connecting the processor 203 and the random number generator 215, Decrypting the response signal of the RF processing circuit 1 through the communication interface unit 201 to the processor 203 according to the random number generated by the random number generator 215, and also for processing the processor according to the random number generated by the random number generator 215 203 received valid data for encryption processing.
  • a random number generator 215 for generating a random number of one or more bits
  • an encryption and decryption unit 213 connecting the processor 203 and the random number generator 215, Decrypting the response signal of the RF processing circuit 1 through the communication interface unit 201 to the processor 203 according to the random number generated by the random number generator 215, and also for processing the processor according to the random number generated by the random number generator 215 203 received valid data for encryption processing.
  • the encryption and decryption unit 213 is a 3DES encryption and decryption module, an AES encryption and decryption module, an RSA encryption and decryption module, an SM1 encryption and decryption module, SM2 encryption and decryption module, SM3 encryption and decryption module, SM4 encryption and decryption module.
  • the data error correction and retransmission mechanism may also be integrated in the audio signal processing unit 205. Specifically, when the audio signal processing unit 205 receives the interfered data, it will attempt to recover the correct data, if the interference is severely restricted. If the data is reliably restored, no response signal will be generated, and when the signal source does not receive the response signal, the last transmitted data will be retransmitted.
  • the reader/writer integrated chip 2 can also solidify the monitoring and debugging software, and can be used for IC testing and assisting end user software development. At this time, after the processor 203 is powered on and working, first judge a certain lead. Whether the pin is a specified level value determines whether the power-on needs to enter the monitoring, debugging mode or normal application software mode.
  • the reader integrated chip 2 can also control the working mode by the voltage applied by the programming voltage pin, specifically: when the voltage applied by the programming voltage pin is a high voltage, the OTP programming mode is specified, and the voltage applied by the programming voltage pin is specified. When it is high, it is in the normal working mode, and when the voltage applied to the programming voltage pin is low, it is forced reset mode.
  • the reader/writer integrated chip 2 may further include: a low power consumption control unit 214 mounted on the system bus 207 and connected to the audio signal processing unit 205 or the radio frequency processing circuit 1 for use in the processor Under the control of the 203 and the system clock, the trigger of the control audio signal processing unit 205 or the flip-flop of the RF processing circuit 1 does not flip in the non-operating state, thereby reducing the dynamic power consumption of the system.
  • a low power consumption control unit 214 mounted on the system bus 207 and connected to the audio signal processing unit 205 or the radio frequency processing circuit 1 for use in the processor Under the control of the 203 and the system clock, the trigger of the control audio signal processing unit 205 or the flip-flop of the RF processing circuit 1 does not flip in the non-operating state, thereby reducing the dynamic power consumption of the system.
  • FIG. 6 shows the structure of the low power control unit 214 of FIG.
  • the low power consumption control unit 214 may include: a trigger register of the audio signal processing unit 205 or a working register 2145 of the trigger of the radio frequency processing circuit 1; mounted on the system bus 207 and working on System clock A clock enable register 2141 under SCLK for outputting a clock enable signal CLKEN in the configuration of the processor 203; a clock gating unit 2142 connected to the clock enable register 2141 and the work register 2145 and operating under the system clock SCLK For generating the clock gating signal CLKX according to the clock enable signal CLKEN and outputting the clock gating signal CLKX to the working register 2145, and the clock gating signal CLKX is constantly at a high level or low when the clock enable signal CLKEN is inactive.
  • the phase of the clock gating signal CLKX changes with the change of the system clock SCLK; mounted on the system bus a work enable register 2143 operating on the system clock SCLK, for outputting the work enable signal ENABLEX in the configuration of the processor 203; and an operation mode selection unit 2144 connecting the work register 2145 for enabling according to the work
  • the signal ENABLEX selects the data input signal DINX of the working register 2145 from the input signal of the operation mode selecting unit 2144 and outputs the data input signal DINX to the working register 2145, and selects the working mode selecting unit 2144 when the work enable signal ENABLEX is active.
  • the normal input signal DY is used as the data input signal DINX, and the normal input signal DY is used as the working register.
  • the reset initial value input of 2145 selects the constant initial value input signal DX of the operating mode selecting unit 2144 as the data input signal DINX when the work enable signal ENABLEX is invalid.
  • the clock gating signal CLKX is constantly at a high level or a low level, that is, no flipping occurs, there is no clock edge, and the working register 44 is not changed, thereby achieving the purpose of reducing the dynamic power consumption of the circuit;
  • the work enable signal ENABLEX is invalid, the data input signal DINX sent from the working mode selecting unit 2144 to the working register 2145 is a constant value DX.
  • the output of the working register 2145 is not inverted. Achieve the purpose of reducing the dynamic power consumption of the circuit.
  • the working register 2145 of the audio signal processing unit 205 is turned on.
  • the clock when the clock enable signal CLKEN is "1", will turn off the clock of the working register 2145 of the audio signal processing unit 205; the effective value of the work enable signal ENABLEX is "1", and the invalid value is "0", that is to say
  • the audio signal processing unit 205 is selected to be in the normal function mode.
  • the work enable signal ENABLEX is "0"
  • the audio signal processing unit 205 is selected to be in the reset mode, and the working register 44 will stop flipping. .
  • the working mode selecting unit 2144 selects the normal input signal DY of the working mode selecting unit 2144 as the data input signal DINX, if the processor 203 simultaneously sets the clock enable.
  • the signal CLKEN is a valid value "0", so that the clock gating signal CLKX is enabled, the working register 2145 can work normally; when the processor 203 sets the work enable signal ENABLEX to the invalid value "0", the working mode selecting unit 2144
  • the constant initial value input signal DX of the operating mode selection unit 2144 is selected as the data input signal DINX.
  • the working register 2145 will maintain the output constant value to reduce the dynamic power consumption; 203 setting the clock enable signal CLKEN to an invalid value "1", the clock gating signal CLKX is a constant value of "1" and will not flip to reduce dynamic power consumption. Since the dynamic power consumption of the clock is the main dynamic power consumption of the RF reader, reducing the dynamic power of the clock will greatly reduce the RF reader. The overall dynamic power consumption.
  • the embodiment of the present invention further provides a radio frequency identification system, including a read/write application terminal and a radio frequency reader/writer as described above, which are not described herein.
  • the radio frequency reader/writer proposed by the present invention is connected to the reading and writing application terminal through an audio communication interface, and integrates various functional units for processing the interaction signal between the radio frequency processing circuit and the read/write application terminal.
  • the single card reader integrated chip because the audio communication interface standard is mature and unified, using it to realize data transmission can improve the adaptability of the RF reader and improve the versatility, which is conducive to the promotion of the product, and at the same time, realizes the single chip.
  • the integration greatly reduces the size, weight, power consumption and cost of the RF reader, and improves the portability of the RF reader.
  • the RF reader provides a rich and flexible interface unit that is modular and reduces the complexity of developing more sophisticated IC card applications.
  • the clock enable and work enable modes are adopted, which greatly reduces the dynamic power consumption of the RF reader and realizes the purpose of extending the standby time.

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Abstract

L'invention concerne un dispositif de lecture/écriture RFID, comprenant une antenne (3), un circuit de traitement RF (1), et une puce intégrée de lecteur de carte (2) ; le circuit de traitement RF (1) étant utilisé pour délivrer, par l'intermédiaire de l'antenne (3), une séquence d'instructions pour qu'une carte à puce effectue une opération sous-jacente, et par l'intermédiaire d'un signal haute fréquence passant par ladite antenne (3) et véhiculant des données de réponse, traiter ladite carte à puce afin d'obtenir un signal de réponse ; ladite puce intégrée de lecteur de carte (2) se connectant à un terminal d'application de lecture/écriture au moyen d'une interface de communication audio et étant utilisée pour décoder une instruction, délivrée par ledit terminal d'application de lecture/écriture au moyen de ladite interface de communication audio, afin d'obtenir un signal numérique identifiable, décomposer ledit signal numérique sous la forme d'une séquence d'instructions et ensuite l'envoyer audit circuit de traitement RF (1), et traiter ledit signal de réponse obtenu par ledit circuit de traitement RF (1), et après avoir obtenu les données de réponse, les renvoyer audit terminal d'application de lecture/écriture au moyen de ladite interface de communication audio. L'invention concerne en outre un système RFID comprenant ledit dispositif de lecture/écriture RFID et un terminal d'application de lecture/écriture.
PCT/CN2014/086713 2013-12-31 2014-09-17 Dispositif de lecture/écriture rfid et système rfid WO2015101067A1 (fr)

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CN201310754644.5A CN103679239B (zh) 2013-12-31 2013-12-31 一种射频读写器及射频识别系统
CN201310754644.5 2013-12-31

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CN107798367A (zh) * 2017-11-08 2018-03-13 天津职业技术师范大学 一种基于ZigBee技术的无线RFID读写设备
CN107832818A (zh) * 2017-12-08 2018-03-23 江苏本能科技有限公司 基于多区域识别的射频识别读写器及路侧停车管理系统
CN107994315A (zh) * 2017-12-28 2018-05-04 上海互惠信息技术有限公司 一种通用rfid读写器天线阵列及其配套产品
CN107994315B (zh) * 2017-12-28 2024-05-31 上海互惠信息技术有限公司 一种通用rfid读写器天线阵列及其配套产品

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CN104122820A (zh) * 2014-07-22 2014-10-29 深圳市吉芯微半导体有限公司 传感器接口芯片及传感器信号检测系统
CN105844313A (zh) * 2016-04-12 2016-08-10 深圳市迅远科技有限公司 一种基于Linux系统的射频识别读写设备及其读写方法
CN105930885B (zh) * 2016-04-18 2018-08-28 上海秒通网络通讯技术有限公司 基于非接触式射频技术芯片大量的一体化处理方法及设备
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CN106295434A (zh) * 2016-08-16 2017-01-04 江门市汇朗工业机器人有限公司 一种基于rf技术的身份识别系统
CN106339649A (zh) * 2016-08-16 2017-01-18 江门市汇朗工业机器人有限公司 一种基于rf射频通信的读卡器
CN108877695A (zh) * 2018-09-07 2018-11-23 天津光电通信技术有限公司 一种无线图像接收显示电路及装置
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CN110457968A (zh) * 2019-08-13 2019-11-15 欧科华创自动化(深圳)有限公司 一种rfid读写器
CN110838204B (zh) * 2019-11-05 2021-04-13 艾体威尔电子技术(北京)有限公司 一种磁条卡刷卡终端解码方法

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