CN103679239A - Radio frequency reader-writer and radio frequency identification system - Google Patents
Radio frequency reader-writer and radio frequency identification system Download PDFInfo
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- CN103679239A CN103679239A CN201310754644.5A CN201310754644A CN103679239A CN 103679239 A CN103679239 A CN 103679239A CN 201310754644 A CN201310754644 A CN 201310754644A CN 103679239 A CN103679239 A CN 103679239A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
- G06K7/10009—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves
Abstract
The invention belongs to the technical field of radio frequency identification, and provides a radio frequency reader-writer and a radio frequency identification system, wherein the radio frequency reader-writer is connected with a reading and writing application terminal through an audio communication interface, in addition, all functional units used for processing interaction signals between a radio processing circuit and the reading and writing application terminal are integrated into a single card reader integrated chip, the audio communication interface standards are mature and unified, when the mature and unified audio communication interface standards are used for realizing data transmission, the adaptability of a radio frequency reader-writer can be improved, the universality can be improved, the products can be favorably popularized, meanwhile, the single chip integration is realized, the size, the weight, the power consumption and the cost of the radio frequency reader-writer are greatly reduced, and the portability of the radio frequency reader-writer is improved.
Description
Technical field
The invention belongs to REID field, relate in particular to a kind of frequency read/write and radio-frequency recognition system.
Background technology
Frequency read/write is the intelligent wireless read-write equipment that is widely used at present the fields such as fiscard mobile payment, the read-write of residents ' health card and identification, the read-write of public transport card and identification, resident identification card read-write and identification, the management of product, logistics management, and the intelligence of can achieve a butt joint touch IC-card or non-contact IC card reads and identifies.
As shown in Figure 1, the frequency read/write that prior art provides comprises: antenna, rf processing circuitry, field programmable gate array chip, processor circuit, local display circuit, peripheral interface circuit.When work, antenna is used for and the coil formation resonant tank of IC-card as antenna, produces the carrier wave with certain resonance frequency, utilizes this carrier wave to realize the two-way communication of data; Rf processing circuitry is for the treatment of the ultra-high frequency signal of front end; Field programmable gate array chip is for realizing the base band data encoding and decoding that radio frequency protocol is stipulated; Processor circuit is for realizing the redirect control of instruction and the certain operations interfaces such as demonstration of return data; Peripheral interface circuit is used for connecting the peripheral hardwares such as computer, mobile phone, storage card; Local display circuit is for realizing the local Presentation Function of transmission data.As shown in Figure 2, rf processing circuitry wherein further comprises and flows to two contrary signalling channels, be respectively: sendaisle, first sendaisle is produced the carrier signal of relevant work frequency by the quartz oscillator of frequency stabilization, this carrier signal by modulation circuit by carrying out amplitude shift key modulation by the carry information sequence of sending out of Manchester or modification Miller or NRZ rule encoding, after amplifying finally by drive amplification circuit, by antenna, sent; Receiving cable, receiving cable first by filtering circuit filtering antenna reception to high-frequency signal in interference and noise, to extract the faint answer signal of IC-card, then by amplifying circuit and by sending field programmable gate array chip further to process after demodulator circuit demodulation.
The above-mentioned frequency read/write that prior art provides has following shortcoming: one, processor circuit is to be received and had the operational order that send the read-write application terminal of upper application software by peripheral interface circuit, read-write application terminal connects peripheral interface circuit by exclusive data interface, and the exclusive data interface standard that different manufacturers adopts differs, cause the suitability of frequency read/write not high, versatility is poor, is unfavorable for the popularization of product; Two, rf processing circuitry, field programmable gate array chip, processor circuit are discrete individual chips, make the volume of frequency read/write large, weight is large, power consumption and cost high, be not easy to carrying of frequency read/write.
Summary of the invention
The object of the embodiment of the present invention is to provide a kind of frequency read/write, being intended to solve existing frequency read/write adopts exclusive data interface to connect peripheral hardware, cause the problem that frequency read/write suitability is not high, and existing frequency read/write integrated level is low, cause that frequency read/write volume is large, weight is large, power consumption and cost is high, the problem of carrying that is not easy to frequency read/write.
The embodiment of the present invention is achieved in that a kind of frequency read/write, and described frequency read/write comprises:
Antenna;
Rf processing circuitry, for send the command sequence of IC-card being carried out to bottom operation via described antenna, and the high-frequency signal that is loaded with response data that described IC-card is imported into through described antenna processes, and signal meets with a response;
Card reader integrated chip, described card reader integrated chip connects read-write application terminal by voice communication interface, described card reader integrated chip is decoded for the order that described read-write application terminal is sent by described voice communication interface, obtaining can discriminating digit signal, after being resolved to command sequence, described digital signal sends to described rf processing circuitry, and the described response signal that described rf processing circuitry is obtained is processed, meet with a response after data, by described voice communication interface, return to described read-write application terminal.
Another object of the embodiment of the present invention is to provide a kind of radio-frequency recognition system, comprises read-write application terminal and frequency read/write, and described frequency read/write is frequency read/write as above.
The frequency read/write that the embodiment of the present invention proposes is to connect read-write application terminal by voice communication interface, and each functional unit that the interactive signal between rf processing circuitry and read-write application terminal is processed is integrated in single card reader integrated chip, because voice communication interface standard is ripe unified, with it, realize data transmission, can improve the suitability of frequency read/write, improve versatility, be conducive to the popularization of product, simultaneously, realized single-chip integrated, greatly reduce the volume of frequency read/write, weight, power consumption and cost, improved the portability of frequency read/write.
Accompanying drawing explanation
Fig. 1 is the structural drawing of the frequency read/write that provides of prior art;
Fig. 2 is the structural drawing of rf processing circuitry in Fig. 1;
Fig. 3 is the structural drawing of the frequency read/write that provides of the embodiment of the present invention;
Fig. 4 is the structural drawing of read write line integrated chip in Fig. 3;
Fig. 5 is that in the embodiment of the present invention, voltage comparator carries out the signal waveforms example after binary conversion treatment;
Fig. 6 is the structural drawing of low power consumption control unit in Fig. 4.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
The problem existing for existing frequency read/write, the present invention proposes a kind of frequency read/write, this frequency read/write is to connect read-write application terminal by voice communication interface, and each functional unit that the interactive signal between rf processing circuitry and read-write application terminal is processed is integrated in single card reader integrated chip.
Fig. 3 shows the structure of the frequency read/write that the embodiment of the present invention provides, and for convenience of explanation, only shows the part relevant to the embodiment of the present invention.
Specifically the frequency read/write that, the embodiment of the present invention provides comprises: antenna 3; Rf processing circuitry 1, for send the command sequence of IC-card being carried out to bottom operation via antenna 3, and the high-frequency signal that is loaded with response data that IC-card is imported into through antenna 3 processes, and signal meets with a response; Card reader integrated chip 2, card reader integrated chip 2 connects read-write application terminal by voice communication interface, card reader integrated chip 2 is decoded for the order that read-write application terminal is sent by voice communication interface, obtaining can discriminating digit signal, after being resolved to command sequence, this digital signal sends to rf processing circuitry 1, and the response signal that rf processing circuitry 1 is obtained processes, meet with a response after data, by voice communication interface, return to read-write application terminal.
Wherein, read-write application terminal refers to all kinds of terminal devices that upper strata Card Reader application software are installed and have voice communication interface, such as being computer, mobile phone, PDA etc.
Wherein, rf processing circuitry 1 can adopt standard small size packing forms with card reader integrated chip 2, further to dwindle the volume of frequency read/write.This standard small size packing forms can be TSSOP encapsulation, QFN encapsulation etc.
Wherein, rf processing circuitry 1 can be integrated or be independent of read write line integrated chip 2, and rf processing circuitry 1 can complete meeting identification and the read-write of the IC-card of ISO/IEC14443 standard, TypeA/B standard, ISO/IEC15693 standard, ISO/IEC18092 standard, ISO/IEC21481 standard, Sony Felica standard.
Further, frequency read/write also can comprise: connect the Circuit for Non-contact IC Chip (not shown) of antenna 3, this Circuit for Non-contact IC Chip can be the IC-card chip that meets ISO/IEC14443 standard, TypeA/B standard, ISO/IEC15693 standard or Sony Felica standard.Like this, frequency read/write can directly be realized read-write operation to its this built-in Circuit for Non-contact IC Chip.
Fig. 4 shows the structure of read write line integrated chip 2 in Fig. 3.
Specifically, read write line integrated chip 2 can comprise: control register 204; The communications interface unit 201 that connects rf processing circuitry 1; The voice communication interface 202 that connects read-write application terminal; Processor 203, processes for the response signal that rf processing circuitry 1 is inputted by communications interface unit 201, the data that meet with a response, and the value of configuration control register 204; Voltage comparator 206, carries out binary conversion treatment for the order that read-write application terminal is sent by voice communication interface 202, and extracts the hopping edge after binaryzation; Audio signal processing unit 205, the time interval between the adjacent hopping edge extracting for calculating voltage comparer 206, and respectively the value of each time interval and control register 204 is compared, obtain multidigit valid data, and multidigit valid data are carried out sending to processor 203 after respective handling, by processor 203, by communications interface unit 201, send to rf processing circuitry 1, also for the response data that processor 203 is obtained, carry out respective handling, and by voice communication interface 202, the response data after respective handling is returned to read-write application terminal; System bus 207, control register 204, communications interface unit 201, processor 203, control register 204, audio signal processing unit 205 are all mounted on system bus 207, and realize mutual by system bus 207.
Wherein, the respective handling of audio signal processing unit 205 refers to: for the signal receiving by voice communication interface 202, carry out the processing such as synchronous despreading, carrier synchronization and demodulation, frame synchronization, decoding verification; For to be sently encoding to the signal of read-write application terminal, spread spectrum, and the processing such as after filtering.
Wherein, processor 203 can be the combination of central processing unit or digital signal processor or central processing unit and digital signal processor.And central processing unit or digital signal processor can be, but not limited to adopt 8,16 or 32 s' kernel.
Wherein, when rf processing circuitry 1 is independent of read write line integrated chip 2, it is universal asynchronous receiving-transmitting transmitter (Universal Asynchronous Receiver/Transmitter that communications interface unit 201 can be, but not limited to, UART) interface, USB (universal serial bus) (Universal Serial Bus, USB) interface, Serial Peripheral Interface (SPI) (Serial Peripheral Interface, SPI), parallel interface, I2C bus interface etc.
Wherein, voice communication interface 202 comprises three signal wires and a ground wire.Three signal wires are respectively left channel signals line, right-channel signals line and microphone signal line.One in left channel signals line or right-channel signals line in order to realize read-write application terminal to the signal transmission of read write line integrated chip 2; Another in left channel signals line or right-channel signals line is in order to charging or realize read-write application terminal to the signal transmission of read write line integrated chip 2; Microphone signal line is in order to realize read write line integrated chip 2 to the signal transmission of read-write application terminal.
Further, the value of control register 204 can comprise flag, threshold value Configuration Values Lx, minimum effective value Lmin and the maximum effective value Lmax of carrier frequency and modulation system, and Lmin<Lx<Lmax.Voltage comparator 206 carries out signal waveforms example after binary conversion treatment as shown in Figure 5, suppose that n(n is positive integer) time interval between individual adjacent hopping edge is Ln, audio signal processing unit 205 can judge current signal transmission content: if Ln<Lmin or Ln>Lmax, represent the current undesired signal that is transmitted as, discard processing; What under non-data transmission state, Lmin<Ln<Lx represented current transmission is carrier signal, and the data bit of the current transmission of the next expression of data transmission state is identical with the value of a data before; Under non-data transmission state, Lx<Ln<Lmax represents currently for data transmission start bit, and switches to data transmission state, and the data bit of the current transmission of the next expression of data transmission state is different with the value of a data before.According to this rule, when receiving the data of a location number and proof test value is subsequently correct, these bit data are combined as to valid data word, and switch to non-data transmission state, produce look-at-me notification processor 203 simultaneously and carry out next step processing.
In the embodiment of the present invention, frequency read/write can be used external power source, or adopts carry rechargeable battery powered, or adopts the power supply of combining of external power source and rechargeable battery.When frequency read/write comprises rechargeable battery, read write line integrated chip 2 also can comprise: battery protecting circuit 208, for rechargeable battery is carried out to short-circuit protection, overcurrent protection, over-charge protective and/or Cross prevention; Battery management unit 209, for realizing the management of charging and discharging to rechargeable battery 208, and the current charged state of rechargeable battery 208 is sent to processor 203 in real time, so that processor 203 can be carried out subsequent action accordingly, for example, if current charged state has reached certain value, can be from external power supply power switching to rechargeable battery 208 power supplies.Preferably, rechargeable battery 208 is lithium batteries.
Wherein, short-circuit protection refers to that the positive/negative Voltage-output pin for rechargeable battery occurs that the situation of short circuit detects, and when short circuit being detected, carries out protection action; Overcurrent protection refers to while having larger electric current to flow through on load being detected, controls rechargeable battery and stops to load discharge, to protect rechargeable battery; Over-charge protective, when the voltage of rechargeable battery being detected and rise to charge threshold, is controlled and is stopped charging to rechargeable battery; Cross prevention refers to when rechargeable battery is in discharge condition lower time, if when the voltage of rechargeable battery being detected and being down to discharge threshold, control rechargeable battery and stop powering to the load.
In the embodiment of the present invention, read write line integrated chip 2 also can comprise: voltage conversion unit 210, for the voltage transitions of external power source or rechargeable battery 208 outputs is become after the required voltage of each electricity consumption some work, export to corresponding electricity consumption part; Be connected to the detecting unit 211 in each electricity consumption current supply circuit partly, whether abnormal for detection of the supply voltage of corresponding electricity consumption part, and testing result is sent to processor 203, so that processor 203 responds in time, with protection device security of operation.
In the embodiment of the present invention, read write line integrated chip 2 also can comprise: Peripheral Interface unit 212.Peripheral Interface unit 212 can be the peripheral interface units of the peripheral communications such as connecting fluid crystal display, touch-screen or smart card or opertaing device, can be also the memory controller that can produce external memory storage (as: external data memory) interface sequence.Further, if Peripheral Interface unit 212 is peripheral interface units, this peripheral interface units can be, but not limited to comprise: UART interface, USB interface, ISO/IEC7816 standard interface, SPI, parallel interface, I2C bus interface, SWP/eSWP interface or NFC-WI interface etc.Wherein, if peripheral interface units is ISO/IEC7816 standard interface, on ISO/IEC7816 standard interface, can connect all kinds of contact chip cards, such as: E-SAM card, P-SAM card, all kinds of contact storage card, cipher card or smart chip card etc.Wherein, if peripheral interface units is parallel interface, whether parallel interface can be selected input undesired signal to be filtered.This filtering function while leading directly to is set and does not act on, otherwise the undesired signal that duration is less than n clock period is stablized in filtering.
In the embodiment of the present invention, read write line integrated chip 2 also can comprise: randomizer 215, for generation of the random number of unit or multidigit; The encryption/decryption element 213 that connects processor 203 and randomizer 215, for the random number producing according to randomizer 215, response signal to rf processing circuitry 1 by communications interface unit 201 input processors 203 is decrypted processing, the random number for producing according to randomizer 215 also, the valid data that processor 203 is received are encrypted.Preferably, encryption/decryption element 213 is 3DES encryption and decryption module, AES encryption and decryption module, RSA encryption and decryption module, SM1 encryption and decryption module, SM2 encryption and decryption module, SM3 encryption and decryption module, SM4 encryption and decryption module.
In the embodiment of the present invention, also can integrated data error correction and retransmission mechanism in audio signal processing unit 205, be specially: when audio signal processing unit 205 is received disturbed data, to attempt to recover correct data, some disturbing more seriously limited data and reliably reduced, to not produce answer signal, and signal source is not while receiving answer signal, will retransmit the last data that send.
In the embodiment of the present invention, read write line integrated chip 2 inner also curable monitoring, debugging software, can be used for IC test and assist final user's software development, now, processor 203 is after powering on and working, first judge whether certain pin is specified level value, to determine that this powers on, whether need to enter monitoring, debugging mode or normal use software pattern.Read write line integrated chip 2 also can carry out the control of mode of operation by its program voltage pin institute making alive, be specially: when its program voltage pin institute making alive is high voltage, regulation is OTP programming mode, its program voltage pin institute making alive is normal mode of operation while being high level, and its program voltage pin institute making alive is forced resetting pattern while being low level.
In the embodiment of the present invention, read write line integrated chip 2 also can comprise: carry is on system bus 207 and connect the low power consumption control unit 214 of audio signal processing unit 205 or rf processing circuitry 1, for under the control of processor 203 and system clock, control the trigger of audio signal processing unit 205 or the trigger of rf processing circuitry 1 and export and do not overturn under off working state, thus the dynamic power consumption of reduction system.
Fig. 6 shows the structure of low power consumption control unit 214 in Fig. 4.
Because the dynamic power consumption of frequency read/write is mainly because the upset of circuit node level produces, therefore, by reducing circuit node, overturn, just can reach the object that reduces dynamic power consumption.Based on this, in the embodiment of the present invention, low power consumption control unit 214 can comprise: as the work register 2145 of the trigger of audio signal processing unit 205 or the trigger of rf processing circuitry 1, carry is on system bus 207 and be operated in the clock enable register 2141 under system clock SCLK, under the configuration at processor 203, and output clock enable signal CLKEN, connect clock enable register 2141 and work register 2145 and be operated in the clock gating unit 2142 under system clock SCLK, for producing Clock gating signal CLKX and Clock gating signal CLKX exported to work register 2145 according to clock enable signal CLKEN, and when clock enable signal CLKEN is invalid clock gate-control signal CLKX constant be high level or low level, when clock enable signal CLKEN is effective, the phase place of clock gate-control signal CLKX changes with the change of system clock SCLK, carry is on system bus 207 and be operated in the work enable register 2143 under system clock SCLK, under the configuration at processor 203, and output services enable signal ENABLEX, the mode of operation selected cell 2144 that connects work register 2145, be used for according to work enable signal ENABLEX, from the input signal of mode of operation selected cell 2144, select the data input signal DINX of work register 2145 and data input signal DINX is exported to work register 2145, and select the normal input signal DY of mode of operation selected cell 2144 as data input signal DINX when work enable signal ENABLEX is effective, normal input signal DY is as the reset initial value input of work register 2145, when work enable signal ENABLEX is invalid, select the constant initial value input signal DX of mode of operation selected cell 2144 as data input signal DINX.
Wherein, work register 2145 is the trigger of audio signal processing unit 205 or the trigger of rf processing circuitry 1.The feature of trigger is: only at place, clock hopping edge, and sampled signal input, and input signal is remained in output; Under the normal mode of operation of work register 2145, when data input signal DINX is normal input signal DY, audio signal processing unit 205 or rf processing circuitry 1 just can complete corresponding processing capacity.Like this, if Clock gating signal CLKX constant be high level or low level, do not overturn, there is not clock edge, work register 44 just can not change yet, and can reach the object that reduces circuit dynamic power consumption; When if work enable signal ENABLEX is invalid, the data input signal DINX that mode of operation selected cell 2144 is given work register 2145 is constant DX, now no matter whether Clock gating signal CLKX overturns, the output of work register 2145 can not overturn, and can reach the object that reduces circuit dynamic power consumption.
For instance, if the effective value of clock enable signal CLKEN is " 0 ", invalid value is " 1 ", that is to say, when clock enable signal CLKEN is " 0 ", will open the clock of the work register 2145 of audio signal processing unit 205, clock enable signal CLKEN will close the clock of the work register 2145 of audio signal processing unit 205 while being " 1 "; The effective value of work enable signal ENABLEX is " 1 ", invalid value is " 0 ", that is to say, work enable signal ENABLEX will select audio signal processing unit 205 for normal function pattern while being " 1 ", work enable signal ENABLEX will select audio signal processing unit 205 for reset mode while being " 0 ", and work register 44 will stop upset.When processor 203 arranges work enable signal ENABLEX and is effective value " 1 ", mode of operation selected cell 2144 selects the normal input signal DY of mode of operation selected cell 2144 as data input signal DINX, if it is effective value " 0 " that processor 203 arranges clock enable signal CLKEN simultaneously, thereby Clock gating signal CLKX is enabled, and work register 2145 can normally be worked; When processor 203 arranges work enable signal ENABLEX and is invalid value " 0 ", mode of operation selected cell 2144 selects the constant initial value input signal DX of mode of operation selected cell 2144 as data input signal DINX, now, no matter whether clock enable signal CLKEN is effective, work register 2145 will keep the normal value of output, to reduce dynamic power consumption; When processor 203 arranges clock enable signal CLKEN and is invalid value " 1 ", Clock gating signal CLKX is constant " 1 ", can not overturn, to reduce dynamic power consumption, because the dynamic power consumption of clock is the main dynamic power consumption of frequency read/write, therefore reduce clock dynamic power consumption, will greatly reduce the overall dynamics power consumption of frequency read/write.
In addition, the embodiment of the present invention also provides a kind of radio-frequency recognition system, comprises read-write application terminal and frequency read/write as above, is not repeated herein.
In sum, first, the frequency read/write that the present invention proposes is to connect read-write application terminal by voice communication interface, and each functional unit that the interactive signal between rf processing circuitry and read-write application terminal is processed is integrated in single card reader integrated chip, because voice communication interface standard is ripe unified, with it, realize data transmission, can improve the suitability of frequency read/write, improve versatility, be conducive to the popularization of product, simultaneously, realized single-chip integrated, greatly reduce the volume of frequency read/write, weight, power consumption and cost, improved the portability of frequency read/write.Secondly, this frequency read/write provides abundant and interface unit has flexibly been realized modularization, has reduced the complexity of the more most advanced and sophisticated IC-card application system of exploitation.Finally, employing clock enables and work enables two kinds of modes, has greatly reduced the dynamic power consumption of frequency read/write, has realized the object of prolongs standby time.
One of ordinary skill in the art will appreciate that and realize all or part of in above-described embodiment method, can control relevant hardware by program completes, described program can be stored in a computer read/write memory medium, and described storage medium, as ROM/RAM, disk, CD etc.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (12)
1. a frequency read/write, is characterized in that, described frequency read/write comprises:
Antenna;
Rf processing circuitry, for send the command sequence of IC-card being carried out to bottom operation via described antenna, and the high-frequency signal that is loaded with response data that described IC-card is imported into through described antenna processes, and signal meets with a response;
Card reader integrated chip, described card reader integrated chip connects read-write application terminal by voice communication interface, described card reader integrated chip is decoded for the order that described read-write application terminal is sent by described voice communication interface, obtaining can discriminating digit signal, after being resolved to command sequence, described digital signal sends to described rf processing circuitry, and the described response signal that described rf processing circuitry is obtained is processed, meet with a response after data, by described voice communication interface, return to described read-write application terminal.
2. frequency read/write as claimed in claim 1, is characterized in that, described read write line integrated chip comprises:
Control register;
The communications interface unit that connects described rf processing circuitry;
The voice communication interface that connects described read-write application terminal;
Processor, processes for the described response signal that described rf processing circuitry is inputted by described communications interface unit, the data that meet with a response, and configure the value of described control register;
Voltage comparator, carries out binary conversion treatment for the described order that described read-write application terminal is sent by described voice communication interface, and extracts the hopping edge after binaryzation;
Audio signal processing unit, for calculating the time interval between the adjacent hopping edge that described voltage comparator extracts, and respectively the value of each time interval and described control register is compared, obtain multidigit valid data, and described multidigit valid data are carried out sending to described processor after respective handling, by described processor, by described communications interface unit, send to described rf processing circuitry, described audio signal processing unit also carries out respective handling for the described response data that described processor is obtained, and by described voice communication interface, the response data after respective handling is returned to described read-write application terminal,
System bus, described control register, described communications interface unit, described processor, described control register, described audio signal processing unit are all mounted on described system bus.
3. frequency read/write as claimed in claim 2, is characterized in that, described frequency read/write also comprises rechargeable battery, and described read write line integrated chip also comprises:
Battery protecting circuit, for carrying out short-circuit protection, overcurrent protection, over-charge protective and/or Cross prevention to described rechargeable battery;
Battery management unit, for realizing the management of charging and discharging to described rechargeable battery, and sends to described processor in real time by the current charged state of described rechargeable battery.
4. frequency read/write as claimed in claim 3, is characterized in that, described read write line integrated chip comprises:
Voltage conversion unit, for the voltage transitions of external power source or the output of described rechargeable battery is become after the required voltage of described each electricity consumption some work of read write line integrated chip, exports to corresponding electricity consumption part;
Be connected to the detecting unit in described each electricity consumption current supply circuit partly, whether abnormal for detection of the supply voltage of corresponding electricity consumption part, and testing result is sent to described processor.
5. frequency read/write as claimed in claim 2, is characterized in that, described read write line integrated chip comprises Peripheral Interface unit;
Described Peripheral Interface unit comprises: UART interface, USB interface, ISO/IEC7816 standard interface, SPI, parallel interface, I2C bus interface, SWP/eSWP interface, NFC-WI interface and/or memory controller;
Described ISO/IEC7816 standard interface is used for connecting E-SAM card, P-SAM card, contact storage card, cipher card or smart chip card.
6. frequency read/write as claimed in claim 2, is characterized in that, described read write line integrated chip comprises:
Randomizer, for generation of random number;
The encryption/decryption element that connects described processor and described randomizer, for the random number producing according to described randomizer, the described response signal that described rf processing circuitry is inputted to described processor by described communications interface unit is decrypted processing, the random number for producing according to described randomizer also, the described valid data that described processor is received are encrypted.
7. frequency read/write as claimed in claim 2, it is characterized in that, described read write line integrated chip comprises: carry is on described system bus and connect the low power consumption control unit of described audio signal processing unit or described rf processing circuitry, and described low power consumption control unit comprises:
Work register as the trigger of described audio signal processing unit or the trigger of described rf processing circuitry;
Carry is on described system bus and be operated in the clock enable register under described system clock, under the configuration of described processor, and output clock enable signal;
Connect described clock enable register and described work register and be operated in the clock gating unit under described system clock, for producing Clock gating signal and described Clock gating signal exported to described work register according to described clock enable signal, and Clock gating signal constant is decided to be high level or low level described in when described clock enable signal is invalid at that time, when described clock enable signal is effective described in the phase place of Clock gating signal with the change of described system clock, change;
Carry is on described system bus and be operated in the work enable register under described system clock, under the configuration of described processor, and output services enable signal;
The mode of operation selected cell that connects described work register, be used for according to described work enable signal, from the input signal of described mode of operation selected cell, select the data input signal of described work register and described data input signal is exported to described work register, and when described work enable signal is effective, select the normal input signal of described mode of operation selected cell as described data input signal, when described work enable signal is invalid, select the constant initial value input signal of described mode of operation selected cell as described data input signal.
8. frequency read/write as claimed in claim 2, is characterized in that, described communications interface unit is UART interface, USB interface, SPI, parallel interface, I2C bus interface.
9. frequency read/write as claimed in claim 2, is characterized in that, described voice communication interface comprises three signal wires and a ground wire, and described three signal wires comprise left channel signals line, right-channel signals line and microphone signal line;
One in described left channel signals line or described right-channel signals line for realizing described read-write application terminal to the signal transmission of described read write line integrated chip, another in described left channel signals line or described right-channel signals line is for realizing charging or described read-write application terminal to the signal transmission of described read write line integrated chip, and described microphone signal line is for realizing described read write line integrated chip to the signal transmission of described read-write application terminal.
10. frequency read/write as claimed in claim 1, is characterized in that, described rf processing circuitry is integrated on described read write line integrated chip;
Described rf processing circuitry has been used for meeting identification and the read-write of the IC-card of ISO/IEC14443 standard, TypeA/B standard, ISO/IEC15693 standard, ISO/IEC18092 standard, ISO/IEC21481 standard, Sony Felica standard.
11. frequency read/writes as claimed in claim 1, is characterized in that, described frequency read/write also comprises:
The Circuit for Non-contact IC Chip that connects described antenna, described Circuit for Non-contact IC Chip is the IC-card chip that meets ISO/IEC14443 standard, TypeA/B standard, ISO/IEC15693 standard or Sony Felica standard.
12. 1 kinds of radio-frequency recognition systems, comprise read-write application terminal and frequency read/write, it is characterized in that, described frequency read/write is the frequency read/write as described in claim 1 to 11 any one.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310754644.5A CN103679239B (en) | 2013-12-31 | 2013-12-31 | Radio frequency reader-writer and radio frequency identification system |
| PCT/CN2014/086713 WO2015101067A1 (en) | 2013-12-31 | 2014-09-17 | Rfid reader/writer and rfid system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310754644.5A CN103679239B (en) | 2013-12-31 | 2013-12-31 | Radio frequency reader-writer and radio frequency identification system |
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| WO2015101067A1 (en) * | 2013-12-31 | 2015-07-09 | 深圳市吉芯微半导体有限公司 | Rfid reader/writer and rfid system |
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| CN105930885A (en) * | 2016-04-18 | 2016-09-07 | 上海秒通网络通讯技术有限公司 | Method and device for integrated processing of large number of chips based on non-contact radio frequency technology |
| CN106096482A (en) * | 2016-08-05 | 2016-11-09 | 成都国腾实业集团有限公司 | There is the identity card reader of wifi wireless routing function |
| CN106295434A (en) * | 2016-08-16 | 2017-01-04 | 江门市汇朗工业机器人有限公司 | A kind of identification system based on RF technology |
| CN106339649A (en) * | 2016-08-16 | 2017-01-18 | 江门市汇朗工业机器人有限公司 | Card reader based on RF radio frequency communication |
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| CN110838204A (en) * | 2019-11-05 | 2020-02-25 | 艾体威尔电子技术(北京)有限公司 | Decoding method for magnetic stripe card swiping terminal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103679239B (en) | 2017-04-26 |
| WO2015101067A1 (en) | 2015-07-09 |
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