WO2015096732A1 - 过零检测电路及功率因数校正电路 - Google Patents

过零检测电路及功率因数校正电路 Download PDF

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Publication number
WO2015096732A1
WO2015096732A1 PCT/CN2014/094798 CN2014094798W WO2015096732A1 WO 2015096732 A1 WO2015096732 A1 WO 2015096732A1 CN 2014094798 W CN2014094798 W CN 2014094798W WO 2015096732 A1 WO2015096732 A1 WO 2015096732A1
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WIPO (PCT)
Prior art keywords
voltage
power factor
primary winding
factor correction
limiting resistor
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Application number
PCT/CN2014/094798
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English (en)
French (fr)
Inventor
李志峰
余世伟
Original Assignee
欧普照明股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from CN201310730851.7A external-priority patent/CN104749426B/zh
Priority claimed from CN201320869463.2U external-priority patent/CN203858288U/zh
Application filed by 欧普照明股份有限公司 filed Critical 欧普照明股份有限公司
Priority to DE212014000237.0U priority Critical patent/DE212014000237U1/de
Publication of WO2015096732A1 publication Critical patent/WO2015096732A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/175—Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the invention relates to a zero crossing detection circuit and a power factor correction circuit.
  • Power factor correction can generally be divided into active power factor correction (APFC) and passive power factor correction (PPFC).
  • Active power factor correction can usually use critical conduction mode (CRM) and continuous conduction mode (CCM), and active power factor correction control methods can usually include peak current control mode, fixed on-time mode, and fixed frequency. way to control.
  • CCM critical conduction mode
  • CCM continuous conduction mode
  • active power factor correction control methods can usually include peak current control mode, fixed on-time mode, and fixed frequency. way to control.
  • the present invention provides a zero-crossing detection circuit and a power factor correction circuit that generate a zero-crossing detection signal by adding a bias voltage at a zero-crossing detection point so that a current flowing through the boosting inductor actually drops to zero
  • the control switch is turned on to ensure that the zero-crossing detection circuit and the power factor correction circuit actually operate in the critical conduction mode of the active power factor correction, thereby avoiding continuous current flowing through the boost inductor in the active power factor correction.
  • a zero-crossing detecting circuit comprising: a transformer including a primary winding and a secondary winding, a second end of the secondary winding being grounded; a current limiting resistor having a first end and the a first end of the secondary winding is connected; a voltage conversion module, an input end thereof and the current limiting resistor a two-terminal connection; and a bias resistor having a first end connected to the second end of the current limiting resistor and a second end connected to the bias voltage source; wherein the voltage at the second end of the current limiting resistor is lower than The first voltage threshold, the voltage conversion module outputs a first voltage; and when the voltage of the second terminal of the current limiting resistor is higher than the first voltage threshold, the voltage conversion module outputs a second voltage.
  • the primary winding has a first end and a second end, the first end of the primary winding being the same end as the second end of the secondary winding.
  • the primary winding has a voltage at its first terminal that is higher than the voltage at its second terminal when charging, and its first terminal voltage is lower than the voltage at its second terminal when discharging.
  • the first voltage indicates that the voltage of the first end of the primary winding is higher than the voltage of the second end of the primary winding
  • the second voltage indicates that the voltage of the first end of the primary winding is low a voltage at a second end of the primary winding
  • the voltage at the second end of the current limiting resistor satisfies:
  • VCC is a bias voltage provided by said bias voltage source
  • R1 is a resistance value of said bias resistor
  • R2 is a resistance value of said current limiting resistor
  • VA is a first end of said secondary winding Voltage.
  • the first voltage threshold is less than or equal to Positive voltage threshold.
  • the voltage conversion module includes a voltage comparator, a non-inverting input of the voltage comparator is coupled to the second end of the voltage comparator, and the non-inverting input of the voltage comparator receives the a first voltage threshold, the first voltage is a low level, the second voltage is a high level; or a non-codirectional input of the voltage comparator is connected to a second end of the current limiting resistor, The non-inverting input of the voltage comparator receives the first voltage threshold, the first voltage is a high level, and the second voltage is a low level.
  • a power factor correction circuit comprising: a transformer including a primary winding and a secondary winding, a second end of the secondary winding being grounded; a current limiting resistor having a first end The first end of the secondary winding is connected; the voltage conversion module has an input end connected to the second end of the current limiting resistor; and the control switch has a first end connected to the output end of the voltage conversion module, and a second The terminal is connected to the second end of the primary winding, the third end thereof is grounded; and the bias resistor has a first end connected to the second end of the current limiting resistor and a second end connected to the bias voltage source; In When the voltage of the second end of the current limiting resistor is lower than the first voltage threshold, the output end of the voltage conversion module outputs a first voltage to turn on the control switch; the voltage at the second end of the current limiting resistor Above the first voltage threshold, the output of the voltage conversion module outputs a second voltage to open the control switch.
  • the voltage conversion module includes a voltage comparator, a non-inverting input of the voltage comparator is coupled to the second end of the voltage comparator, and the non-inverting input of the voltage comparator receives the The first voltage threshold, the first voltage is a low level, the second voltage is a high level, and the control switch is a PMOS transistor.
  • the voltage conversion module includes a voltage comparator, a non-codirectional input of the voltage comparator is coupled to a second end of the current limiting resistor, and a non-inverting input terminal of the voltage comparator receives
  • the first voltage threshold is described, the first voltage is a high level, the second voltage is a low level, and the control switch is an NMOS transistor.
  • the voltage conversion module is an active power factor correction integrated chip that operates in a critical conduction mode and uses a peak current control approach.
  • the zero-crossing detection circuit and the power factor correction circuit generate a zero-crossing detection signal by adding a bias voltage at a zero-crossing detection point so that the current flowing through the boosting inductor L1 actually drops to zero
  • the control switch Q1 is turned on, thereby ensuring that the zero-crossing detection circuit and the power factor correction circuit actually operate in the critical conduction mode of the active power factor correction, thereby avoiding the current flowing through the boost inductor in the active power factor correction. continuous.
  • FIG. 1 is a schematic diagram showing a boost type active power factor correction circuit in the prior art
  • FIG. 2 is a schematic diagram of the boosting type active power factor correction circuit shown in FIG. 1 when the control switch is turned on;
  • FIG. 3 is a schematic diagram of the boosting type active power factor correction circuit shown in FIG. 1 when the control switch is turned off;
  • FIG. 4 shows a schematic diagram of a zero crossing detection circuit in accordance with an embodiment of the present invention
  • FIG. 5 is a schematic diagram showing an implementation of a zero crossing detection circuit according to an embodiment of the present invention.
  • FIG. 6 shows a schematic diagram of a power factor correction circuit in accordance with an embodiment of the present invention
  • FIG. 7 shows a schematic diagram of one implementation of a power factor correction circuit in accordance with an embodiment of the present invention.
  • Figure 8 is a diagram showing signal waveforms in a prior art power factor correction circuit
  • Fig. 9 is a view showing signal waveforms in the power factor correction circuit shown in Fig. 7.
  • FIG. 1 a schematic diagram of a known step-up active power factor correction circuit is shown, in which DB1 is a full-wave rectifier bridge, C1 is a first capacitor, and L1 is a boost inductor, Q1. To control the switch, D1 is the diode, C2 is the storage capacitor, and U1 is the active power factor correction control chip, which operates in the critical conduction mode and adopts the peak current control mode. To simplify the description, the peripheral elements of U1 are not shown in FIG.
  • FIG. 2 a schematic diagram of the boosting type active power factor correction circuit shown in FIG. 1 when the control switch Q1 is turned on is shown, wherein the direction of the current is indicated by an arrow, specifically, the voltage is boosted.
  • the current of the inductor L1 flows through the control switch Q1, and no current flows through the diode D1.
  • the boost inductor L1 performs energy storage (ie, charging), and the current flowing through the boost inductor L1 satisfies the following formula:
  • U(t) is the instantaneous voltage across the boost inductor L1
  • L is the inductance of the boost inductor L1
  • t is the time
  • i(t) is the current flowing through the boost inductor L1.
  • the active power factor correction chip U1 detects whether the boost inductor L1 has reached the preset peak current i max , and in the case where it is detected that the boost inductor L1 reaches the preset peak current, there is The source power factor correction chip U1 turns off the control switch Q1.
  • FIG. 3 a schematic diagram of the boosting type active power factor correction circuit shown in FIG. 1 when the control switch Q1 is turned off is shown, wherein the direction of the current is indicated by an arrow, specifically, the voltage is boosted.
  • the current of the inductor L1 flows through the diode D1, and no current flows through the control switch Q1.
  • the boost inductor L1 is discharged (ie, discharged), and the current flowing through the boost inductor L1 still satisfies the above formula (1).
  • U(t) is still the instantaneous voltage across the boosting inductor L1. Since the control switch Q1 is turned off and the diode D1 is turned on in the circuit shown in Fig. 3, U(t) is equal in this stage. The difference between the output voltage Uo(t) and the input voltage Ui(t), in this phase, it is considered that the output voltage Uo(t) is constant to Vo and the input voltage Ui(t) is constant to Vi, correspondingly U(t) Constant to Vo-Vi.
  • the active power factor correction chip U1 detects the zero-crossing point of the current flowing through the boosting current L1, and turns on the control switch Q1 when the zero-crossing point is detected.
  • the off time of the control switch Q1 can be:
  • the primary winding of the transformer is used as the boosting inductor L1
  • the secondary winding of the transformer is used for current zero-crossing detection, and current is detected.
  • the control switch Q1 is turned on.
  • the active power factor correction chip U1 Since the positive voltage reference value is used in the active power factor correction chip U1, the active power factor is not actually reduced to zero when the current of the boosting inductor L1 has not actually decreased to zero during the initial period of power-on, during the power-off of the control switch Q1.
  • the correction chip U1 outputs a control signal to turn on the control switch Q1, causing the current flowing through the boost inductor L1 to rise again.
  • FIG. 4 a schematic diagram of a zero-crossing detection circuit 1 according to an embodiment of the present invention is shown, wherein the zero-crossing detection circuit 1 includes a transformer 2, a voltage conversion module 3, a current limiting resistor R2, and an offset. Resistor R1.
  • the transformer 2 includes a primary winding 21 and a secondary winding 22, the primary winding 21 including a first end 211 and a second end 212, the secondary winding 22 including a first end 221 and a second end 222.
  • the second end 222 of the secondary winding 22 is grounded.
  • a first end of the current limiting resistor R2 is coupled to the first end 221 of the secondary winding for limiting current flow into the voltage conversion module 3.
  • a first end of the bias resistor R1 is coupled to the second end of the current limiting resistor R2, and a second end of the bias resistor R1 is coupled to the bias voltage source VCC.
  • An input end of the voltage conversion module 3 is connected to a second end of the current limiting resistor R2 and a first end of the bias resistor R1.
  • the voltage conversion module 3 When the voltage at the input end of the voltage conversion module 3 is lower than the first voltage threshold, the voltage conversion module 3 outputs a first voltage; and the voltage at the input end of the voltage conversion module 3 is higher than or equal to the first At the voltage threshold, the voltage conversion module 3 outputs a second voltage.
  • the first voltage indicates that a voltage of a first end of the primary winding is higher than a voltage of a second end of the primary winding
  • the second voltage indicates that a voltage of a first end of the primary winding is lower than the primary winding The voltage at the second end.
  • the voltage VC at the connection point of the second end of the current limiting resistor R2 and the first end of the bias resistor R1 can be expressed as:
  • R1 represents the resistance value of the bias resistor R1
  • R2 represents the resistance value of the current limiting resistor R2
  • VCC represents the voltage value of the bias voltage source VCC
  • VA represents the first value of the current limiting resistor R2.
  • the first voltage threshold may be a positive voltage threshold greater than zero and may be a small positive voltage, such as 0.7V or the like.
  • the first term in the above formula (6) may be set equal to the first voltage threshold, in which case the voltage VA at the first end 221 of the secondary winding 22 (ie, point A) is equal to zero and While continuing to decrease, the output of the voltage conversion module 3 transitions from the second voltage to the first voltage, thereby providing a zero crossing detection signal.
  • the first term in the above formula (6) may be set to be slightly higher than the first voltage threshold, in which case, at the first end 221 of the secondary winding 22 (ie, point A)
  • the output of the voltage conversion module 3 is The second voltage transitions to a first voltage to provide a zero crossing detection signal. In this case, it can be further ensured that the boosting inductor L1 can be completely discharged, and the charge accumulation of the boosting inductor L1 is avoided.
  • the first end 211 of the primary winding 21 and the second end 222 of the secondary winding 22 are of the same name, having applied a charging voltage through the first end 211 of the primary winding 21 and The second end 212 is grounded to store electrical energy in the primary winding 21, and the first term in equation (6) above is set equal to the first voltage threshold.
  • the primary winding 21 when the primary winding 21 is energized, the voltage at its first end 211 is lower than the voltage at its second end 212, and current flows from its first end 211 to the second end 212, which The voltage of the point A is a positive voltage, and accordingly, the voltage of the point C is higher than the first voltage threshold.
  • the output of the voltage conversion module 3 outputs a second voltage;
  • the winding 21 continues to discharge, the current flowing through the primary winding 21 gradually decreases to zero, and then reverses until the voltage at its first end 211 becomes equal to the voltage at the second terminal 212, at this time,
  • the voltage at point A also drops to zero, and accordingly the voltage at point C becomes equal to the first voltage threshold, and then less than the first voltage threshold, and therefore, the output of the voltage conversion module 3 outputs A voltage
  • the switching of the output of the voltage conversion module 3 from the second voltage to the first voltage is equivalent to outputting a zero-crossing detection signal to indicate that a zero-crossing of the current of the primary winding 21 occurs.
  • the first end 211 of the primary winding 21 and the second end 222 of the secondary winding 22 are of the same name, having applied a charging voltage through the first end 211 of the primary winding 21 and Its second end 212 is grounded to store electrical energy in the primary winding 21, and the first term in equation (6) above is set slightly above the first voltage threshold.
  • the primary winding 21 when the primary winding 21 is energized, the voltage at its first end 211 is lower than the voltage at its second end 212, and current flows from its first end 211 to the second end 212, which The voltage of the point A is a positive voltage, and accordingly, the voltage of the point C is higher than the first voltage threshold.
  • the output of the voltage conversion module 3 outputs a second voltage;
  • the winding 21 continues to discharge, the current flowing through the primary winding 21 gradually decreases to zero, and then reverses until the voltage at its first end 211 becomes equal to the voltage at the second terminal 212, then the A
  • the voltage of the point continues to decrease to VA' (the absolute value is the difference between the first term in equation (6) and the first voltage threshold), and accordingly the voltage at point C becomes equal to this time.
  • the first voltage threshold therefore, the output of the voltage conversion module 3 outputs a first voltage, and the switching of the output of the voltage conversion module 3 from the second voltage to the first voltage is equivalent to outputting a zero-cross detection signal To appear at the zero crossing of the current indicating the primary winding 21.
  • the voltage at its first end 211 is higher than the voltage at its second end 212, and current flows from its first end 211 to the second end 212, At this time, the voltage of the point A is a negative voltage, and accordingly, the voltage of the point C is smaller than the first voltage threshold, and therefore, the output end of the voltage conversion module 3 outputs the first voltage.
  • the bias voltage source VCC can be an independent DC power source or can also be provided by a secondary winding.
  • the voltage conversion module 3 may include a voltage comparator 31, the non-inverting input terminal of the voltage comparator 31 is connected to the C point, and the voltage comparator 31 is different.
  • Receiving, by the input terminal, the first voltage threshold when the input voltage received by the non-inverting input terminal of the voltage comparator 31 (ie, the voltage of the C point) is not higher than the first voltage threshold, the voltage The comparator 31 outputs a first voltage; and when the input voltage received at the non-inverting input of the voltage comparator 31 (ie, the voltage at the C point) is higher than the first voltage threshold, the voltage comparator outputs The second voltage.
  • the first voltage is a low level and the second voltage is a high level.
  • the voltage conversion module 3 may include a voltage comparator 31 and an inverter, the non-inverting input of the voltage comparator 31 being connected to the C point, the voltage comparator 31
  • the non-co-input input receives the first voltage threshold
  • the output of the voltage comparator 31 is coupled to the input of the inverter, and the input voltage received at the non-inverting input of the voltage comparator 31 ( That is, when the voltage of the C point is not higher than the first voltage threshold, the output of the voltage comparator 31 outputs a second voltage, the inverter outputs a first voltage; and at the voltage comparator
  • the input voltage received by the co-directional input of 31 ie, the voltage of the C point
  • the output of the voltage comparator outputs a first voltage
  • the inverter outputs a second Voltage.
  • the first voltage is a high level and the second voltage is a low level.
  • the voltage conversion module 3 may include a voltage comparator 31, the non-codirectional input of the voltage comparator 31 is connected to the C point, and the voltage comparator 31 is the same Receiving the first voltage threshold to an input terminal, when an input voltage received by the non-inverting input terminal of the voltage comparator 31 (ie, a voltage of the C point) is not higher than the first voltage threshold, The voltage comparator 31 outputs a first voltage; and when the input voltage received at the non-inverting input of the voltage comparator 31 (ie, the voltage at the C point) is higher than the first voltage threshold, the voltage comparison Output The second voltage.
  • the first voltage is a high level and the second voltage is a low level.
  • the voltage conversion module 3 may include a voltage comparator 31 and an inverter, the non-inverting input of the voltage comparator 31 being connected to the C point, the voltage comparison
  • the same direction input terminal of the device 31 receives the first voltage threshold, and the input voltage received at the non-inverting input end of the voltage comparator 31 (ie, the voltage at the C point) is not higher than the first voltage threshold
  • the output of the voltage comparator 31 outputs a second voltage
  • the inverter outputs a first voltage
  • the input voltage received at the non-inverting input of the voltage comparator 31 ie, the C point
  • the output of the voltage comparator 31 outputs a first voltage
  • the inverter outputs a second voltage.
  • the first voltage is a low level and the second voltage is a high level.
  • the voltage comparator 31 is shown as the voltage conversion module 3 in the example of FIG. 5, those skilled in the art will appreciate that the peripheral components of the voltage comparator 31 may also be added as long as the voltage is retained.
  • the voltage conversion function of the conversion module 3 is sufficient.
  • a clamping element can be added at the point C to clamp the voltage of the non-inverting input of the voltage comparator 31 to the second voltage threshold when the voltage at the point C is higher than the second voltage threshold. And clamping the voltage of the non-inverting input terminal of the voltage comparator 31 to the third voltage threshold when the voltage of the C point is lower than the third voltage threshold.
  • the power factor correction circuit 100 includes: a full-wave rectifier bridge DB1, a first capacitor C1, a transformer 2, a voltage conversion module 3, a control switch Q1, a diode D1, a bias resistor R1, and a current limiting resistor R2. , output resistor R3, and storage capacitor C2.
  • the transformer 2 includes a primary winding 21 and a secondary winding 22, the primary winding 21 including a first end 211 and a second end 212, the secondary winding 22 including a first end 221 and a second end 222.
  • the second end 222 of the secondary winding 22 is grounded.
  • a first end of the current limiting resistor R2 is coupled to the first end 221 of the secondary winding 22.
  • the input end of the voltage conversion module 3 is connected to the second end of the current limiting resistor R2.
  • the first end of the control switch Q1 is connected to the output end of the voltage conversion module 3, the second end thereof is connected to the second end 212 of the primary winding 21, and the third end thereof is grounded.
  • the control switch Q1 can be a field effect transistor or other switching transistor.
  • the first end of the bias resistor R1 is connected to the second end of the current limiting resistor R2, and the second end thereof is connected to the bias voltage source VCC.
  • the voltage is turned
  • the output terminal of the replacement module 3 outputs a first voltage to turn on the control switch Q1; when the voltage of the second terminal of the current limiting resistor R2 is higher than the first voltage threshold, the output of the voltage conversion module 3 The terminal outputs a second voltage to disconnect the control switch.
  • the first voltage indicates that the voltage of the first end of the primary winding is higher than the voltage of the second end of the primary winding
  • the second voltage indicates that the voltage of the first end of the primary winding is lower than the voltage The voltage at the second end of the primary winding.
  • the primary winding has a first end and a second end, the first end of the primary winding being the same end as the second end of the secondary winding, the primary winding being first when charging
  • the voltage at the terminal is higher than the voltage at its second terminal, and the voltage at its first terminal is lower than the voltage at its second terminal during discharge.
  • the conduction of the control switch Q1 is controlled by the output voltage of the voltage conversion module based on the zero-crossing detection circuit described above with reference to FIGS. 4 and 5. Specifically, when the primary winding 21 of the transformer 2 is discharged and its current has not passed zero, the voltage conversion module outputs a second voltage to open the control switch Q1; and at the primary winding of the transformer 2 After the energy is discharged 21 and its current crosses zero, the voltage conversion module 3 outputs a first voltage to turn on the control switch Q1.
  • the voltage conversion module 3 may include a voltage comparator 31, the non-inverting input terminal of the voltage comparator 31 is connected to the C point, and the voltage comparator 31 is different. Receiving the first voltage threshold to an input terminal, the first voltage is a low level, the second voltage is a high level, and the control switch is a PMOS transistor.
  • the voltage conversion module 3 may include a voltage comparator 31 and an inverter, the non-inverting input of the voltage comparator 31 being connected to the C point, the voltage comparator 31 The non-co-input input receives the first voltage threshold, the output of the voltage comparator 31 is connected to the input of the inverter, the first voltage is a high level, and the second voltage is a low Level, the control switch is an NMOS transistor.
  • the voltage conversion module 3 may include a voltage comparator 31, the non-codirectional input of the voltage comparator 31 is connected to the C point, and the voltage comparator 31 is the same Receiving the first voltage threshold to an input terminal, the first voltage is a high level, the second voltage is a low level, and the control switch is an NMOS transistor.
  • the voltage conversion module 3 may include a voltage comparator 31 and an inverter, the non-inverting input of the voltage comparator 31 being connected to the C point, the voltage comparison The same input terminal of the device 31 receives the first voltage threshold, and the output of the voltage comparator 31 is connected Connected to the input of the inverter, the first voltage is a low level, the second voltage is a high level, and the control switch is a PMOS transistor.
  • the voltage conversion module 3 can be implemented as an existing active power factor correction chip that operates in a critical conduction mode and adopts a peak current control mode.
  • the MC33262 dedicated integrated control chip produced by Motorola of the United States
  • the L6561/L6562/6562A dedicated integrated control chip produced by ST STMicroelectronics
  • the FAN7527/FAN7528 integrated control chip produced by Fairchild Company of the United States
  • the TDA4817 produced by Siemens.
  • /TDA4862 dedicated integrated control chip, and SN03A dedicated integrated control chip produced by Angbao Electronics Co., Ltd., etc.
  • the present invention is not limited thereto, but can be applied to existing or future developed other devices operating in a critical conduction mode and employing a peak current control mode. Active power factor correction chip.
  • the power factor correction circuit according to the embodiment of the present invention may be as shown in FIG. 7, wherein the first pin of the active power factor correction chip is a feedback voltage input terminal, and the second pin is a compensation signal input terminal.
  • the third pin is the input end of the multiplier
  • the fourth pin is the current detection signal input end
  • the fifth pin is the zero current detection signal input end
  • the sixth pin is the ground end
  • the seventh pin is the drive signal output end
  • the eighth pin It It is the bias power supply terminal.
  • the first end of the primary winding 21 of the transformer 2 (hereinafter referred to as the boosting inductor L1) and the second end of the secondary winding 22 are exemplified by the same name.
  • the present invention is not limited thereto, and those skilled in the art can make the first end of the primary winding 21 of the transformer 2 and the first end of the secondary winding 22 the same name end, and change accordingly, based on the disclosure of the present invention.
  • a charge and discharge cycle of the boost inductor L1 can be divided into two phases: an energy storage phase and a release phase.
  • the zero current detection technical solution of the embodiment of the present invention does not involve the transition from the energy storage phase to the energy release phase. Therefore, in the following description, the transition from the energy storage phase to the release phase is not excessively described, so as not to obscure the implementation of the present invention.
  • Example of zero current detection technology is not excessively described.
  • the boost inductor L1 (ie, the primary winding of the transformer) stores energy and rectifies
  • the voltage of the bridge output charges the boosting inductor L1
  • the charging current flows from the first end of the boosting inductor L1 to the second end, and the voltage of the first end of the boosting inductor L1 is higher than that of the second end Voltage.
  • the voltage of the first end of the secondary winding of the transformer is lower than the voltage of the second end, that is, the voltage of the first end of the secondary winding of the transformer is a negative voltage, so that the current limiting resistor R2
  • the voltage of the two terminals is lower than the first voltage threshold, so that the voltage conversion module or the seventh pin of the active power factor correction chip outputs a first voltage to continue to turn on the control switch Q1.
  • the first voltage is a high level
  • the control switch Q1 is an NMOS transistor.
  • the first voltage is a low level
  • the control switch Q1 is a PMOS transistor.
  • the boost inductor L1 (ie, the primary winding of the transformer) is discharged, and current still flows from the first end of the boost inductor L1 to the second end, however, with the energy storage phase Differently, the voltage of the first end of the boosting inductor L1 is lower than the voltage of the second terminal in the energy dissipating phase.
  • the voltage of the first end of the secondary winding of the transformer is higher than the voltage of the second end, that is, the voltage of the first end of the secondary winding of the transformer is a positive voltage, so that the current limiting resistor R2
  • the voltage at the two terminals is higher than the first voltage threshold such that the voltage conversion module or the seventh pin of the active power factor correction chip outputs a second voltage to continue to open the control switch Q1.
  • the second voltage is a low level
  • the control switch Q1 is an NMOS transistor.
  • the second level is a high level and the control switch Q2 is a PMOS transistor.
  • the voltage is the voltage at point A, and can be expressed as: (VC2(t)-Vi(t))/n, where VC2(t) represents the instantaneous voltage across the storage capacitor C2, and Vi(t) represents The instantaneous voltage across the first capacitor C1, n represents the turns ratio of the primary winding to the secondary winding of the transformer.
  • VC2(t)-Vi(t) is a small value because the output voltage is close to the input voltage, and further (VC2(t)-Vi(t))/n Small, thus causing the voltage at point C at this time to be less than the first voltage threshold, the first voltage threshold being a positive voltage greater than zero, such as 0.7V. Accordingly, an erroneous current zero crossing detection is caused, and the voltage conversion module or the active power factor correction chip erroneously generates a control signal that turns on the control switch Q1.
  • the voltage at point C satisfies the above formula (6). Even in the initial stage of power-on, as long as the voltage at point A is greater than zero, the voltage at point C must be greater than the first voltage threshold, so that the voltage conversion module or the active power factor correction chip can correctly generate and maintain A control signal that controls the opening of switch Q1 is described. This Thereafter, as the boost inductor L1 continues to discharge, the current flowing through the boost inductor L1 gradually decreases until it decreases to zero, and the voltage at the point A also decreases to zero.
  • the voltage conversion module or the active power factor correction chip When the first voltage threshold is equal to the first term in the above formula (6), the voltage conversion module or the active power factor correction chip generates zero-crossing detection when the voltage at the point A decreases to zero. Signaling and turning on the control switch Q1.
  • the first voltage threshold is less than the first term in the above formula (6), when the current flowing from the first end to the second end of the boosting inductor L1 decreases to zero, due to the control switch Q1
  • the boosting inductor L1 and the control switch Q1 start to oscillate until the voltage of the first end of the boosting inductor L1 starts to become higher than the voltage of the second terminal, and correspondingly, the point A
  • the voltage becomes a negative voltage
  • the voltage at the point A reaches a predetermined negative voltage
  • the voltage at the point C becomes smaller than the first voltage threshold, thereby the voltage conversion module or the active power factor correction
  • the chip generates a zero-crossing detection signal to turn on the control switch Q1. In the
  • FIG. 8 shows a voltage waveform of each point in the active power factor correction circuit when the output voltage is close to the input voltage at the initial stage of power-on, which is acquired by the oscilloscope without adding the bias resistor.
  • 801 indicates the voltage waveform at point B in Fig. 7
  • 802 indicates the voltage waveform of D in Fig. 7
  • 803 indicates the current of the boosting inductor L1 in Fig. 7,
  • 804 indicates the waveform of the voltage at point C in Fig. 7.
  • the boost inductor L1 is discharged, and the current of the boost inductor L1 is gradually decreased.
  • the storage capacitor C2 supplies power to the load alone, so the voltage across the storage capacitor C2 (ie, the voltage at point D) drops, and the boost inductor L1 stores energy.
  • the boosting inductor L1 is released, and the current of the boosting inductor L1 is gradually decreased.
  • the active power factor correction chip since the output voltage and the input voltage are close in the initial stage of power-on, the current in the boosting inductor L1 has not yet been When it is really zero, the active power factor correction chip generates a control signal for controlling the conduction of the control switch Q1, so that the current of the boosting inductor L1 is superimposed, that is, it has not decreased to zero and begins to rise again.
  • the storage capacitor C2 supplies power to the load alone, so the voltage across the storage capacitor C2 (ie, the voltage at point D) drops, and the boost inductor L1 stores energy.
  • FIG. 9 shows the electric power of each point in the active power factor correction circuit when the output voltage is close to the input voltage at the initial stage of power-on, which is acquired by the oscilloscope with the addition of the bias resistor R1.
  • 901 indicates the voltage waveform at point B in Fig. 7
  • 902 indicates the voltage waveform of D in Fig. 7
  • 903 indicates the current of the boosting inductor L1 in Fig. 7
  • 904 indicates the waveform of the voltage at point C in Fig. 7.
  • the boost inductor L1 is discharged, and the current of the boost inductor L1 is gradually decreased.
  • the storage capacitor C2 supplies power to the load alone, so the voltage across the storage capacitor C2 (ie, the voltage at point D) drops, and the boost inductor L1 stores energy.
  • the active power factor correction chip When the current of the boosting inductor L1 actually drops to zero or even reverses, the active power factor correction chip generates a control signal for controlling the conduction of the control switch Q1, thereby effectively avoiding the current of the boosting inductor L1. The situation of overlays appears.
  • a zero-crossing detection circuit and a power factor correction circuit generate a zero-crossing detection signal by adding a bias voltage at a zero-crossing detection point such that a current flowing through the boosting inductor L1 actually drops to zero And correspondingly turning on the control switch Q1, thereby ensuring that the zero-crossing detection circuit and the power factor correction circuit actually operate in the critical conduction mode of active power factor correction, thereby avoiding the flow of the boost inductor in the active power factor correction.
  • the current is continuous.

Abstract

一种过零检测电路（1）及功率因数校正电路，所述过零检测电路（1）包括：变压器（2），其包括初级绕组（21）和次级绕组（22）；限流电阻，其第一端与次级绕组（22）的第一端（221）连接；电压转换模块（3），其输入端与限流电阻的第二端连接；以及偏置电阻。所述功率因数校正电路包括：所述过零检测电路（1）；以及控制开关。其中，限流电阻的第二端的电压低于第一电压阈值时，所述电压转换模块（3）输出第一电压以导通控制开关；在限流电阻的第二端的电压高于第一电压阈值时，所述电压转换模块（3）输出第二电压以断开控制开关。保证所述过零检测电路（1）以及功率因数校正电路真正工作在有源功率因数校正的临界导通模式下，避免了有源功率因数校正中流过升压电感的电流连续。

Description

过零检测电路及功率因数校正电路 技术领域
本发明涉及一种过零检测电路及功率因数校正电路。
背景技术
目前，对电网的品质要求越来越高，这相应地对电气产品的功率因数提出了更高的要求。功率因数校正通常可以分为有源功率因数校正(APFC)和无源功率因数校正(PPFC)。有源功率因数校正通常可以采用临界导通模式(CRM)和连续导通模式(CCM)，并且有源功率因数校正的控制方式通常可以包括峰值电流控制方式、固定导通时间方式、以及固定频率控制方式。
然而，已经发现，在这样的有源功率因数校正电路中，在上电初期，由于储能电容两端的电压尚未达到预期值而且与输入电压比较接近，在此情况下，在控制开关断开期间，升压电感两端的电压值比较小，在变压器的初级和次级匝数比为n的情况下，次级绕组上的电压相应地是升压电感两端的电压的1/n并且因此更小。由于在有源功率因数校正芯片中采用了正电压参考值，因此，在上电初期，在控制开关断开期间，在升压电感的电流尚未真正降低到零时，有源功率因数校正芯片会输出控制信号以将控制开关导通，导致流过升压电感的电流重新上升。
因此，需要一种能够准确进行电流过零检测的过零检测电路以及功率因数校正电路。
发明内容
本发明提供了一种过零检测电路以及功率因数校正电路，其通过在过零检测点处添加偏置电压，使得在流过升压电感的电流真正下降到零时才产生过零检测信号并相应地导通控制开关，从而保证所述过零检测电路以及功率因数校正电路真正工作在有源功率因数校正的临界导通模式下，避免了有源功率因数校正中流过升压电感的电流连续。
根据本发明一方面，提供了一种过零检测电路，包括：变压器，其包括初级绕组和次级绕组，所述次级绕组的第二端接地；限流电阻，其第一端与所述次级绕组的第一端连接；电压转换模块，其输入端与所述限流电阻的第 二端连接；以及偏置电阻，其第一端与所述限流电阻的第二端连接，其第二端连接偏置电压源；其中，在所述限流电阻的第二端的电压低于第一电压阈值时，所述电压转换模块输出第一电压；在所述限流电阻的第二端的电压高于所述第一电压阈值时，所述电压转换模块输出第二电压。
在一个示例中，所述初级绕组具有第一端和第二端，所述初级绕组的第一端与所述次级绕组的第二端为同名端。
在一个示例中，所述初级绕组在充电时其第一端的电压高于其第二端的电压，并且在放电时其第一端的电压低于其第二端的电压。
在一个示例中，所述第一电压指示所述初级绕组的第一端的电压高于所述初级绕组的第二端的电压，所述第二电压指示所述初级绕组的第一端的电压低于所述初级绕组的第二端的电压。
在一个示例中，所述限流电阻的第二端的电压满足：
Figure PCTCN2014094798-appb-000001
其中，VCC为所述偏置电压源提供的偏置电压，R1为所述偏置电阻的电阻值，R2为所述限流电阻的电阻值，VA为所述次级绕组的第一端的电压。
在一个示例中，所述第一电压阈值为小于或等于
Figure PCTCN2014094798-appb-000002
的正电压阈值。
在一个示例中，所述电压转换模块包括电压比较器，所述电压比较器的同向输入端连接所述限流电阻的第二端，所述电压比较器的非同向输入端接收所述第一电压阈值，所述第一电压为低电平，所述第二电压为高电平；或者所述电压比较器的非同向输入端连接所述限流电阻的第二端，所述电压比较器的同向输入端接收所述第一电压阈值，所述第一电压为高电平，所述第二电压为低电平。
根据本发明另一方面，提供了一种功率因数校正电路，包括：变压器，其包括初级绕组和次级绕组，所述次级绕组的第二端接地；限流电阻，其第一端与所述次级绕组的第一端连接；电压转换模块，其输入端与所述限流电阻的第二端连接；控制开关，其第一端与所述电压转换模块的输出端连接，其第二端与所述初级绕组的第二端连接，其第三端接地；以及偏置电阻，其第一端与所述限流电阻的第二端连接，其第二端连接偏置电压源；其中，在 所述限流电阻的第二端的电压低于第一电压阈值时，所述电压转换模块的输出端输出第一电压，以导通所述控制开关；在所述限流电阻的第二端的电压高于所述第一电压阈值时，所述电压转换模块的输出端输出第二电压，以断开所述控制开关。
在一个示例中，所述电压转换模块包括电压比较器，所述电压比较器的同向输入端连接所述限流电阻的第二端，所述电压比较器的非同向输入端接收所述第一电压阈值，所述第一电压为低电平，所述第二电压为高电平，所述控制开关为PMOS管。
在另一示例中，所述电压转换模块包括电压比较器，所述电压比较器的非同向输入端连接所述限流电阻的第二端，所述电压比较器的同向输入端接收所述第一电压阈值，所述第一电压为高电平，所述第二电压为低电平，所述控制开关为NMOS管。
在一个示例中，所述电压转换模块为操作于临界导通模式的并且使用峰值电流控制方式的有源功率因数校正集成芯片。
根据本发明实施例的过零检测电路和功率因数校正电路，通过在过零检测点处添加偏置电压，使得在流过升压电感L1的电流真正下降到零时才产生过零检测信号并相应地导通控制开关Q1，从而保证所述过零检测电路以及功率因数校正电路真正工作在有源功率因数校正的临界导通模式下，避免了有源功率因数校正中流过升压电感的电流连续。
附图说明
通过结合附图对本发明的实施例进行详细描述，本发明的上述和其它目的、特征、优点将会变得更加清楚，其中：
图1示出了现有技术中一种升压型有源功率因数校正电路的示意图；
图2示出了图1所示的升压型有源功率因数校正电路在控制开关导通时的示意图；
图3示出了图1所示的升压型有源功率因数校正电路在控制开关断开时的示意图；
图4示出了根据本发明实施例的过零检测电路的示意图；
图5示出了根据本发明实施例的过零检测电路的一种实现方式的示意图；
图6示出了根据本发明实施例的功率因数校正电路的示意图；
图7示出了根据本发明实施例的功率因数校正电路的一种实现方式的示意图；
图8示出了现有技术的功率因数校正电路中的信号波形图；以及
图9示出了图7所示的功率因数校正电路中的信号波形图。
具体实施方式
据发明人所知，对于小功率场合，诸如电子镇流器应用中，经常采用临界导通模式。如在图1中所示，示出了一种已知的升压型有源功率因数校正电路的示意图，其中，DB1为全波整流桥，C1为第一电容，L1为升压电感，Q1为控制开关，D1为二极管，C2为储能电容，U1为有源功率因数校正控制芯片，其操作于临界导通模式下并且采用峰值电流控制方式。为了简化描述，在图1中没有示出U1的周边元件。
如图2所示，示出了图1所示的升压型有源功率因数校正电路在控制开关Q1导通时的示意图，其中，用箭头示出了电流方向，具体地，流过升压电感L1的电流流过控制开关Q1，没有电流流过二极管D1，在此阶段中，升压电感L1进行储能(即充电)，并且流过升压电感L1的电流满足以下公式：
Figure PCTCN2014094798-appb-000003
其中，U(t)为升压电感L1两端的瞬时电压，L为升压电感L1的电感值，t表示时间，i(t)表示流过升压电感L1的电流。
由于在图2所示的电路中，控制开关Q1导通，因此，U(t)在此阶段中等于输入电压Ui(t)，即第一电容C1两端的电压，在此阶段中，可以近似认为Ui(t)和U(t)均恒定为Vi，因此，上述公式(1)可以变形为：
Figure PCTCN2014094798-appb-000004
在升压电感L1的导通时间为ton的情况下，流过升压电感L1的电流达到：
Figure PCTCN2014094798-appb-000005
在峰值电流控制方式下，有源功率因数校正芯片U1检测流过升压电感L1是否达到预设峰值电流imax，并且在检测到流过升压电感L1达到预设峰值 电流的情况下，有源功率因数校正芯片U1使控制开关Q1断开。
如图3所示，示出了图1所示的升压型有源功率因数校正电路在控制开关Q1断开时的示意图，其中，用箭头示出了电流方向，具体地，流过升压电感L1的电流流过二极管D1，没有电流流过控制开关Q1，在此阶段中，升压电感L1释能(即放电)，并且流过升压电感L1的电流仍满足上述公式(1)。
此时，U(t)仍为升压电感L1两端的瞬时电压，由于在图3所示的电路中，控制开关Q1断开并且二极管D1导通，因此，U(t)在此阶段中等于输出电压Uo(t)与输入电压Ui(t)之差，在此阶段中，近似认为输出电压Uo(t)恒定为Vo和输入电压Ui(t)恒定为Vi，相应地U(t)也恒定为Vo－Vi。
因此，在此阶段中，上述公式(1)可以变形为：
Figure PCTCN2014094798-appb-000006
在临界电流控制模式下，有源功率因数校正芯片U1检测流过升压电流L1的电流的过零点，并且在检测到该过零点时将控制开关Q1导通。
在理想情况下，控制开关Q1的断开时间可以为：
Figure PCTCN2014094798-appb-000007
如图1和图3所示，在已知的有源功率因数校正芯片中，利用变压器的初级绕组作为升压电感L1，并且利用变压器的次级绕组进行电流过零检测，并且在检测到电流过零时将控制开关Q1导通。
然而，已经发现，在这样的有源功率因数校正电路中，在上电初期，由于储能电容C2两端的电压尚未达到预期值而且与输入电压比较接近，在此情况下，在控制开关Q1断开期间，升压电感L1两端的电压为：Vo－Vi，该电压值比较小，在变压器的初级和次级匝数比为n的情况下，次级绕组上的电压相应地是升压电感L1两端的电压的1/n并且因此更小。由于在有源功率因数校正芯片U1中采用了正电压参考值，因此，在上电初期，在控制开关Q1断开期间，在升压电感L1的电流尚未真正降低到零时，有源功率因数校正芯片U1会输出控制信号以将控制开关Q1导通，导致流过升压电感L1的电流重新上升。
下面将参考附图来说明根据本发明实施例的过零检测电路以及功率因数校正电路。
如图4所示，示出了根据本发明实施例的过零检测电路1的示意图，其中，所述过零检测电路1包括：变压器2、电压转换模块3、限流电阻R2、以及偏置电阻R1。
变压器2包括初级绕组21和次级绕组22，所述初级绕组21包括第一端211和第二端212，所述次级绕组22包括第一端221和第二端222。所述次级绕组22的第二端222接地。
限流电阻R2的第一端与所述次级绕组的第一端221连接，用于限制流入电压转换模块3的电流。
偏置电阻R1的第一端与所述限流电阻R2的第二端连接，并且偏置电阻R1的第二端连接偏置电压源VCC。
电压转换模块3的输入端与所述限流电阻R2的第二端以及所述偏置电阻R1的第一端连接。
在所述电压转换模块3的输入端的电压低于第一电压阈值时，所述电压转换模块3输出第一电压；而在所述电压转换模块3的输入端的电压高于或等于所述第一电压阈值时，所述电压转换模块3输出第二电压。
所述第一电压指示所述初级绕组的第一端的电压高于所述初级绕组的第二端的电压，所述第二电压指示所述初级绕组的第一端的电压低于所述初级绕组的第二端的电压。
在如图4所示的电路中，所述限流电阻R2的第二端与所述偏置电阻R1的第一端的连接点(即C点)处的电压VC可以表示为：
Figure PCTCN2014094798-appb-000008
其中，R1表示所述偏置电阻R1的电阻值，R2表示所述限流电阻R2的电阻值，VCC表示所述偏置电压源VCC的电压值，VA表示所述限流电阻R2的第一端与所述次级绕组22的第一端221的连接点(即A点)处的电压。
所述第一电压阈值可以为大于零的正电压阈值，并且可以为很小的正电压，例如0.7V等。
上述公式(6)中的第一项可以被设置为等于所述第一电压阈值，在此情况下，在所述次级绕组22的第一端221(即A点)处的电压VA等于零并继续降低时，所述电压转换模块3的输出从第二电压跳变到第一电压，从而提供过零检测信号。
另一方面，上述公式(6)中的第一项可以被设置为稍高于所述第一电压阈值，在此情况下，在所述次级绕组22的第一端221(即A点)处的电压VA等于预定负电压(其绝对值等于上述公式(6)中的第一项的值与所述第一电压阈值之差)并继续降低时，所述电压转换模块3的输出才从第二电压跳变到第一电压，从而提供过零检测信号。在此情况下，可以更进一步保证所述升压电感L1能够彻底放电，避免了所述升压电感L1的电荷累积情况。
在一个示例中，所述初级绕组21的第一端211和所述次级绕组22的第二端222为同名端，已经通过在所述初级绕组21的第一端211施加充电电压并且使其第二端212接地而在初级绕组21中储存了电能，并且上述公式(6)中的第一项被设置为等于所述第一电压阈值。在此情况下，在所述初级绕组21释能时，其第一端211处的电压低于其第二端212处的电压，并且电流从其第一端211流到第二端212，此时，所述A点的电压为正电压，相应地所述C点的电压高于所述第一电压阈值，因此，所述电压转换模块3的输出端输出第二电压；随着所述初级绕组21继续释能，流过所述初级绕组21的电流逐渐减小到零，并且继而反向直至其第一端211处的电压变得与第二端212处的电压相等，此时，所述A点的电压也降到零，相应地所述C点的电压变得等于所述第一电压阈值，继而小于所述第一电压阈值，因此，所述电压转换模块3的输出端输出第一电压，所述电压转换模块3的输出端从第二电压到第一电压的切换相当于输出了过零检测信号，以指示所述初级绕组21的电流的过零点出现。
在另一示例中，所述初级绕组21的第一端211和所述次级绕组22的第二端222为同名端，已经通过在所述初级绕组21的第一端211施加充电电压并且使其第二端212接地而在初级绕组21中储存了电能，并且上述公式(6)中的第一项被设置为稍高于所述第一电压阈值。在此情况下，在所述初级绕组21释能时，其第一端211处的电压低于其第二端212处的电压，并且电流从其第一端211流到第二端212，此时，所述A点的电压为正电压，相应地所述C点的电压高于所述第一电压阈值，因此，所述电压转换模块3的输出端输出第二电压；随着所述初级绕组21继续释能，流过所述初级绕组21的电流逐渐减小到零，并且继而反向直至其第一端211处的电压变得与第二端212处的电压相等，然后所述A点的电压继续降低到VA’(其绝对值为公式(6)中第一项与第一电压阈值之差)，相应地所述C点的电压此时变得等于 所述第一电压阈值，因此，所述电压转换模块3的输出端输出第一电压，所述电压转换模块3的输出端从第二电压到第一电压的切换相当于输出了过零检测信号，以指示所述初级绕组21的电流的过零点出现。另一方面，在所述初级绕组21正向储能时，其第一端211处的电压高于其第二端212处的电压，并且电流从其第一端211流到第二端212，此时，所述A点的电压为负电压，相应地所述C点的电压小于所述第一电压阈值，因此，所述电压转换模块3的输出端输出第一电压。
所述偏置电压源VCC可以为独立的直流电源，或者也可以通过次级绕组提供。
在一个示例中，如图5所示，所述电压转换模块3可以包括电压比较器31，所述电压比较器31的同向输入端连接所述C点，所述电压比较器31的非同向输入端接收所述第一电压阈值，在所述电压比较器31的同向输入端接收的输入电压(即所述C点的电压)不高于所述第一电压阈值时，所述电压比较器31输出第一电压；而在所述电压比较器31的同向输入端接收的输入电压(即所述C点的电压)高于所述第一电压阈值时，所述电压比较器输出第二电压。所述第一电压为低电平，所述第二电压为高电平。
在一个示例中(未图示)，所述电压转换模块3可以包括电压比较器31和反向器，所述电压比较器31的同向输入端连接所述C点，所述电压比较器31的非同向输入端接收所述第一电压阈值，所述电压比较器31的输出端连接所述反向器的输入端，在所述电压比较器31的同向输入端接收的输入电压(即所述C点的电压)不高于所述第一电压阈值时，所述电压比较器31的输出端输出第二电压，所述反向器输出第一电压；而在所述电压比较器31的同向输入端接收的输入电压(即所述C点的电压)高于所述第一电压阈值时，所述电压比较器的输出端输出第一电压，所述反向器输出第二电压。所述第一电压为高电平，所述第二电压为低电平。
在另一示例中(未图示)，所述电压转换模块3可以包括电压比较器31，所述电压比较器31的非同向输入端连接所述C点，所述电压比较器31的同向输入端接收所述第一电压阈值，在所述电压比较器31的非同向输入端接收的输入电压(即所述C点的电压)不高于所述第一电压阈值时，所述电压比较器31输出第一电压；而在所述电压比较器31的非同向输入端接收的输入电压(即所述C点的电压)高于所述第一电压阈值时，所述电压比较器输出 第二电压。所述第一电压为高电平，所述第二电压为低电平。
在另一示例中(未图示)，所述电压转换模块3可以包括电压比较器31和反向器，所述电压比较器31的非同向输入端连接所述C点，所述电压比较器31的同向输入端接收所述第一电压阈值，在所述电压比较器31的非同向输入端接收的输入电压(即所述C点的电压)不高于所述第一电压阈值时，所述电压比较器31的输出端输出第二电压，所述反向器输出第一电压；而在所述电压比较器31的非同向输入端接收的输入电压(即所述C点的电压)高于所述第一电压阈值时，所述电压比较器31的输出端输出第一电压，所述反向器输出第二电压。所述第一电压为低电平，所述第二电压为高电平。
尽管在图5的示例中仅示出了电压比较器31作为所述电压转换模块3，但是本领域技术人员应了解，还可以添加所述电压比较器31的外围元件，只要保留了所述电压转换模块3的电压转换功能即可。例如，可以在所述C点添加箝位元件，以便在所述C点的电压高于第二电压阈值时将所述电压比较器31的同向输入端的电压箝位于所述第二电压阈值，并且在所述C点的电压低于第三电压阈值时将所述电压比较器31的同向输入端的电压箝位于所述第三电压阈值。
接下来，将参考图6来描述根据本发明实施例的功率因数校正电路。
如图6所示，所述功率因数校正电路100包括：全波整流桥DB1、第一电容C1、变压器2、电压转换模块3、控制开关Q1、二极管D1、偏置电阻R1、限流电阻R2、输出电阻R3、以及储能电容C2。
变压器2包括初级绕组21和次级绕组22，所述初级绕组21包括第一端211和第二端212，所述次级绕组22包括第一端221和第二端222。所述次级绕组22的第二端222接地。
限流电阻R2的第一端与所述次级绕组22的第一端221连接。
电压转换模块3的输入端与所述限流电阻R2的第二端连接。
控制开关Q1的第一端与所述电压转换模块3的输出端连接，其第二端与所述初级绕组21的第二端212连接，其第三端接地。控制开关Q1可以为场效应管或其他开关管。
偏置电阻R1的第一端与所述限流电阻R2的第二端连接，其第二端连接偏置电压源VCC。
在所述限流电阻R2的第二端的电压低于第一电压阈值时，所述电压转 换模块3的输出端输出第一电压，以导通所述控制开关Q1；在所述限流电阻R2的第二端的电压高于所述第一电压阈值时，所述电压转换模块3的输出端输出第二电压，以断开所述控制开关。
此外，所述第一电压指示所述初级绕组的第一端的电压高于所述初级绕组的第二端的电压，所述第二电压指示所述初级绕组的第一端的电压低于所述初级绕组的第二端的电压。
在一个示例中，所述初级绕组具有第一端和第二端，所述初级绕组的第一端与所述次级绕组的第二端为同名端，所述初级绕组在充电时其第一端的电压高于其第二端的电压，并且在放电时其第一端的电压低于其第二端的电压。
基于上面参考图4和图5所描述的过零检测电路，利用所述电压转换模块的输出电压来控制所述控制开关Q1的导通。具体地，在所述变压器2的初级绕组21释能并且其电流尚未过零时，所述电压转换模块输出第二电压，以断开所述控制开关Q1；而在所述变压器2的初级绕组21继续释能并且其电流过零后，所述电压转换模块3输出第一电压，以导通所述控制开关Q1。
在一个示例中，如图5所示，所述电压转换模块3可以包括电压比较器31，所述电压比较器31的同向输入端连接所述C点，所述电压比较器31的非同向输入端接收所述第一电压阈值，所述第一电压为低电平，所述第二电压为高电平，所述控制开关为PMOS管。
在一个示例中(未图示)，所述电压转换模块3可以包括电压比较器31和反向器，所述电压比较器31的同向输入端连接所述C点，所述电压比较器31的非同向输入端接收所述第一电压阈值，所述电压比较器31的输出端连接所述反向器的输入端，所述第一电压为高电平，所述第二电压为低电平，所述控制开关为NMOS管。
在另一示例中(未图示)，所述电压转换模块3可以包括电压比较器31，所述电压比较器31的非同向输入端连接所述C点，所述电压比较器31的同向输入端接收所述第一电压阈值，所述第一电压为高电平，所述第二电压为低电平，所述控制开关为NMOS管。
在另一示例中(未图示)，所述电压转换模块3可以包括电压比较器31和反向器，所述电压比较器31的非同向输入端连接所述C点，所述电压比较器31的同向输入端接收所述第一电压阈值，所述电压比较器31的输出端连 接所述反向器的输入端，所述第一电压为低电平，所述第二电压为高电平，所述控制开关为PMOS管。
此外，所述电压转换模块3可以被实现为现有的操作于临界导通模式下并采用峰值电流控制方式的有源功率因数校正芯片。例如，美国摩托罗拉公司生产的MC33262专用集成控制芯片，美国意法ST半导体公司生产的L6561/L6562/6562A专用集成控制芯片，美国仙童公司生产的FAN7527/FAN7528专用集成控制芯片，西门子公司生产的TDA4817/TDA4862专用集成控制芯片，以及昂宝电子公司生产的SN03A专用集成控制芯片等等。应了解，尽管这里给出了一些专用集成控制芯片的示例，然而本发明不限于此，而是可以应用于现有的或将来开发的操作于临界导通模式下并采用峰值电流控制方式的其它有源功率因数校正芯片。
在此情况下，根据本发明实施例的功率因数校正电路可以如图7所示，其中，所述有源功率因数校正芯片的第1脚为反馈电压输入端、第2脚为补偿信号输入端，第3脚为乘法器输入端，第4脚为电流检测信号输入端，第5脚为零电流检测信号输入端，第6脚为接地端，第7脚为驱动信号输出端，第8脚为偏置电源接入端。
为了不混淆本发明提出的技术方案，下面仅描述图7的功率因数校正电路中与本发明实施例的零电流检测方案相关的电路部分。
在图6所示的功率因数校正电路中，以变压器2的初级绕组21(下文中称为升压电感L1)的第一端和次级绕组22的第二端为同名端为例，然而，应了解本发明不限于此，本领域技术人员可以在本发明公开内容的基础上，将变压器2的初级绕组21的第一端和次级绕组22的第一端作为同名端，并且相应地改变所述电压转换模块3中的第一电压阈值以及所述电压转换模块3中电压比较器的同向输入端和非同向输入端的连接方式。
下面，将具体描述图6和图7所示的功率因数校正电路的各工作阶段，在上电初期，所述储能电容C2尚未被充电到稳定的输出电压Vo(例如400V)。
升压电感L1的一个充放电周期可以被划分为两个阶段：储能阶段和释能阶段。本发明实施例的零电流检测技术方案不涉及储能阶段到释能阶段的过渡，因此，在下面的描述中也不对储能阶段到释能阶段的过渡进行过多描述，以免混淆本发明实施例的零电流检测技术方案。
在储能阶段中，所述升压电感L1(即，变压器的初级绕组)储能，整流 桥输出的电压对所述升压电感L1充电，充电电流从所述升压电感L1的第一端流到第二端，并且所述升压电感L1的第一端的电压高于第二端的电压。此时，所述变压器的次级绕组的第一端的电压低于第二端的电压，即所述变压器的次级绕组的第一端的电压为负电压，使得所述限流电阻R2的第二端的电压低于所述第一电压阈值，从而所述电压转换模块或所述有源功率因数校正芯片的第7脚输出第一电压，以便继续导通所述控制开关Q1。例如，所述第一电压为高电平，所述控制开关Q1为NMOS管。可替代地，所述第一电压为低电平，所述控制开关Q1为PMOS管。
在释能阶段中，所述升压电感L1(即，变压器的初级绕组)释能，电流仍从所述升压电感L1的第一端流到第二端，然而，与所述储能阶段不同，在释能阶段中所述升压电感L1的第一端的电压低于第二端的电压。此时，所述变压器的次级绕组的第一端的电压高于第二端的电压，即所述变压器的次级绕组的第一端的电压为正电压，使得所述限流电阻R2的第二端的电压高于所述第一电压阈值，从而所述电压转换模块或所述有源功率因数校正芯片的第7脚输出第二电压，以便继续断开所述控制开关Q1。例如，所述第二电压为低电平，所述控制开关Q1为NMOS管。替代地，所述第二电平为高电平，所述控制开关Q2为PMOS管。
在上电初期，由于输出电压尚未上升到预定电压，并且输出电压与输入电压接近，在所述升压电感L1释能时，在没有添加所述偏置电阻R1的情况下，所述C点的电压即为A点的电压，并且可以被表示为：(VC2(t)－Vi(t))/n，其中，VC2(t)表示储能电容C2两端的瞬时电压，Vi(t)表示第一电容C1两端的瞬时电压，n表示所述变压器的初级绕组与次级绕组的匝数比。
如前所述，在上电初期，由于输出电压与输入电压接近，因此VC2(t)－Vi(t)为较小的值，并且进而(VC2(t)－Vi(t))/n更小，因此导致此时C点的电压小于所述第一电压阈值，所述第一电压阈值为大于零的正电压，例如0.7V。相应地，导致错误的电流过零检测，并且所述电压转换模块或所述有源功率因数校正芯片错误地产生将所述控制开关Q1导通的控制信号。
根据本发明实施例，即在添加了所述偏置电阻R1的情况下，C点的电压满足上述公式(6)。即使在上电初期，只要A点的电压大于零，C点的电压就一定大于所述第一电压阈值，从而所述电压转换模块或所述有源功率因数校正芯片可以正确地产生继续保持所述控制开关Q1断开的控制信号。此 后，随着所述升压电感L1继续释能，流过所述升压电感L1的电流逐渐减小直至减小到零，所述A点的电压也降低至零。在所述第一电压阈值等于上述公式(6)中的第一项时，在所述A点的电压降低至零时，所述电压转换模块或所述有源功率因数校正芯片产生过零检测信号，并且将所述控制开关Q1导通。在所述第一电压阈值小于上述公式(6)中的第一项时，在从所述升压电感L1的第一端流到第二端的电流减小至零时，由于所述控制开关Q1中存在寄生电容，所述升压电感L1和所述控制开关Q1开始振荡，直至所述升压电感L1的第一端的电压开始变得高于第二端的电压，相应地，所述A点的电压变为负电压，在所述A点的电压达到预定负电压时，所述C点的电压变得小于所述第一电压阈值，从而所述电压转换模块或所述有源功率因数校正芯片产生过零检测信号，从而将所述控制开关Q1导通。在后者情况下，可以进一步避免所述变压器的初级绕组的电流叠加的情况，能够更有效地避免所述变压器饱和。
在图8中示出了在没有添加所述偏置电阻的情况下，利用示波器采集的在上电初期输出电压与输入电压接近时有源功率因数校正电路中各点的电压波形。在图8中，801指示图7中B点的电压波形，802指示图7中D的电压波形，803表示图7中升压电感L1的电流，804表示图7中C点电压的波形。
如图8所示，按照四个阶段来描述操作。
在第一阶段I中，升压电感L1释能，并且升压电感L1的电流逐渐减小。
在第二阶段II中，储能电容C2独自给负载供电，因此储能电容C2两端的电压(即D点电压)出现跌落，升压电感L1储能。
在第三阶段III中，升压电感L1释能，并且升压电感L1的电流逐渐减小，如前所述，由于在上电初期输出电压和输入电压接近，在升压电感L1的电流尚未真正到零时，所述有源功率因数校正芯片即产生控制所述控制开关Q1导通的控制信号，从而使得升压电感L1的电流出现叠加，即尚未减小到零又开始继续上升。
在第四阶段IV中，储能电容C2独自给负载供电，因此储能电容C2两端的电压(即D点电压)出现跌落，升压电感L1储能。
在图9中示出了在添加了所述偏置电阻R1的情况下，利用示波器采集的在上电初期输出电压与输入电压接近时有源功率因数校正电路中各点的电 压波形。在图9中，901指示图7中B点的电压波形，902指示图7中D的电压波形，903表示图7中升压电感L1的电流，904表示图7中C点电压的波形。
如图9所示，按照两个阶段来描述操作。
在第一阶段I中，升压电感L1释能，并且升压电感L1的电流逐渐减小。
在第二阶段II中，储能电容C2独自给负载供电，因此储能电容C2两端的电压(即D点电压)出现跌落，升压电感L1储能。
如图9所示，由于添加了偏置电阻R1，使得所述C点的电压为：
Figure PCTCN2014094798-appb-000009
在升压电感L1的电流真正降低到零或者甚至反向时，所述有源功率因数校正芯片才产生控制所述控制开关Q1导通的控制信号，从而有效地避免了升压电感L1的电流出现叠加的情况。
根据本发明实施例的过零检测电路以及功率因数校正电路，其通过在过零检测点处添加偏置电压，使得在流过升压电感L1的电流真正下降到零时才产生过零检测信号并相应地导通控制开关Q1，从而保证所述过零检测电路以及功率因数校正电路真正工作在有源功率因数校正的临界导通模式下，避免了有源功率因数校正中流过升压电感的电流连续。
尽管这里已经参考附图描述了示例实施例，应理解上述示例实施例仅仅是示例性的，并且不意图将本发明的范围限制于此。本领域普通技术人员可以在其中进行各种改变和修改，而不偏离本发明的范围和精神。所有这些改变和修改意在被包括在所附权利要求所要求的本发明的范围之内。
本申请要求于2013年12月26日递交的中国发明专利申请第201310730851.7号以及于2013年12月26日递交的中国实用新型专利第201320869463.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种过零检测电路，包括：
    变压器，其包括初级绕组和次级绕组，所述次级绕组的第二端接地；
    限流电阻，其第一端与所述次级绕组的第一端连接；
    电压转换模块，其输入端与所述限流电阻的第二端连接；以及
    偏置电阻，其第一端与所述限流电阻的第二端连接，其第二端连接偏置电压源；
    其中，在所述限流电阻的第二端的电压低于第一电压阈值时，所述电压转换模块输出第一电压；在所述限流电阻的第二端的电压高于所述第一电压阈值时，所述电压转换模块输出第二电压。
  2. 如权利要求1所述的过零检测电路，其中，所述初级绕组具有第一端和第二端，所述初级绕组的第一端与所述次级绕组的第二端为同名端。
  3. 如权利要求1或2所述的过零检测电路，其中，所述初级绕组在充电时其第一端的电压高于其第二端的电压，并且在放电时其第一端的电压低于其第二端的电压。
  4. 如权利要求1-3中的任一个所述的过零检测电路，其中，所述第一电压指示所述初级绕组的第一端的电压高于所述初级绕组的第二端的电压，所述第二电压指示所述初级绕组的第一端的电压低于所述初级绕组的第二端的电压。
  5. 如权利要求1-4中的任一个所述的过零检测电路，其中，所述限流电阻的第二端的电压VC满足：
    Figure PCTCN2014094798-appb-100001
    其中，VCC为所述偏置电压源提供的偏置电压，R1为所述偏置电阻的电阻值，R2为所述限流电阻的电阻值，VA为所述次级绕组的第一端的电压。
  6. 如权利要求1-5中的任一个所述的过零检测电路，其中，所述第一电压阈值为小于或等于
    Figure PCTCN2014094798-appb-100002
    的正电压阈值。
  7. 如权利要求1-6中的任一个所述的过零检测电路，其中，所述电压转换模块包括电压比较器，
    所述电压比较器的同向输入端连接所述限流电阻的第二端，所述电压比 较器的非同向输入端接收所述第一电压阈值，所述第一电压为低电平，所述第二电压为高电平；或者
    所述电压比较器的非同向输入端连接所述限流电阻的第二端，所述电压比较器的同向输入端接收所述第一电压阈值，所述第一电压为高电平，所述第二电压为低电平。
  8. 一种功率因数校正电路，包括：
    变压器，其包括初级绕组和次级绕组，所述次级绕组的第二端接地；
    限流电阻，其第一端与所述次级绕组的第一端连接；
    电压转换模块，其输入端与所述限流电阻的第二端连接；
    控制开关，其第一端与所述电压转换模块的输出端连接，其第二端与所述初级绕组的第二端连接，其第三端接地；以及
    偏置电阻，其第一端与所述限流电阻的第二端连接，其第二端连接偏置电压源；
    其中，在所述限流电阻的第二端的电压低于第一电压阈值时，所述电压转换模块的输出端输出第一电压，以导通所述控制开关；在所述限流电阻的第二端的电压高于所述第一电压阈值时，所述电压转换模块的输出端输出第二电压，以断开所述控制开关。
  9. 如权利要求8所述的功率因数校正电路，其中，所述初级绕组具有第一端和第二端，所述初级绕组的第一端与所述次级绕组的第二端为同名端。
  10. 如权利要求8或9所述的功率因数校正电路，其中，所述初级绕组在充电时其第一端的电压高于其第二端的电压，并且在放电时其第一端的电压低于其第二端的电压。
  11. 如权利要求8-10中的任一个所述的功率因数校正电路，其中，所述第一电压指示所述初级绕组的第一端的电压高于所述初级绕组的第二端的电压，所述第二电压指示所述初级绕组的第一端的电压低于所述初级绕组的第二端的电压。
  12. 如权利要求8-11中的任一个所述的功率因数校正电路，其中，所述限流电阻的第二端的电压VC满足：
    Figure PCTCN2014094798-appb-100003
    其中，VCC为所述偏置电压源提供的偏置电压，R1为所述偏置电阻的 电阻值，R2为所述限流电阻的电阻值，VA为所述次级绕组的第一端的电压。
  13. 如权利要求8-12中的任一个所述的功率因数校正电路，其中，所述第一电压阈值为小于或等于
    Figure PCTCN2014094798-appb-100004
    的正电压阈值。
  14. 如权利要求8-13中的任一个所述的功率因数校正电路，其中，所述电压转换模块包括电压比较器，
    所述电压比较器的同向输入端连接所述限流电阻的第二端，所述电压比较器的非同向输入端接收所述第一电压阈值，所述第一电压为低电平，所述第二电压为高电平，所述控制开关为PMOS管；或者
    所述电压比较器的非同向输入端连接所述限流电阻的第二端，所述电压比较器的同向输入端接收所述第一电压阈值，所述第一电压为高电平，所述第二电压为低电平，所述控制开关为NMOS管。
  15. 如权利要求8-14中的任一个所述的功率因数校正电路，其中，所述电压转换模块为操作于临界导通模式的并且使用峰值电流控制方式的有源功率因数校正集成芯片。
PCT/CN2014/094798 2013-12-26 2014-12-24 过零检测电路及功率因数校正电路 WO2015096732A1 (zh)

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