WO2015096209A1 - 一种内嵌式触控阵列基板结构 - Google Patents

一种内嵌式触控阵列基板结构 Download PDF

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Publication number
WO2015096209A1
WO2015096209A1 PCT/CN2014/070327 CN2014070327W WO2015096209A1 WO 2015096209 A1 WO2015096209 A1 WO 2015096209A1 CN 2014070327 W CN2014070327 W CN 2014070327W WO 2015096209 A1 WO2015096209 A1 WO 2015096209A1
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Prior art keywords
lines
gate scan
line
gate
array substrate
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English (en)
French (fr)
Inventor
徐向阳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/240,474 priority Critical patent/US9367163B2/en
Publication of WO2015096209A1 publication Critical patent/WO2015096209A1/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads

Definitions

  • the present invention relates to the field of image display, and in particular to an in-cell touch array substrate.
  • LCD liquid crystal display
  • Touching the LCD screen is one of the important carriers for integrating the input and output terminals.
  • Touching the LCD screen is one of the important carriers for integrating the input and output terminals.
  • the demand for touch-screen LCDs has surged.
  • the development of touch technology has low cost, high yield, large size, high reliability and so on.
  • built-in touch structures such as On-Cell and In-Cell have been developed in terms of structural technology.
  • the In-Cdl structure has high integration and low pass rate, and the overall thickness of the touch device is thin and light.
  • 4 is a circuit structure of a conventional In-Cdl touch array substrate panel, comprising a plurality of staggered gate scan lines 91 for display functions, data lines 92, scan drivers 93 connected to the gate scan lines 91, and The data driver 94 is connected to the gate scan line 92.
  • the data driver 94 and the scan driver 93 are respectively packaged on the top and side of the in-cell touch panel substrate, so that the frameless structure at both ends of the liquid crystal display cannot be realized.
  • the technical problem to be solved by the present invention is to provide an in-cell touch array substrate structure, which can realize a narrow frame structure at both ends of the in-cell touch array substrate, so as to have a more relaxed visual experience.
  • the present invention provides an in-cell touch array substrate structure, including: staggered data lines and horizontal gate scan lines; and adjacent horizontal gate scan lines and data, respectively a pixel switch electrically connected to the pixel; a pixel electrode electrically connected to the pixel switch; a vertical gate scan line disposed between the two adjacent data lines and intersecting the lateral gate scan line, wherein: the vertical gate scan line is scanned between the horizontal gate and the horizontal gate A via is disposed at at least one intersection of the lines, and the vertical gate scan line is electrically connected to the lateral gate scan line through the via; the horizontal gate scan line includes parallel adjacent first gate scan lines and second gate scan lines, adjacent The spacing between the two lateral gate scan lines is much larger than the spacing between the first gate scan line and the second gate scan line.
  • the pixel switch and the pixel electrode electrically connected to the first gate scan line and the pixel switch and the pixel electrode electrically connected to the second gate scan line are respectively disposed on both sides of the data line.
  • a first insulating layer is laid around the lateral gate scanning line, and the via hole is opened on the first insulating layer.
  • a second insulating layer is laid on the outer circumference of the vertical gate scanning line.
  • the vertical gate scan line and the data line are alternately spaced and arranged in parallel with each other to make the gate scan line and the data line have the same driving direction.
  • an in-cell touch array substrate structure comprising: staggered data lines and horizontal gate scan lines; and adjacent horizontal gate scans respectively a pixel switch electrically connected to the line and the data line; a pixel electrode electrically connected to the pixel switch; a vertical gate scan line disposed between the two adjacent data lines and intersecting the horizontal gate scan line, wherein: the vertical gate scan line is in A via is provided at at least one intersection of the lateral gate scan lines, and the vertical gate scan line is electrically connected to the lateral gate scan line through the via.
  • the vertical gate scan line and the data line are alternately spaced and arranged in parallel with each other to make the gate scan line and the data line have the same driving direction.
  • the horizontal gate scan line includes parallel adjacent first gate scan lines and second gate scan lines, and a spacing between adjacent two lateral gate scan lines is much larger than between the first gate scan line and the second gate scan line Pitch.
  • the pixel switch and the pixel electrode electrically connected to the first gate scan line and the pixel switch and the pixel electrode electrically connected to the second gate scan line are respectively disposed on both sides of the data line.
  • a first insulating layer is laid around the lateral gate scanning line, and the via hole is opened on the first insulating layer.
  • a second insulating layer is laid on the outer circumference of the vertical gate scanning line.
  • the method further includes: a data driver connected to the data line and a scan driver connected to the vertical gate scan line, wherein: the data driver and the scan driver package the phase of the in-cell touch array substrate On both sides.
  • the via hole is made by the GI mask process.
  • the pixel switch is a thin film field effect transistor TFT.
  • an in-cell touch array substrate structure comprising: staggered data lines and gate scan lines; and adjacent gate scan lines And a pixel switch electrically connected to the data line; a pixel electrode electrically connected to the pixel switch; and a data driver connected to the data line and a scan driver connected to the gate scan line, wherein: the data driver and the scan driver package are in-cell touch The opposite sides of the array substrate.
  • the in-cell touch array substrate structure provided by the present invention has a vertical gate scan line intersecting a horizontal gate scan line between two adjacent data lines, the vertical gate scan line intersecting at least one of the horizontal gate scan lines A via hole is arranged at the point, and the vertical gate scan line is electrically connected to the horizontal gate scan line through the via hole, so that the gate scan line and the data line have the same driving direction, and the in-cell touch is realized under the condition that the cell package limit is satisfied.
  • the narrow bezel structure of the array substrate provides a more relaxed visual experience.
  • FIG. 1 is a schematic structural view of an in-cell touch array substrate according to an embodiment of the present invention.
  • FIG. 2 is a partial structural schematic view of an in-cell touch array substrate according to an embodiment of the invention.
  • FIG. 3 is a cross-sectional structural view of the in-cell touch array substrate of the embodiment of the present invention as shown in FIG. 2A.
  • FIG. 4 is a schematic structural view of a conventional in-cell touch array substrate.
  • FIG. 2 it is a first embodiment of an in-cell touch array substrate structure according to the present invention, which includes:
  • a pixel switch 3 electrically connected to the adjacent gate scan line 2 and the data line 1, respectively; a pixel electrode 4 electrically connected to the pixel switch 3;
  • the gate scan line 2 and the data line 1 of the embodiment have the same driving direction, so that the data driver 5 and the scan driver 6 can be packaged on the upper and lower sides of the in-cell touch array substrate as shown in FIG.
  • the touch array substrate has a narrow frame structure or a frameless structure on the left and right sides as shown in FIG. 1, so that the user has a more relaxed visual experience.
  • the gate scan line 2 of the present embodiment includes: a lateral gate scan line 21 and a vertical gate scan line 22 disposed between the two adjacent data lines 1 and intersecting the horizontal gate scan line 21.
  • the lateral gate scan line 21 includes parallel adjacent first gate scan lines 211 and second gate scan lines 212, and the spacing T between adjacent two lateral gate scan lines 21 is much larger than the first gate scan lines 211 and The pitch t between the two gate scan lines 212, that is, the pitch t of the first gate scan line 211 and the second first gate scan line 212 is small, and the pitch T of the adjacent two lateral gate scan lines is large to provide sufficient The wiring space.
  • the vertical gate scan lines 22 and the data lines 1 are alternately spaced and arranged in parallel with each other.
  • the odd columns shown in FIG. 2 are the data lines 1 and the even columns are the vertical gate scan lines 22.
  • FIG. 2 it is a partial structural diagram of FIG. 1 for explaining the connection relationship between the pixel unit (including the pixel switch 3 and the pixel electrode 4) of the embodiment and the horizontal gate scanning line 21 and the data line 1.
  • the first gate scan line 211 and the second gate scan line 212 are interleaved with the data line 1
  • the "well" font structure wherein the first gate scan line 211 is located above the second gate scan line 212.
  • the first pixel switch 31 is electrically connected to the first gate scan line 211 and the data line 1, respectively, and the first pixel electrode 41 is electrically connected to the first pixel switch 31; the second pixel switch 32 is electrically connected to the second gate scan line 212, respectively.
  • the second pixel electrode 42 is electrically connected to the second pixel switch 32. That is, the pixel switch 31 and the pixel electrode 41 electrically connected to the first gate scan line 211, and the pixel switch 32 and the pixel electrode 42 electrically connected to the second gate scan line 212 are respectively disposed on the data line 1 side.
  • the pixel switches 31 and 32 are respectively thin film field effect transistors (TFTs).
  • the vertical gate scan line 22 is provided with a via hole 7 at its intersection with at least one of the lateral gate scan lines 21 (intersection point a, intersection point b, intersection point c, intersection point d) as shown in FIG.
  • the vertical gate scan line 22 is electrically connected to the lateral gate scan line 21 through the via 7.
  • the gate scan line 21 includes parallel adjacent first gate scan lines 211 and second gate scan lines 212, and at least one vertical gate scan line 22 may be in contact with the first gate scan line 211 or the second gate scan line 212 therein.
  • the intersection of the contacts is formed by a mask GI mask gate insulation such that the vertical gate scan line 22 is electrically connected to the first gate scan line 211 or the second gate scan line 212.
  • the pixel switch 31 and the pixel electrode 41, and the pixel switch 32 and the pixel electrode 42 are electrically connected to the at least one vertical gate scan line 22 through the first gate scan line 211 and the second gate scan line 212, respectively, and
  • the gate scan line 22 and the data line 1 are alternately spaced and arranged in parallel with each other such that the gate scan line 2 and the data line 1 have the same driving direction.
  • a photomask can be added to the GI mark (GI, Gate Insulation) to form a via hole 7 on the basis of the above-mentioned five mask process, so that the vertical gate scan line 22 and the lateral gate scan line 21 are electrically connected.
  • the in-cell touch array substrate structure of the embodiment further includes: a data driver 5 connected to the data line 1 and a scan driver 6 connected to the vertical gate scan line 22. Since the gate scan line 2 and the data line 1 have the same driving direction, the problem of the peripheral traces at both ends of the gate drive line is eliminated, and the data driver 5 and the scan driver 6 can be packaged in the in-cell touch array substrate.
  • the upper and lower sides of the upper and lower sides of FIG. 1 realize a narrow frame structure of the in-cell touch array substrate.
  • a first insulating layer 81 is disposed around the lateral gate scan line 21, and the via hole 7 is formed on the first insulating layer 81, and the vertical gate scan line 22 and the first gate scan line 211 or the second The gate scan lines 212 are electrically connected, and the second insulating layer 82 is laid on the outer circumference of the vertical gate scan lines 22.
  • the first insulating layer 81 and the second insulating layer 82 function as insulation protection, and are made of silicon nitride material.
  • the embedded touch array substrate structure embodying the present invention has the following beneficial effects: a vertical gate scan line intersecting the horizontal gate scan line is disposed between two adjacent data lines, and the vertical gate scan line is in the same direction as the horizontal gate scan line A via hole is disposed at at least one intersection point, and the vertical gate scan line is electrically connected to the lateral gate scan line through the via hole, so that the gate scan line and the data line have the same driving direction, and the inner package limit is satisfied,
  • the narrow frame structure of the embedded touch array substrate provides a more relaxed visual experience.

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  • Crystallography & Structural Chemistry (AREA)
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Abstract

一种内嵌式触控阵列基板结构包括交错排列的数据线（1）和横向栅扫描线（21），分别与相邻的横向栅扫描线（21）及数据线（1）电连接的像素开关（3），与像素开关（3）电连接的像素电极（4），设置在两相邻数据线（1）之间且与横向栅扫描线（21）相交的纵向栅扫描线（22），纵向栅扫描线（22）在其与横向栅扫描线（21）的至少一个相交点（a，b，c，d）处设置过孔（7），纵向栅扫描线（22）通过过孔（7）与横向栅扫描线（21）电连接。由于纵向栅扫描线（22）通过过孔（7）与横向栅扫描线（21）电连接，使栅扫描线（2）和数据线（1）具有相同的驱动方向，实现了内嵌式触控阵列基板的窄边框结构。

Description

一种内嵌式触控阵列羞 结构
本申请要求于 2013 年 12 月 26 日提交中国专利局、 申请号为 201310730277.5、 发明名称为 "一种内嵌式触控阵列基板结构" 的中国专利 申请的优先权， 上述专利的全部内容通过引用结合在本申请中。 技术领域
本发明涉及图像显示领域， 尤其涉及一种内嵌式触控阵列基板。
背景技术
近来，液晶显示器（Liquid Crystal Display, LCD )技术有了飞速的发展， 从屏幕的尺寸到显示的质量都取得了极大的进步， LCD具有体积小、功耗低、 无辐射等特点， 现已占据了平面显示领域的主导地位。
触摸液晶显示屏是将输入、 输出终端一体化的重要载体之一。 近年来， 随着小巧、 轻盈的手持设备等一系列产品的问世， 市场对触摸液晶显示屏的 需求激增。
触控技术的发展方向有低成本、 高良率、 大尺寸、 高可靠性等等。 为了 达到此目标， 在结构技术上， 发展了外挂式（On-Cell )和内嵌式（ In- Cell ) 等内置触控结构。 In-Cdl结构的集成度高、 合格率低， 触控装置的整体厚度 薄， 重量轻。 图 4所示为现有 In-Cdl触控阵列基板面板电路结构， 包括多 条交错排列的用作显示功能的栅扫描线 91、 数据线 92、 与栅扫描线 91相连 的扫描驱动器 93和与栅扫描线 92相连的数据驱动器 94,其中， 由于数据驱 动器 94和扫描驱动器 93分别封装在内嵌式触控阵列基板的顶端和侧边， 无 法实现液晶显示器两端的无边框结构。
发明内容
本发明所要解决的技术问题在于， 提供一种内嵌式触控阵列基板结构， 可实现内嵌式触控阵列基板两端的窄边框结构， 使具有更宽松的视觉体验。
为了解决上述技术问题， 本发明提供一种内嵌式触控阵列基板结构， 包 括： 交错排列的数据线和横向栅扫描线； 分别与相邻的横向栅扫描线及数据 线电连接的像素开关； 与像素开关电连接的像素电极； 设置在两相邻数据线 之间且与横向栅扫描线相交的纵向栅扫描线， 其中： 纵向栅扫描线在其与横 向栅扫描线的至少一个相交点处设置过孔，纵向栅扫描线通过过孔与横向栅 扫描线电连接； 横向栅扫描线包括平行相邻的第一栅扫描线和第二栅扫描 线，相邻的两横向栅扫描线之间的间距远大于第一栅扫描线和第二栅扫描线 之间的间距。
其中， 电连接在第一栅扫描线上的像素开关和像素电极， 与电连接在第 二栅扫描线上的像素开关和像素电极分别设置在数据线的两侧。
其中，横向栅扫描线的四周铺设第一绝缘层，过孔开设在第一绝缘层上。 其中， 纵向栅扫描线的外周铺设第二绝缘层。
其中， 纵向栅扫描线与数据线交替间隔且相互平行排列， 用以使栅扫描 线和数据线具有相同的驱动方向。
为解决上述技术问题， 本发明提供的另一种技术方案是： 一种内嵌式触 控阵列基板结构， 其包括： 交错排列的数据线和横向栅扫描线； 分别与相邻 的横向栅扫描线及数据线电连接的像素开关； 与像素开关电连接的像素电 极；设置在两相邻数据线之间且与横向栅扫描线相交的纵向栅扫描线，其中： 纵向栅扫描线在其与横向栅扫描线的至少一个相交点处设置过孔， 纵向栅扫 描线通过过孔与横向栅扫描线电连接。
其中， 纵向栅扫描线与数据线交替间隔且相互平行排列， 用以使栅扫描 线和数据线具有相同的驱动方向。
其中， 横向栅扫描线包括平行相邻的第一栅扫描线和第二栅扫描线， 相 邻的两横向栅扫描线之间的间距远大于第一栅扫描线和第二栅扫描线之间 的间距。
其中， 电连接在第一栅扫描线上的像素开关和像素电极， 与电连接在第 二栅扫描线上的像素开关和像素电极分别设置在数据线的两侧。
其中，横向栅扫描线的四周铺设第一绝缘层，过孔开设在第一绝缘层上。 其中， 纵向栅扫描线的外周铺设第二绝缘层。
其中， 还包括： 与数据线相连的数据驱动器和与纵向栅扫描线相连的扫 描驱动器， 其中： 数据驱动器和扫描驱动器封装在内嵌式触控阵列基板的相 对两侧。
其中， 过孔为 GI光罩工艺制得。
其中， 像素开关是薄膜场效应晶体管 TFT。
为解决上述技术问题， 本发明还提供了另一种技术方案是： 一种内嵌式 触控阵列基板结构， 其包括： 交错排列的数据线和栅扫描线； 分别与相邻的 栅扫描线及数据线电连接的像素开关； 与像素开关电连接的像素电极； 以及 与数据线相连的数据驱动器和与栅扫描线相连的扫描驱动器， 其中： 数据驱 动器和扫描驱动器封装在内嵌式触控阵列基板的相对两侧。
本发明所提供的内嵌式触控阵列基板结构，在两相邻数据线之间设置与 横向栅扫描线相交的纵向栅扫描线，纵向栅扫描线在其与横向栅扫描线的至 少一个相交点处设置过孔， 纵向栅扫描线通过过孔与横向栅扫描线电连接， 使栅扫描线和数据线具有相同的驱动方向， 在满足 cell封装极限的条件下， 实现了内嵌式触控阵列基板的窄边框结构， 使具有更宽松的视觉体验。
附图说明
图 1是本发明实施例内嵌式触控阵列基板的结构示意图。
图 2是本发明实施例内嵌式触控阵列基板的局部结构示意图。
图 3是本发明实施例内嵌式触控阵列基板如图 2所示 A-A的截面结构示 意图。
图 4是现有内嵌式触控阵列基板的结构示意图。
具体实施方式
以下各实施例的说明是参考附图， 用以示例本发明可以用以实施的特定 实施例。 本发明所提到的方向和位置用语， 例如「上」、 「中」、 「下」、 「前」、 「后」、 「左」、 「右」、 「内」、 「夕卜」、 「侧面」等， 仅是参考附加图式的方向和 位置。 因此， 使用的方向和位置用语是用以说明及理解本发明， 而非用以限 制本发明。
请参照图 2所示， 为本发明一种内嵌式触控阵列基板结构的实施例一， 其包括：
交错排列的数据线 1和栅扫描线 2;
分别与相邻的栅扫描线 2及数据线 1电连接的像素开关 3; 与像素开关 3电连接的像素电极 4; 以及
与数据线 1相连的数据驱动器 5和与栅扫描线 2相连的扫描驱动器 6, 其中：数据驱动器 5和扫描驱动器 6封装在内嵌式触控阵列基板的相对两侧。
本实施例的栅扫描线 2和数据线 1具有相同的驱动方向，使得数据驱动 器 5和扫描驱动器 6能够封装在内嵌式触控阵列基板如图 1所示的上下两侧， 可以实现内嵌式触控阵列基板在如图 1所示左右两侧的窄边框结构或无边框 结构， 使用户具有更宽松的视觉体验。
具体的， 本实施例的栅扫描线 2包括： 横向栅扫描线 21和设置在两相 邻数据线 1之间且与横向栅扫描线 21相交的纵向栅扫描线 22。 其中： 横向 栅扫描线 21包括平行相邻的第一栅扫描线 211和第二栅扫描线 212,相邻的 两横向栅扫描线 21之间的间距 T远大于第一栅扫描线 211和第二栅扫描线 212之间的间距 t, 即第一栅扫描线 211和第二第一栅扫描线 212的间距 t较 小， 而相邻两横向栅扫描线的间距 T较大， 以便提供足够的走线空间。
本实施例中， 纵向栅扫描线 22与数据线 1交替间隔且相互平行排列， 如图 2所示的奇数列为数据线 1 , 偶数列为纵向栅扫描线 22。
再请参照图 2所示， 为图 1的局部结构示意图， 用以说明本实施例的像 素单元（包括像素开关 3和像素电极 4 )与横向栅扫描线 21和数据线 1的连 接关系。 第一栅扫描线 211和第二栅扫描线 212, 与数据线 1彼此交错形成
"井" 字形结构， 其中， 第一栅扫描线 211位于第二栅扫描线 212的上方。 第一像素开关 31分别电连接在第一栅扫描线 211和数据线 1上， 第一像素 电极 41与第一像素开关 31电连接； 第二像素开关 32分别电连接在第二栅 扫描线 212和数据线 1上， 第二像素电极 42与第二像素开关 32电连接。 也 就是说， 电连接在第一栅扫描线 211上的像素开关 31和像素电极 41 , 与电 连接在第二栅扫描线 212上的像素开关 32和像素电极 42分别设置在数据线 1的两侧。
本实施例中， 像素开关 31 , 32分别为薄膜场效应晶体管 （TFT )。
进一步的， 纵向栅扫描线 22在其与横向栅扫描线 21的至少一个相交点 处设置过孔 7 (如图 1所示的相交点 a, 相交点 b, 相交点 c, 相交点 d ), 纵 向栅扫描线 22通过过孔 7与横向栅扫描线 21电连接。 本实施例中， 由于横 向栅扫描线 21包括平行相邻的第一栅扫描线 211和第二栅扫描线 212,至少 一条纵向栅扫描线 22可与其中的第一栅扫描线 211或第二栅扫描线 212在 两者的相交处通过光罩 GI mask光罩工艺 （ Gate Insulation )形成过孔 7 , 使 得纵向栅扫描线 22与第一栅扫描线 211或第二栅扫描线 212电连接。 也就 是说， 像素开关 31和像素电极 41 , 以及像素开关 32和像素电极 42分别通 过第一栅扫描线 211和第二栅扫描线 212电连接在至少一条纵向栅扫描线 22 上， 又由于纵向栅扫描线 22和数据线 1交替间隔且相互平行排列， 使得栅 扫描线 2和数据线 1具有相同的驱动方向。
具体实施时，相对于传统得内嵌式触控阵列基板结构的 5光罩工艺 [Gate patterning、 Active(a-Si) patterning、 S/D patterning、 Pas sivation( PVX patterning、 Pixel ITO patterning]而言， 本实施例中可在上述 5光罩工艺的基础上增加一 道光罩为 GI mark ( GI, Gate Insulation )形成过孔 7, 从而达到使纵向栅扫 描线 22与横向栅扫描线 21电连接，统一栅扫描线 2和数据线 1驱动方向的 目的。
进一步的， 本实施例内嵌式触控阵列基板结构还包括： 与数据线 1相连 的数据驱动器 5和与纵向栅扫描线 22相连的扫描驱动器 6。 由于栅扫描线 2 和数据线 1具有相同的驱动方向，从而消除了栅极驱动线两端外围走线的问 题， 进而可将数据驱动器 5和扫描驱动器 6封装在内嵌式触控阵列基板如图 1所示的上下相对两侧， 实现内嵌式触控阵列基板的窄边框结构。
请结合参见图 4所示， 横向栅扫描线 21的四周铺设第一绝缘层 81 , 过 孔 7开设在第一绝缘层 81上， 将纵向栅扫描线 22与第一栅扫描线 211或第 二栅扫描线 212电连接，纵向栅扫描线 22的外周铺设第二绝缘层 82。其中： 第一绝缘层 81和第二绝缘层 82起到绝缘保护的作用，使用氮化硅材料制成。
实施本发明的内嵌式触控阵列基板结构， 具有如下有益效果： 在两相邻 数据线之间设置与横向栅扫描线相交的纵向栅扫描线， 纵向栅扫描线在其与 横向栅扫描线的至少一个相交点处设置过孔， 纵向栅扫描线通过过孔与横向 栅扫描线电连接， 使栅扫描线和数据线具有相同的驱动方向， 在满足 cell封 装极限的条件下， 实现了内嵌式触控阵列基板的窄边框结构， 使具有更宽松 的视觉体验。

Claims

权 利 要 求
1、 一种内嵌式触控阵列基板结构， 其特征在于， 包括：
交错排列的数据线和横向栅扫描线；
分别与相邻的所述横向栅扫描线及所述数据线电连接的像素开关； 与所述像素开关电连接的像素电极；
设置在所述两相邻数据线之间且与所述横向栅扫描线相交的纵向栅扫描 线， 其中： 所述纵向栅扫描线在其与所述横向栅扫描线的至少一个相交点处设 置过孔， 所述纵向栅扫描线通过所述过孔与所述横向栅扫描线电连接；
所述横向栅扫描线包括平行相邻的第一栅扫描线和第二栅扫描线， 相邻的 所述两横向栅扫描线之间的间距远大于所述第一栅扫描线和第二栅扫描线之间 的间距。
2、 如权利要求 1所述的内嵌式触控阵列基板结构， 其特征在于， 电连接在 所述第一栅扫描线上的像素开关和像素电极， 与电连接在所述第二栅扫描线上 的像素开关和像素电极分别设置在所述数据线的两侧。
3、 如权利要求 2所述的内嵌式触控阵列基板结构， 其特征在于， 所述横向 栅扫描线的四周铺设第一绝缘层， 所述过孔开设在所述第一绝缘层上。
4、 如权利要求 3所述的内嵌式触控阵列基板结构， 其特征在于， 所述纵向 栅扫描线的外周铺设第二绝缘层。
5、 如权利要求 4所述的内嵌式触控阵列基板结构， 其特征在于， 所述纵向 栅扫描线与所述数据线交替间隔且相互平行排列， 用以使栅扫描线和数据线具 有相同的驱动方向。
6、 一种内嵌式触控阵列基板结构， 其特征在于， 包括：
交错排列的数据线和横向栅扫描线；
分别与相邻的所述横向栅扫描线及所述数据线电连接的像素开关； 与所述像素开关电连接的像素电极；
设置在所述两相邻数据线之间且与所述横向栅扫描线相交的纵向栅扫描 线， 其中： 所述纵向栅扫描线在其与所述横向栅扫描线的至少一个相交点处设 置过孔， 所述纵向栅扫描线通过所述过孔与所述横向栅扫描线电连接。
7、 如权利要求 6所述的内嵌式触控阵列基板结构， 其特征在于， 所述纵向 栅扫描线与所述数据线交替间隔且相互平行排列， 用以使栅扫描线和数据线具 有相同的驱动方向。
8、 如权利要求 7所述的内嵌式触控阵列基板结构， 其特征在于， 所述横向 栅扫描线包括平行相邻的第一栅扫描线和第二栅扫描线， 相邻的所述两横向栅 扫描线之间的间距远大于所述第一栅扫描线和第二栅扫描线之间的间距。
9、 如权利要求 8所述的内嵌式触控阵列基板结构， 其特征在于， 电连接在 所述第一栅扫描线上的像素开关和像素电极， 与电连接在所述第二栅扫描线上 的像素开关和像素电极分别设置在所述数据线的两侧。
10、 如权利要求 7所述的内嵌式触控阵列基板结构， 其特征在于， 所述横 向栅扫描线的四周铺设第一绝缘层， 所述过孔开设在所述第一绝缘层上。
11、 如权利要求 7所述的内嵌式触控阵列基板结构， 其特征在于， 所述纵 向栅扫描线的外周铺设第二绝缘层。
12、 如权利要求 6所述的内嵌式触控阵列基板结构， 其特征在于， 还包括： 与所述数据线相连的数据驱动器和与所述纵向栅扫描线相连的扫描驱动器， 其 中： 所述数据驱动器和所述扫描驱动器封装在所述内嵌式触控阵列基板的相对 两侧。
13、 如权利要求 6所述的内嵌式触控阵列基板结构， 其特征在于， 所述过 孔为 GI光罩工艺制得。
14、 如权利要求 6所述的内嵌式触控阵列基板结构， 其特征在于， 所述像 素开关是薄膜场效应晶体管 TFT。
15、 一种内嵌式触控阵列基板结构， 其特征在于， 包括：
交错排列的数据线和栅扫描线；
分别与相邻的所述栅扫描线及所述数据线电连接的像素开关；
与所述像素开关电连接的像素电极； 以及
与所述数据线相连的数据驱动器和与所述栅扫描线相连的扫描驱动器， 其 中： 所述数据驱动器和所述扫描驱动器封装在所述内嵌式触控阵列基板的相对 两侧。
PCT/CN2014/070327 2013-12-26 2014-01-08 一种内嵌式触控阵列基板结构 Ceased WO2015096209A1 (zh)

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