WO2015096041A1 - 一种多时钟域的时钟同步方法、线卡及以太网设备 - Google Patents

一种多时钟域的时钟同步方法、线卡及以太网设备 Download PDF

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Publication number
WO2015096041A1
WO2015096041A1 PCT/CN2013/090352 CN2013090352W WO2015096041A1 WO 2015096041 A1 WO2015096041 A1 WO 2015096041A1 CN 2013090352 W CN2013090352 W CN 2013090352W WO 2015096041 A1 WO2015096041 A1 WO 2015096041A1
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WO
WIPO (PCT)
Prior art keywords
line card
clock
interfaces
uplink
interface
Prior art date
Application number
PCT/CN2013/090352
Other languages
English (en)
French (fr)
Inventor
刘凡
林连魁
吕昕
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP13900079.8A priority Critical patent/EP3076572B1/en
Priority to CN201380002722.4A priority patent/CN103959688B/zh
Priority to PCT/CN2013/090352 priority patent/WO2015096041A1/zh
Publication of WO2015096041A1 publication Critical patent/WO2015096041A1/zh
Priority to US15/190,881 priority patent/US20160308633A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697—Synchronisation in a packet node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H04L12/4641—Virtual LANs, VLANs, e.g. virtual private networks [VPN]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a clock synchronization method for multiple clock domains, a line card, and an Ethernet device. Background technique
  • Ethernet will gradually replace PDH (Plesiochronous Digital Hierarchy; bad plesiochronous digital line 1 J) in a telecommunications service provider network ⁇ SONET (Synchronous Optical Network; Synchronous Optical Network) / SDH (Synchronous Digital Hierarchy; synchronous digital system) transmission network.
  • PDH Plesiochronous Digital Hierarchy; bad plesiochronous digital line 1 J
  • SONET Synchronous Optical Network
  • SDH Synchronous Digital Hierarchy
  • FIG. 1 is a typical Ethernet clock synchronization scheme.
  • the double-directional arrow solid line represents the path of data packet exchange between each line card through the switch module. Then, each line card recovers the clock from the received line, and then reports the line recovery clock to the clock board.
  • the clock board selects one of them as the synchronous reference source of the device according to the configuration, and the synchronized clock after the phase-locked processing is sent to each line card. As the reference clock sent by the line card, the synchronous clock is transmitted.
  • the embodiment of the invention provides a multi-clock domain clock synchronization method, a line card and an Ethernet device, which are used to solve the problem that the clock synchronization mechanism in the prior art cannot implement a multi-clock domain clock.
  • the first aspect of the present application provides a clock synchronization method for multiple clock domains, including:
  • the sending line card obtains M clock frequency differences of the M uplink interfaces corresponding to the M downlink interfaces of the sending line card determined by the receiving line card; wherein, the M uplink interfaces are uplinks on the receiving line card Interface, M is a positive integer;
  • the transmission line card is adjusted according to the correspondence between the M downlink interfaces and the M uplink interfaces, and each of the M clock frequency differences of the M uplink interfaces is respectively adjusted and corresponding to each clock frequency difference.
  • the send clock of the interface is adjusted according to the correspondence between the M downlink interfaces and the M uplink interfaces, and each of the M clock frequency differences of the M uplink interfaces is respectively adjusted and corresponding to each clock frequency difference.
  • the transmitting line card obtains M of the M uplink interfaces that are determined by the receiving line card and corresponding to the M downlink interfaces of the sending line card.
  • the method further includes: the receiving line card recovering the line clocks of the N uplink interfaces of the receiving line card, and obtaining N line recovery clocks, where N is greater than or equal to M; and the receiving line card determines the N The clock recovery frequency of each of the line recovery clocks and the clock of the system clock is obtained, and N clock frequency differences of the N uplink interfaces are obtained; wherein the M clock frequency differences are frequency differences among the N clock frequency differences.
  • the sending line card obtains, by the receiving line card, M downlink interfaces that are determined by the receiving line card and the sending line card Before the M clock frequency differences of the corresponding M uplink interfaces, the method further includes: the receiving line card further determining, according to the correspondence between the uplink interface and the interface of the sending line card, the sending and the sending in the N uplink interfaces M uplink interfaces corresponding to the M downlink interfaces of the line card; the receiving line card sends M clock frequency differences of the M uplink interfaces to the sending line card.
  • the sending line card obtains, by the receiving line card, corresponding to the M downlink interfaces of the sending line card M clock frequency differences of the M uplink interfaces, including: the sending line card receiving N clock frequency differences of the N uplink interfaces sent by the receiving line card; the sending line card is based on the sending line
  • the M uplink interfaces corresponding to the M downlink interfaces are determined by the corresponding relationship between the interface and the uplink interface, and the M line frequency differences are obtained by the sending line card based on the M uplink interfaces.
  • each of the M clock frequency differences using the M lines is separately adjusted with each of the clocks
  • the sending clock of the interface corresponding to the frequency difference includes: the sending line card respectively adjusting a sending clock of each of the M downlink interfaces to a sum of a clock frequency difference corresponding to each interface and a time difference of the system .
  • a second aspect of the present application provides a line card, including:
  • M interfaces M is a positive integer; an interface circuit, configured to recover M uplink interfaces corresponding to the M interfaces, and obtain M line recovery clocks; a frequency difference determining circuit, configured to determine M line recovery clocks respectively a clock frequency difference of the system clock, to obtain M clock frequency differences of the M uplink interfaces; a processor, configured to send the M clock frequency differences to the transmission line card, so that the sending line card is based on the M clock frequency difference adjusts a transmission clock of an interface of the transmission line card; and is further configured to receive M clock frequency differences of M uplink interfaces corresponding to the M interfaces sent by the receiving line card; And adjusting, according to the correspondence between each interface of the transmission line card and the M uplink interfaces, each clock frequency difference of the M clock frequency differences of the M uplink interfaces sent by using the other line cards respectively The transmit clock of the interface corresponding to the frequency difference.
  • the processor is further configured to determine, according to a correspondence between an uplink interface and an interface of the sending line card, that the frequency difference determining circuit is ok; The clock frequency difference of the uplink interface corresponding to the interface of the sending line card is sent to the corresponding sending line card.
  • the processor is further configured to receive N clock frequency differences of the N uplink interfaces sent by the receiving line card, where the N clock frequency differences The M clock frequency difference of the M uplink interfaces corresponding to the M interfaces, where N is a positive integer greater than or equal to M, and is further configured to determine, according to the correspondence between each interface of the sending line card and the uplink interface, M uplink interfaces corresponding to the M interfaces; determining M clock frequency differences of M uplink interfaces corresponding to the M interfaces.
  • the clock adjustment circuit is used Adjusting the transmit clocks of each of the M interfaces to the corresponding interfaces The sum of the clock frequency difference and the system time difference.
  • the frequency difference determining circuit is specifically a counter or a phase locked loop phase detector.
  • the clock adjustment circuit is specifically a phase locked loop discriminator.
  • the M interfaces are specifically Ethernet interfaces.
  • the third aspect of the present application further provides an Ethernet device, including:
  • a clock board configured to generate a system clock, and send the system clock to each of the plurality of line cards
  • each of the plurality of line cards is in accordance with the second aspect or the first possible implementation of the second aspect to any one of the sixth possible implementation manners of the second aspect Line card.
  • the sending line card obtains M clock frequency differences of the M uplink interfaces corresponding to the M downlink interfaces of the sending line card determined by the receiving line card; wherein, the M uplink interfaces are uplinks on the receiving line card.
  • M is a positive integer; the transmission line card is based on the correspondence between each interface of the transmission line card and the M uplink interfaces, and each clock frequency difference of the M clock frequency differences of the M uplink interfaces is respectively adjusted and each clock The transmit clock of the interface corresponding to the frequency difference.
  • the receiving line card first determines the clock frequency difference between each line and the system clock, and then the transmitting line card adjusts the sending clock of each interface according to the clock frequency difference of the corresponding line, so each Interfaces can track different lines, that is, track different clock sources, so clock synchronization in multiple clock domains can be achieved. Further, the solution in the embodiment of the present application recovers the clock from the receiving line card, and recovers the physical layer clock, so the present application The application is processed from the physical layer and has nothing to do with the message, so the performance is better.
  • FIG. 1 is a schematic diagram of a clock synchronization scheme in the prior art
  • FIG. 2 is a functional block diagram of an Ethernet device according to an embodiment of the present invention.
  • FIG. 3 is a flowchart of a clock synchronization method in an embodiment of the present invention.
  • FIG. 4a is a schematic diagram of a correspondence between an uplink interface and a downlink interface according to an embodiment of the present invention
  • FIG. 4b is a schematic diagram showing a correspondence between a line and an interface from a packet switching path according to an embodiment of the present invention
  • FIG. 5 is a functional block diagram of a line card according to an embodiment of the present invention.
  • FIG. 6 is a conceptual diagram showing an example of hardware implementation of a line card in an embodiment of the present invention. detailed description
  • the embodiment of the invention provides a multi-clock domain clock synchronization method, a line card and an Ethernet device, which are used to solve the problem that the clock synchronization mechanism in the prior art cannot implement a multi-clock domain clock.
  • the technical solution in the embodiment of the present application is to solve the above technical problem.
  • the general idea is as follows:
  • the sending line card obtains M clock frequency differences of the M uplink interfaces corresponding to the M downlink interfaces of the sending line card determined by the receiving line card;
  • the M uplink interfaces are the uplink interfaces on the receiving line card, and M is a positive integer;
  • the sending line card is based on the correspondence between each interface of the sending line card and the M uplink interfaces, and uses M clock frequency differences of the M uplink interfaces.
  • Each clock frequency difference in each of the clocks adjusts the transmission clock of the interface corresponding to each clock frequency difference.
  • the receiving line card first determines the clock frequency difference between each line and the system clock, and then the transmitting line card adjusts the sending clock of each interface according to the clock frequency difference of the corresponding line, so each Interfaces can track different lines, that is, track different clock sources, so clock synchronization in multiple clock domains can be achieved.
  • the solution in the embodiment of the present application recovers the clock from the receiving line card, and recovers the physical layer clock. Therefore, the embodiment of the present application processes from the physical layer, and has nothing to do with the message, so the performance is better.
  • FIG. 2 is a functional block diagram of an Ethernet device, which includes: multiple line cards, such as line card 1, line card 2, ... line card N, the number of specific line cards can be based on actual needs Configuration, usually two or more; clock board, used to generate the system clock, and send the system clock to multiple line cards. Multiple line cards and clock boards can be installed on the backplane of the Ethernet device.
  • the Ethernet device can also include a switch module for packet switching.
  • the Ethernet device may specifically be an Ethernet device such as a switch, a router, or an OLT (optical line terminal) that needs to receive and transmit data packets.
  • the clock synchronization method of the multi-clock domain of the Ethernet device is introduced.
  • each line card it can be used as both the receiving line card and the transmitting line card, that is, playing and transmitting roles, when one line
  • the other line card can be used as the transmitting line card with respect to the line card.
  • the other line card can be used as the receiving line card with respect to the line card.
  • the interfaces of some line cards are connected to the uplink, and the interfaces of some line cards are connected to the downlink. According to the configuration, some or all of the uplink interfaces need to recover the interface clock, and calculate the frequency difference. The frequency difference is sent to the downlink interface.
  • the downlink interface uses different uplink interfaces to recover the clock. Which uplink interface is used to recover the clock, the corresponding uplink frequency difference is used to generate the transmission clock. Therefore, in the process of describing the clock synchronization method, each line card is named by role. Please refer to Figure 3, the method includes:
  • Step 101 The sending line card obtains M clock frequency differences of the M uplink interfaces corresponding to the M downlink interfaces of the sending line card determined by the receiving line card; wherein, the M uplink interfaces are uplink interfaces on the receiving line card, M Is a positive integer;
  • Step 102 The sending line card is based on the correspondence between the M downlink interfaces and the M uplink interfaces.
  • the transmission clock of the interface corresponding to each clock frequency difference is respectively adjusted by using each of the M clock frequency differences of the M uplink interfaces.
  • the method further includes: receiving the line card to recover the line clock of the N uplink interfaces of the receiving line card, obtaining N line recovery clocks, N being greater than or equal to M; receiving the line card determining N line recovery clocks The clock frequency difference between the clock and the system clock is respectively obtained, and N clock frequency differences of the N uplink interfaces are obtained; wherein the M clock frequency differences are frequency differences among the N clock frequency differences.
  • the step of the receiving line card recovering the line clocks of the N uplink interfaces of the receiving line card may be performed periodically, or the line clock is restored in real time, and the N uplink interfaces are generally and the receiving line card is N.
  • the interfaces are - corresponding, N uplink interfaces correspond to N lines.
  • the number of actual interfaces of the receiving line card may be greater than the number of uplink interfaces.
  • the N uplink interfaces in step 101 may be uplink interfaces from different line cards, and the number of interfaces on each receiving line card may be The same, or different, the total amount is N.
  • the obtained s line recovery clocks are respectively recorded as Fin_nO/1/2...s, s, s represents the total number of line cards n, and s is a positive integer and Less than or equal to N.
  • the receiving line card determines the clock difference between the N line recovery clocks and the system clock, specifically Said, for example, using a counter to calculate the clock frequency difference between each line recovery clock and the system clock, and then using, for example, a phase-locked loop phase discrimination method; it is also possible to utilize a 3-stage clock phase-locked loop chip currently available on the market, the phase-locked loop chip can Read the frequency offset between the input clock and the system clock, that is, the clock frequency difference.
  • the first method is that the receiving line card determines the clock frequency difference required for the sending line card and then sends it to the sending line card; the second type is that the receiving line card sends all the determined N clock frequency differences to the sending line card. Send the line card to choose the M clock frequency difference that you need.
  • the first method is in the following steps: after the receiving line card determines the clock frequency difference between the N line recovery clocks and the system clock, before the step 101, the method further includes: receiving the line card based on the uplink interface and sending Corresponding relationship of the interface of the line card, determining M uplink interfaces corresponding to the M downlink interfaces of the sending line card in the N uplink interfaces, and then transmitting the M clock frequency differences of the M uplink interfaces to the sending line card
  • the line card then correspondingly, the sending line card performs step 103 to obtain M clock frequency differences of the M uplink interfaces corresponding to the interfaces of the M.
  • the M clock frequency difference is the frequency difference among the N clock frequency differences obtained in step 102, where ⁇ is less than or equal to N and is a positive integer.
  • step 101 specifically includes The sending line card receives the clock frequency difference of the one uplink interface sent by the receiving line card; the sending line card determines the uplink corresponding to the one of the downlink interfaces based on the corresponding relationship between each interface of the sending line card and the uplink interface. Interface; The sending line card is based on one uplink interface and obtains one clock frequency difference.
  • step 101 the clock frequency differences of the two uplink interfaces corresponding to one of the downlink interfaces are obtained, and then step 102 is performed, that is, each interface and one uplink interface are based on the transmission line card.
  • step 102 each of the clock frequency differences of the one line is used to adjust the transmission clock of the interface corresponding to each clock frequency difference.
  • the transmission clock is adjusted by up- or down-regulating the frequency of the system clock, or the phase-locked loop is used, and the transmission clock is adjusted in real time according to the target value of the frequency difference, that is, the determined clock frequency difference.
  • the transmission line card is the transmission line card m
  • the interface 0 of the line card m is configured to track the first path clock of the line card n, that is, the uplink interface 0, then according to the first path clock of the line card n
  • the clock frequency difference adjusts the transmission clock of interface 0 of line card m, for example, adjusts the transmission clock Fout_m0 of interface 0 of line card m to F0 + ⁇ . That is, in step 104, specifically, the sending line card adjusts the sending clock of each interface of each downlink interface to the sum of the clock frequency difference and the system time difference of each interface, so that the sending clock is consistent with the recovered line clock. .
  • 4 Ethernet devices include 3 line cards, namely line card 1, line card 2 and line card 3, each line card has two interfaces, interface 0 and interface 1 , that is, for the transmission line card, each line card can track up to two line clocks, and for the receiving line card, each line card can receive up to two lines, and Figure 4a shows the receiving line card.
  • FIG. 4b shows the correspondence between the uplink interface of the receiving line card and the interface of the transmitting line card embodied from the packet switching path.
  • the corresponding line cards corresponding to the line card 3 are assumed to be the line card 1 and the line card 2, respectively.
  • the receiving line card restores the line clock of the N uplink interfaces of the receiving line card, and obtains the line clocks of the N line recovery clocks
  • the line card 1 restores the line clocks of the 2 lines, respectively corresponding to the uplink interface 0 of the line card 1
  • the line recovery clock of the first line is recorded as the line recovery clock of the line 10
  • the line recovery clock of the second line corresponding to the uplink interface 1 of the line card 1 is recorded as the line recovery clock of the line 11; the line card 2 is restored.
  • the line clock of the two lines is the line recovery clock of the first line corresponding to the uplink interface 0 of the line card 2, and is recorded as the line 20 line recovery clock, and the second line of the line interface 1 corresponding to the uplink line 1
  • the line recovery clock is recorded as the line recovery clock for line 21. Therefore, in this step, a total of four line recovery clocks are obtained.
  • N is 4.
  • line card 1 and line card 2 respectively calculate the clock frequency difference between the four line recovery clocks and the system clock, and obtain four lines, that is, four clock frequency differences of four uplink interfaces, for example, ⁇ 10, ⁇ 11, ⁇ 20, and ⁇ 21 , where the first digit represents the card number of the line card, and the second digit represents the line identifier.
  • the line card 1 and the line card 2 can first determine the clock frequency difference required by the line card 3 according to the correspondence table shown in FIG. 4a.
  • the line card 1 determines the line and the line according to the correspondence between the interface of the uplink interface and the transmission line card.
  • the uplink interface corresponding to interface 0 of card 3 is the uplink interface 1 of line card 1, that is, the corresponding line.
  • the line card 2 determines that the uplink interface corresponding to the interface 1 of the line card 3 is the uplink interface 1 of the line card 2 according to the corresponding relationship between the interface of the uplink interface and the transmission line card, that is, the corresponding line is the line 21, Then, the line card 1 transmits the clock frequency difference ⁇ 11 corresponding to the line 11 to the line card 3, and the line card 2 transmits the clock frequency difference ⁇ 21 corresponding to the line 21 to the line card 3.
  • the line card 1 and the line card 2 respectively send the two clock frequency differences obtained by themselves, and a total of four clock frequency differences are sent to the line card 3, and then the line card 3 transmits the line card according to the transmission line shown in FIG. 4a.
  • the line card 3 determines that the line corresponding to the interface 0 of the line card 3 is the line 11, and the line corresponding to the interface 1 of the line card 3 is the line 21, then the line card 3 obtains the clock frequency difference of the line 11. ⁇ 11 , and the clock frequency difference ⁇ 21 of the line 21 is obtained.
  • step 102 is performed, that is, each clock frequency difference of the obtained two clock frequency differences is respectively adjusted to the transmission clock of the interface corresponding to each clock frequency difference, based on the correspondence between the one downlink interface and the one uplink interface.
  • the transmission clock of the interface 0 of the line card 3 is adjusted using the clock frequency difference ⁇ 11
  • the transmission clock of the interface 1 of the line card 3 is adjusted using the clock frequency difference ⁇ 21.
  • the specific adjustment method for example, as described above, adjusts the transmission clock to the sum of the clock frequency difference and the system clock.
  • the interface 0 of the line card 3 tracks the clock source of the line 11
  • the interface 1 of the line card 3 tracks the clock source of the line 21, realizing clock synchronization of multiple clock domains.
  • the receiving line card first calculates the clock frequency difference between each line and the system clock, and then sends the line card to send the sending clock of each interface according to the clock of its corresponding line.
  • the frequency difference is adjusted, so each interface can track different lines, that is, track different clock sources, so clock synchronization in multiple clock domains can be achieved.
  • the solution in the embodiment of the present application recovers the clock from the receiving line card, and recovers the physical layer clock. Therefore, the embodiment of the present application processes from the physical layer, and has nothing to do with the >3 ⁇ 4 text, so the performance is better.
  • each line card includes: a clock recovery unit 201 for recovering one uplink interface corresponding to one of the line cards
  • the line clock is obtained by the line recovery clock;
  • the frequency difference determining unit 202 is configured to determine a clock frequency difference between each of the line recovery clocks and the system clock, and obtain a clock frequency difference of the one uplink interface;
  • the sending unit 203 Send one clock frequency difference to the sending line card; so that the sending line card is based on one time
  • the clock frequency difference adjusts the transmission clock of the interface of the transmission line card;
  • the receiving unit 204 is configured to receive M clock frequency differences of the M uplink interfaces corresponding to the M interfaces sent by the receiving line card;
  • the clock adjustment unit 205 is configured to Corresponding relationship between each interface of the line card and the M uplink interfaces, and using each of the M clock frequency differences of the M uplink interfaces sent by the other line cards to adjust the interface corresponding to each clock frequency difference respectively Send the clock.
  • the processing unit further includes: determining, according to the correspondence between the uplink interface and the interface of the sending line card, that the M clock frequency differences determined by the frequency difference determining unit 202 respectively correspond to the interfaces of the sending line card The clock frequency difference of the line; the transmitting unit 203 is configured to send a clock frequency difference of the line corresponding to the interface of the transmission line card to the corresponding transmission line card.
  • the method further includes a processing unit, where the receiving unit 204 is configured to receive N clock frequency differences of N lines of M clock frequency differences that are sent by the line card and include M uplink interfaces corresponding to the M interfaces.
  • the N is a positive integer greater than or equal to M.
  • the processing unit is configured to determine M uplink interfaces corresponding to the M interfaces based on the correspondence between each interface of the sending line card and the uplink interface, and determine corresponding to the M interfaces. M clock frequency differences of M uplink interfaces.
  • the clock adjustment unit 205 is configured to adjust the transmission clock of each interface of the M interfaces to the sum of the clock frequency difference and the system time difference corresponding to each interface.
  • Each line card includes: M interfaces 401; and an interface circuit 402 for restoring The line clocks of the M uplink interfaces corresponding to the M interfaces 401 of the line card obtain M line recovery clocks; the frequency difference determining circuit 403 is configured to determine the clock frequency difference between the M line recovery clocks and the system clock, and obtain M M clock frequency difference of the uplink interface; the processor 404, configured to send the M clock frequency differences to the transmission line card; so that the transmission line card adjusts the transmission clock of the interface 401 of the transmission line card based on the M clock frequency differences; Also used to receive the M corresponding to the M interfaces 401 sent by the receiving line card.
  • a clock adjustment circuit 405 configured to use each of the M clock frequency differences of the M uplink interfaces sent by the other line cards based on the corresponding relationship between the line and the interface 401 The transmission clock of the interface 401 corresponding to each clock frequency difference is adjusted.
  • M is a positive integer.
  • the processor 404 is further configured to determine, according to the correspondence between the uplink interface and the interface of the sending line card, the interface 401 of the M clock frequency differences determined by the frequency difference determining circuit 403 and the sending line card respectively.
  • the clock frequency difference of the corresponding uplink interface is sent to the corresponding transmission line card by the clock frequency difference of the uplink interface corresponding to the interface 401 of the transmission line card.
  • the processor 404 is further configured to receive N clock frequency differences of the N uplink interfaces that are sent by the line card, where the N clock frequency differences include M of the M uplink interfaces corresponding to the M interfaces 401.
  • the clock frequency difference is different from the M interfaces 401.
  • the clock adjustment circuit 405 is configured to adjust the transmission clock of each interface 401 of the M interfaces 401 to the sum of the clock frequency difference and the system time difference corresponding to each interface 401.
  • bus 400 can include any number of interconnected buses and bridges, and bus 400 will include one or more processors 404 and memory 406 represented by processor 404.
  • the various circuits representing the memory are linked together.
  • the bus 400 can also link various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and, therefore, will not be further described herein.
  • Bus interface 407 provides an interface between bus 400 and components.
  • the processor 404 is responsible for managing the bus 400 and the usual processing, and the memory 406 can be used to store the correspondence table as shown in Figure 4a, and is also used to store the data used by the processor 404 in performing the operations.
  • the frequency difference determining circuit 403 is specifically a counter or a phase locked loop phase detector.
  • the clock adjustment circuit 405 is specifically a phase locked loop discriminator.
  • the M interfaces 401 are specifically Ethernet interfaces.
  • the various variations and specific examples in the foregoing clock synchronization method in the embodiments of FIG. 3 to FIG. 4b are also applicable to the line card of this embodiment.
  • the foregoing detailed description of the clock synchronization method can be clearly known to those skilled in the art. The method for implementing the line card in this embodiment is therefore not described in detail for the sake of brevity of the description.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can be embodied in the form of one or more computer program products embodied on a computer-usable storage medium (including but not limited to disk storage, CD-ROM, optical storage, etc.) in which computer usable program code is embodied.
  • a computer-usable storage medium including but not limited to disk storage, CD-ROM, optical storage, etc.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
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  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

本发明公开了一种多时钟域的时钟同步方法、线卡及以太网设备，该方法包括：发送线卡获得接收线卡确定的与所述发送线卡的M个下行接口对应的M个上行接口的M个时钟频差；其中，所述M个上行接口为所述接收线卡上的上行接口，M为正整数；所述发送线卡基于所述M个下行接口与M个上行接口的对应关系，使用M个上行接口的M个时钟频差中的每个时钟频差分别调整与所述每个时钟频差对应的接口的发送时钟。

Description

一种多时钟域的时钟同步方法、 线卡及以太网设备 技术领域
本发明涉及通信技术领域， 特别涉及一种多时钟域的时钟同步方法、 线 卡及以太网设备。 背景技术
在电信服务提供商网络向下一代网络的演进中， 以太网将逐步取代 PDH ( Plesiochronous Digital Hierarchy;准同步数字系歹1 J )^^SONET( Synchronous Optical Network; 同步光纤网络） / SDH ( Synchronous Digital Hierarchy; 同 步数字体系）传输网。
在以太网中， 一个重要的要素就是同步时钟， 请参考图 1所示， 为一种典 型的以太网时钟同步方案， 其中双向箭头实线代表各个线卡通过交换模块进 行数据包交换的路径， 然后各线卡从接收的线路上恢复时钟， 然后向时钟板 上报线路恢复时钟， 时钟板根据配置选择其中的一路作为设备的同步参考源， 经锁相处理后的同步时钟下发到各线卡， 作为线卡发送的参考时钟， 从而实 现同步时钟的发送。
然而， 在现有的以太网中， 运营商通常会把以太网设备出租给不同的服 务商， 而服务商有各自不同的时钟源， 所以需要跟踪不同的时钟源， 即需要 以太网设备支持多时钟域。 但是在现有时钟同步机制中， 单个设备的以太网 接口， 下发的物理层同步时钟， 一个系统只能有一个， 即所有线路都使用相 同的发送时钟， 所以无法实现多时钟域时钟的传递。 发明内容
本发明实施例提供一种多时钟域的时钟同步方法、 线卡及以太网设备， 用以解决现有技术中的时钟同步机制无法实现多时钟域时钟的问题。
本申请第一方面提供一种多时钟域的时钟同步方法， 包括： 发送线卡获得接收线卡确定的与所述发送线卡的 M个下行接口对应的 M 个上行接口的 M个时钟频差； 其中， 所述 M个上行接口为所述接收线卡上的 上行接口， M为正整数；
所述发送线卡基于所述 M个下行接口与 M个上行接口的对应关系 ,使用 M个上行接口的 M个时钟频差中的每个时钟频差分别调整与所述每个时钟频 差对应的接口的发送时钟。
结合第一方面， 在第一方面的第一种可能的实现方式中， 在所述发送线 卡获得接收线卡确定的与所述发送线卡的 M个下行接口对应的 M个上行接口 的 M个时钟频差之前， 还包括： 所述接收线卡恢复所述接收线卡的 N个上行 接口的线路时钟， 得到 N个线路恢复时钟， N大于等于 M; 所述接收线卡确 定所述 N个线路恢复时钟分别与系统时钟的时钟频差， 得到所述 N个上行接 口的 N个时钟频差； 其中， M个时钟频差为所述 N个时钟频差中的频差。
结合第一方面的第一种可能的实现方式， 在第一方面的第二种可能的实 现方式中， 在所述发送线卡获得接收线卡确定的与所述发送线卡的 M个下行 接口对应的 M个上行接口的 M个时钟频差之前，还包括： 所述接收线卡还基 于上行接口和发送线卡的接口的对应关系， 在所述 N个上行接口中确定出与 所述发送线卡的 M个下行接口对应的 M个上行接口；所述接收线卡发送所述 M个上行接口的 M个时钟频差给所述发送线卡。
结合第一方面的第一种可能的实现方式， 在第一方面的第三种可能的实 现方式中， 所述发送线卡获得接收线卡发送的与所述发送线卡的 M个下行接 口对应的 M个上行接口的 M个时钟频差， 包括： 所述发送线卡接收所述接收 线卡发送的所述 N个上行接口的 N个时钟频差； 所述发送线卡基于所述发送 线卡每个接口与上行接口的对应关系， 确定出与所述 M个下行接口对应的 M 个上行接口；所述发送线卡基于所述 M个上行接口，获得所述 M个时钟频差。
结合第一方面或第一方面的第一种可能的实现方式至第一方面的第三种 可能的实现方式中的任意一种， 在第一方面的第四种可能的实现方式中， 所 述使用 M个线路的 M个时钟频差中的每个时钟频差分别调整与所述每个时钟 频差对应的接口的发送时钟 ， 包括： 所述发送线卡将所述 M个下行接口中每 个接口的发送时钟分别调整为所述每个接口对应的时钟频差与所述系统时差 的和。
本申请第二方面提供一种线卡， 包括：
M个接口； M为正整数； 接口电路， 用于恢复与所述 M个接口对应的 M 个上行接口， 得到 M个线路恢复时钟； 频差确定电路， 用于确定 M个线路恢 复时钟分别与系统时钟的时钟频差，得到所述 M个上行接口的 M个时钟频差； 处理器， 用于将所述 M个时钟频差发送给发送线卡； 以使所述发送线卡基于 所述 M个时钟频差调整所述发送线卡的接口的发送时钟； 还用于接收接收线 卡发送的与所述 M个接口对应的 M个上行接口的 M个时钟频差； 时钟调整 电路， 用于基于发送线卡每个接口与 M个上行接口的对应关系， 使用所述其 他线卡发送的 M个上行接口的 M个时钟频差中的每个时钟频差分别调整与所 述每个时钟频差对应的接口的发送时钟。
结合第二方面， 在第二方面的第一种可能的实现方式中， 所述处理器还 用于基于上行接口和发送线卡的接口的对应关系， 确定所述频差确定电路确 差； 将所述与所述发送线卡的接口对应的上行接口的时钟频差发送给对应的 发送线卡。
结合第二方面， 在第二方面的第二种可能的实现方式中， 所述处理器还 用于接收接收线卡发送的 N个上行接口的 N个时钟频差，所述 N个时钟频差 包含与所述 M个接口对应的 M个上行接口的 M个时钟频差； 其中， N为大 于等于 M的正整数； 还用于基于发送线卡每个接口与上行接口的对应关系， 确定出与所述 M个接口对应的 M个上行接口； 确定与所述 M个接口对应的 M个上行接口的 M个时钟频差。
结合第二方面或第二方面的第一种可能的实现方式或第二方面的第二种 可能的实现方式， 在第二方面的第三种可能的实现方式中， 所述时钟调整电 路用于将所述 M个接口中每个接口的发送时钟分别调整为所述每个接口对应 的时钟频差与所述系统时差的和。
结合第二方面或第二方面的第一种可能的实现方式至第二方面的第三种 可能的实现方式中的任意一种， 在第二方面的第四种可能的实现方式中， 所 述频差确定电路具体为计数器或锁相环鉴相器。
结合第二方面或第二方面的第一种可能的实现方式至第二方面的第四种 可能的实现方式中的任意一种， 在第二方面的第五种可能的实现方式中， 所 述时钟调整电路具体为锁相环鉴频器。
结合第二方面或第二方面的第一种可能的实现方式至第二方面的第五种 可能的实现方式中的任意一种， 在第二方面的第六种可能的实现方式中， 所 述 M个接口具体为以太网接口。
本申请第三方面还提供一种以太网设备， 包括：
多个线卡；
时钟板， 用于产生系统时钟， 并将所述系统时钟发送给所述多个线卡中 的每个线卡；
其中， 所述多个线卡中的每个线卡为如第二方面或第二方面的第一种可 能的实现方式至第二方面的第六种可能的实现方式中的任意一种所述的线 卡。
本发明有益效果如下：
本发明实施例中，发送线卡获得接收线卡确定的与发送线卡的 M个下行接 口对应的 M个上行接口的 M个时钟频差； 其中， M个上行接口为接收线卡上的 上行接口， M为正整数； 发送线卡基于发送线卡每个接口与 M个上行接口的对 应关系，使用 M个上行接口的 M个时钟频差中的每个时钟频差分别调整与每个 时钟频差对应的接口的发送时钟。 因此在本实施例中， 接收线卡先确定每个 线路与系统时钟的时钟频差， 然后发送线卡将每个接口的发送时钟都根据其 对应的线路的时钟频差进行调整， 所以每个接口都可以跟踪不同的线路， 即 跟踪不同的时钟源， 所以可以实现多时钟域的时钟同步。 进一步， 本申请实 施例中的方案是由接收线卡恢复时钟， 恢复的是物理层时钟， 所以本申请实 施例是从物理层进行处理， 跟报文无关， 所以性能更好。 附图说明
图 1为现有技术中时钟同步方案的示意图；
图 2为本发明实施例中的以太网设备的功能框图；
图 3为本发明实施例中的时钟同步方法的流程图；
图 4a为本发明实施例中的上行接口和下行接口的对应关系表示意图； 图 4b为本发明实施例中的从包交换路径角度体现线路和接口的对应关系 示意图；
图 5为本发明实施例中的线卡的功能框图；
图 6为本发明实施例中的线卡的硬件实现的示例概念图。 具体实施方式
本发明实施例提供一种多时钟域的时钟同步方法、 线卡及以太网设备， 用以解决现有技术中的时钟同步机制无法实现多时钟域时钟的问题。
本申请实施例中的技术方案为解决上述的技术问题， 总体思路如下： 发送线卡获得接收线卡确定的与发送线卡的 M个下行接口对应的 M个上 行接口的 M个时钟频差； 其中， M个上行接口为接收线卡上的上行接口， M 为正整数； 发送线卡基于发送线卡每个接口与 M个上行接口的对应关系， 使 用 M个上行接口的 M个时钟频差中的每个时钟频差分别调整与每个时钟频差 对应的接口的发送时钟。 因此在本实施例中， 接收线卡先确定每个线路与系 统时钟的时钟频差， 然后发送线卡将每个接口的发送时钟都根据其对应的线 路的时钟频差进行调整， 所以每个接口都可以跟踪不同的线路， 即跟踪不同 的时钟源， 所以可以实现多时钟域的时钟同步。 进一步， 本申请实施例中的 方案是由接收线卡恢复时钟， 恢复的是物理层时钟， 所以本申请实施例是从 物理层进行处理， 跟报文无关， 所以性能更好。 为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例中的附图， 对本发明实施例中的技术方案进行清楚、 完整地描述， 显然， 所描述的实施例是本发明一部分实施例， 而不是全部的实施例。 基于 本发明中的实施例， 本领域普通技术人员在没有作出创造性劳动前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
下面结合附图对本发明优选的实施方式进行详细说明。
请参考图 2所示， 为一个以太网设备的功能框图， 该以太网设备包括： 多个线卡， 如线卡 1、 线卡 2、 …线卡 N, 具体线卡的数量可以根据实际 需求进行配置， 通常为两个或两个以上； 时钟板， 用于产生系统时钟， 并将 系统时钟发送给多个线卡。 多个线卡和时钟板均可以安装在以太网设备的背 板上， 该以太网设备还可以包括交换模块， 用于进行包交换。 该以太网设备 具体可以是交换机、 路由器、 OLT ( optical line terminal; 光线路终端）等需要 进行接收和发送数据包的以太网设备。
接下来介绍该以太网设备的多时钟域的时钟同步方法， 其中， 对于每个 线卡而言， 均可以同时作为接收线卡和发送线卡， 即扮演接收和发送两种角 色， 当一个线卡作为接收线卡时， 其他线卡可以作为相对于该线卡的发送线 卡， 当一个线卡作为发送线卡时， 其他线卡则可以作为相对于该线卡的接收 线卡。 在实际应用中， 部分线卡的接口接到上行， 部分线卡的接口接到下行。 根据配置， 部分或全部上行接口需要恢复接口时钟， 并计算频差， 频差下发 给下行接口使用。 根据配置， 下行接口选用不同的上行接口恢复时钟， 选用 了哪个上行接口恢复时钟， 就使用对应的上行接口频差产生发送时钟。 所以 以下在描述时钟同步方法的过程中， 是以角色命名各线卡。 请参考图 3所示， 该方法包括：
步骤 101 : 发送线卡获得接收线卡确定的与发送线卡的 M个下行接口对 应的 M个上行接口的 M个时钟频差； 其中， M个上行接口为接收线卡上的 上行接口， M为正整数；
步骤 102: 发送线卡基于 M个下行接口与 M个上行接口的对应关系， 使 用 M个上行接口的 M个时钟频差中的每个时钟频差分别调整与每个时钟频差 对应的接口的发送时钟。
其中，在步骤步骤 101之前， 该方法还包括： 接收线卡恢复接收线卡的 N 个上行接口的线路时钟， 得到 N个线路恢复时钟， N大于等于 M; 接收线卡 确定 N个线路恢复时钟分别与系统时钟的时钟频差， 得到 N个上行接口的 N 个时钟频差； 其中， M个时钟频差为 N个时钟频差中的频差。
在本实施例中， 接收线卡恢复接收线卡的 N个上行接口的线路时钟的步 骤具体可以是周期性实施， 或者是实时的进行恢复线路时钟， N个上行接口 通常和接收线卡的 N个接口是——对应的， N个上行接口与 N路线路——对 应。 在实际运用中， 接收线卡的实际接口数量也可以大于上行接口的数量； 另外， 步骤 101中的 N个上行接口可以是来自不同线卡的上行接口， 每个接 收线卡上的接口数量可以相同， 也可以不相同， 总量为 N。
例如对于接收线卡 n 来讲， 得到的 s 个线路恢复时钟， 例如分别记为 Fin— nO/1/2... ... s, s表示线卡 n的总数量， s为正整数且小于等于 N。
当得到 N个线路恢复时钟时， 同时， 因为时钟板也在实时的将系统时钟 发送给每个线卡， 所以接收线卡就确定 N个线路恢复时钟分别与系统时钟的 时钟频差， 具体来说， 例如利用计数器计算每个线路恢复时钟和系统时钟的 时钟频差， 再例如利用锁相环鉴相的方法； 还可以利用现在市面上 3 级时钟 锁相环芯片， 该锁相环芯片可以读取输入时钟与系统时钟之间的频偏， 即时 钟频差。
举例来说， 在本实施例中， 系统时钟例如为 F0, 那么经过步骤 102可以 获得 N个上行接口的 N时钟频差， 例如为 ΔηΟ = Fin nO - F0; Δηΐ = Fin nl - FO; Ans = Fin ns - F0。 理方式， 第一种是接收线卡确定出发送线卡需要的时钟频差然后发送给发送 线卡； 第二种是接收线卡将确定出来的 N个时钟频差全部发送给发送线卡， 发送线卡自己选择自己所需要的 M个时钟频差。 具体来讲， 第一种的方式， 就在步骤： 接收线卡确定 N个线路恢复时钟 分别与系统时钟的时钟频差之后， 步骤 101 之前， 该方法还包括： 接收线卡 基于上行接口和发送线卡的接口的对应关系， 在 N个上行接口中确定出于发 送线卡的 M个下行接口对应的 M个上行接口， 然后接收线卡就发送 M个上 行接口的 M个时钟频差给发送线卡， 那么对应的， 发送线卡就执行步骤 103 , 获得与其 M各接口对应的 M个上行接口的 M个时钟频差。 其中， M个时钟 频差为步骤 102中得到的 N个时钟频差中的频差，Μ小于等于 N且为正整数。
对于第二种方式， 在步骤： 接收线卡确定 Ν个线路恢复时钟分别与系统 时钟的时钟频差之后， 接收线卡就将 Ν个时钟频差均发送给发送线卡， 那么 步骤 101具体包括： 发送线卡接收接收线卡发送的 Ν个上行接口的 Ν个时钟 频差； 发送线卡基于发送线卡每个接口与上行接口的对应关系， 确定出与 Μ 个下行接口对应的 Μ个上行接口； 发送线卡基于 Μ个上行接口， 获得 Μ个 时钟频差。
不管通过以上哪种方式， 在步骤 101中获得与其 Μ个下行接口对应的 Μ 个上行接口的 Μ个时钟频差， 接下来就执行步骤 102, 即基于发送线卡每个 接口与 Μ个上行接口的对应关系， 使用 Μ个线路的 Μ个时钟频差中的每个 时钟频差分别调整与每个时钟频差对应的接口的发送时钟。
具体来说， 例如通过上调或者下调系统时钟的频率调整发送时钟， 或者 是釆用锁相环的方式， 根据频差的目标值， 即确定出的时钟频差， 实时调整 发送时钟。
举例来说， 例如发送线卡为发送线卡 m, 而且线卡 m的接口 0被配置为 跟踪线卡 n的第 1路时钟， 即上行接口 0, 那么就根据线卡 n的第 1路时钟的 时钟频差调整线卡 m的接口 0的发送时钟， 例如将线卡 m的接口 0的发送时 钟 Fout— m0调整到 F0 + Δηΐ。 即在步骤 104中， 具体为发送线卡将 Μ个下行 接口中每个接口的发送时钟分别调整为每个接口对应的时钟频差与系统时差 的和， 使得发送时钟与恢复的线路时钟保持一致。
在实际系统中， 由于时钟漂移， F0/ Fin— ηΟ/1/2等会实时变化， 同样， Δηΐ/ Fout— m0也会实时跟随变化。
为了便于本领域技术人员更清楚的了解本发明， 以下将举一个具体是实 例来说明本申请实施例中时钟同步方法的实施过程。
请同时参考图 4a和图 4b所示， 4叚设以太网设备包括 3个线卡， 分别为 线卡 1、 线卡 2和线卡 3 , 每个线卡具有两个接口， 接口 0和接口 1 , 即对于 发送线卡来讲， 每个线卡最多可以跟踪两路线路时钟， 而对于接收线卡来讲， 每个线卡最多可以接收两路线路， 图 4a表示的是接收线卡的上行接口和发送 线卡的接口之间的对应关系的关系表， 其中， 空白表示没有对应关系， 数值 1 表示有对应关系， 该表可以配置在每个线卡上， 并且该关系表可以人工配置， 也可以是根据不同的通信协议进行不同的配置； 图 4b表示的是从包交换路径 来体现的接收线卡的上行接口和发送线卡的接口之间的对应关系。
在本实施例中，假设发送线卡为线卡 3 , 那么相对应于线卡 3的接收线卡 假设分别为线卡 1和线卡 2。 那么在步骤： 接收线卡恢复接收线卡的 N个上 行接口的线路时钟， 得到 N个线路恢复时钟中， 线卡 1恢复 2路线路的线路 时钟， 分别为与线卡 1的上行接口 0对应的第 1路线路的线路恢复时钟， 记 为线路 10的线路恢复时钟， 线卡 1的上行接口 1对应的第 2路线路的线路恢 复时钟， 记为线路 11的线路恢复时钟； 线卡 2恢复 2路线路的线路时钟， 分 别为与线卡 2的上行接口 0对应的第 1路线路的线路恢复时钟， 记为线路 20 线路恢复时钟， 线卡 1的上行接口 1对应的第 2路线路的线路恢复时钟， 记 为线路 21的线路恢复时钟。 因此， 在该步骤中， 共得到 4个线路恢复时钟。 在本实施例中， N为 4。
然后线卡 1和线卡 2分别计算 4个线路恢复时钟与系统时钟的时钟频差， 得到 4路线路， 即 4个上行接口的 4个时钟频差， 例如分别记为 Δ10、 Δ11、 Δ20和 Δ21 , 其中第一位数字表示线卡的卡号， 第二位数字表示线路标识。
那么线卡 1和线卡 2可以分别先根据图 4a所示的对应表确定出线卡 3需 要的时钟频差， 例如线卡 1 根据上行接口和发送线卡的接口的对应关系， 确 定出与线卡 3的接口 0对应的上行接口为线卡 1的上行接口 1 ,即对应的线路 为线路 11 , 线卡 2根据上行接口和发送线卡的接口的对应关系， 确定出与线 卡 3的接口 1对应的上行接口为线卡 2的上行接口 1 , 即对应的线路为线路 21 , 那么线卡 1就将线路 11对应的时钟频差 Δ11发送给线卡 3 , 线卡 2就将 线路 21对应的时钟频差 Δ21发送给线卡 3。
或者是， 线卡 1和线卡 2分别将自己获得的 2个时钟频差， 共 4个时钟 频差均发给线卡 3 , 然后线卡 3根据如图 4a中所示的发送线卡每个接口与上 行接口的对应关系， 确定出与线卡 3的接口 0对应的线路为线路 11 , 线卡 3 的接口 1对应的线路为线路 21 , 那么线卡 3就获得线路 11的时钟频差 Δ11 , 并获得线路 21的时钟频差 Δ21。
然后执行步骤 102, 即基于 Μ个下行接口与 Μ个上行接口的对应关系， 使用获得的 2个时钟频差中的每个时钟频差分别调至与每个时钟频差对应的 接口的发送时钟， 例如使用时钟频差 Δ11调整线卡 3的接口 0的发送时钟，使 用时钟频差 Δ21调整线卡 3的接口 1的发送时钟。具体的调整方式例如前述所 述的， 将发送时钟调整到时钟频差与系统时钟的和。
因此， 线卡 3的接口 0就跟踪线路 11的时钟源， 线卡 3的接口 1就跟踪 线路 21的时钟源， 实现多时钟域的时钟同步。
由上述的描述可以看出， 在本申请实施例中， 接收线卡先计算每个线路 与系统时钟的时钟频差， 然后发送线卡将每个接口的发送时钟都根据其对应 的线路的时钟频差进行调整， 所以每个接口都可以跟踪不同的线路， 即跟踪 不同的时钟源， 所以可以实现多时钟域的时钟同步。 进一步， 本申请实施例 中的方案是由接收线卡恢复时钟， 恢复的是物理层时钟， 所以本申请实施例 是从物理层进行处理 ， 跟 >¾文无关， 所以性能更好。
接下来请参考图 5 所示， 为多个线卡中每个线卡的功能框图， 每个线卡 包括： 时钟恢复单元 201 , 用于恢复与线卡的 Μ个接口对应的 Μ个上行接口 的线路时钟， 得到 Μ个线路恢复时钟； 频差确定单元 202, 用于确定 Μ个线 路恢复时钟分别与系统时钟的时钟频差，得到 Μ个上行接口的 Μ个时钟频差； 发送单元 203 , 将 Μ个时钟频差发送给发送线卡； 以使发送线卡基于 Μ个时 钟频差调整发送线卡的接口的发送时钟； 接收单元 204, 用于接收接收线卡发 送的与 M个接口对应的 M个上行接口的 M个时钟频差； 时钟调整单元 205 , 用于基于发送线卡每个接口与 M个上行接口的对应关系， 使用其他线卡发送 的 M个上行接口的 M个时钟频差中的每个时钟频差分别调整与每个时钟频差 对应的接口的发送时钟。
在进一步的实施例中， 还包括处理单元， 用于基于上行接口和发送线卡 的接口的对应关系， 确定频差确定单元 202确定出的 M个时钟频差中分别与 发送线卡的接口对应的线路的时钟频差； 发送单元 203 用于将与发送线卡的 接口对应的线路的时钟频差发送给对应的发送线卡。
在另一实施例中， 还包括处理单元， 接收单元 204用于接收接收线卡发 送的包含与 M个接口对应的 M个上行接口的 M个时钟频差的 N个线路的 N 个时钟频差； 其中， N为大于等于 M的正整数； 处理单元用于基于发送线卡 每个接口与上行接口的对应关系， 确定出与 M个接口对应的 M个上行接口； 确定与 M个接口对应的 M个上行接口的 M个时钟频差。
进一步， 时钟调整单元 205用于将 M个接口中每个接口的发送时钟分别 调整为每个接口对应的时钟频差与系统时差的和。
前述图 3至图 4b实施例中的时钟同步方法中的各种变化方式和具体实例 同样适用于本实施例的线卡， 通过前述对时钟同步方法的详细描述， 本领域 技术人员可以清楚的知道本实施例中线卡的实施方法， 所以为了说明书的简 洁， 在此不再详述。
接下来请再参考图 6所示， 为本申请实施例中多个线卡中每个线卡的硬 件实现示例的框图， 每个线卡包括： M个接口 401 ; 接口电路 402, 用于恢复 与线卡的 M个接口 401对应的 M个上行接口的线路时钟， 得到 M个线路恢 复时钟； 频差确定电路 403 , 用于确定 M个线路恢复时钟分别与系统时钟的 时钟频差， 得到 M个上行接口的 M个时钟频差； 处理器 404, 用于将 M个 时钟频差发送给发送线卡； 以使发送线卡基于 M个时钟频差调整发送线卡的 接口 401的发送时钟； 还用于接收接收线卡发送的与 M个接口 401对应的 M 个上行接口的 M个时钟频差； 时钟调整电路 405, 用于基于线路与接口 401 的对应关系，使用其他线卡发送的 M个上行接口的 M个时钟频差中的每个时 钟频差分别调整与每个时钟频差对应的接口 401的发送时钟。 其中， M为正 整数。
在进一步的实施例中， 处理器 404,还用于基于上行接口和发送线卡的接 口的对应关系， 确定频差确定电路 403确定出的 M个时钟频差中分别与发送 线卡的接口 401对应的上行接口的时钟频差； 将与发送线卡的接口 401对应 的上行接口的时钟频差发送给对应的发送线卡。
在另一实施例中， 处理器 404, 还用于接收接收线卡发送的 N个上行接 口的 N个时钟频差， N个时钟频差包含与 M个接口 401对应的 M个上行接 口的 M个时钟频差； 其中， N为大于等于 M的正整数； 还用于基于上行接口 与接口的对应关系，确定出与 M个接口 401对应的 M个上行接口；确定与 M 个接口 401对应的 M个上行接口的 M个时钟频差。
进一步， 时钟调整电路 405用于将 M个接口 401中每个接口 401的发送 时钟分别调整为每个接口 401对应的时钟频差与系统时差的和。
其中， 在图 6中， 总线架构 （用总线 400来代表）， 总线 400可以包括任 意数量的互联的总线和桥， 总线 400将包括由处理器 404代表的一个或多个 处理器 404和存储器 406代表的存储器的各种电路链接在一起。 总线 400还 可以将诸如外围设备、 稳压器和功率管理电路等之类的各种其他电路链接在 一起， 这些都是本领域所公知的， 因此， 本文不再对其进行进一步描述。 总 线接口 407在总线 400和各元器件之间提供接口。
处理器 404负责管理总线 400和通常的处理， 而存储器 406可以被用于 存储如图 4a中所示的对应关系表， 还被用于存储处理器 404在执行操作时所 使用的数据。
结合以上各实施例， 频差确定电路 403具体为计数器或锁相环鉴相器。 结合以上各实施例， 时钟调整电路 405具体为锁相环鉴频器。
结合以上各实施例， M个接口 401具体为以太网接口。 前述图 3至图 4b实施例中的时钟同步方法中的各种变化方式和具体实例 同样适用于本实施例的线卡， 通过前述对时钟同步方法的详细描述， 本领域 技术人员可以清楚的知道本实施例中线卡的实施方法， 所以为了说明书的简 洁， 在此不再详述。
本领域内的技术人员应明白， 本发明的实施例可提供为方法、 系统、 或 计算机程序产品。 因此， 本发明可釆用完全硬件实施例、 完全软件实施例、 或结合软件和硬件方面的实施例的形式。 而且， 本发明可釆用在一个或多个 其中包含有计算机可用程序代码的计算机可用存储介质 (包括但不限于磁盘 存储器、 CD-ROM、 光学存储器等）上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、 设备（系统）、 和计算机程序产 品的流程图和 /或方框图来描述的。 应理解可由计算机程序指令实现流程图 和 /或方框图中的每一流程和 /或方框、 以及流程图和 /或方框图中的流程 和 /或方框的结合。 可提供这些计算机程序指令到通用计算机、 专用计算机、 嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器， 使得通 过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流 程图一个流程或多个流程和 /或方框图一个方框或多个方框中指定的功能的 装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设 备以特定方式工作的计算机可读存储器中， 使得存储在该计算机可读存储器 中的指令产生包括指令装置的制造品， 该指令装置实现在流程图一个流程或 多个流程和 /或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上， 使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的 处理， 从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图 一个流程或多个流程和 /或方框图一个方框或多个方框中指定的功能的步 骤。
尽管已描述了本发明的优选实施例， 但本领域内的技术人员一旦得知了 基本创造性概念， 则可对这些实施例做出另外的变更和修改。 所以， 所附权 利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。 脱离本发明实施例的精神和范围。 这样， 倘若本发明实施例的这些修改和变 型属于本发明权利要求及其等同技术的范围之内， 则本发明也意图包含这些 改动和变型在内。

Claims

权 利 要 求
1、 一种多时钟域的时钟同步方法， 其特征在于， 所述方法包括： 发送线卡获得接收线卡确定的与所述发送线卡的 M个下行接口对应的 M 个上行接口的 M个时钟频差； 其中， 所述 M个上行接口为所述接收线卡上的 上行接口， M为正整数；
所述发送线卡基于所述 M个下行接口与 M个上行接口的对应关系 ,使用 M个上行接口的 M个时钟频差中的每个时钟频差分别调整与所述每个时钟频 差对应的接口的发送时钟。
2、 如权利要求 1所述的方法， 其特征在于， 在所述发送线卡获得接收线 卡确定的与所述发送线卡的 M个下行接口对应的 M个上行接口的 M个时钟 频差之前， 还包括：
所述接收线卡恢复所述接收线卡的 N个上行接口的线路时钟， 得到 N个 线路恢复时钟， N大于等于 M;
所述接收线卡确定所述 N个线路恢复时钟分别与系统时钟的时钟频差， 得到所述 N个上行接口的 N个时钟频差； 其中， M个时钟频差为所述 N个时 钟频差中的频差。
3、 如权利要求 2所述的方法， 其特征在于， 在所述发送线卡获得接收线 卡确定的与所述发送线卡的 M个下行接口对应的 M个上行接口的 M个时钟 频差之前， 还包括：
所述接收线卡还基于上行接口和发送线卡的接口的对应关系， 在所述 N 个上行接口中确定出与所述发送线卡的 M个下行接口对应的 M个上行接口； 所述接收线卡发送所述 M个上行接口的 M个时钟频差给所述发送线卡。
4、 如权利要求 2所述的方法， 其特征在于， 所述发送线卡获得接收线卡 发送的与所述发送线卡的 M个下行接口对应的 M个上行接口的 M个时钟频 差， 包括：
所述发送线卡接收所述接收线卡发送的所述 N个上行接口的 N个时钟频 所述发送线卡基于所述发送线卡每个接口与上行接口的对应关系， 确定 出与所述 M个下行接口对应的 M个上行接口；
所述发送线卡基于所述 M个上行接口， 获得所述 M个时钟频差。
5、 如权利要求 1-4任一项所述的方法， 其特征在于， 所述使用 M个线路 的 M个时钟频差中的每个时钟频差分别调整与所述每个时钟频差对应的接口 的发送时钟 ， 包括：
所述发送线卡将所述 M个下行接口中每个接口的发送时钟分别调整为所 述每个接口对应的时钟频差与所述系统时差的和。
6、 一种线卡， 其特征在于， 包括：
M个接口； M为正整数；
接口电路， 用于恢复与所述 M个接口对应的 M个上行接口， 得到 M个 线路恢复时钟；
频差确定电路，用于确定 M个线路恢复时钟分别与系统时钟的时钟频差， 得到所述 M个上行接口的 M个时钟频差；
处理器， 用于将所述 M个时钟频差发送给发送线卡； 以使所述发送线卡 基于所述 M个时钟频差调整所述发送线卡的接口的发送时钟； 还用于接收接 收线卡发送的与所述 M个接口对应的 M个上行接口的 M个时钟频差；
时钟调整电路，用于基于发送线卡每个接口与 M个上行接口的对应关系， 使用所述其他线卡发送的 M个上行接口的 M个时钟频差中的每个时钟频差分 别调整与所述每个时钟频差对应的接口的发送时钟。
7、 如权利要求 6所述的线卡， 其特征在于， 所述处理器还用于基于上行 接口和发送线卡的接口的对应关系， 确定所述频差确定电路确定出的 M个时 钟频差中分别与所述发送线卡的接口对应的上行接口的时钟频差； 将所述与 所述发送线卡的接口对应的上行接口的时钟频差发送给对应的发送线卡。
8、 如权利要求 6所述的线卡， 其特征在于， 所述处理器还用于接收接收 线卡发送的 N个上行接口的 N个时钟频差，所述 N个时钟频差包含与所述 M 个接口对应的 M个上行接口的 M个时钟频差； 其中， N为大于等于 M的正 整数；
还用于基于发送线卡每个接口与上行接口的对应关系， 确定出与所述 M 个接口对应的 M个上行接口； 确定与所述 M个接口对应的 M个上行接口的 M个时钟频差。
9、 如权利要求 6-8任一项所述的线卡， 其特征在于， 所述时钟调整电路 用于将所述 M个接口中每个接口的发送时钟分别调整为所述每个接口对应的 时钟频差与所述系统时差的和。
10、 如权利要求 6-9任一项所述的线卡， 其特征在于， 所述频差确定电路 具体为计数器或锁相环鉴相器。
11、 如权利要求 6-10所述的线卡， 其特征在于， 所述时钟调整电路具体 为锁相环鉴频器。
12、 如权利要求 6-11所述的线卡， 其特征在于， 所述 M个接口具体为以 太网接口。
13、 一种以太网设备， 其特征在于， 包括：
多个线卡；
时钟板， 用于产生系统时钟， 并将所述系统时钟发送给所述多个线卡中 的每个线卡；
其中，所述多个线卡中的每个线卡为如权利要求 6-12任一项所述的线卡。
PCT/CN2013/090352 2013-12-24 2013-12-24 一种多时钟域的时钟同步方法、线卡及以太网设备 WO2015096041A1 (zh)

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