WO2015081673A1 - 薄膜晶体管阵列基板及其制备方法、显示装置 - Google Patents

薄膜晶体管阵列基板及其制备方法、显示装置 Download PDF

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WO2015081673A1
WO2015081673A1 PCT/CN2014/078546 CN2014078546W WO2015081673A1 WO 2015081673 A1 WO2015081673 A1 WO 2015081673A1 CN 2014078546 W CN2014078546 W CN 2014078546W WO 2015081673 A1 WO2015081673 A1 WO 2015081673A1
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layer
gate
insulating layer
groove
drain
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French (fr)
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刘凤娟
王美丽
张立
闫梁臣
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
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    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections

Definitions

  • Embodiments of the present invention relate to a thin film transistor array substrate, a method of fabricating the same, and a display device. Background technique
  • scan lines and data lines on a display thin film transistor (TFT) array substrate are generally made of a relatively stable alloy such as Ta, Mo, Cr or AlNd.
  • a relatively stable alloy such as Ta, Mo, Cr or AlNd.
  • copper has a lower resistivity and is a preferred material that can replace existing aluminum and aluminum alloy materials and reduce RC retardation.
  • copper has a lower resistivity and is a preferred material that can replace existing aluminum and aluminum alloy materials and reduce RC retardation.
  • the adhesion between copper and glass is poor, and the diffusion of copper atoms in semiconductors and oxides is serious. It is necessary to add a barrier layer on the upper and lower surfaces of copper to improve the adhesion of copper wires on glass. Prevent copper from spreading.
  • the patterned copper gate electrode needs to have a certain slope angle to prevent the fault of the gate insulating layer, so that the barrier layer cannot completely cover the upper surface of the copper film, and some copper is still exposed outside the protective layer at the boundary.
  • One embodiment of the present invention provides a method of fabricating a thin film transistor array substrate, including the following steps:
  • first insulating layer Forming a first insulating layer on the substrate, forming a first photoresist layer on the first insulating layer, and forming a gate recess on the first insulating layer on which the first photoresist layer is formed, the gate
  • the periphery of the pole groove is surrounded by the first insulating layer;
  • the first photoresist layer on the substrate on which the gate layer is formed and the gate layer above the first photoresist layer are peeled off to form a gate surrounded by the first insulating layer.
  • a gate insulating layer, an active layer, and a second insulating layer are sequentially formed on a substrate forming a gate surrounded by the first insulating layer;
  • the step of forming a gate recess on the first insulating layer on which the first photoresist layer is formed includes:
  • first photoresist layer retention region and a first photoresist layer removal region Forming a first photoresist layer retention region and a first photoresist layer removal region by exposure and development, the first photoresist layer removal region corresponding to a position at which the gate recess is to be formed;
  • the source recess and the drain recess are formed on the second insulating layer on which the second photoresist layer is formed, and the periphery of the source recess and the drain recess are second insulated Surrounded by layers, the steps of exposing part of the active layer include:
  • a second photoresist layer retention region and a second photoresist layer removal region Forming, by exposure and development, a second photoresist layer retention region and a second photoresist layer removal region, wherein the second photoresist layer removal region corresponds to forming the source recess and the drain recess a second insulating layer is etched, and a second insulating layer of the second photoresist layer removing region is etched to form the source recess and the drain recess.
  • the thickness of the gate layer is formed to be the same as the depth of the gate trench; the thickness of the source drain layer is formed to be the same as the depth of the source and drain trenches.
  • the step of forming a gate layer and/or forming a source drain layer comprises: forming a metal layer or forming a metal conductive composite layer.
  • the step of forming a metal conductive composite layer includes:
  • a thin film transistor array substrate including a substrate, a gate electrode sequentially formed on the substrate, a gate insulating layer, an active layer, a source and a drain, and the substrate is formed with a first insulating layer having a gate recess, the gate being formed in the gate recess.
  • a second insulating layer having a source recess and a drain recess is formed on the gate insulating layer and the active layer, and the source and the drain are respectively disposed on the second insulating layer.
  • the source trench and the drain recess are inside.
  • the thickness of the gate layer is the same as the depth of the gate trench.
  • the source and drain layers have the same thickness as the source and drain grooves.
  • At least one of the gate, the source, and the drain includes a metal layer or a metal conductive composite layer.
  • the metal conductive composite layer comprises a copper metal film or an alloy film containing copper metal and at least one metal barrier layer on two opposite surfaces of the copper metal film or the alloy film containing copper metal. At least one of them.
  • Still another embodiment of the present invention provides a display device comprising the thin film transistor array substrate according to any of the above embodiments.
  • FIG. 1 is a cross-sectional view showing a first insulating layer deposited on a substrate in an embodiment of the present invention
  • FIG. 2 is a cross-sectional view showing a first photoresist layer applied and exposed and developed in an embodiment of the present invention
  • FIG. 4 is a cross-sectional view showing a gate layer after deposition in an embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of the first photoresist layer and the gate layer over the first photoresist layer in the embodiment of the present invention
  • Figure 6 is a cross-sectional view showing a gate insulating layer deposited in an embodiment of the present invention
  • Figure 7 is a cross-sectional view showing an active layer in an embodiment of the present invention
  • Figure 8 is a cross-sectional view showing a second insulating layer in the embodiment of the present invention.
  • Figure 9 is a cross-sectional view showing a photoresist coated on a second insulating layer and exposed and developed in the embodiment of the present invention.
  • Figure 10 is a cross-sectional view showing the second insulating layer after being etched in the embodiment of the present invention.
  • Figure 11 is a cross-sectional view showing a source/drain layer after deposition in an embodiment of the present invention.
  • Figure 12 is a cross-sectional view showing the second photoresist and the source and drain layers on the second photoresist layer in the embodiment of the present invention. detailed description
  • a thin film transistor array substrate includes a substrate 1, a gate electrode 4 formed on the substrate 1 in order from bottom to top, a gate insulating layer 5, an active layer 6 and Source 9, drain 10.
  • a first insulating layer 2 having a gate recess is formed on the substrate 1, and a gate electrode 4 is formed in the gate recess, and the first insulating layer 2 can isolate the gate 4 from the outside.
  • the gate 4 of the embodiment of the present invention is formed in the gate recess of the first insulating layer 2 such that the gate is surrounded by the first insulating layer 2, and the patterned gate 4 has no slope, which can prevent the gate insulating layer from being The fault layer, in turn, effectively blocks copper diffusion in the thin film transistor (TFT) array substrate.
  • TFT thin film transistor
  • the substrate 1 referred to in the embodiment of the present invention may be generally referred to as a general substrate such as a glass substrate, or may be a substrate on which other film layers or patterns are formed.
  • a second insulating layer 7 having a source recess and a drain recess is formed on the gate insulating layer 5 and the active layer 6.
  • the source 9 and the drain 10 are respectively formed on the source recess of the second insulating layer 7.
  • a second insulating layer 7 is provided around the source 9 and the drain 10 for isolating the source 9 and the drain 10 from the outer boundary.
  • the gate 4 and/or source 9 and drain 10 may comprise a metal layer or a metal conductive composite layer.
  • the gate 4 and/or the source 9 and the drain 10 include a metal.
  • a conductive composite layer comprising a copper metal film or an alloy film containing copper metal and at least one metal barrier layer located on the upper and/or lower layers of the copper metal film or the alloy film containing copper metal, that is, The metal barrier layer is formed on at least one of two opposite surfaces of the copper metal film or the alloy film containing the copper metal.
  • the thickness of the gate 4 is equal to the depth of the gate recess of the first insulating layer 2
  • the thickness of the source 9 and the drain 10 is equal to the depth of the source and drain recesses of the second insulating layer 7.
  • the metal barrier layer of the gate electrode 4 is located on the upper layer of the copper metal or the alloy thin film layer containing the copper metal to block the diffusion of the Cu metal into the gate insulating layer and the active layer.
  • the metal barrier layer of the source 9 and the drain 10 is located under the copper metal or the alloy thin film layer containing the copper metal to block the diffusion of the Cu metal into the second insulating layer 7 and the active layer 6.
  • the material of the metal barrier layer of the gate electrode 4 and the source electrode 9 and the drain electrode 10 is, for example, an elemental metal containing Al, In, Ti, Ta, and Mo, an alloy thereof, or the like.
  • a display device includes the TFT array substrate provided by the above technical solution.
  • the embodiment of the invention further provides a method for preparing a thin film transistor array substrate provided by the above technical solution, which comprises the following steps:
  • a first insulating layer 2 is formed on the substrate 1, and a first photoresist layer 3 is formed on the first insulating layer 2, and a gate recess is formed on the first insulating layer 2 on which the first photoresist layer 3 is formed. a groove, the periphery of the gate groove is surrounded by the first insulating layer;
  • the first photoresist layer 3 on the substrate on which the gate layer is formed and the gate layer above the first photoresist layer 3 are peeled off to form the gate electrode 4 surrounded by the first insulating layer.
  • first insulating layer 2 on the substrate 1, wherein the thickness of the first insulating layer 2 is equal to the thickness of the desired gate and gate metal composite layers, and is first
  • the first photoresist layer 3 is formed on the insulating layer 2 by a process such as coating or spraying. After exposure and development, a first photoresist layer retention region and a first photoresist layer removal region are formed.
  • the first photoresist layer removal region corresponds to a location where a gate recess is to be formed.
  • the first insulating layer 2 is etched by using the patterned first photoresist layer as a mask, so that the first insulating layer of the first photoresist layer removal region is etched to form a gate recess, the gate The periphery of the recess is surrounded by the first insulating layer 2, and the photoresist on the first insulating layer 2 around the gate recess is retained for stripping of the subsequent gate layer; 52, as shown in FIG.
  • the gate layer 4a is formed by a process such as deposition or sputtering, in this case, whether in the gate recess or around the gate recess
  • the first photoresist layer is covered with a gate layer 4a, and the gate layer 4a comprises a metal layer or a metal conductive composite layer, wherein the metal conductive composite layer comprises copper metal or a composite thin film layer containing copper metal and at least one The layer is located on the upper or lower metal barrier layer of the copper metal or the composite film layer containing copper metal to effectively inhibit copper diffusion;
  • the substrate 1 on which the gate layer is formed is immersed in the stripping solution, so that the photoresist on the photoresist and the gate layer above the photoresist are peeled off to form the first insulating layer 2.
  • the gate 4 has a thickness equal to the depth of the gate recess of the first insulating layer 2, so that a flat surface is formed on the substrate 1, and the process does not require copper etching;
  • the gate insulating layer 5 is deposited on the substrate 1, and an active layer is deposited on the gate insulating layer 5.
  • the active layer 6 is a patterned pattern, which may include indium (In), gallium (Ga), dynes (Zn), (Hf), tin (Sn), aluminum (A1).
  • source 9 and drain 10 are:
  • the second insulating layer 7 is formed on the substrate 1 after the active layer 6 is formed by deposition, sputtering, or the like, and is coated on the second insulating layer 7.
  • a second photoresist layer 8 is formed by a process such as coating or spraying, and after exposure and development, a second photoresist retention region and a second photoresist removal region are formed.
  • the second photoresist removal region corresponds to a position where a source recess and a drain recess are to be formed.
  • the second insulating layer 7 is etched and patterned by using the patterned second photoresist layer as a mask, the second insulating layer 7 of the second photoresist removing region is etched, and finally the source recess is formed and a drain recess, the active layer 6 partially exposes the source recess and the drain recess to be connected to the subsequently formed source and drain, and the periphery of the source trench and the drain trench is surrounded by the second insulating layer 7, wherein The photoresist on the second insulating layer 7 around the source and drain recesses is retained for subsequent stripping of the source and drain layers, which does not require copper etching; wherein the second insulating layer 7 contains silicon oxides, nitrides and oxynitrides One or more
  • the substrate 1 on which the active drain layer is formed is immersed in the stripping solution, and the second photoresist layer and the source/drain layer above the second photoresist layer are peeled off to form
  • the source 9 and the drain 10 surrounded by the second insulating layer 7, the thickness of the source 9 and the drain 10 are equal to the depths of the source and drain grooves of the second insulating layer, so that a flatness is formed on the substrate.
  • the patterned gate has no slope, which can prevent the fault of the gate insulating layer, thereby effectively blocking the copper diffusion in the TFT array substrate; and the metal barrier layer completely covers the composite copper metal or the gate or source-drain level composite containing copper metal
  • the upper surface and/or the lower surface of the film layer can well block the diffusion of copper, and more importantly, it does not need to etch copper, which reduces the cost and improves the yield.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)

Abstract

一种TFT阵列基板及其制备方法，以及包括该TFT阵列基板的显示装置，包括在第一绝缘层（2）的栅极凹槽内形成栅极（4），使得栅极（4）被第一绝缘层（2）所包围，图形化的栅极（4）不存在坡度，第一绝缘层（2）将栅极（4）与外界隔离，可防止栅绝缘层（5）的断层，进而有效阻挡薄膜晶体管阵列基板中的铜扩散。进一步地，金属阻挡层完全覆盖复合铜金属或包含铜金属的复合薄膜层的上表面和/或下表面，能够起到很好的阻挡铜扩散的作用，同时更重要的是不需要对铜进行刻蚀，降低了成本、提高了良品率。

Description

薄膜晶体管阵列基板及其制备方法、 显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管阵列基板及其制备方法、显示装置。 背景技术
目前， 制作显示器薄膜晶体管 （简称 TFT ) 阵列基板上的扫描线和数据 线一般釆用比较稳定的 Ta、 Mo、 Cr等金属或 AlNd等合金材料。 随着显示 技术的发展， 显示器的尺寸不断增大、 分辨率不断提高， 大型电视或者高分 辨率监视器等产品也要求扫描线和数据线的 RC延迟（即电阻 /电容延迟）较 小， 这就要求扫描线和数据线使用电阻率更低的材料。
在金属材料中， 铜的电阻率更低， 是能够替代现有铝和铝合金材料、 减 小 RC延迟的优选材料。 但是目前釆用铜作为布线材料还存在以下一些的问 题：
一、铜与玻璃的粘附力差，而且铜原子在半导体和氧化物中的扩散严重， 需要在铜的上下表面各增加一层阻挡层，可以提高铜导线在玻璃上的附着力， 还可以防止铜扩散。 但是经过图形化后的铜栅电极需要存在一定坡度角才能 防止栅绝缘层的断层， 这样就导致阻挡层不能完全覆盖铜薄膜的上表面， 边 界处仍有部分铜棵露于保护层外。
二、 铜的刻蚀能力差， 无论釆用湿法刻蚀还是干法刻蚀都很困难， 刻蚀 效果不理想， 而且刻蚀液开发费用较高。 发明内容
本发明的一个实施例提供一种薄膜晶体管阵列基板的制备方法， 包括以 下步骤：
在基板上形成第一绝缘层， 并在所述第一绝缘层上形成第一光刻胶层， 在形成有第一光刻胶层的第一绝缘层上形成栅极凹槽， 所述栅极凹槽的周围 被第一绝缘层包围；
在具有栅极凹槽的基板上形成栅极层； 将形成有栅极层的基板上的第一光刻胶层及第一光刻胶层以上的栅极层 剥离， 以形成被第一绝缘层包围的栅极。
在一个示例中， 在形成由第一绝缘层包围的栅极的基板上依次形成栅极 绝缘层、 有源层、 第二绝缘层；
并在所述第二绝缘层上形成第二光刻胶层， 在形成有第二光刻胶层的第 二绝缘层上形成源极凹槽和漏极凹槽， 所述源极凹槽和漏极凹槽的周围被第 二绝缘层包围， 部分有源层露出；
在具有源极凹槽和漏极凹槽的基板上形成源漏极层；
将形成有源漏极层的基板上的第二光刻胶层及第二光刻胶层以上的源漏 极层剥离， 以形成被第二绝缘层包围的源极和漏极； 所述源极和漏极接触所 述有源层。
在一个示例中， 所述在形成有第一光刻胶层的第一绝缘层上形成栅极凹 槽的步骤包括：
通过曝光、 显影， 形成第一光刻胶层保留区和第一光刻胶层去除区， 该 第一光刻胶层去除区对应于要形成所述栅极凹槽的位置；
刻蚀第一绝缘层， 第一光刻胶层去除区的第一绝缘层被刻蚀， 形成所述 栅极凹槽。
在一个示例中， 所述在形成有第二光刻胶层的第二绝缘层上形成源极凹 槽和漏极凹槽， 所述源极凹槽和漏极凹槽的周围被第二绝缘层包围， 部分有 源层露出的步骤包括：
通过曝光、 显影， 形成第二光刻胶层保留区和第二光刻胶层去除区， 该 第二光刻胶层去除区对应于要形成所述源极凹槽和所述漏极凹槽的位置； 刻蚀第二绝缘层， 第二光刻胶层去除区的第二绝缘层被刻蚀， 形成所述 源极凹槽和漏极凹槽。
在一个示例中， 形成所述栅极层的厚度与所述栅极凹槽的深度相同； 形成所述源漏极层的厚度与所述源极凹槽和漏极凹槽的深度相同。 在一个示例中， 所述形成栅极层和 /或形成源漏极层的步骤包括： 形成金属层或者形成金属导电复合层。
在一个示例中， 所述形成金属导电复合层的步骤包括：
形成铜金属薄膜或者形成包含铜金属的合金薄膜； 以及形成至少一层金属阻挡层位于所述铜金属薄膜或者所述包含铜金属 的合金薄膜的两个相反表面的至少之一上。
本发明的另一个实施例提供一种薄膜晶体管阵列基板， 包括基板、 依次 形成在所述基板上的栅极、 栅极绝缘层、 有源层、 源极和漏极， 所述基板上 形成有具有栅极凹槽的第一绝缘层， 所述栅极形成于所述栅极凹槽内。
在一个示例中， 所述栅极绝缘层和有源层上形成有具有源极凹槽和漏极 凹槽的第二绝缘层， 所述源极、 漏极分别设于所述第二绝缘层的源极凹槽和 漏极凹槽内。
在一个示例中， 所述栅极层的厚度与所述栅极凹槽的深度相同。
在一个示例中， 所述源漏极层的厚度与所述源极凹槽和漏极凹槽的深度 相同。
在一个示例中， 所述栅极、 所述源极和漏极至少之一包括金属层或者金 属导电复合层。
在一个示例中， 所述金属导电复合层包括铜金属薄膜或者包含铜金属的 合金薄膜和至少一层金属阻挡层位于所述铜金属薄膜或者所述包含铜金属的 合金薄膜的两个相反表面的至少之一上。
本发明的再一个实施例提供一种显示装置， 包括根据上述任一实施例的 薄膜晶体管阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1是本发明实施例中在基板上沉积第一绝缘层后的横截面图； 图 2是本发明实施例中涂敷第一光刻胶层并曝光、 显影后的横截面图； 图 3是本发明实施例中第一绝缘层被刻蚀后的横截面图；
图 4是本发明实施例中沉积栅极层后的横截面图；
图 5是本发明实施例中剥离第一光刻胶层及第一光刻胶层之上的栅极层 后的横截面图；
图 6是本发明实施例中沉积栅绝缘层后的横截面图； 图 7是本发明实施例中形成有源层后的横截面图；
图 8是本发明实施例中形成第二绝缘层后的横截面图；
图 9是本发明实施例中在第二绝缘层上涂敷光刻胶并曝光、 显影后的横 截面图；
图 10是本发明实施例中第二绝缘层被刻蚀后的横截面图；
图 11是本发明实施例中沉积源漏极层后的横截面图；
图 12是本发明实施例中剥离第二光刻胶及第二光刻胶层之上的源漏极 层后的横截面图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
如图 12所示，根据本发明实施例的一种薄膜晶体管阵列基板，其包括基 板 1、 自下而上依次形成在基板 1上的栅极 4、 栅极绝缘层 5、 有源层 6和源 极 9、 漏极 10。 基板 1上形成有具有栅极凹槽的第一绝缘层 2， 栅极 4形成 于该栅极凹槽内， 第一绝缘层 2可将栅极 4与外界隔离。 本发明实施例的栅 极 4形成在第一绝缘层 2的栅极凹槽内， 使得栅极被第一绝缘层 2所包围， 图形化的栅极 4不存在坡度， 可防止栅绝缘层的断层， 进而有效阻挡薄膜晶 体管 （TFT ) 阵列基板中的铜扩散。
需要指出的是， 本发明实施例中所指的基板 1可以泛指一般的基板如玻 璃基板， 也可以为形成有其它膜层或图形的基板。
栅极绝缘层 5和有源层 6上形成有具有源极凹槽和漏极凹槽的第二绝缘 层 7，源极 9和漏极 10分别形成于该第二绝缘层 7的源极凹槽和漏极凹槽内。 在源极 9和漏极 10的周围设置第二绝缘层 7， 用于将源极 9和漏极 10与外 界隔离。
栅极 4和 /或源极 9和漏极 10可包括金属层或者金属导电复合层。例如， 为了提高栅极 4与基板 1的结合力， 栅极 4和 /或源极 9和漏极 10包括金属 导电复合层， 该金属导电复合层包括铜金属薄膜或者包含铜金属的合金薄膜 和至少一层位于铜金属薄膜或者包含铜金属的合金薄膜的上层和 /或下层的 金属阻挡层， 也就是说， 金属阻挡层形成在铜金属薄膜或者包含铜金属的合 金薄膜的两个相反表面的至少之一上。
例如， 栅极 4的厚度与第一绝缘层 2的栅极凹槽的深度相等， 源极 9和 漏极 10的厚度与第二绝缘层 7的源极凹槽和漏极凹槽的深度相等。
一般来说， 栅极 4的金属阻挡层位于铜金属或包含铜金属的合金薄膜层 的上层， 以阻挡 Cu金属扩散到栅极绝缘层以及有源层中。 而源极 9和漏极 10 的金属阻挡层位于铜金属或包含铜金属的合金薄膜层的下层， 用以阻挡 Cu金属扩散到第二绝缘层 7和有源层 6中。 栅极 4和源极 9和漏极 10的金 属阻挡层的材料例如为含 Al、 In、 Ti、 Ta及 Mo等的单质金属及其合金等。
本发明实施例的一种显示装置，其包括上述技术方案所提供的 TFT阵列 基板。
本发明实施例还提供一种上述技术方案所提供的薄膜晶体管阵列基板的 制备方法， 包括以下步骤：
在基板 1上形成第一绝缘层 2， 并在该第一绝缘层 2上形成第一光刻胶 层 3， 在形成有第一光刻胶层 3的第一绝缘层 2上形成栅极凹槽， 该栅极凹 槽的周围被第一绝缘层包围；
在具有栅极凹槽的基板 1上形成栅极层；
将形成有栅极层的基板上的第一光刻胶层 3及第一光刻胶层 3以上的栅 极层剥离， 以形成被第一绝缘层包围的栅极 4。
以下为本发明薄膜晶体管阵列基板的制备方法实施例的步骤：
Sl、 如图 1-3所示， 在基板 1上形成第一绝缘层 2， 其中， 该第一绝缘 层 2的厚度与所需栅极及栅线金属复合层的厚度相等， 并在第一绝缘层 2上 釆用涂覆或喷涂等工艺形成第一光刻胶层 3， 通过曝光、 显影后， 形成第一 光刻胶层保留区和第一光刻胶层去除区。 第一光刻胶层去除区对应于要形成 栅极凹槽的位置。 以图案化的第一光刻胶层为掩模， 刻蚀第一绝缘层 2, 使 得第一光刻胶层去除区的第一绝缘层被刻蚀， 以形成栅极凹槽， 该栅极凹槽 的周围被第一绝缘层 2包围， 在栅极凹槽周围的第一绝缘层 2上的光刻胶被 保留以进行后续栅极层的剥离； 52、 如图 4所示， 在具有栅极凹槽的基板 1上釆用沉积或溅射等工艺形 成栅极层 4a， 此时， 无论是在栅极凹槽内还是在栅极凹槽周围的第一光刻胶 层上都覆盖有栅极层 4a, 该栅极层 4a包括金属层或者金属导电复合层， 其 中， 金属导电复合层包括铜金属或包含铜金属的复合薄膜层和至少一层位于 该铜金属或包含铜金属的复合薄膜层的上层或下层的金属阻挡层， 以有效抑 制铜扩散；
53、 如图 5所示， 将形成有栅极层的基板 1在剥离液中浸泡， 使得其上 的光刻胶及光刻胶以上的栅极层剥离， 以形成被第一绝缘层 2包围的栅极 4， 该栅极 4的厚度与第一绝缘层 2的栅极凹槽的深度相等， 使得在基板 1上形 成平整的表面， 此过程不需要进行铜刻蚀；
54、 如图 6-12所示， 在形成由第一绝缘层 1包围的栅极 4之后， 依次在 基板 1上形成栅极绝缘层 5、 有源层 6、 第二绝缘层 7、 源极 9和漏极 10， 如 图 6所示， 在形成由第一绝缘层 2包围的栅极 4之后， 在基板 1上沉积栅极 绝缘层 5， 并在栅极绝缘层 5上沉积有源层 6， 如图 7所示， 该有源层 6为图 案化的图形， 其可以包括铟（In )、镓（Ga )、辞（Zn )、給（Hf )、锡（Sn )、 铝（A1 )等金属元素中一种或多种形成的非晶或多晶金属氧化物半导体， 如 ZnO， InZnO(IZO) , GaZnO(GZO)， InGaZnO(IGZO) , HflnZnO(HIZO) , SnlnO(ITO), ZnSnO ( ZTO ) ， AllnZnO ( AIZO )等， 并通过一次构图工艺 形成 TFT的沟道层， 最后形成源极 9和漏极 10， 如图 8-12所示。
源极 9和漏极 10的形成过程为：
S10、 如图 8、 9和 10所示， 在形成有源层 6后的基板 1上釆用沉积、 溅射等工艺形成第二绝缘层 7， 并在该第二绝缘层 7上釆用涂覆或喷涂等工 艺形成第二光刻胶层 8, 通过曝光、 显影后， 形成第二光刻胶保留区和第二 光刻胶去除区。第二光刻胶去除区对应于要形成源极凹槽和漏极凹槽的位置。 利用图案化的第二光刻胶层作为掩模， 对第二绝缘层 7进行刻蚀图形化， 第 二光刻胶去除区的第二绝缘层 7被刻蚀， 最后形成源极凹槽和漏极凹槽， 有 源层 6部分露出源极凹槽和漏极凹槽与后续形成的源、 漏极连接， 源极凹槽 和漏极凹槽的周围被第二绝缘层 7包围， 其中， 在源极凹槽和漏极凹槽周围 的第二绝缘层 7上的光刻胶被保留以进行后续源漏极层的剥离， 此过程不需 要进行铜刻蚀； 其中， 第二绝缘层 7包含硅的氧化物、 氮化物及氮氧化物中 的一种或多种；
S20、 如图 11所示， 在具有源极凹槽和漏极凹槽的基板 1上釆用沉积或 溅射等工艺依次形成源漏极层， 该源漏极层金属层或者金属导电复合层， 其 中， 金属导电复合层包括铜金属或包含铜金属的复合薄膜层和至少一层位于 该铜金属或包含铜金属的复合薄膜层的上层或下层的金属阻挡层， 以有效抑 制铜扩散；
S30、 如图 12所示， 将形成有源漏极层的基板 1在剥离液中浸泡， 使其 上的第二光刻胶层及第二光刻胶层以上的源漏极层剥离， 形成被第二绝缘层 7包围的源极 9和漏极 10，源极 9和漏极 10的厚度与第二绝缘层的源极凹槽 和漏极凹槽的深度相等， 使得在基板上形成平整的表面， 最后完成整个 TFT 阵列基板的制备。
本发明实施例所提供的 TFT 阵列基板及其制备方法、 以及包括该 TFT 阵列基板的显示装置， 栅极形成在第一绝缘层的栅极凹槽内， 使得栅极被第 一绝缘层所包围， 图形化的栅极不存在坡度， 可防止栅绝缘层的断层， 进而 有效阻挡 TFT阵列基板中的铜扩散；且金属阻挡层完全覆盖复合铜金属或包 含铜金属的栅极或源漏级复合薄膜层的上表面和 /或下表面，能够起到很好的 阻挡铜扩散的作用， 同时更重要的是不需要对铜进行刻蚀， 降低了成本、 提 高了良品率。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。
本申请要求于 2013年 12月 4日递交的中国专利申请第 201310648419.3 号的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims

权利要求书
1、 一种薄膜晶体管阵列基板的制备方法， 包括以下步骤：
在基板上形成第一绝缘层， 并在所述第一绝缘层上形成第一光刻胶层， 在形成有第一光刻胶层的第一绝缘层上形成栅极凹槽， 所述栅极凹槽的周围 被第一绝缘层包围；
在具有栅极凹槽的基板上形成栅极层；
将形成有栅极层的基板上的第一光刻胶层及第一光刻胶层以上的栅极层 剥离， 以形成被第一绝缘层包围的栅极。
2、 如权利要求 1所述的薄膜晶体管阵列基板的制备方法， 其中， 在形成由第一绝缘层包围的栅极的基板上依次形成栅极绝缘层、有源层、 第二绝缘层；
并在所述第二绝缘层上形成第二光刻胶层， 在形成有第二光刻胶层的第 二绝缘层上形成源极凹槽和漏极凹槽， 所述源极凹槽和漏极凹槽的周围被第 二绝缘层包围， 部分有源层露出；
在具有源极凹槽和漏极凹槽的基板上形成源漏极层；
将形成有源漏极层的基板上的第二光刻胶层及第二光刻胶层以上的源漏 极层剥离， 以形成被第二绝缘层包围的源极和漏极； 所述源极和漏极接触所 述有源层。
3、 如权利要求 2所述的薄膜晶体管阵列基板的制备方法， 其中， 所述在形成有第一光刻胶层的第一绝缘层上形成栅极凹槽的步骤包括： 通过曝光、 显影， 形成第一光刻胶层保留区和第一光刻胶层去除区， 该 第一光刻胶层去除区对应于要形成所述栅极凹槽的位置；
刻蚀第一绝缘层， 第一光刻胶层去除区的第一绝缘层被刻蚀， 形成所述 栅极凹槽。
4、 如权利要求 2或 3所述的薄膜晶体管阵列基板的制备方法， 其中， 所述在形成有第二光刻胶层的第二绝缘层上形成源极凹槽和漏极凹槽， 所述源极凹槽和漏极凹槽的周围被第二绝缘层包围， 部分有源层露出的步骤 包括：
通过曝光、 显影， 形成第二光刻胶层保留区和第二光刻胶层去除区， 该 第二光刻胶层去除区对应于要形成所述源极凹槽和所述漏极凹槽的位置； 刻蚀第二绝缘层， 第二光刻胶层去除区的第二绝缘层被刻蚀， 形成所述 源极凹槽和漏极凹槽。
5、如权利要求 2-4任一项所述的薄膜晶体管阵列基板的制备方法，其中， 形成所述栅极层的厚度与所述栅极凹槽的深度相同；
形成所述源漏极层的厚度与所述源极凹槽和漏极凹槽的深度相同。
6、如权利要求 2-5任一项所述的薄膜晶体管阵列基板的制备方法，其中， 所述形成栅极层和 /或形成源漏极层的步骤包括：
形成金属层或者形成金属导电复合层。
7、 如权利要求 6所述的薄膜晶体管阵列基板的制备方法， 其中， 所述形成金属导电复合层的步骤包括：
形成铜金属薄膜或者形成包含铜金属的合金薄膜；
以及形成至少一层金属阻挡层位于所述铜金属薄膜或者所述包含铜金属 的合金薄膜的两个相反表面的至少之一上。
8、一种薄膜晶体管阵列基板，包括基板、依次形成在所述基板上的栅极、 栅极绝缘层、 有源层、 源极和漏极， 所述基板上形成有具有栅极凹槽的第一 绝缘层， 所述栅极形成于所述栅极凹槽内。
9、如权利要求 8所述的薄膜晶体管阵列基板， 其中， 所述栅极绝缘层和 有源层上形成有具有源极凹槽和漏极凹槽的第二绝缘层， 所述源极、 漏极分 别设于所述第二绝缘层的源极凹槽和漏极凹槽内。
10、 根据权利要求 8或 9所述的薄膜晶体管阵列基板， 其中，
所述栅极层的厚度与所述栅极凹槽的深度相同。
11、 根据权利要求 9所述的薄膜晶体管阵列基板， 其中，
所述源漏极层的厚度与所述源极凹槽和漏极凹槽的深度相同。
12、 如权利要求 8-11任一项所述的薄膜晶体管阵列基板， 其中， 所述栅 极、 所述源极和漏极至少之一包括金属层或者金属导电复合层。
13、如权利要求 12所述的薄膜晶体管阵列基板， 其中， 所述金属导电复 合层包括铜金属薄膜或者包含铜金属的合金薄膜和至少一层金属阻挡层位于 所述铜金属薄膜或者所述包含铜金属的合金薄膜的两个相反表面的至少之一 上。
14、 一种显示装置， 包括如权利要求 8-13任一项所述的薄膜晶体管阵列 基板。
PCT/CN2014/078546 2013-12-04 2014-05-27 薄膜晶体管阵列基板及其制备方法、显示装置 Ceased WO2015081673A1 (zh)

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