WO2015074371A1 - 一种时钟频偏检测的方法、装置和设备 - Google Patents

一种时钟频偏检测的方法、装置和设备 Download PDF

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Publication number
WO2015074371A1
WO2015074371A1 PCT/CN2014/075381 CN2014075381W WO2015074371A1 WO 2015074371 A1 WO2015074371 A1 WO 2015074371A1 CN 2014075381 W CN2014075381 W CN 2014075381W WO 2015074371 A1 WO2015074371 A1 WO 2015074371A1
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WIPO (PCT)
Prior art keywords
clock
frequency offset
tested
port
clock port
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PCT/CN2014/075381
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English (en)
French (fr)
Inventor
赵贵余
何力
李延源
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中兴通讯股份有限公司
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Publication of WO2015074371A1 publication Critical patent/WO2015074371A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays

Definitions

  • the present invention relates to the field of communications, and in particular, to a method, an apparatus, and a device for detecting a clock frequency offset.
  • BACKGROUND In various telecommunication services, PTN networks, and SDH transport networks, in order to ensure the integrity of timing transmission, there are certain requirements for network synchronization quality.
  • the entire network In the network synchronization system, by locking the upper-level clock reference source step by step, the entire network is required to lock the same clock reference source.
  • the clock synchronization of the entire network can be finally achieved by locking the mode of the upper-level clock reference source step by step. Under normal circumstances, after the clock is synchronized, the service will not have errors due to the frequency offset of the clock.
  • the frequency offset detection may also be used to determine whether there is a clock false lock phenomenon.
  • traditional clock maintenance only the clock status can be checked to see if it is locked.
  • FREQ frequency offset performance monitoring is not implemented. Therefore, it cannot be judged whether the clock quality in the network meets the requirements.
  • Embodiments of the present invention provide a clock frequency offset detection method, apparatus, and device, which solve the problem of measuring a synchronous clock frequency deviation in a communication network, requiring a test instrument and complicated operations.
  • an embodiment of the present invention provides a clock frequency offset detection method, including: determining a clock port to be tested of the clock node according to a state of each clock port of the clock node to be tested; determining that the clock port to be tested corresponds to The clock source of the clock port to be tested is obtained as a frequency offset detection signal according to the frequency offset detection signal; and the frequency offset value of the clock port to be tested is obtained according to the frequency offset detection signal.
  • the obtaining a frequency offset value of the clock port to be tested according to the frequency offset detection signal includes: acquiring a frequency offset phase of the frequency offset detection signal in a preset time And calculating a frequency offset value of the clock port to be tested according to the offset phase and a time value of the preset detection time.
  • the acquiring a frequency offset phase of the frequency offset signal in a preset time period includes: collecting a time stamp of each time synchronization message in a preset detection time; The timestamp is filtered to calculate an offset phase; and the offset phase sum of each offset phase obtained in the preset detection time is calculated.
  • determining whether the clock source corresponding to the clock port to be tested can be locked comprises: determining whether a frequency offset of a clock signal of the clock port to be tested is greater than a frequency offset threshold; Or determine whether the crystal that generates the clock source is aging.
  • when the determining whether the clock source corresponding to the clock port to be tested can be locked comprises determining whether the frequency offset of the clock signal of the clock port to be tested is greater than a lockout frequency deviation threshold
  • the method includes: obtaining the clock signal of the clock port to be tested; performing synchronous counting on the clock signal of the clock port to be tested and the preset reference clock signal in a preset counting time, and acquiring the preset counting time a first pulse number of the clock signal of the clock port to be tested and a second pulse number of the reference clock signal until the timing reaches a preset counting time; calculating a difference between the first pulse number and the second pulse number as a frequency offset value of the clock port to be tested; determining whether the frequency offset value is greater than a lockout frequency offset threshold.
  • the clock signal for acquiring the clock port to be detected is the first valid downstream clock signal of the clock port to be tested.
  • the method further includes: after obtaining the frequency offset value of the clock port to be tested according to the frequency offset detection signal, whether the obtained frequency offset value is greater than a preset a first frequency offset threshold, if yes, reporting a violation alarm; and/or comparing the obtained frequency offset value after obtaining the frequency offset value of the clock port to be tested according to the frequency offset detection signal The preset second frequency offset threshold, if yes, reports the loss of lock alarm.
  • determining the clock port to be tested according to the state of each clock port of the clock node to be tested includes: setting at least one of each clock port of the clock node to be tested as a slave clock port and/or a passive clock port The clock port serves as the clock port to be tested.
  • the time synchronization message of the clock port to be tested includes: when the clock port to be tested is a slave clock port, acquiring a time synchronization message of the slave clock port as a frequency offset detection
  • the clock port to be tested is a passive clock port
  • the time synchronization message between the clock port to be tested and its corresponding master clock port is triggered, and the time synchronization message of the clock port to be tested is obtained as the frequency offset detection. signal.
  • the present invention provides a clock frequency offset detecting device, including: at least one processor, wherein the processor is configured to determine a clock port to be tested of the clock node according to a state of each clock port of the clock node to be tested; The processor is further configured to determine whether the clock source corresponding to the clock port to be tested can be locked; if not, acquiring a time synchronization message of the clock port to be tested as a frequency offset detection signal; and according to the frequency offset The detection signal obtains a frequency offset value of the clock port to be tested.
  • an embodiment of the present invention provides a clock frequency offset detecting apparatus, where the apparatus includes a selecting module, a determining module, and a detecting module: the selecting module is configured as a port according to each clock of the clock node to be tested. The state determining the clock port to be tested; the determining module is configured to determine whether the clock source corresponding to the clock port to be tested can be locked; if not, acquiring the time synchronization message of the clock port to be tested as the frequency offset detection signal; The detecting module is configured to obtain a frequency offset value of the clock port to be tested according to the frequency offset detection signal.
  • the detecting module includes an acquiring submodule and a frequency offset calculating submodule: the acquiring submodule is configured to acquire a frequency offset phase of the frequency offset detecting signal within a preset time The frequency offset calculation sub-module is configured to calculate a frequency offset value of the clock port to be tested according to the offset phase and a time value of the preset detection time.
  • the acquiring sub-module includes an acquiring unit, a filtering unit, and a calculating unit: the collecting unit is configured to sequentially collect timestamps of time synchronization messages in a preset detection time; The filtering unit is configured to perform filtering calculation according to the time stamp to obtain an offset phase; and the calculating unit is configured to calculate an offset phase sum of each offset phase obtained in the preset detection time.
  • the determining module includes a collecting submodule, a counting submodule, a calculating difference submodule, and a loss of lock judging submodule: the collecting submodule is configured to obtain the clock port to be tested.
  • the counting module is configured to synchronously count the clock signal of the clock port to be tested and the preset reference clock signal in a preset counting time, and obtain the clock port to be tested in the preset counting time. a first pulse number of the clock signal and a second pulse number of the reference clock signal until the timing reaches a preset count time; the difference calculation sub-module is configured to calculate between the first pulse number and the second pulse number The difference value is used as the frequency offset value of the clock port to be tested; the loss of lock determination sub-module is configured to determine whether the frequency offset value is greater than a loss-locking frequency offset threshold.
  • the apparatus further includes a reporting module, configured to compare the obtained frequency offset value after obtaining the frequency offset value of the clock port to be tested according to the frequency offset detection signal If the value is greater than the preset first frequency offset threshold, if yes, the over-limit alarm is reported; and/or the obtained frequency is obtained after obtaining the frequency offset value of the clock port to be tested according to the frequency offset detection signal. Whether the bias value is greater than the preset second frequency offset threshold, and if so, reporting the loss of lock alarm.
  • the clock port to be tested of the clock node is determined according to the state of each clock port of the clock node to be tested; Then determining that the clock port to be tested corresponds to Whether the clock source can be locked; if not, the time synchronization message of the clock port to be tested is obtained as the frequency offset detection signal; finally, the frequency offset value of the clock port to be tested is obtained according to the frequency offset detection signal.
  • FIG. 1 is a schematic flowchart of a clock frequency offset detection method according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a clock signal distribution structure according to an embodiment of the present invention
  • FIG. 4 is a schematic flowchart 1 of a clock signal detection method according to an embodiment of the present invention
  • FIG. 5 is a schematic flowchart 1 of a PTP packet frequency offset detection method according to an embodiment of the present invention
  • FIG. 6 is a schematic flowchart of a method for detecting a frequency offset of a clock signal according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of an apparatus for detecting a clock frequency deviation according to an embodiment of the present invention.
  • the embodiment of the invention provides a clock frequency offset detection method, which can implement the frequency offset detection of the clock simply and accurately.
  • the clock frequency offset detection method includes the following steps: Step S101 : Determine a clock port to be tested according to a port state of each clock of the node to be tested, that is, each clock of the node to be tested. At least one slave clock port and/or passive clock port in the port is used as the port to be tested. Determine the port status of each node by observing the nodes of the network clock, such as the master clock port, the slave clock port, and the passive clock port. Select at least one slave port or passive clock port as the port to be tested.
  • Step S102 Determine whether the clock source corresponding to the clock port to be tested can be locked; if not, obtain a time synchronization message of the clock port to be tested as the frequency offset detection signal.
  • the determining whether the clock source corresponding to the clock port to be tested can be locked comprises: determining whether the frequency offset of the clock signal of the clock port to be tested is greater than a lock-off frequency offset threshold or determining whether the crystal oscillator generating the clock source is aged.
  • the time synchronization message of the slave clock port is obtained as a frequency offset detection signal; when the clock port to be tested is a passive clock port, the clock port to be tested is triggered to be corresponding to the master port. The time synchronization message between the clock ports obtains the time synchronization message of the clock port to be tested as the frequency offset detection signal.
  • Step S103 Obtain a frequency offset value of the clock port to be tested according to the frequency offset detection signal, including collecting timestamps of each time synchronization packet in a preset detection time; and performing filtering calculation according to the collected timestamp to obtain an offset Phase; calculating an offset phase sum of each offset phase obtained in a preset detection time; calculating a frequency offset value of the clock port to be tested according to the calculated offset phase and a time value of the preset detection time. Further, the data is reported to the network management system. The reporting period is 15 minutes by default, including the maximum value, the minimum value, and the average value. It supports real-time query, supports over-limit alarms, and can set alarm thresholds.
  • the function works in the active detection mode and supports manual setting to open/close.
  • step 102 it is determined whether the clock source corresponding to the clock port to be tested can be locked, and whether the crystal oscillator generating the clock source is aged is determined by manual direct observation or by other detecting methods or tools, and further, determining the clock to be tested Whether the frequency offset of the clock signal of the port is greater than the unlocking frequency offset threshold can be detected by using the physical layer clock signal, and the frequency offset performance of the clock signal of the physical layer is monitored. It can be manually specified, which means manually selecting the clock signal or automatic detection in the signal to which the port is to be detected. According to the current node, an optimal clock is selected from all the extracted clocks according to the SSM algorithm, and the automatic detection detects the most Excellent pumping clock. As further illustrated in FIG.
  • node 21 is NE21
  • node 22 is NE22
  • node 23 is NE23
  • node 24 is NE24
  • the port 1 of the NE24 that is, the port port is the slave clock port
  • the port 2 port 2 port is the passive clock port.
  • the solid arrow between the nodes in the figure indicates that the pumping clock is configured between the two points and is consistent with the current clock transmission direction.
  • the dotted arrow between the nodes in the figure indicates that the pumped clock is configured between the two points, but the clock does not take effect.
  • the nodes NE21, NE22, and NE23 have a clock signal in one direction, that is, the pumped clock of the port 1 and the Port1 port is the current clock signal of the node, and the downstream clock signal of the current node is calculated according to the SSM protocol stack, and the first effective downstream clock is used.
  • the signal is the clock signal to be detected. That is to say, with its downstream clock signal, the first valid downstream clock signal is used as the detection clock signal.
  • Clock signal (1) The pumped clock of the Portl port of the node NE24 is the current clock signal of the node; (2) The pumped clock of the port 2 of the node NE24, that is, the port 2 port is the clock signal in the node priority list.
  • the port 1 of the node NE24 is the current clock signal of the node, the first valid downstream clock signal of the downstream clock signal of the node NE24 is used as the detection clock signal; if the port clock of the port 2 port of the node NE24 is used For the clock signal in the node priority list, manually designating the detection clock signal, that is, triggering the clock synchronization between the port and its corresponding master clock port, acquires the clock signal of the passive clock port as a detection signal. It is worth noting that the port 2 ports of nodes NE22 and NE23 are used as the master clock port.
  • Step S401 Acquire The clock signal of the clock port is measured, wherein the acquisition of the clock signal includes manual designation, that is, manually selecting a clock signal in the signal to be detected which port is incoming or automatically detecting, that is, the current node selects one of the most selected clocks according to the SSM algorithm. Excellent clock, automatic detection detects this optimal pumping clock.
  • Step S402 Synchronously counting the clock signal of the clock port to be tested and the preset reference clock signal within a preset counting time, and acquiring the first pulse number and the reference clock signal of the clock signal of the clock port to be tested in the preset counting time. The second number of pulses until the timer reaches the preset count time. Specifically, the clock signal of the clock port to be tested and the preset reference clock signal are latched, wherein the clock signal of the port to be tested and the preset reference clock signal are the clock signal of the port to be tested and the preset reference clock signal.
  • the latching that is, the clock signal of the port to be tested and the preset reference clock signal, simultaneously with the rising clock edge or the falling clock edge, that is, the two signals need to be synchronously locked.
  • the system clock signal is the clock of the device under test itself.
  • the time counter may be a system clock signal or a frequency division or multiplication signal of the system clock source.
  • Step S403 Calculate a difference between the first pulse number and the second pulse number as a frequency offset value of the clock port to be tested.
  • Step S404 Determine whether the frequency offset value is greater than a lockout frequency offset threshold. Specifically, the value calculated in step S403 is compared with a preset unlocking frequency offset threshold, and if the value is greater than the preset unlocking frequency deviation threshold, a lockout warning is issued.
  • the acquiring the synchronization packet is specifically: when the clock port to be tested is the slave clock port, the time synchronization packet of the slave clock port is obtained as the frequency offset detection signal; when the clock port to be tested is the passive clock port, The time synchronization message between the clock port to be tested and the corresponding master clock port is triggered, and the time synchronization message of the clock port to be tested is obtained as the frequency offset detection signal.
  • the detection packet includes the time-synchronized packet that is detected as 1588 time synchronization, that is, the packet from the slave port or the device triggers the transmission of the 1588 packet from the passive port. Message.
  • the master port the port that publishes the synchronization time
  • the slave port the port that receives the synchronization time
  • the passive port the port that does not receive the synchronization time or the synchronization time.
  • node 11 is NE11
  • node 12 is NE12
  • node 13 is NE13
  • node 14 is NE14
  • node 15 is NE15
  • node 16 is NE16.
  • the connection between the nodes in the figure indicates that 1588 time synchronization is configured between the two points, and the two ports connected are PTP ports.
  • the direction of the arrow of the connection is the PTP time synchronization direction.
  • port 1 is used as the port port
  • port 2 is the port 2 port
  • the current port port status of each node port is: NE11 Portl: master
  • NE12 Port3 master NE 13 Portl: slave
  • NE15 Port2 master NE 16 Portl: slave
  • the NE16 Port2 master shows that there are slave ports for the nodes NE12, NE13, NE15, and NE 16, that is, there are 1588 time synchronization time synchronization messages, which can directly use the packets of the slave port as the signal to be tested.
  • For the port of the port there is a slave port and a passive port. Therefore, you can select either the slave port or the packet of the passive port.
  • the packets of the passive port need to be sent by the device to send 1588.
  • the master sends a message to it, that is, for the node NE14, it can detect the time synchronization message of the 1588 time synchronization of the node NE14 Port1.
  • the 1588 packet triggered by the device on the node NE14 Port2 can be detected.
  • the above step 103 further includes: recording the time offset phase offset value, that is, the offset value, in the detection time, accumulating the phase sum, and calculating the frequency offset according to the detection time and the phase sum, and the detecting time is the current time being TO, After the time T, the time is T0+T. Further, the following steps are included in conjunction with FIG.
  • Step S501 Collect timestamps of each time synchronization message in sequence in a preset detection time.
  • Step S502 Perform filtering calculation according to the timestamp to obtain an offset phase.
  • Step S503 Calculate the offset phase sum of the offset phases obtained in the preset detection time.
  • Step S504 Calculate the frequency offset value of the clock port to be tested according to the calculated offset phase and the time value of the preset detection time.
  • This embodiment is specifically described with reference to the node 24 of FIG. 2 and FIG. 6, for example, the frequency offset estimation is performed by the node ⁇ 24 in FIG. 2, wherein the detection signal monitoring mode selects the frequency deviation performance monitoring of the current detection signal FREQ, that is, the slave port. signal.
  • the detection clock signal is the current reference clock signal, that is, the clock signal carried by the port of the node NE24 Port1 is used as the detection signal.
  • the time counter, the reference signal is the node NE24 system clock signal, and the locked multiplier signal is used as the time counter.
  • the time counter, the reference signal is the node NE24 system clock, and the locked multiplier signal is used as the time counter.
  • the system clock signal is a clock signal of the device to be tested itself.
  • the time counter may be a system clock source, a frequency division or multiplication signal of the system clock source, or a system clock signal.
  • Step S601 Extracting the test signal from the slave clock port (NE24 Portl port), that is, from the NE24
  • the Portl port extracts the clock signal as a detection signal, that is, the first valid downstream clock signal of its port as a detection signal.
  • Step S602 latching the start rising clock edge of the detection signal, initializing the time counter, and setting the time counter to 0. That is to say, it is necessary to simultaneously process the detection signal and the reference clock signal simultaneously, and at the same time, ensure the accuracy of the measured data.
  • Step S603 When detecting the Nth pulse of the signal, the time counter is read, and the current value of the time counter is M.
  • Step S604 Calculate the current frequency offset value according to the N and M values, that is, calculate the difference as the frequency offset value according to the first pulse number M and the second pulse number N obtained in the foregoing, that is, the current detection clock signal.
  • the frequency offset value that is, the frequency offset value of the current port clock signal relative to the primary port, that is, the frequency offset value relative to the clock signal of the primary clock port.
  • the frequency offset calculation for other nodes and other ports can be implemented, but the acquisition of the port clock signal of the detection signal is different, and does not affect the solution of the present invention.
  • the device reports the result to the network management, and the reported content is the frequency offset estimation value and the detection clock signal information of the detection clock signal relative to the system clock.
  • the frequency offset detection is performed on the slave port and the passive port of the NE 14 , which includes: acquiring the PTP port status of the node NE 14 , are: (1) NE14 port2: passive (2) NE14 portl: slaver.
  • the detection result is further reported; the reported detection result specifically includes the reported frequency offset value and the detection signal information.
  • the reported content is a frequency offset estimation value (ppb) of the reference source relative to the system clock, and the detection clock source information, the reported content is a frequency offset estimation value of the slaver port relative to the master, and the corresponding ptp logical port number or the reported content is a passive port.
  • the present invention further provides a clock frequency offset detecting device. As shown in FIG.
  • the device includes: a selecting module, a determining module, and a detecting module, wherein: the selecting module is configured to determine a clock to be tested according to a port state of each clock of the clock node to be tested.
  • the determining module is configured to determine whether the clock source corresponding to the clock port to be tested can be locked; if not, obtaining the time synchronization message of the clock port to be tested as the frequency offset detection signal; and the detecting module is configured to detect the signal according to the frequency offset Get the frequency offset value of the clock port to be tested.
  • the determining module determines, according to the port state of each clock of the clock node to be tested, the clock port to be tested, including: at least one of the clock ports and/or the passive clock port of the clock node to be tested as the clock port to be tested. Further, the determining, by the determining module, the time synchronization packet of the clock port to be tested includes: when the clock port to be tested is the slave clock port, obtaining the time synchronization packet of the slave clock port as the frequency offset detection signal; when the clock port to be tested is passive When the clock port is used, the time synchronization message between the clock port to be tested and its corresponding master clock port is triggered, and the time synchronization message of the clock port to be tested is obtained as the frequency offset detection signal.
  • the foregoing detection module includes an acquisition submodule and a frequency offset calculation submodule, wherein the acquisition submodule is configured to acquire a frequency offset phase of the frequency offset detection signal within a preset time; and the frequency offset calculation submodule is set to be based on the offset The phase value of the phase and the preset detection time is used to calculate the frequency offset value of the clock port to be tested.
  • the acquiring sub-module includes an acquiring unit, a filtering unit, and a calculating unit, where the collecting unit is configured to collect a timestamp of each time synchronization message within a preset detection time; the filtering unit is set according to the timestamp Performing a filtering calculation to obtain an offset phase; the calculating unit is configured to calculate an offset phase sum of each offset phase obtained within a preset detection time.
  • the determining module includes a collecting sub-module, a counting sub-module, a calculating difference sub-module and a loss-lock judging sub-module, wherein the collecting sub-module is configured to acquire a clock signal of the clock port to be tested; the counting sub-module is set to be pre-designed The clock signal of the clock port to be measured and the preset reference clock signal are synchronously counted in a plurality of times, and the first pulse number of the clock signal of the clock port to be tested and the second pulse number of the reference clock signal are obtained during the preset counting time.
  • the difference calculation sub-module is set to calculate the first pulse number and the second pulse The difference between the impulses is used as the frequency offset value of the clock port to be tested; the loss of lock determination sub-module is set to determine whether the frequency offset value is greater than the loss-locking frequency offset threshold.
  • the device further includes a reporting module configured to: after obtaining a frequency offset value of the clock port to be tested according to the frequency offset detection signal, whether the compared frequency offset value is greater than a preset first frequency offset threshold, if And reporting the over-limit alarm; and/or, after obtaining the frequency offset value of the clock port to be tested according to the frequency offset detection signal, comparing whether the obtained frequency offset value is greater than a preset second frequency offset threshold, and if so, Then the lock alarm is lost.
  • the invention also provides a clock frequency offset detecting device, the frequency offset detecting device comprising at least one processor.
  • the processor is configured to determine a clock port to be tested of the clock node according to the state of each clock port of the clock node to be tested; and determine whether the clock source corresponding to the clock port to be tested can be locked; if not, obtain the clock port to be tested.
  • the time synchronization message is used as the frequency offset detection signal; and the frequency offset value of the clock port to be tested is obtained according to the frequency offset detection signal.
  • the processor in this embodiment may specifically invoke the corresponding program instruction to implement the foregoing functions.
  • the clock frequency offset detecting apparatus in this embodiment may further include a memory for storing program instructions and calling by the processor.
  • An embodiment of the present invention provides a storage medium, where the storage medium is executed according to the following instructions: determining a clock port to be tested of the clock node according to a state of each clock port of the clock node to be tested; determining a clock source corresponding to the clock port to be tested If it is not, the time synchronization message of the clock port to be tested is obtained as a frequency offset detection signal; and the frequency offset value of the clock port to be tested is obtained according to the frequency offset detection signal.
  • the frequency offset detecting device in this embodiment may be any hardware entity device of a specific storage function and processing function in the clock synchronization network.
  • clock synchronization is implemented between each base station, and the frequency offset detecting device may be disposed in each base station, and may also be configured to detect clock synchronization of the network in the mobile terminal.
  • the detecting device may be set in the server, or may be set in each technical terminal to detect the clock synchronization to the local network.
  • each module/unit in the above embodiment may be implemented in the form of hardware or in the form of a software function module.
  • the invention is not limited to any specific form of combination of hardware and software.
  • the above is only a preferred embodiment of the present invention, and of course, the present invention may be embodied in various other embodiments without departing from the spirit and scope of the invention. Corresponding changes and modifications are intended to be included within the scope of the appended claims.

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Abstract

本发明提供的时钟频偏检测方法、装置和设备，属于通信领域。在通信网络中，根据待测时钟节点各时钟端口的状态确定该时钟节点的待测时钟端口；然后判断该待测时钟端口对应的时钟源是否能被锁定；如否，则获取所述待测时钟端口的时间同步报文作为频偏检测信号；最后根据所述频偏检测信号得到所述待测时钟端口的频偏值。可以实现在通信网络中不依靠其他的仪器设备，实现对通信网络中的同步时钟进行频偏检测，从而判断是否真正实现时钟同步，是否存在假同步现象，更加精确简单的实现对网络时钟频偏检测。

Description

一种时钟频偏检测的方法、 装置和设备
技术领域 本发明涉及通信领域， 具体涉及一种时钟频偏检测的方法、 装置和设备。 背景技术 各种电信业务、 PTN网络和 SDH传送网中， 为确保定时传输的完整性， 对网同 步质量有一定要求。 在网同步体系中， 通过逐级锁定上一级时钟参考源的方法， 最终 要求整网锁定同一个时钟基准源。 通过逐级锁定上一级时钟参考源的模式最终可实现全网的时钟同步。正常情况下， 时钟同步后， 业务不会出现因为时钟存在频偏而引起的误码。 但是， 当需要了解时钟 网络中的两点之间是否存在频偏， 是否真正锁定时， 需要一种频偏检测技术。 另外， 当网络传输的业务产生了误码， 逐点分析时钟锁定情况显示已经锁定时， 也可以通过 频偏检测来确定是否存在着时钟假锁现象。 在传统的时钟维护中， 只能通过时钟状态察看是否锁定， 未实现 FREQ频偏性能 监控， 因此并不能真正判断网络中的时钟质量是否符合要求。 当现场出现了业务受损 现象， 只能通过仪表现场测量， 才能确定是否是因为频偏而引起的故障， 设备还无法 实现不依靠仪表的情况下， 测量频偏， 检测比较麻烦， 操作复杂。 发明内容 本发明实施例提供了一种时钟频偏检测方法、 装置和设备， 解决通信网络中测量 同步时钟频率偏差需要测试仪表且复杂操作的问题。 根据本发明的一个方面， 本发明实施例提供了一种时钟频偏检测方法,包括： 根据待测时钟节点各时钟端口的状态确定该时钟节点的待测时钟端口； 判断该待测时钟端口对应的时钟源是否能被锁定； 如否， 则获取所述待测时钟端 口的时间同步报文作为频偏检测信号； 根据所述频偏检测信号得到所述待测时钟端口的频偏值。 在本发明的一种实施例中， 所述根据所述频偏检测信号得到所述待测时钟端口的 频偏值包括： 在预设时间内， 获取所述频偏检测信号的频偏相位和； 根据所述偏移相位和和所述预设的检测时间的时间值计算所述待测时钟端口的频 偏值。 在本发明的一种实施例中， 所述在预设时间内， 获取所述频偏信号的频偏相位和 包括： 在预设的检测时间内， 采集各时间同步报文的时间戳； 根据所述时间戳进行滤波计算得到偏移相位； 计算所述预设的检测时间内得到的各偏移相位的偏移相位和。 在本发明的一种实施例中， 所述判断所述待测时钟端口对应的时钟源是否能被锁 定包括： 判断所述待测时钟端口的时钟信号的频偏是否大于失锁频偏阈值； 或判断产生所述时钟源的晶振是否老化。 在本发明的一种实施例中， 当所述判断所述待测时钟端口对应的时钟源是否能被 锁定包括判断所述待测时钟端口的时钟信号的频偏是否大于失锁频偏阈值时， 包括： 所述获取待测时钟端口的时钟信号； 在预设计数时间内对所述待测时钟端口的时钟信号和预设的参考时钟信号进行同 步计数， 获取该预设计数时间内所述待测时钟端口的时钟信号的第一脉冲数和所述参 考时钟信号的第二脉冲数， 直到计时达到预设计数时间； 计算第一脉冲数与所述第二脉冲数之间的差值作为所述待测时钟端口的频偏值； 判断所述频偏值是否大于失锁频偏阈值。 在本发明的一种实施例中， 所述获取待检测时钟端口的时钟信号为所述待测时钟 端口的第一条有效下游时钟信号。 在本发明的一种实施例中， 所述方法还包括： 在根据所述频偏检测信号得到所述 待测时钟端口的频偏值后， 比较得到的所述频偏值是否大于预设的第一频偏门限值， 若是， 则上报越限告警； 和 /或在根据所述频偏检测信号得到所述待测时钟端口的频偏 值后， 比较得到的所述频偏值是否大于预设的第二频偏门限值， 若是， 则上报失锁告 警。 在本发明的一种实施例中， 根据待测时钟节点各时钟端口的状态确定待测时钟端 口包括： 将待测时钟节点各时钟端口中的至少一个状态为从时钟端口和 /或被动时钟端口 的时钟端口作为待测时钟端口。 在本发明的一种实施例中， 所述待测时钟端口的时间同步报文包括： 当所述待测时钟端口为从时钟端口时， 获取该从时钟端口的时间同步报文作为频 偏检测信号； 当所述待测时钟端口为被动时钟端口时， 触发该待测时钟端口与其对应的主时钟 端口之间的时间同步报文， 获取该待测时钟端口的时间同步报文作为频偏检测信号。 为解决上述技术问题，本发明提供一种时钟频偏检测设备，包括:至少一个处理器， 所述处理器设置为根据待测时钟节点各时钟端口的状态确定该时钟节点的待测时 钟端口； 所述处理器还设置为判断该待测时钟端口对应的时钟源是否能被锁定； 如否， 则 获取所述待测时钟端口的时间同步报文作为频偏检测信号； 并根据所述频偏检测信号 得到所述待测时钟端口的频偏值。 根据本发明的另一方面， 本发明实施例提供了一种时钟频偏检测装置， 所述装置 包括选择模块、 判断模块和检测模块： 所述选择模块设置为根据待测时钟节点各时钟的端口状态确定待测时钟端口； 所述判断模块设置为判断该待测时钟端口对应的时钟源是否能被锁定； 如否， 则 获取所述待测时钟端口的时间同步报文作为频偏检测信号； 所述检测模块设置为根据所述频偏检测信号得到所述待测时钟端口的频偏值。 在本发明的一种实施例中， 所述检测模块包括获取子模块和频偏计算子模块： 所述获取子模块设置为在预设时间内， 获取所述频偏检测信号的频偏相位和； 所述频偏计算子模块设置为根据所述偏移相位和和所述预设的检测时间的时间值 计算所述待测时钟端口的频偏值。 在本发明的一种实施例中，所述获取子模块包括采集单元、滤波单元和计算单元： 所述采集单元设置为在预设的检测时间内， 依次采集各时间同步报文的时间戳； 所述滤波单元设置为根据所述时间戳进行滤波计算得到偏移相位； 所述计算单元设置为计算所述预设的检测时间内得到的各偏移相位的偏移相位 和。 在本发明的一种实施例中， 所述判断模块包括采集子模块、 计数子模块、 计算差 值子模块和失锁判断子模块： 所述采集子模块设置为获取所述待测时钟端口的时钟信号； 所述计数模块设置为在预设计数时间内对所述待测时钟端口的时钟信号和预设的 参考时钟信号进行同步计数， 获取该预设计数时间内所述待测时钟端口的时钟信号的 第一脉冲数和所述参考时钟信号的第二脉冲数， 直到计时达到预设计数时间； 所述差值计算子模块设置为计算第一脉冲数与所述第二脉冲数之间的差值作为所 述待测时钟端口的频偏值； 所述失锁判断子模块设置为判断所述频偏值是否大于失锁频偏阈值。 在本发明的一种实施例中， 所述装置还包括上报模块， 设置为在根据所述频偏检 测信号得到所述待测时钟端口的频偏值后， 比较得到的所述频偏值是否大于预设的第 一频偏门限值， 若是， 则上报越限告警； 和 /或在根据所述频偏检测信号得到所述待测 时钟端口的频偏值后， 比较得到的所述频偏值是否大于预设的第二频偏门限值，若是， 则上报失锁告警。 本发明的上述实施例具有以下有益效果： 在本发明上述实施例提供的时钟频偏检测方法、 装置和设备中， 根据待测时钟节 点各时钟端口的状态确定该时钟节点的待测时钟端口； 然后判断该待测时钟端口对应 的时钟源是否能被锁定； 如否， 则获取待测时钟端口的时间同步报文作为频偏检测信 号； 最后根据频偏检测信号得到待测时钟端口的频偏值。 该检测过程并不需要任何配 套的测试仪表； 且相对现有使用测试仪表进行检测的操作更为简单， 也不会因为测试 仪表不准等因素影响测试的结果， 因此得到的测试结果也更为精确。 附图说明 图 1为本发明一种实施例提供的时钟频偏检测方法流程示意图； 图 2为本发明一种实施例提供的时钟信号分布结构示意图； 图 3为本发明一种实施例提供的 PTP报文分布结构示意图； 图 4为本发明一种实施例提供的基于时钟信号检测方法流程示意图一； 图 5为本发明一种实施例提供的基于 PTP报文频偏检测方法流程示意图一； 图 6为本发明一种实施例提供的时钟信号频偏检测方法流程示意图二； 以及 图 7为本发明一种实施例提供的检测时钟频率偏差的装置结构示意图。 具体实施方式 下面通过具体实施方式结合附图对本发明实施例作进一步详细说明。 目前为了实现网络时钟同步采用通过逐级锁定上一级时钟参考源的方法， 最终要 求整网锁定同一个时钟基准源。 如果需要判断网络中两点是否真正锁定时， 需要一种 频偏检测技术。 本发明实施例提供一种时钟频偏检测方法， 可以简单准确的实现对时 钟的频偏检测， 下面结合具体的方法进行进一步的说明。 请参见图 1所示， 本实施例提供的时钟频偏检测方法， 其包括以下步骤： 步骤 S101 : 根据待测节点各时钟的端口状态确定待测时钟端口， 也就是说将待测 节点各时钟端口中的至少一个从时钟端口和 /或被动时钟端口作为待测端口。通过对网 络时钟的各个节点观察， 确定各个节点的端口状态， 如为主时钟端口， 从时钟端口， 被动时钟端口。 选择至少存在一个从时钟端口或被动时钟端口作为待测端口。 如果不 存在， 该节点就不能作为待测节点。 步骤 S102: 判断该待测时钟端口对应的时钟源是否能被锁定； 如否， 则获取待测 时钟端口的时间同步报文作为频偏检测信号。 其中， 判断待测时钟端口对应的时钟源 是否能被锁定包括： 判断待测时钟端口的时钟信号的频偏是否大于失锁频偏阈值或判 断产生时钟源的晶振是否老化。 进一步， 当待测时钟端口为从时钟端口时， 获取该从 时钟端口的时间同步报文作为频偏检测信号； 当待测时钟端口为被动时钟端口时， 触 发该待测时钟端口与其对应的主时钟端口之间的时间同步报文， 获取该待测时钟端口 的时间同步报文作为频偏检测信号。 步骤 S103: 根据频偏检测信号得到待测时钟端口的频偏值， 包括在预设的检测时 间内， 依次采集各时间同步报文的时间戳； 根据所采集的时间戳进行滤波计算得到偏 移相位； 计算在预设的检测时间内得到的各偏移相位的偏移相位和； 根据计算得到偏 移相位和和该预设的检测时间的时间值计算该待测时钟端口的频偏值。 进一步， 支持向网管上报数据， 上报周期默认 15分钟， 包含最大值， 最小值， 平 均值； 支持实时查询， 支持越限告警， 并可设置告警门限值。 具体包括在根据检测信 号得到待测时钟端口的频偏值后，比较得到的频偏值是否大于预设的第一频偏门限值， 若是， 则上报越限告警； 和 /或在根据检测信号得到待测时钟端口的频偏值后， 比较得 到的频偏值是否大于预设的第二频偏门限值， 若是， 则上报失锁告警。 进一步， 该功能工作在主动检测模式， 支持人工设置为打开 /闭塞方式。 在上述步骤 102中， 判断该待测时钟端口对应的时钟源是否能被锁定， 判断产生 时钟源的晶振是否老化， 可以通过人工直接观察或通过其他检测方法或工具进行， 进 一步， 判断待测时钟端口的时钟信号的频偏是否大于失锁频偏阈值可采用物理层时钟 信号作为检测， 通过对物理层的时钟信号进行频偏性能监控。 可以人工指定， 就是指 人工选择要检测哪个端口进来的信号中的时钟信号或自动检测， 根据当前节点会根据 SSM算法，从所有抽时钟中选择一个最优的时钟， 自动检测就检测这条最优的抽时钟。 结合图 2进一步进行详细说明： 如图 2所示， 时钟域内有 1个时钟源和 4个节点： 节 点 21即 NE21、 节点 22即 NE22、 节点 23即 NE23、 节点 24即 NE24, 需要说明的是 对于节点 24即 NE24的端口 1即 Portl端口为从时钟端口， 端口 2即 Port2端口为被 动时钟端口。 其中， 图中节点之间的实线箭头表示两点之间配置了抽时钟， 并且与当 前时钟的传递方向一致。其中， 图中节点之间的虚线箭头表示两点之间配置了抽时钟， 但是时钟并未生效。 进一步的， 节点 NE21、 NE22、 NE23有一个方向的时钟信号， 即 是端口 1即 Portl端口的抽时钟为节点当前时钟信号， 根据 SSM协议栈计算当前节点 下游时钟信号， 以第一条有效下游时钟信号为待检测时钟信号。 也就是说以其下游时 钟信号， 第一条有效下游时钟信号作为检测时钟信号。 对于节点 NE24有两个方向的 时钟信号：（1 )节点 NE24的 Portl端口的抽时钟为节点当前时钟信号；（2)节点 NE24 的端口 2即 Port2端口的抽时钟为节点优先级列表中的时钟信号。如果采用节点 NE24 的端口 1即 Portl端口的抽时钟为节点当前时钟信号，就以节点 NE24的下游时钟信号 的第一条有效下游时钟信号作为检测时钟信号；如果采用节点 NE24的 Port2端口的抽 时钟为节点优先级列表中的时钟信号， 就人工指定检测时钟信号也就是触发该被端口 与其对应的主时钟端口之间的时钟同步， 获取该被动时钟端口的时钟信号作为检测信 号。 需要值得注意的是节点 NE22、 NE23的 Port2端口作为主时钟端口。 进一步， 当判断待测时钟端口对应的时钟源是否能被锁定包括判断待测时钟端口 的时钟信号的频偏是否大于失锁频偏阈值时包括以下步骤结合图 4进行说明： 步骤 S401 : 获取待测时钟端口的时钟信号， 其中获取时钟信号包括人工指定， 就 是指人工选择要检测哪个端口进来的信号中的时钟信号或者自动检测， 就是当前节点 会根据 SSM算法， 从所有抽时钟中选择一个最优的时钟， 自动检测就检测这条最优的 抽时钟。 步骤 S402:在预设计数时间内对待测时钟端口的时钟信号和预设的参考时钟信号 进行同步计数， 获取该预设计数时间内待测时钟端口的时钟信号的第一脉冲数和参考 时钟信号的第二脉冲数， 直到计时达到预设计数时间。 具体为对待测时钟端口的时钟 信号和预设的参考时钟信号进行锁存， 其中锁存待测端口的时钟信号和预设的参考时 钟信号即对待测端口的时钟信号和预设的参考时钟信号进行锁存， 也就是对待测端口 的时钟信号和预设的参考时钟信号的同时对其上升时钟沿或者下降时钟沿也就是说需 要对两个信号进行同步锁定。 系统时钟信号为待测设备本身的时钟。 更进一步的， 时 间计数器， 可以是系统时钟信号， 也可以是系统时钟源的分频或者倍频信号。 当锁存 成功时， 开始计时， 获取该检测时间内待测时钟端口的时钟信号的第一脉冲数和参考 时钟信号的第二脉冲数， 直到计时达到预设检测时间， 具体包括在检测时间内， 当锁 定成功时， 就开始对待检测时钟信号以及参考时钟信号的通过的脉冲数也就是上升沿 或者下降沿的次数。 当计时到达预设的检测时间， 就读取当时待测时钟端口的时钟信 号的脉冲数为第一脉冲数， 参考时钟信号的脉冲数为第二脉冲数。 步骤 S403 : 计算第一脉冲数与第二脉冲数之间的差值作为待测时钟端口的频偏 值。 步骤 S404: 判断频偏值是否大于失锁频偏阈值。 具体为将步骤 S403计算所得的 值， 通过与预设的失锁频偏阈值进行比较， 如果其值大于预设的失锁频偏阈值就发出 失锁警告。 在上述步骤 102中， 获取同步报文具体为当待测时钟端口为从时钟端口时， 获取 该从时钟端口的时间同步报文作为频偏检测信号；当待测时钟端口为被动时钟端口时， 触发该待测时钟端口与其对应的主时钟端口之间的时间同步报文， 获取该待测时钟端 口的时间同步报文作为频偏检测信号。 结合图 3进一步进行详细说明： 如图 3所示， 检测报文具体包括检测报文为 1588时间同步的时间同步报文即来自 slaver端口的报文 或设备触发发送 1588报文即来自 passitive端口的报文。 其中， 主端口 (master Port):发 布同步时间的端口， 从端口（slave Port):接收同步时间的端口， 被动端口 (passive Port): 既不接收同步时间、 也不对外发布同步时间的端口。 结合图 3进一步进行详细说明： 如图 3所示， 时钟域内有 6个节点： 节点 11即 NE11、 节点 12即 NE12、 节点 13即 NE13、 节点 14即 NE14、 节点 15即 NE15、 节点 16即 NE16。 其中， 图中节点之间的 连线表示两点之间配置了 1588时间同步， 连线的两个端口为 PTP端口。 其中， 连线 的箭头方向为 PTP时间同步方向。其中，图中节点之间的虚线表示两点之间存在 passive 端口。 需要说明的是这里把端口 1作为 Portl端口， 端口 2作为 Port2端口， 当前各节 点端口的 FTP端口状态： NE11 Portl: master
NE11 Port2: master
NE 12 Portl: slave
NE12 Port2: master
NE12 Port3: master NE 13 Portl: slave
NE14 Portl: slave
NE14 Port2: passive
NE15 Portl: slave
NE15 Port2: master NE 16 Portl: slave
NE16 Port2: master 由图可知对于节点 NE12、 NE13、 NE15、 NE 16存在 slaver端口， 也就是说存在 1588时间同步的时间同步报文， 可以直接以其 slaver端口的报文作为待测信号也就是 Portl端口的报文；对于节点 NE14既存在 slaver端口又存在 passive端口，所以既可以 选择 slaver端口的报文又可以选择 passive端口的报文， 对于 passive端口的报文需要 通过设备触发其发送 1588报文， 再检测其报文， 既触发相邻节点 NE16 Port2: master 给其发送报文，也就是说对于节点 NE14来说，既可以通过检测节点 NE14 Portl的 1588 时间同步的时间同步报文， 也可以检测节点 NE14 Port2的通过设备触发的 1588报文。 上述步骤 103还包括在在检测时间内，记录时间同步的相位偏移量值即 offset值， 累加得到相位和， 频偏估算值根据检测时间与相位和计算得到,检测时间为当前时间为 TO, 经过时间 T后， 时间为 T0+T。 进一步包括以下步骤包括结合图 5进行说明： 步骤 S501 : 在预设的检测时间内， 依次采集各时间同步报文的时间戳。 步骤 S502: 根据时间戳进行滤波计算得到偏移相位。 步骤 S503: 计算预设的检测时间内得到的个偏移相位的偏移相位和。 步骤 S504:根据计算得到偏移相位和和预设的检测时间的时间值计算待测时钟端 口的频偏值。 本实施例以图 2中节点 24以及结合图 6进行具体说明例如以图 2中的节点 ΝΕ24 进行频偏估算， 其中检测信号监控方式选择对当前检测信号 FREQ频偏性能监控也就 是说对从端口信号。 其中， 检测时钟信号为当前参考时钟信号， 即节点 NE24 Portl端 口所携带的时钟信号作为检测信号。 时间计数器， 参考信号为节点 NE24系统时钟信 号， 锁定后的倍频信号作为时间计数器。 时间计数器， 参考信号为节点 NE24系统时 钟， 锁定后的倍频信号作为时间计数器。 进一步的， 系统时钟信号为待测设备本身的 时钟信号。 更进一步的， 时间计数器， 可以是系统时钟源， 也可以是系统时钟源的分 频或者倍频信号， 也可为系统时钟信号。 具体实施包括以下步骤： 步骤 S601 : 从从时钟端口（NE24 Portl端口）中提取测试信号，也就是说从 NE24
Portl端口提取时钟信号为检测信号，也就是以其端口的第一条有效下游时钟信号作为 检测信号。 步骤 S602:锁存检测信号的起始上升时钟沿,初始化时间计数器，将时间计数器设 置为 0。 也就是说需要同时对检测信号和参考时钟信号同步处理， 同时进行保证测得 数据的准确性。 步骤 S603 : 检测信号的第 N个脉冲时， 读取时间计数器,时间计数器当前数值为 M。 也就是说在检测时间内， 或者说在一段时间内， 或者说到达指定预设的检测时间， 对检测信号和参考信号的脉冲数进行统计， 检测信号， 也就是检测时钟信号的脉冲数 为第一脉冲数为 N， 参考信号也就是参考时钟信号， 也就是时间计数器当前数， 也就 是参考信号的脉冲数为第二脉冲数 M。 步骤 S604: 根据 N和 M值计算当前频偏值， 也就是说根据前面所得到的第一脉 冲数 M和第二脉冲数 N，计算其差值为频偏值，也就是为当前检测时钟信号的频偏值， 也就是当前端口时钟信号相对于主端口的频偏值， 也就是相对于主时钟端口时钟信号 的频偏值。 同理对于其他节点以及其他端口的频偏计算都能实现， 只是将检测信号的端口时 钟信号的获取有一定的不同， 不影响本发明的方案。 进一步上报检测结果， 获得频偏结果后， 设备上报结果给网管， 上报内容为检测 时钟信号相对系统时钟的频偏估算值和检测时钟信号信息。 进一步， 针对部署 1588时间同步的网络， 对相邻的 2个节点设备， 当输入参考频 偏过大或晶振老化时， 无法锁定时钟源， 导致无法进行时钟同步时， 或者根据上报的 失锁警告得知无法进行时钟同步， 支持通过相邻节点之间的 PTP事件报文实现频偏估 算和越界检查。 另一实施例结合图 3、 图 5进行详细说明， 实施例中将要对图 3中的 节点 NE14进行频偏估算。 NE14的两个 PTP端口状态分别是 slave和 passive也就是 从端口状态和被动端口状态， 所以本实施例中对 NE14的 slave端口和 passive端口进 行频偏检测， 具体包括:获取节点 NE14的 PTP端口状态， 分别是： （1 ) NE14 port2: passive (2) NE14 portl : slaver。 其中， 对于 NE14 port2端口的频偏检测也就是对于被 动端口的检测：记录当前时间 το，当时间经过了 Τ时间后完成检测，即时间到达 T0+T 的时刻完成检测； 记录当前时间的同时， 初始化相位偏差和： Theta (单位为 ns) =0； 设备触发发送 1588报文， 检测并回应来自 passitive端口 （即 NE14 port2端口） 的报 文； 使用时间计数器采集 tl、 t2、 t3、 t4时间戳， 滤波计算 offset即 Offset= [ t2— tl t4+t3 ] /2; 累加每次的 offset值， Theta=Theta+offset; 判断当前时间是否到达 T0+T; 进一步的， 当前时间未到达 T0+T时， 重复进行 offset值的检测以及累加； 进一步的， 当前时间到达 T0+T时， 完成本次的频偏检测； 计算得到频偏值， f=Theta/T， 单位为
其中， 对于 NE14 portl端口的频偏检测也就是对于被动端口的检测： 记录当前时 间的同时， 初始化相位偏差和： Theta (单位为 ns) =0； 检测报文为 1588时间同步的 时间同步报文， 检测并回应来自 slaver端口 （即 NE14 portl端口） 的报文； 使用时间 计数器采集 tl、 t2、 t3、 t4时间戳， 滤波计算 offset即； Offset= [ t2_tl _t4 + t3 ] /2累 加每次的 offset值， Theta=Theta+offset; 判断当前时间是否到达 T0+T; 进一步的， 当 前时间未到达 T0+T时， 重复进行 offset值的检测以及累加； 进一步的， 当前时间到达 T0+T时， 完成本次的频偏检测； 计算得到频偏值， f=Theta T， 单位为 ppb。 进一步上报检测结果； 上报检测结果具体包括上报频偏值和检测信号信息。 进一 步具体包括上报内容为参考源相对系统时钟的频偏估算值 （ppb) 和检测时钟源信息、 上报内容为 slaver端口相对于 master的频偏估算值和对应 ptp逻辑端口号或上报内容 为 passive端口相对于 master的频偏估算值和对应 ptp逻辑端口号。 本发明还提供一种时钟频偏检测装置， 如图 7所示， 装置包括： 选择模块、 判断 模块、 检测模块， 其中： 选择模块设置为根据待测时钟节点各时钟的端口状态确定待 测时钟端口；判断模块设置为判断该待测时钟端口对应的时钟源是否能被锁定； 如否， 则获取待测时钟端口的时间同步报文作为频偏检测信号； 检测模块设置为根据频偏检 测信号得到待测时钟端口的频偏值。 进一步， 选择模块根据待测时钟节点各时钟的端 口状态确定待测时钟端口包括： 将待测时钟节点各时钟端口中的至少一个从时钟端口 和 /或被动时钟端口作为待测时钟端口。 进一步， 判断模块获取待测时钟端口的时间同步报文包括： 当待测时钟端口为从 时钟端口时， 获取该从时钟端口的时间同步报文作为频偏检测信号； 当待测时钟端口 为被动时钟端口时，触发该待测时钟端口与其对应的主时钟端口之间的时间同步报文， 获取该待测时钟端口的时间同步报文作为频偏检测信号。 在上述检测模块中包括获取子模块和频偏计算子模块， 其中， 获取子模块设置为 在预设时间内， 获取频偏检测信号的频偏相位和； 频偏计算子模块设置为根据偏移相 位和和预设的检测时间的时间值计算待测时钟端口的频偏值。 进一步， 在所述获取子 模块中包括采集单元、 滤波单元和计算单元， 其中， 采集单元设置为在预设的检测时 间内， 采集各时间同步报文的时间戳； 滤波单元设置为根据时间戳进行滤波计算得到 偏移相位； 计算单元设置为计算预设的检测时间内得到的各偏移相位的偏移相位和。 在上述判断模块中包括采集子模块、 计数子模块、 计算差值子模块和失锁判断子 模块， 其中， 采集子模块设置为获取待测时钟端口的时钟信号； 计数子模块设置为在 预设计数时间内对待测时钟端口的时钟信号和预设的参考时钟信号进行同步计数， 获 取该预设计数时间内待测时钟端口的时钟信号的第一脉冲数和参考时钟信号的第二脉 冲数， 直到计时达到预设计数时间； 差值计算子模块设置为计算第一脉冲数与第二脉 冲数之间的差值作为待测时钟端口的频偏值； 失锁判断子模块设置为判断频偏值是否 大于失锁频偏阈值。 进一步， 在上述装置中还包括上报模块， 设置为在根据频偏检测信号得到待测时 钟端口的频偏值后， 比较得到的频偏值是否大于预设的第一频偏门限值， 若是， 则上 报越限告警； 和 /或在根据频偏检测信号得到所述待测时钟端口的频偏值后， 比较得到 的频偏值是否大于预设的第二频偏门限值， 若是， 则上失锁告警。 本发明还提供一种时钟频偏检测设备， 该频偏检测设备包括至少一个处理器。 其 中处理器用于根据待测时钟节点各时钟端口的状态确定该时钟节点的待测时钟端口； 以及判断该待测时钟端口对应的时钟源是否能被锁定； 如否， 则获取待测时钟端口的 时间同步报文作为频偏检测信号； 并根据频偏检测信号得到待测时钟端口的频偏值。 本实施例中的处理器具体可调用相应的程序指令实现上述功能， 此时本实施例中的时 钟频偏检测设备还可进一步包括用于存储程序指令并供处理器调用的存储器。 本发明实施例提供了一种存储介质， 所述存储介质按照以下指令执行： 根据待测时钟节点各时钟端口的状态确定该时钟节点的待测时钟端口； 判断该待测时钟端口对应的时钟源是否能被锁定； 如否， 则获取所述待测时钟端 口的时间同步报文作为频偏检测信号； 根据所述频偏检测信号得到所述待测时钟端口的频偏值。 应当理解的是， 本实施例中频偏检测设备可为时钟同步网络中的具体储存功能和 处理功能的任何硬件实体装置。 例如在 GPS网络中， 各基站之间实现时钟同步， 该频 偏检测设备可以设置在各基站中， 还可设置在移动终端中对该网络的时钟同步进行检 测。 又例如在办公室内的本地网中， 该检测设备可设置在服务器中， 也可设置在各技 术终端中对给本地网的时钟同步进行检测。 本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序来指令相 关硬件完成， 程序可以存储于计算机可读存储介质中， 如只读存储器、 磁盘或光盘等。 可选地， 上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现。 相应 地， 上述实施例中的各模块 /单元可以采用硬件的形式实现， 也可以采用软件功能模块 的形式实现。 本发明不限制于任何特定形式的硬件和软件的结合。 以上仅为本发明的优选实施例， 当然， 本发明还可有其他多种实施例， 在不背离 本发明精神及其实质的情况下， 熟悉本领域的技术人员当可根据本发明作出各种相应 的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。

Claims

权 利 要 求 书
1. 一种时钟频偏检测方法， 包括：
根据待测时钟节点各时钟端口的状态确定该时钟节点的待测时钟端口； 判断该待测时钟端口对应的时钟源是否能被锁定； 如果否， 则获取所述待 测时钟端口的时间同步报文作为频偏检测信号；
根据所述频偏检测信号得到所述待测时钟端口的频偏值。
2. 如权利要求 1所述的时钟频偏检测方法， 其中， 所述根据所述频偏检测信号得 到所述待测时钟端口的频偏值包括： 在预设时间内， 获取所述频偏检测信号的频偏相位和；
根据所述偏移相位和和所述预设的检测时间的时间值计算所述待测时钟端 口的频偏值。
3. 如权利要求 2所述的时钟频偏检测方法， 其中， 所述在预设时间内， 获取所述 频偏信号的频偏相位和包括：
在预设的检测时间内， 采集各时间同步报文的时间戳； 根据所述时间戳进行滤波计算得到偏移相位；
计算所述预设的检测时间内得到的各偏移相位的偏移相位和。
4. 如权利要求 1所述的时钟频偏检测方法， 其中， 所述判断所述待测时钟端口对 应的时钟源是否能被锁定包括： 判断所述待测时钟端口的时钟信号的频偏是否大于失锁频偏阈值； 或判断产生所述时钟源的晶振是否老化。
5. 如权利要求 4所述的时钟频偏检测方法， 其中， 当所述判断所述待测时钟端口 对应的时钟源是否能被锁定包括判断所述待测时钟端口的时钟信号的频偏是否 大于失锁频偏阈值时， 包括：
获取所述待测时钟端口的时钟信号； 在预设计数时间内对所述待测时钟端口的时钟信号和预设的参考时钟信号 进行同步计数， 获取该预设计数时间内所述待测时钟端口的时钟信号的第一脉 冲数和所述参考时钟信号的第二脉冲数， 直到计时达到预设计数时间；
计算第一脉冲数与所述第二脉冲数之间的差值作为所述待测时钟端口的频 偏值；
判断所述频偏值是否大于失锁频偏阈值。
6. 如权利要求 5所述的时钟频率偏差方法， 其中， 所述获取待检测时钟端口的时 钟信号为所述待测时钟端口的第一条有效下游时钟信号。
7. 如权利要求 1-6任一项所述的时钟频偏检测方法， 其中， 所述方法还包括： 在 根据所述频偏检测信号得到所述待测时钟端口的频偏值后， 比较得到的所述频 偏值是否大于预设的第一频偏门限值， 若是， 则上报越限告警； 和 /或在根据所 述频偏检测信号得到所述待测时钟端口的频偏值后， 比较得到的所述频偏值是 否大于预设的第二频偏门限值， 若是， 则上报失锁告警。
8. 如权利要求 1-6任一项所述的时钟频偏检测方法， 其中， 根据待测时钟节点各 时钟端口的状态确定待测时钟端口包括：
将待测时钟节点各时钟端口中的至少一个状态为从时钟端口和 /或被动时 钟端口的时钟端口作为待测时钟端口。
9. 如权利要求 8所述的时钟频偏检测方法， 其中， 所述待测时钟端口的时间同步 报文包括：
当所述待测时钟端口为从时钟端口时， 获取该从时钟端口的时间同步报文 作为频偏检测信号；
当所述待测时钟端口为被动时钟端口时， 触发该待测时钟端口与其对应的 主时钟端口之间的时间同步报文， 获取该待测时钟端口的时间同步报文作为频 偏检测信号。
10. 一种时钟频偏检测设备， 包括:至少一个处理器； 所述处理器设置为根据待测时钟节点各时钟端口的状态确定该时钟节点的 待测时钟端口； 所述处理器还设置为判断该待测时钟端口对应的时钟源是否能被锁定； 如 否， 则获取所述待测时钟端口的时间同步报文作为频偏检测信号， 并根据所述 频偏检测信号得到所述待测时钟端口的频偏值。
11. 一种时钟频偏检测装置,包括选择模块、 判断模块和检测模块： 选择模块设置为根据待测时钟节点各时钟的端口状态确定待测时钟端口； 判断模块设置为判断该待测时钟端口对应的时钟源是否能被锁定； 如否， 则获取所述待测时钟端口的时间同步报文作为频偏检测信号； 检测模块设置为根据所述频偏检测信号得到所述待测时钟端口的频偏值。
12. 如权利要求 11所述的时钟频偏检测装置， 其中，所述检测模块包括获取子模块 和频偏计算子模块：
所述获取子模块设置为在预设时间内， 获取所述频偏检测信号的频偏相位 和；
所述频偏计算子模块设置为根据所述偏移相位和和所述预设的检测时间的 时间值计算所述待测时钟端口的频偏值。
13. 如权利要求 12所述的时钟频偏检测装置，其中，所述获取子模块包括采集单元、 滤波单元和计算单元：
所述采集单元设置为在预设的检测时间内， 依次采集各时间同步报文的时 间戳；
所述滤波单元设置为根据所述时间戳进行滤波计算得到偏移相位； 所述计算单元设置为计算所述预设的检测时间内得到的各偏移相位的偏移 相位和。
14. 如权利要求 13所述的时钟频偏检测装置，其中，所述判断模块包括采集子模块、 计数子模块、 计算差值子模块和失锁判断子模块：
所述采集子模块设置为获取所述待测时钟端口的时钟信号；
所述计数子模块设置为在预设计数时间内对所述待测时钟端口的时钟信号 和预设的参考时钟信号进行同步计数， 获取该预设计数时间内所述待测时钟端 口的时钟信号的第一脉冲数和所述参考时钟信号的第二脉冲数， 直到计时达到 预设计数时间； 所述差值计算子模块设置为计算第一脉冲数与所述第二脉冲数之间的差值 作为所述待测时钟端口的频偏值；
所述失锁判断子模块设置为判断所述频偏值是否大于失锁频偏阈值。 如权利要求 9-14任一项所述的时钟频偏检测装置， 其中， 所述装置还包括上报 模块， 设置为在根据所述频偏检测信号得到所述待测时钟端口的频偏值后， 比 较得到的所述频偏值是否大于预设的第一频偏门限值，若是，则上报越限告警; 和 /或在根据所述频偏检测信号得到所述待测时钟端口的频偏值后， 比较得到的 所述频偏值是否大于预设的第二频偏门限值， 若是， 则上报失锁告警。
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