WO2015068676A1 - 表示装置およびその駆動方法 - Google Patents
表示装置およびその駆動方法 Download PDFInfo
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- WO2015068676A1 WO2015068676A1 PCT/JP2014/079170 JP2014079170W WO2015068676A1 WO 2015068676 A1 WO2015068676 A1 WO 2015068676A1 JP 2014079170 W JP2014079170 W JP 2014079170W WO 2015068676 A1 WO2015068676 A1 WO 2015068676A1
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- data
- refresh
- drive control
- control circuit
- image
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
Definitions
- the present invention relates to a display device and a driving method thereof, and more particularly, to a display device that performs rest driving and a driving method thereof.
- a plurality of pixel forming portions are formed in a matrix.
- Each pixel formation portion is provided with a thin film transistor (Thin Transistor: hereinafter referred to as “TFT”) operating as a switching element and a pixel capacitor connected to the data signal line through the TFT.
- TFT Thin Transistor
- a data signal for displaying an image is written as a data voltage in a pixel capacitor in the pixel formation portion.
- This data voltage is applied to the liquid crystal layer of the pixel formation portion, and the orientation direction of the liquid crystal molecules is changed in a direction corresponding to the voltage value of the data signal.
- the liquid crystal display device displays an image on the display unit by controlling the light transmittance of the liquid crystal layer of each pixel forming unit.
- a control signal or the like can be prevented from being supplied to the gate driver as the scanning signal line driver circuit and / or the source driver as the data signal line driver circuit. Accordingly, the operation of the gate driver and / or the source driver can be paused, so that power consumption can be reduced.
- driving performed by providing a pause period after the refresh period is referred to as “pause driving”, for example.
- This pause drive is also called “low frequency drive” or “intermittent drive”. Such pause driving is suitable for still image display.
- a liquid crystal display device for a portable electronic device has a driving circuit such as a source driver that drives a display unit of a liquid crystal panel and a timing controller (hereinafter referred to as “TCON”) as a display control circuit that generates a control signal for the driving circuit.
- TCON timing controller
- An IC Integrated Circuit
- Such an IC is called a “one-chip driver” or a “system driver”.
- an abnormality such as a display shift may occur when an image update is performed during pause driving.
- the present invention provides a display device in which an abnormality such as a display shift at the time of image update does not occur even when pause driving is performed in a configuration in which a display unit (data signal line) is driven by a plurality of driver ICs.
- the purpose is to do.
- a first aspect of the present invention is a display device that displays an image based on input data given from outside, A display for displaying the image; A drive control unit for driving the display unit such that a refresh period for refreshing the display image on the display unit and a non-refresh period for pausing refreshing of the display image on the display unit appear alternately based on the input data
- the drive control unit includes a plurality of drive control circuits respectively corresponding to a plurality of sub display regions obtained by dividing the display region of the display unit, Each drive control circuit, when data for refreshing the display image in the display unit is given from the outside as the input data, refresh start information associated with the refresh start timing based on the input data, Obtained within the drive control circuit based on the input data, or obtained from another drive control circuit or from outside, and based on the obtained refresh start information, display in the sub display area corresponding to the drive control circuit
- the display unit is driven so that the image refresh is started in synchronization with the refresh of the display
- the data path includes a plurality of sub data paths respectively corresponding to the plurality of sub display areas,
- Each drive control circuit receives, as sub input data, data for displaying an image in the corresponding sub display area from the input data from the outside via a sub data path corresponding to the sub display area.
- the display unit is driven so that an image is displayed in the sub display area.
- Each drive control circuit receives the input data from the outside through the data path, and drives the display unit so that an image is displayed in a corresponding sub display area based on the input data.
- the display unit is arranged in a matrix along a plurality of data signal lines, a plurality of scanning signal lines intersecting with the plurality of data signal lines, and the plurality of data signal lines and the plurality of scanning signal lines.
- a plurality of pixel forming portions Each pixel forming portion is connected to any one of the plurality of data signal lines and to any one of the plurality of scanning signal lines,
- the drive control unit drives the plurality of data signal lines and the plurality of scanning signal lines so that an image is displayed by the plurality of pixel forming units based on the input data,
- the data path is Among the input data, data corresponding to odd-numbered pixel columns composed of pixels arranged along the data signal lines in a pixel matrix constituting an image to be displayed by the plurality of pixel forming units is externally set as odd-numbered column data.
- Odd-number sub-data paths for transferring from to each drive control circuit Of the input data, an even-numbered sub-data path for transferring data corresponding to even-numbered pixel columns composed of pixels arranged along the data signal lines in the pixel matrix from the outside to the respective drive control circuits as even-numbered column data Including
- Each drive control circuit Pixels arranged along the scanning signal line in the pixel matrix by receiving the odd column data from the outside through the odd sub data path and receiving the even column data from the outside through the even sub data path
- the input data is given from the outside by one line data corresponding to one pixel row consisting of:
- the data signal line in the sub display area of the display unit is driven based on data for displaying an image in a corresponding sub display area among the odd column data and the even column data.
- the display unit is arranged in a matrix along a plurality of data signal lines, a plurality of scanning signal lines intersecting with the plurality of data signal lines, and the plurality of data signal lines and the plurality of scanning signal lines.
- a plurality of pixel forming portions Each pixel forming portion is connected to any one of the plurality of data signal lines and to any one of the plurality of scanning signal lines,
- the drive control unit drives the plurality of data signal lines and the plurality of scanning signal lines so that an image is displayed by the plurality of pixel forming units based on the input data,
- the data path is Out of the input data, data corresponding to odd-numbered pixel rows composed of pixels arranged along the scanning signal lines in a pixel matrix that constitutes an image to be displayed by the plurality of pixel forming units is externally set as odd-numbered row data.
- Odd-number sub-data paths for transferring from to each drive control circuit Of the input data, an even-numbered sub-data path for transferring data corresponding to even-numbered pixel rows made up of pixels arranged along the scanning signal line in the pixel matrix from the outside to the respective drive control circuits as even-numbered row data Including
- Each drive control circuit Pixels arranged along the data signal lines in the pixel matrix by receiving the odd row data from outside through the odd sub data path and receiving the even row data from outside through the even sub data path
- the input data is given from the outside by two line data corresponding to two pixel rows consisting of:
- the data signal line in the sub display area of the display unit is driven based on data for displaying an image in a corresponding sub display area among the odd line data and the even line data.
- Each drive control circuit includes a refresh detection unit for detecting a refresh start timing of the display image in the display unit based on data for displaying an image in a corresponding sub display area of the input data
- the plurality of drive control circuits are composed of one drive control circuit identified as a master drive control circuit and a drive control circuit other than the master drive control circuit identified as a slave drive control circuit, A signal path is provided between the master drive control circuit and the slave drive control circuit,
- the refresh detection unit detects the refresh start timing
- the slave drive control circuit sends a refresh detection signal indicating the start timing as the refresh start information to the master drive control circuit via the signal path.
- the master drive control circuit starts the refresh.
- a refresh control signal to be instructed is sent as the refresh start information to the slave drive control circuit via the signal path, and the sub display area is based on data for displaying an image in the corresponding sub display area of the input data.
- Driving the display unit to start refreshing the display image at When the slave drive control circuit receives the refresh control signal from the master drive control circuit via the signal path, the slave drive control circuit performs sub display based on data for displaying an image in a corresponding sub display area of the input data. The display unit is driven so that refresh of the display image in the region is started.
- the plurality of drive control circuits are composed of one drive control circuit identified as a master drive control circuit and a drive control circuit other than the master drive control circuit identified as a slave drive control circuit, A signal path is provided between the master drive control circuit and the slave drive control circuit,
- the master drive control circuit A refresh detection unit for detecting a refresh start timing of the display image on the display unit based on the input data; When the refresh detection unit detects the refresh start timing, a refresh control signal instructing the start of the refresh is sent as the refresh start information to the slave drive control circuit via the signal path, and the input data Driving the display unit to start refreshing the display image in the sub display area based on the data for displaying the image in the corresponding sub display area,
- the slave drive control circuit receives the refresh control signal from the master drive control circuit via the signal path, the slave drive control circuit performs sub display based on data for displaying an image in a corresponding sub display area of the input data.
- An eighth aspect of the present invention provides any of the second to fifth aspects of the present invention, A signal path interconnecting the plurality of drive control circuits;
- Each drive control circuit A refresh detection unit for detecting a start timing of refresh of the display image in the display unit based on data for displaying an image in a corresponding sub display area of the input data,
- a refresh detection signal indicating the start timing is sent as the refresh start information to the other drive control circuit via the signal path, and the input data
- Driving the display unit to start refreshing the display image in the sub display area based on the data for displaying the image in the corresponding sub display area,
- display in the sub display area is performed based on data for displaying an image in the corresponding sub display area of the input data.
- the display unit is driven such that image refresh is started.
- Each drive control circuit A refresh detection unit for detecting a refresh start timing of the display image on the display unit based on the input data; When the refresh detection timing is detected by the refresh detection unit, refresh of the display image in the sub display area is started based on data for displaying an image in the corresponding sub display area in the input data. And the display unit is driven.
- each drive control circuit receives the refresh control signal from the outside via the control signal path, the display image in the sub display area is based on data for displaying an image in the corresponding sub display area among the input data.
- the display unit is driven so that the refreshing is started.
- An eleventh aspect of the present invention is any one of the second to fifth aspects of the present invention,
- Each drive control circuit is configured as a single IC chip.
- a twelfth aspect of the present invention is any one of the second to fifth aspects of the present invention.
- the display unit includes a thin film transistor in which a channel layer is formed of an oxide semiconductor as a switching element for forming each pixel constituting an image to be displayed.
- each drive control circuit responds to the refresh start timing based on the input data when data for refreshing the display image of the display unit is given as input data from the outside.
- the obtained refresh start information is acquired in the drive control circuit based on the input data, or is acquired from another drive control circuit or the outside, and the drive control circuit is acquired based on the acquired refresh start information.
- the display unit is driven so that the refresh of the display image in the corresponding sub display area is started in synchronization with the refresh of the display image in the sub display area corresponding to the other drive control circuit.
- each drive control circuit uses the data for displaying an image in the corresponding sub display area of the input data as the sub input data, and sets the sub data path corresponding to the sub display area. Receive from outside through.
- each drive control circuit performs sub display corresponding to the drive control circuit based on the sub input data of the input data.
- the refresh of the display image in the area is started in synchronization with the refresh of the display image in the sub display area corresponding to the other drive control circuit.
- the second aspect of the present invention has an advantage that the operating frequency for data transfer from the outside to each drive control circuit is low while achieving the same effect as the first aspect of the present invention.
- each drive control circuit receives input data from the outside via a data path. If the input data is data for refreshing the display image on the display unit, each drive control circuit refreshes the display image in the sub display area corresponding to the drive control circuit based on the input data. Is started in synchronization with refresh of the display image in the sub display area corresponding to the other drive control circuit. Thereby, the effect similar to the 1st aspect of this invention is acquired.
- each drive control circuit receives odd-numbered column data from the outside through the odd-numbered subdata path, and externally receives even-numbered column data through the even-numbered subdata path. Receive from.
- each drive control circuit displays an image in a sub display area corresponding to the drive control circuit among the odd-numbered column data and the even-numbered column data. Based on the data for displaying the display, refresh of the display image in the sub display area is started in synchronization with refresh of the display image in the sub display area corresponding to the other drive control circuit.
- the fourth aspect of the present invention has the same effects as those of the first aspect of the present invention, and the input data is driven through two data paths (odd sub data path and even sub data path). Since it is transferred to the control circuit, there is an advantage that the operating frequency for the data transfer is low.
- each drive control circuit receives odd-numbered row data from the outside via the odd-numbered sub-data path, and externally receives even-numbered row data via the even-numbered sub-data path. Receive from.
- each drive control circuit displays an image in a sub display area corresponding to the drive control circuit among the odd-numbered row data and the even-numbered row data. Based on the data for displaying the display, refresh of the display image in the sub display area is started in synchronization with refresh of the display image in the sub display area corresponding to the other drive control circuit.
- the fifth aspect of the present invention has the same effects as those of the first aspect of the present invention, and the input data is driven through two data paths (odd sub data path and even sub data path). Since it is transferred to the control circuit, there is an advantage that the operating frequency for the data transfer is low.
- the master drive control circuit starts the refresh when the refresh detection timing is detected by the refresh detection unit or when the refresh detection signal is received from the slave drive control circuit.
- the display unit sends a refresh control signal to instruct the slave drive control circuit and starts refreshing the display image in the sub display area based on the data for displaying the image in the corresponding sub display area in the input data.
- the slave drive control circuit sends a refresh detection signal indicating the start timing to the master drive control circuit and receives a refresh control signal from the master drive control circuit. Based on the data for displaying the image in the corresponding sub display area of the input data, the display unit is driven so as to start refreshing the display image in the sub display area.
- the master drive control circuit when the refresh detection unit detects the refresh start timing, sends a refresh control signal instructing the start of refresh to the slave drive control circuit, Based on the data for displaying the image in the corresponding sub display area in the input data, the display unit is driven so that refresh of the display image in the sub display area is started.
- the slave drive control circuit receives the refresh control signal from the master drive control circuit, the slave drive control circuit starts refreshing the display image of the sub display area based on the data for displaying the image in the corresponding sub display area of the input data.
- the display unit is driven as described above. Thereby, the same effect as that of the sixth aspect of the present invention can be obtained.
- each drive control circuit when the refresh detection unit detects a refresh start timing, each drive control circuit sends a refresh detection signal indicating the start timing to another drive control circuit, Based on the data for displaying an image in the corresponding sub display area of the input data, the display unit is driven so as to start refreshing the display image in the sub display area, and any of the other drive control circuits
- the refresh detection signal is received from the display, the display unit is driven so as to start refreshing the display image of the sub display area based on the data for displaying the image in the corresponding sub display area of the input data.
- each drive control circuit converts the input data into data for displaying an image in the corresponding sub display area. Based on this, the display unit is driven so as to start refreshing the display image in the sub display area.
- the same effect as that of the first aspect of the present invention can be obtained without exchanging signals such as a refresh detection signal and a refresh control signal between the plurality of drive control circuits.
- each drive control circuit when each drive control circuit receives a refresh control signal from the outside, each drive control circuit is configured to store the sub display area based on data for displaying an image in the corresponding sub display area of the input data.
- the display unit is driven so that the refresh of the display image is started.
- each drive control circuit can start refreshing the display image in the corresponding sub display area in synchronization with refreshing the display image in the sub display area corresponding to the other drive control circuit. For this reason, the effect similar to the 1st aspect of this invention is acquired.
- refresh synchronization for a plurality of sub display areas of the display unit is based on an external refresh control signal, a signal such as a refresh detection signal or a refresh control signal is not exchanged between a plurality of drive control circuits.
- the refresh can be reliably synchronized.
- the same effect as in the first aspect of the present invention is obtained, and the display unit is driven using a plurality of drive control circuits configured as a single IC chip. Can display a high-definition image satisfactorily.
- a thin film transistor in which a channel layer is formed of an oxide semiconductor is used as a switching element for forming each pixel constituting an image to be displayed on the display unit.
- the off-leakage current of the thin film transistor is significantly reduced, and the display device can be satisfactorily driven.
- 1 is a diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention. 4 is a timing chart for explaining the operation of the liquid crystal display device according to the first embodiment.
- basic configuration ⁇ 0.
- Basic configuration> ⁇ 0.1 Overall configuration>
- FIG. 1 is a block diagram showing a configuration example of a general liquid crystal display device.
- the liquid crystal display device 2 includes a liquid crystal display panel 10 and a backlight unit 30.
- the liquid crystal display panel 10 is provided with an FPC (Flexible Printed Circuit) for connection to the outside.
- FPC Flexible Printed Circuit
- a display unit 100, a display control circuit 200, a source driver 310 as a data signal line driving circuit, and a gate driver 320 as a scanning signal line driving circuit are provided on the liquid crystal display panel 10.
- the source driver 310, the gate driver 320, and the display control circuit 200 constitute a drive control unit according to the present invention, and either or both of the source driver 310 and the gate driver 320 are provided in the display control circuit 200. Also good.
- both or one of the source driver 310 and the gate driver 320 may be formed integrally with the display unit 100.
- a host 80 (system) mainly composed of a CPU is provided outside the liquid crystal display device 2.
- the display unit 100 includes source lines SL1 to SLm as a plurality (m) of data signal lines, gate lines GL1 to GLn as a plurality (n) of scanning signal lines, and these m sources.
- a plurality (m ⁇ n) of pixel forming portions 110 provided corresponding to the intersections of the lines SL1 to SLm and the n gate lines GL1 to GLn are formed.
- source lines SL when the m source lines SL1 to SLm are not distinguished, these are simply referred to as “source lines SL”, and when the n gate lines GL1 to GLn are not distinguished, these are simply referred to as “gate lines GL”. .
- the m ⁇ n pixel forming units 110 are formed in a matrix along the source line SL and the gate line GL.
- Each pixel forming unit 110 includes a TFT 111 as a switching element in which a gate terminal as a control terminal is connected to a gate line GL that passes through a corresponding intersection, and a source terminal is connected to a source line SL that passes through the intersection.
- the pixel electrode 112 connected to the drain terminal of the TFT 111, the common electrode 113 provided in common to the m ⁇ n pixel forming portions 110, and the pixel electrode 112 and the common electrode 113 are sandwiched,
- the liquid crystal layer is provided in common for the plurality of pixel formation portions 110.
- a pixel capacitor Cp is constituted by a liquid crystal capacitor formed by the pixel electrode 112 and the common electrode 113. Note that, typically, an auxiliary capacitor is provided in parallel with the liquid crystal capacitor in order to reliably hold the voltage in the pixel capacitor Cp. Therefore, the pixel capacitor Cp is actually composed of a liquid crystal capacitor and an auxiliary capacitor.
- a TFT using an oxide semiconductor layer as a channel layer (hereinafter referred to as “oxide TFT”) is used as the TFT 111.
- the oxide semiconductor layer includes, for example, an In—Ga—Zn—O-based semiconductor.
- an In—Ga—Zn—O-based semiconductor film containing In, Ga, and Zn at a ratio of 1: 1: 1 is used.
- a TFT having an In—Ga—Zn—O-based semiconductor layer has high mobility (more than 20 times that of a TFT using amorphous silicon as a channel layer, ie, an a-Si TFT) and low leakage current (100 minutes compared to an a-Si TFT). Therefore, it is suitably used as a driving TFT and a pixel TFT.
- a TFT having an In—Ga—Zn—O-based semiconductor layer is used, power consumption of the display device can be significantly reduced.
- the In—Ga—Zn—O-based semiconductor may be amorphous, may include a crystalline portion, and may have crystallinity.
- a crystalline In—Ga—Zn—O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.
- Such a crystal structure of an In—Ga—Zn—O-based semiconductor is disclosed in, for example, Japanese Patent Application Laid-Open No. 2012-134475. For reference, the entire disclosure of Japanese Patent Application Laid-Open No. 2012-134475 is incorporated herein by reference.
- the oxide semiconductor layer may include another oxide semiconductor instead of the In—Ga—Zn—O-based semiconductor.
- Zn—O based semiconductor ZnO
- In—Zn—O based semiconductor IZO (registered trademark)
- Zn—Ti—O based semiconductor ZTO
- Cd—Ge—O based semiconductor Cd—Pb—O based
- CdO cadmium oxide
- Mg—Zn—O based semiconductors In—Sn—Zn—O based semiconductors (eg, In 2 O 3 —SnO 2 —ZnO), In—Ga—Sn—O based semiconductors, etc. You may go out.
- the use of an oxide TFT as the TFT 111 is merely an example, and a silicon-based TFT or the like may be used instead.
- the display control circuit 200 receives data DAT for each screen from the host 80 via the FPC 20, and in response thereto, the signal line control signal SCT, the scanning line control signal GCT, And generates and outputs a common potential Vcom.
- the signal line control signal SCT is given to the source driver 310.
- the scanning line control signal GCT is supplied to the gate driver 320.
- the common potential Vcom is supplied to the common electrode 113.
- data DAT is transmitted and received between the display control circuit 200 and the external host 80 using an interface conforming to the DSI (Display Serial Interface) standard proposed by MIPI (Mobile Industry Processor Interface) Alliance. Done through.
- DSI Display Serial Interface
- MIPI Mobile Industry Processor Interface
- the interface compliant with the DSI standard high-speed data transmission is possible.
- Data transmission / reception between the display control circuit 200 and the host in the liquid crystal display device is the same in each embodiment described later.
- the interface used for transmitting and receiving data and signals between the display device and the host in the present invention is not limited to the interface conforming to the DSI standard, and instead of this, other together with this
- an interface conforming to the I2C (Inter Integrated Circuit) standard or the SPI (Serial Peripheral Interface) standard may be used.
- the source driver 310 generates and outputs a data signal to be supplied to the source line SL in accordance with the signal line control signal SCT.
- the signal line control signal SCT includes a digital video signal representing an image to be displayed, a source start pulse signal, a source clock signal, a latch strobe signal, and the like.
- the source driver 310 operates a shift register and a sampling latch circuit (not shown) in accordance with the source start pulse signal, the source clock signal, and the latch strobe signal, and outputs a digital signal obtained based on the digital video signal.
- a data signal as a drive image signal is generated by converting the signal into an analog signal by a DA conversion circuit (not shown).
- the gate driver 320 repeats the application of the active scanning signal to the gate line GL in a predetermined cycle in accordance with the scanning line control signal GCT.
- the scanning line control signal GCT includes, for example, a gate clock signal and a gate start pulse signal.
- the gate driver 320 operates a shift register (not shown) in the gate driver 320 to generate a scanning signal.
- the backlight unit 30 is provided on the back side of the liquid crystal display panel 10 and irradiates the back light of the liquid crystal display panel 10 with backlight light.
- the backlight unit 30 typically includes a plurality of LEDs (Light Emitting Diode).
- the backlight unit 30 may be controlled by the display control circuit 200, or may be controlled by other methods.
- the backlight unit 30 does not need to be provided.
- the data signal is applied to the source line SL, the scanning signal is applied to the gate line GL, and the backlight unit 30 is driven, so that an image corresponding to the data transmitted from the host 80 is displayed on the liquid crystal. It is displayed on the display unit 100 of the display panel 10.
- the image display on the liquid crystal display panel 10 also requires voltage application to the common electrode 113 or driving of the common electrode 113.
- the configuration and operation for this purpose are the features of the present invention. Since they are not directly related, their explanation is omitted below.
- a driver IC 300 shown in FIG. 2 includes a PWR 303 as a power supply circuit in addition to SD301, GD302, and TCON304 corresponding to the source driver 310, the gate driver 320, and the display control circuit 200 in the liquid crystal display device shown in FIG. Therefore, it functions as a drive control circuit in the liquid crystal display device.
- the PWR 303 generates a voltage necessary for the operation of the SD 301, the GD 302, the TCON 304, and the like based on a power supply voltage given from the outside.
- the driver IC 300 may further include a REF 305 as a refresh detection unit described later.
- not all source lines in a liquid crystal display device may be driven by only the source driver (SD301) included in one driver IC 300.
- SD301 source driver
- a plurality of driver ICs are used.
- FIG. 3 is a block diagram showing an example of the configuration of a liquid crystal display device when two driver ICs are used.
- the backlight unit, the common electrode line, and the components related to driving the backlight unit that are not directly related to the present invention are based on well-known technology, and are omitted, and the display unit 100 and the driver IC in the liquid crystal display panel 10 are omitted.
- the constituent elements are mainly shown (this applies also to FIGS. 4 to 7, 14, 20, and 26).
- a display unit 100 is formed on the liquid crystal display panel 10, and driver ICs 300L and 300R are mounted as two drive control circuits constituting the drive control unit.
- Each of these two driver ICs 300L and 300R includes an SD (source driver), a GD (gate driver), a refresh detection unit (REF), a TCON (timing controller), and a PWR (power supply circuit).
- the source line in the left active area 100L which is the left half of the active area (also denoted by reference numeral “100”), in which the display unit 100 is formed in the liquid crystal display panel 10, is the driver IC 300L (
- the source line in the right active area 100R that is the right half of the active area 100 is connected to the SD in the driver IC 300R (hereinafter referred to as the “right driver IC 300R”).
- the right driver IC 300R has been.
- each source line (not shown) in the active area 100 is arranged so as to extend in the vertical direction in the figure (the same applies to the configurations of FIGS. 4 to 6 described later and in each embodiment), and active as a display area.
- the area 100 is divided by a dividing line along the source line into a left active area 100L as a sub display area and a right active area 100R as a sub display area (configurations shown in FIGS. 4 to 6 described later). The same applies to each embodiment).
- the source line in the left active area 100L is driven by SD in the left driver IC 300L
- the source line in the right active area 100R is driven by SD in the right driver IC 300R.
- each gate line (not shown) in the active area 100 is arranged so as to extend in the horizontal direction in the drawing (the same applies to the configuration example of FIG. 4 described later).
- the left end of each gate line is connected to the GD in the left driver IC 300L
- the right end of each gate line is connected to the GD in the right driver IC 300R
- each gate line is driven by both the left and right driver ICs 300L and 300R. Is done.
- the connection configuration between each gate line and the left and right driver ICs 300L and 300R is not limited to this, and each gate line is connected only to the GD in one of the left and right driver ICs 300L and 300R. May be.
- the odd-numbered gate lines may be connected to the GD in the left driver IC 300L, and the even-numbered gate lines may be connected to the GD in the right driver IC 300R. Further, all the gate lines may be connected to only one of the left and right driver ICs 300L and 300R.
- FIG. 4 is a block diagram showing another configuration example of the liquid crystal display device when two driver ICs are used.
- the display unit 100 is formed on the liquid crystal display panel 10 and the driver ICs 300L and 300R are mounted as two drive control circuits, as in the configuration example of FIG.
- a gate driver 320 as a scanning signal line driving circuit is integrally formed with the active area 100, which is different from the configuration example of FIG. That is, the liquid crystal display panel 10 in the configuration example of FIG. 4 is a so-called gate driver monolithic panel.
- the left and right driver ICs 300L and 300R do not include a GD (gate driver).
- the two driver ICs 300 ⁇ / b> L and 300 ⁇ / b> R and the gate driver 320 constitute a drive control unit.
- the gate driver 320 integrally formed with the active area 100 is connected to the TCON in the left driver IC 300L.
- Each gate line in the active area 100 is driven by the gate driver 320 under the control of the TCON.
- the configuration of other parts in the configuration example of FIG. 4 is the same as that of the configuration example of FIG.
- the schematic configuration of the liquid crystal display device according to each embodiment is represented by the block diagram shown in FIG. 5 without distinguishing both configurations.
- the display unit (active area) 100 of the liquid crystal panel in the liquid crystal display device is driven by two driver ICs.
- the present invention is not limited to this, and the display unit ( The active area) 100 may be driven by three or more driver ICs. For example, as shown in FIG.
- the active area 100 is divided into three regions by dividing lines along the source line. Are divided into a left active area 100L, a central active area 100C, and a right active area 100R.
- the source lines in the left, center, and right active areas 100L, 100C, 100R are left, center, and right driver ICs 300L, 300C, 300R (inside SD) is connected to the left, center, and right driver ICs 300L, 300C, and 300R (inside SD), respectively.
- FIG. 7 is a diagram showing an overall configuration of the liquid crystal display device according to the first embodiment of the present invention.
- the liquid crystal display device includes an active matrix type liquid crystal display panel 10.
- a display unit (active area) 100 is formed on the liquid crystal display panel 100, and two driver ICs include a left driver IC 300 ⁇ / b> L and a right driver. It is mounted as IC300R.
- the active area 100 is divided into a left active area 100L and a right active area 100R along a dividing line along the source line.
- the source line in the left active area 100L is driven by the left driver IC 300L, and the source in the right active area 100R
- the line is driven by the right driver IC 300R.
- Both the left and right driver ICs 300L and 300R are connected to the host 80 through the appropriate interface described above, such as an interface conforming to the MIPI-DSI standard.
- this interface data for displaying an image in the left active area 100L (hereinafter referred to as “left half data”) DaL is transferred to the left driver IC 300L, whereby the host 80 for the left half data is transferred from the host 80 to the left driver IC 300L.
- a data path (hereinafter referred to as “left sub data path”) 711 is realized.
- data for displaying an image in the right active area 100R (hereinafter referred to as “right half data”) DaR is transferred to the right driver IC 300R, whereby the host 80 for the right half data DaR sends the right driver.
- a data path (hereinafter referred to as “right sub data path”) 712 to the IC 300R is realized.
- the left half data DaL in addition to image data (hereinafter referred to as “left half image data”) representing an image to be displayed in the left active area 100L (hereinafter referred to as “left half image data”), the left half image is displayed.
- Timing information (information corresponding to a synchronization signal, a data enable signal, a clock signal, etc.) necessary for displaying the image is also included, and the right half data DaR includes an image (hereinafter referred to as an image to be displayed in the right active area 100R).
- image data representing the “right half image” hereinafter referred to as “right half image data”
- timing information necessary for displaying the right half image Is also included).
- FIG. 8 is a timing chart for explaining the operation of the liquid crystal display device according to the present embodiment.
- the pixel voltage held as pixel data in the pixel capacitance Cp of each pixel formation unit 110 in the display unit 100 is rewritten at a predetermined cycle (FIG. 1). reference). That is, the display image on the display unit 100 is refreshed at a predetermined cycle.
- this refresh cycle is 3 frame periods, and 1 frame period as a refresh period is followed by 2 frame periods as a non-refresh period.
- the refresh cycle may be two frame periods or more, and the specific value is determined in consideration of the change frequency of the image to be displayed on the display unit 100.
- a 60 frame period including one frame period as a refresh period (hereinafter also referred to as “RF period”) and 59 frame periods as a subsequent non-refresh period (hereinafter also referred to as “NRF period”) may be set as the refresh period.
- the refresh rate is 1 Hz.
- the refresh period may be longer than two frame periods (the same applies to other embodiments described later).
- TCON in each of the left and right driver ICs 300L and 300R in the present embodiment generates a vertical synchronization signal VSY that is H level for a predetermined period every frame period (one vertical period).
- the synchronization signal VSY is given to the GD (gate driver) as one of the scanning side control signals GCT (see FIGS. 2 to 4).
- Scans applied to the gate lines GL1 to GL4 of the display unit 100 in an effective vertical scanning period that is, a period excluding a vertical blanking period including a period in which the vertical synchronization signal is at an H level
- the signals G1 to G4 are sequentially activated (H level).
- data signals S1 to Sm representing an image to be displayed are applied to the source lines SL1 to SLm of the display unit 100, respectively.
- a pixel voltage representing each pixel constituting an image to be displayed is written as pixel data in the pixel forming unit 110 (pixel capacitance Cp thereof).
- a display configured to drive the source line in the display unit (active area) 100 in a shared manner by a plurality of driver ICs (the left driver IC 300L and the right driver IC 300R) as in the present embodiment and perform the above-described pause driving.
- the left driver IC 300L refreshes the display image in the left active area 100L
- the right driver IC 300R refreshes the display image in the right active area 100R.
- the left driver IC 300L drives the source line in the left active area 100L based on the data received from the host 80 for the image update, so that the left half (left half image) of the new display image is displayed.
- the voltage of the data signal to be expressed is written in each pixel formation unit in the left active area 100L, and the right driver IC 300R drives the source line in the right active area 100R based on the data received from the host 80 for the image update, thereby creating a new
- the voltage of the data signal representing the right half (right half image) of the correct display image is written in each pixel formation portion in the right active area 100R.
- one or both of the left and right driver ICs 300L and 300R drive each gate line in the active area 100 (see FIGS. 3 and 4). Since the configuration and operation relating to driving are not directly related to the features of the present invention and are based on well-known techniques, detailed description thereof will be omitted below.
- each of the plurality of driver ICs shares the active area 100 (in the present embodiment, either the left active area 100L or the right active area 100R).
- an abnormality such as a display shift may occur in the display image in the display unit (active area).
- this embodiment has the following configuration in order to synchronize the refresh by the left driver IC 300L and the refresh by the right driver IC 300R.
- FIG. 9 is a block diagram showing a first configuration example for refresh synchronization in the present embodiment.
- the left and right driver ICs 300L and 300R both incorporate SD (source driver) and TCON (timing controller), but do not have REF (refresh detection unit).
- a refresh control signal RfC instructing the start of the refresh operation for image update is output from the host 80, and a path for transmitting the refresh control signal RfC to both the left and right driver ICs 300L and 300R. (Hereinafter referred to as “control signal path”) 714 is formed.
- the control signal path 714 may be realized by providing a dedicated signal line between the host 80 and the left and right driver ICs 300L and 300R, or alternatively, the host 80 and the left and right driver.
- the refresh control signal RfC may be realized by transferring the refresh control signal RfC from the host 80 to the left and right driver ICs 300L and 300R according to an interface (for example, an interface conforming to the I2C standard or the SPI standard) used for connection with the ICs 300L and 300R.
- the left half data DaL is transferred from the host 80 to the left driver IC 300L among the data (hereinafter referred to as “refresh data”) for displaying a new image by the image update.
- the right half data DaR is transferred from the host 80 to the right driver IC 300R, and the refresh control signal RfC instructing the start of refresh of the display image in the active area 100 by the refresh data is sent from the host 80 to the left and right driver ICs 300L, 300R. Forwarded to
- the TCON receives the left half data DaL and the refresh control signal RfC, generates an image signal and a control signal for operating the SD based on the left half data DaL, and outputs these signals. It outputs to SD at a timing based on the refresh control signal RfC. Based on these signals, the SD drives the source lines by applying data signals representing images (left half images) to be displayed in the left active area 100L to the source lines in the left active area 100L.
- the left driver IC 300L includes a GD and the gate line is driven by the GD
- the TCON generates a control signal for operating the GD based on the left half data DaL. It outputs to GD at the timing based on the refresh control signal RfC. In this case, the GD drives the gate line in the active area 100 based on the control signal.
- the TCON receives the right half data DaR and the refresh control signal RfC, generates an image signal and a control signal for operating the SD based on the right half data DaR, and outputs these signals. It outputs to SD at a timing based on the refresh control signal RfC.
- This SD is based on these image signals and control signals, by applying a data signal representing an image (right half image) to be displayed in the right active area 100R to the source lines in the right active area 100R, respectively. Drive.
- the TCON When the right driver IC 300R includes a GD and the GD drives the gate line, the TCON generates a control signal for operating the GD based on the right half data DaR, It outputs to GD at the timing based on the refresh control signal RfC. In this case, the GD drives the gate line in the active area 100 based on the control signal.
- the left driver IC 300L drives the source line in the left active area 100L to refresh the display image in the left active area 100L
- the right driver IC 300R drives the source line in the right active area 100R.
- the display image in the right active area 100R is refreshed.
- the left and right driver ICs 300L and 300R both drive the source line based on the refresh control signal RfC of the host 80, the left driver IC 300L refreshes the display image of the left active area 100L and the right The refresh of the display image of the right active area 100R by the driver IC 300R is synchronized. For this reason, even when the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment, an abnormality such as a display shift does not occur. Therefore, in the liquid crystal display device that performs the pause driving, the display unit 100 can be driven by the two driver ICs 300L and 300R to display a high-definition image satisfactorily.
- this configuration example requires a configuration for transmitting the refresh control signal RfC from the host 80 to the left and right driver ICs 300L and 300R, the refresh operation is more reliable than the second to fourth configuration examples described later.
- the synchronization is possible, and there is an advantage that it is not necessary to exchange signals for synchronization between the left and right driver ICs 300L and 300R.
- FIG. 10 is a block diagram showing a second configuration example for refresh synchronization in the present embodiment.
- the refresh control signal RfC instructing the start of the refresh operation for updating the image is not output from the host 80.
- the left half data DaL of the refresh data for displaying a new image by the image update is transferred from the host 80 to the left driver IC 300L.
- the right half data DaR is transferred from the host 80 to the right driver IC 300R.
- each of the left and right driver ICs 300L and 300R incorporates REF (refresh detection unit) in addition to SD (source driver) and TCON (timing controller).
- REF refresh detection unit
- This REF detects the refresh start timing by determining whether or not the display image is updated based on half of the image data representing the display image for one screen, and the detected start timing.
- the refresh detection unit that generates the refresh detection signal indicating the start timing of the refresh is referred to as “REF (Half ) ").
- the method for detecting the refresh start timing in REF is not particularly limited.
- CABC Content Adaptive Brightness Control
- the left driver IC 300L performs refresh detection by determining whether or not the display image of the left active area 100L is changed based on the left half data DaL received from the host 80.
- a REF (Half) 305L that generates the signal RfDl is incorporated.
- the right driver IC 300R generates a REF (Half) 305R that generates the refresh detection signal RfDr by determining whether or not the display image of the right active area 100R is changed based on the right half data DaR received from the host 80.
- RfDr refresh detection signal
- first signal path 715 for transmitting the refresh detection signal RfDr generated by the REF (Half) 305R of the right driver IC 300R to the left driver IC 300L is formed.
- second signal path 716 for transmitting the refresh detection signal RfDl generated by the REF (Half) 305L of the left driver IC 300L to the right driver IC 300R is formed.
- the left driver IC 300L and the right driver IC 300R are connected by an interface (bidirectional serial bus) compliant with, for example, the I2C standard or the SPI standard, and the refresh detection signal RfDr is transmitted from the right driver IC 300R to the left driver according to the interface. It may be realized by transferring to the IC 300L and transferring the refresh detection signal RfDl from the left driver IC 300L to the right driver IC 300R.
- the left driver IC 300L sets the start timing.
- the refresh detection signal RfDl shown is sent to the right driver IC 300R, and the refresh operation (the drive of the source line in the left active area 100L based on the left half data DaL) is started based on the start timing.
- the right driver IC 300R detects the start timing of the refresh operation for updating the image based on the right half data DaR from the host 80, the right driver IC 300R sends a refresh detection signal RfDr indicating the start timing to the left driver IC 300L and the start timing.
- the refresh operation (the drive of the source line in the right active area 100R based on the right half data DaR) is started. Further, when both the left and right driver ICs 300L and 300R receive the refresh detection signal RfDl or RfDr from the other, the refresh operation is started. However, the right or left driver IC 300R, 300L that has received the fresh detection signal RfDl or RfDr detects the refresh start timing with its internal REF (Half), and if the refresh operation has already started, it has already started. The refresh operation being continued is continued, and the refresh detection signal RfDl or RfDr received from the other is ignored.
- the refresh detection signal RfDl or RfDr received from the other is ignored.
- the refresh start timing is detected only by the refresh detection unit (REF (Half)) in one of the left and right driver ICs 300L and 300R, for example, in the left active area 100L.
- the refresh detection unit REF (Half)
- the left driver The refresh of the display image of the left active area 100L by the IC 300L and the refresh of the display image of the right active area 100R by the right driver IC 300R are performed in synchronization.
- the display unit 100 can be driven by the two driver ICs 300L and 300R to display a high-definition image satisfactorily.
- FIG. 11 is a block diagram showing a third configuration example for refresh synchronization in the present embodiment.
- This configuration example is based on a system in which one of a plurality of driver ICs used for driving the active area 100 is a master IC and the other is a slave IC, and the master IC controls the refresh start timing by the slave IC. Yes.
- the left driver IC 300L is a master IC
- the right driver IC 300R is a slave IC.
- the left half data DaL of the refresh data for displaying a new image by the image update is transferred from the host 80 to the left driver IC 300L.
- the right half data DaR is transferred from the host 80 to the right driver IC 300R.
- the left and right driver ICs 300L and 300R include a REF (Half) 305L and a REF (Half) 305R, respectively.
- a signal path (first signal path) 715 for transmitting the refresh detection signal RfD generated by the REF (Half) 305R of the slave IC (right driver IC) 300R to the left driver IC 300L is formed.
- a signal path (hereinafter referred to as “third signal path”) 717 for transmitting the refresh control signal RfC instructing the start of the refresh operation from the master IC (left driver IC) 300L to the slave IC 300R is formed.
- the method of realizing the first and third signal paths 715 and 717 is the same as that of the second configuration example.
- the left half data DaL of the refresh data for displaying a new image by the image update is transferred from the host 80 to the master IC (left driver IC) 300L.
- the right half data DaR is transferred from the host 80 to the slave IC (right driver IC) 300R.
- the REF (Half) 305L of the master IC 300L detects the start timing of the refresh operation for updating the image based on the left half data DaL from the host 80, and the REF (Half) 305R of the slave IC 300R receives the right from the host 80.
- the start timing of the refresh operation for updating the image is detected based on the half data DaR.
- FIG. 12 is a sequence diagram showing an operation example for refresh synchronization when the slave IC 300R detects the refresh start timing earlier than the master IC 300L by the REF (Hlaf) 305R (REF of the slave IC 300R ( The same applies when only the Hlaf) 305R detects the start timing of the refresh).
- the slave IC 300R detects the refresh start timing with the REF (Hlaf) 305R, it sends a refresh detection signal RfD indicating the start timing to the master IC 300L.
- the master IC 300L When the master IC 300L receives the refresh detection signal RfD, the master IC 300L sends a refresh control signal RfC instructing the start of the refresh operation to the slave IC 300R, and also performs a refresh operation (based on the left half data DaL) for the left active area 100L of the display unit 100. Drive of the source line in the left active area 100L) is started.
- the slave IC 300R receives the refresh control signal RfC from the master IC 300L, the slave IC 300R starts a refresh operation (drive of the source line in the right active area 100R based on the right half data DaR) for the right active area 100R of the display unit 100. In this way, the refresh of the display image of the left active area 100L by the master IC 300L and the refresh of the display image of the right active area 100R by the slave IC 300R are synchronized.
- FIG. 13 is a sequence diagram illustrating an operation example for synchronization of refresh when the master IC 300L detects the refresh start timing earlier than the slave IC 300R by the REF (Hlaf) 305L (REF of the master IC 300L ( The same applies to the case where only the Hlaf) 305L detects the refresh start timing).
- the master IC 300L detects the refresh start timing with the REF (Hlaf) 305L, it sends a refresh control signal RfC instructing the start of the refresh operation to the slave IC 300R, and for the left active area 100L of the display unit 100
- the refresh operation (drive of the source line in the left active area 100L based on the left half data DaL) is started.
- the slave IC 300R When the slave IC 300R receives the refresh control signal RfC from the master IC 300L, the slave IC 300R starts a refresh operation (drive of the source line in the right active area 100R based on the right half data DaR) for the right active area 100R of the display unit 100. In this way, the refresh of the display image of the left active area 100L by the master IC 300L and the refresh of the display image of the right active area 100R by the slave IC 300R are synchronized.
- the synchronization accuracy of both refreshes is higher than that in the second configuration example described above. high.
- the master IC 300L that has received the refresh detection signal RfD sent from the slave IC 300R sends the refresh control signal RfC to the slave IC 300R. Then, the refresh operation in the slave IC 300R is started.
- the second configuration example is more advantageous than the present configuration example in terms of the time from the occurrence of an event requiring refresh to the start of refresh of the display image, that is, the responsiveness related to refresh.
- FIG. 14 is a diagram showing an overall configuration of a liquid crystal display device according to the second embodiment of the present invention.
- the liquid crystal display device has the same configuration as that of the first embodiment except for the configuration related to the connection with the host 80. For this reason, the same or corresponding parts are denoted by the same reference numerals, and detailed description of the present embodiment is omitted.
- this embodiment is also configured to be able to perform pause driving as in the first embodiment (see FIG. 8).
- the left and right driver ICs 300L and 300R are also connected to the host 80 through the appropriate interface described above, such as an interface conforming to the MIPI-DSI standard.
- the data corresponding to the entire image to be displayed on the display unit (active area) 100 that is, the image for one screen (hereinafter also referred to as “one screen data”).
- a data path 720 for transferring data Da for one screen from the host 80 to both the left and right driver ICs 300L and 300R is realized.
- the single screen data Da includes timing information (synchronization signal, data enable signal, clock signal, etc.) necessary for displaying the image. Is also included.
- This embodiment has the following configuration in order to synchronize the refresh by the left driver IC 300L and the refresh by the right driver IC 300R.
- FIG. 15 is a block diagram illustrating a first configuration example for refresh synchronization in the present embodiment.
- This configuration example is the first configuration in the first embodiment except that a data path 720 for transferring data Da for one screen from the host 80 to both the left and right driver ICs 300L and 300R is formed. It has the same configuration as the example (FIG. 9). Therefore, in this configuration example, the same portions as those in the first configuration example of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- refresh data that is data Da for one screen for displaying a new image by the image update is transferred to the left and right driver ICs 300L and 300R, and the refresh data is used.
- a refresh control signal RfC instructing the start of refreshing the display image in the active area 100 is transferred from the host 80 to the left and right driver ICs 300L and 300R.
- Both the left and right driver ICs 300L and 300R (TCON) receive the data Da for one screen from the host 80 and the refresh control signal RfC.
- TCON is based on data for refreshing the display image of the left active area 100L among the received data for one screen Da, that is, data corresponding to the left half data DaL in the first embodiment.
- An image signal and a control signal for operating SD are generated, and these signals are output to SD at a timing based on the refresh control signal RfC.
- This SD is based on these image signals and control signals, by applying a data signal representing an image (left half image) to be displayed in the left active area 100L to the source lines in the left active area 100L, respectively. Drive.
- TCON is based on data for refreshing the display image of the right active area 100R among the received data Da for one screen, that is, data corresponding to the right half data DaR in the first embodiment.
- An image signal and a control signal for operating SD are generated, and these signals are output to SD at a timing based on the refresh control signal RfC.
- This SD is based on these image signals and control signals, by applying a data signal representing an image (right half image) to be displayed in the right active area 100R to the source lines in the right active area 100R, respectively. Drive.
- the left and right driver ICs 300L and 300R both drive the source line based on the refresh control signal RfC of the host 80, the left driver IC 300L refreshes the display image of the left active area 100L and the right The refresh of the display image of the right active area 100R by the driver IC 300R is synchronized. For this reason, even when the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment, an abnormality such as a display shift does not occur.
- the same effects as those of the first configuration example of the first embodiment can be obtained.
- FIG. 16 is a block diagram showing a second configuration example for refresh synchronization in the present embodiment.
- This configuration example is the second configuration in the first embodiment except that a data path 720 for transferring data Da for one screen from the host 80 to both the left and right driver ICs 300L and 300R is formed. It has the same configuration as the example (FIG. 10). Therefore, in this configuration example, the same portions as those in the second configuration example of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- refresh data which is data for one screen for displaying a new image by the image update, is transferred to the left and right driver ICs 300L and 300R.
- the REF (Half) 305L of the left driver IC 300L corresponds to the data for refreshing the display image of the left active area 100L among the data Da for one screen from the host 80, that is, the left half data DaL in the first embodiment.
- the start timing of the refresh operation for updating the image is detected based on the data to be updated.
- the left driver IC 300L sends a refresh detection signal RfD1 indicating the start timing to the right driver IC 300R, and also performs a refresh operation (the data for one screen described above) based on the start timing.
- the driving of the source line in the left active area 100L based on the data corresponding to the left half data DaL of Da is started.
- the REF (Half) 305R of the right driver IC 300R corresponds to the data for refreshing the display image of the right active area 100L among the data Da for one screen from the host 80, that is, the right half data DaR in the first embodiment.
- the start timing of the refresh operation for updating the image is detected based on the data to be updated.
- the right driver IC 300R sends a refresh detection signal RfDr indicating the start timing to the left driver IC 300L, and also performs a refresh operation (the data for one screen described above) based on the start timing. (Driving of the source line in the right active area 100R based on data corresponding to the right half data DaR of Da) is started.
- the left and right driver ICs 300L and 300R both receive the refresh detection signal RfDl or RfDr from the other, the refresh operation is started.
- the right or left driver IC 300R, 300L that has received the fresh detection signal RfDl or RfDr detects the refresh start timing with its internal REF (Half), and if the refresh operation has already started, it has already started. Continue the refresh operation being performed.
- the left driver IC 300L can refresh the display image of the left active area 100L and the right driver IC 300R can perform the right active area.
- the refresh of the display image of 100R is synchronized. For this reason, even when the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment, an abnormality such as a display shift does not occur.
- FIG. 17 is a block diagram showing a third configuration example for refresh synchronization in the present embodiment.
- This configuration example is the third configuration in the first embodiment except that a data path 720 for transferring data Da for one screen from the host 80 to both the left and right driver ICs 300L and 300R is formed. It has the same configuration as the example (FIG. 11). Therefore, in the present configuration example, the same parts as those in the third configuration example in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- the left driver IC 300L is a master IC and the right driver IC 300R is a slave IC.
- refresh data which is data for one screen for displaying a new image by the image update
- the REF (Half) 305L of the master IC 300L detects the start timing of the refresh operation for updating the image based on the data corresponding to the left half data DaL among the data Da for one screen from the host 80
- the REF of the slave IC 300R detects the start timing of the refresh operation for updating the image based on data corresponding to the right half data DaR among the data Da for one screen from the host 80.
- the left driver IC 300L can refresh the display image of the left active area 100L and the right driver IC 300R can perform the right active area.
- the refresh of the display image of 100R is synchronized. For this reason, even when the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment, an abnormality such as a display shift does not occur.
- FIG. 18 is a block diagram illustrating a fourth configuration example for refresh synchronization in the present embodiment.
- This configuration example can be said to be a modification of the third configuration example (FIG. 17), and the master IC (left driver IC) 300L serves as a refresh detection unit instead of REF (Half) 305L. ) 305La is incorporated, and the slave IC (right driver IC) 300R does not contain the refresh detection unit (REF (Half)), and no signal path is provided for transmitting the refresh detection signal.
- This configuration example has the same configuration as the third configuration example (FIG. 17) in the other portions.
- refresh data which is data for one screen for displaying a new image by the image update
- the REF (All) 305L of the master IC 300L detects the start timing of the refresh operation for updating the image based on the data Da for one screen from the host 80. Therefore, not only the change of the image to be displayed in the left active area 100L but also the change of the image to be displayed in the right active area 100R can be determined by the master IC 300L and the refresh start timing can be detected, and the refresh in the slave IC 300R can be detected. It is not necessary to detect the start timing.
- the master IC 300L detects the refresh start timing based on the one-screen data Da from the host 80, the master IC 300L sends a refresh control signal RfC instructing the start of the refresh operation to the slave IC 300R, and the left active area 100L based on the start timing. Refresh operation (the drive of the source line in the left active area 100L based on the data corresponding to the left half data DaL of the one-screen data Da) is started.
- the slave IC 300R starts a refresh operation for the right active area 100R.
- the same effect as that of the third configuration example (FIG. 17) of the present embodiment is achieved.
- the left driver IC 300L refreshes the display image of the left active area 100L and the right driver IC 300R performs the right active.
- the refresh of the display image in the area 100R is synchronized. For this reason, even when the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment, an abnormality such as a display shift does not occur.
- since not only control of the start timing of the refresh operation but also detection of the start timing is performed only by the master IC 300L, it is more advantageous than the third configuration example of the present embodiment in terms of responsiveness regarding refresh. is there.
- FIG. 19 is a block diagram showing a fifth configuration example for refresh synchronization in the present embodiment.
- the left and right driver ICs 300L and 300R incorporate REF (All) 305La and REF (All) 305Ra as refresh detection units, respectively, and a signal path and refresh control for transmitting a refresh detection signal No signal path is provided for transmitting the signal.
- the data Da for one screen for displaying a new image by the image update is transferred as refresh data to the left driver IC 300L and the right driver IC 300R.
- Both the REF (All) 305La of the left driver IC 300L and the REF (All) 305Ra of the right driver IC 300R detect the start timing of the refresh operation for updating the image based on the data Da for one screen. Therefore, in both the left and right driver ICs 300L and 300R, it is possible to determine both the change of the image to be displayed in the left active area 100L and the change of the image to be displayed in the right active area 100R, and according to the determination result. Thus, the start timing of the refresh can be detected.
- the left driver IC 300L detects the start timing of the refresh operation for updating the image based on the data Da for one screen from the host 80 by the REF (All) 305La
- the left driver IC 300L performs the refresh operation (one screen for the left active area 100L).
- the driving of the source line in the left active area 100L based on the data Da corresponding to the left half data DaL is started.
- the right driver IC 300R detects the start timing of the refresh operation for updating the image based on the one-screen data Da from the host 80, the right driver IC 300R refreshes the right active area 100R (the right of the one-screen data Da
- the driving of the source line in the right active area 100R based on the data corresponding to the half data DaR is started.
- the left and right driver ICs 300L and 300R detect the refresh start timing based on the same one-screen data Da from the host 80, so the left active area by the left driver IC 300L.
- the refresh of the display image of 100L and the refresh of the display image of the right active area 100R by the right driver IC 300R are synchronized. For this reason, even when the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment, an abnormality such as a display shift does not occur.
- FIG. 20 is a diagram showing an overall configuration of a liquid crystal display device according to the third embodiment of the present invention.
- the liquid crystal display device has the same configuration as that of the second embodiment except for the configuration related to the connection with the host 80. For this reason, the same or corresponding parts are denoted by the same reference numerals, and detailed description of the present embodiment is omitted. Hereinafter, parts different from the second embodiment will be mainly described. Note that this embodiment is also configured to be able to perform a rest drive, as in the first and second embodiments (see FIG. 8).
- the left and right driver ICs 300L and 300R are also connected to the host 80 through the appropriate interface described above, such as an interface conforming to the MIPI-DSI standard.
- the left and right drivers according to the above interface are used to transfer data for one screen corresponding to the entire image to be displayed on the display unit (active area) 100, that is, one screen image. Transfer to IC 300L, 300R.
- two data paths for dividing the data for one screen into two half-screen data and transferring them from the host 80 to the left and right driver ICs 300L and 300R are formed based on the interface. .
- One of the two data paths is an odd-numbered column data DodH of the odd-numbered column data DodH and the even-numbered column data DevH corresponding to two images obtained by dividing an image for one screen into an odd number and an even number in the horizontal direction.
- odd column data DodH corresponds to an image composed of odd-numbered pixel columns in a pixel matrix constituting an image for one screen
- even-numbered column data DevH represents even-numbered pixels in the pixel matrix.
- each of the driver ICs 300L and 300R receives the odd-numbered column data DodH via the odd-numbered subdata path 731 and also receives the even-numbered column data DevH via the even-numbered subdata path 732, whereby Input data is supplied from the outside for each line data corresponding to one pixel row arranged along the line.
- this embodiment is the same as the second embodiment in that data for one screen is transferred to the left and right driver ICs 300L and 300R, but two lines of data are used for transferring data for one screen. Since the paths 731 and 732 are used, there is an advantage that the operating frequency for data transfer is low.
- This embodiment has the following configuration in order to synchronize the refresh by the left driver IC 300L and the refresh by the right driver IC 300R.
- FIG. 21 is a block diagram showing a first configuration example for refresh synchronization in the present embodiment.
- the second data path described above is formed between the host 80 and the left and right driver ICs 300L and 300R, except that the above-described two systems of data paths, that is, the odd sub data path 731 and the even sub data path 732 are formed.
- This embodiment has the same configuration as the first configuration example (FIG. 15) in the embodiment. Therefore, in this configuration example, the same portions as those in the first configuration example of the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- refresh data which is data for one screen for displaying a new image by the image update, is divided into odd-numbered column data DodH and even-numbered column data DevH, and the odd-numbered sub data path 731.
- the refresh control signal RfC is transferred from the host 80 to the left and right driver ICs 300L and 300R through the even-numbered sub data path 732 and instructed to start refreshing the display image in the active area 100 by the refresh data. , 300R.
- Both the left and right driver ICs 300L and 300R receive data for one screen composed of the odd-numbered column data DodH and the even-numbered column data DevH, and also receive the refresh control signal RfC.
- the present embodiment is the same as the second embodiment in that both the left and right driver ICs 300L and 300R receive data for one screen, and therefore the left and right drivers in the present configuration example thereafter.
- the operations of the ICs 300L and 300R are the same as those in the first configuration example (FIG. 15) of the second embodiment.
- the same effect as that of the first configuration example of the second embodiment is achieved, and the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment.
- an abnormality such as a display shift does not occur.
- FIG. 22 is a block diagram showing a second configuration example for refresh synchronization in the present embodiment.
- the second data path described above is formed between the host 80 and the left and right driver ICs 300L and 300R, except that the above-described two systems of data paths, that is, the odd sub data path 731 and the even sub data path 732 are formed.
- the second embodiment has the same configuration as that of the second configuration example (FIG. 16). Therefore, in this configuration example, the same portions as those in the second configuration example of the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- refresh data which is data for one screen for displaying a new image by the image update, is divided into odd-numbered column data DodH and even-numbered column data DevH, and the odd-numbered sub data path 731. And are transferred to the left and right driver ICs 300L and 300R through the even-numbered sub data path 732. Both the left and right driver ICs 300L and 300R receive data for one screen including the odd-numbered column data DodH and the even-numbered column data DevH.
- the present embodiment is the same as the second embodiment in that both the left and right driver ICs 300L and 300R receive data for one screen, and therefore the left and right drivers in the present configuration example thereafter.
- the operations of the ICs 300L and 300R are the same as those of the second configuration example (FIG. 16) of the second embodiment.
- the same effects as those of the second configuration example of the second embodiment can be obtained, and the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment.
- an abnormality such as a display shift does not occur.
- FIG. 23 is a block diagram showing a third configuration example for refresh synchronization in the present embodiment.
- the second data path described above is formed between the host 80 and the left and right driver ICs 300L and 300R, except that the above-described two systems of data paths, that is, the odd sub data path 731 and the even sub data path 732 are formed.
- the third embodiment has the same configuration as the third configuration example (FIG. 17). Therefore, in this configuration example, the same portions as those in the third configuration example of the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- refresh data which is data for one screen for displaying a new image by the image update, is divided into odd-numbered column data DodH and even-numbered column data DevH, and the odd-numbered sub data path 731. And are transferred to the left and right driver ICs 300L and 300R through the even-numbered sub data path 732. Both the left and right driver ICs 300L and 300R receive data for one screen including the odd-numbered column data DodH and the even-numbered column data DevH.
- the present embodiment is the same as the second embodiment in that both the left and right driver ICs 300L and 300R receive data for one screen, and therefore the left and right drivers in the present configuration example thereafter.
- the operations of the ICs 300L and 300R are the same as those in the third configuration example (FIG. 17) of the second embodiment.
- the same effect as the third configuration example of the second embodiment is achieved, and the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment.
- an abnormality such as a display shift does not occur.
- FIG. 24 is a block diagram illustrating a fourth configuration example for refresh synchronization in the present embodiment.
- the second data path described above is formed between the host 80 and the left and right driver ICs 300L and 300R, except that the above-described two systems of data paths, that is, the odd sub data path 731 and the even sub data path 732 are formed.
- the fourth embodiment has the same configuration as the fourth configuration example (FIG. 18). Therefore, in this configuration example, the same parts as those in the fourth configuration example of the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- refresh data which is data for one screen for displaying a new image by the image update, is divided into odd-numbered column data DodH and even-numbered column data DevH, and the odd-numbered sub data path 731. And are transferred to the left and right driver ICs 300L and 300R through the even-numbered sub data path 732. Both the left and right driver ICs 300L and 300R receive data for one screen including the odd-numbered column data DodH and the even-numbered column data DevH.
- the present embodiment is the same as the second embodiment in that both the left and right driver ICs 300L and 300R receive data for one screen, and therefore the left and right drivers in the present configuration example thereafter.
- the operations of the ICs 300L and 300R are the same as those in the fourth configuration example (FIG. 18) of the second embodiment.
- the same effect as that of the fourth configuration example of the second embodiment is achieved, and the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment.
- an abnormality such as a display shift does not occur.
- FIG. 25 is a block diagram showing a fifth configuration example for refresh synchronization in the present embodiment.
- data for one screen is divided into odd-numbered column data DodH and even-numbered column data DevH and transferred from the host 80 to the left and right driver ICs 300L and 300R.
- the configuration is the same as that of the fifth configuration example (FIG. 19) in the second embodiment except that the even-numbered sub data path 732 is formed. Therefore, in this configuration example, the same portions as those in the fifth configuration example of the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- refresh data which is data for one screen for displaying a new image by the image update, is divided into odd-numbered column data DodH and even-numbered column data DevH, and the odd-numbered sub data path 731. And are transferred to the left and right driver ICs 300L and 300R through the even-numbered sub data path 732. Both the left and right driver ICs 300L and 300R receive data for one screen including the odd-numbered column data DodH and the even-numbered column data DevH.
- the present embodiment is the same as the second embodiment in that both the left and right driver ICs 300L and 300R receive data for one screen, and therefore the left and right drivers in the present configuration example thereafter.
- the operations of the ICs 300L and 300R are the same as those of the fifth configuration example (FIG. 19) of the second embodiment.
- the same effect as that of the fifth configuration example of the second embodiment is achieved, and the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment.
- an abnormality such as a display shift does not occur.
- FIG. 26 is a diagram showing an overall configuration of a liquid crystal display device according to the fourth embodiment of the present invention.
- This liquid crystal display device has the same configuration as that of the second embodiment except for the configuration related to the connection with the host 80. For this reason, the same or corresponding parts are denoted by the same reference numerals, and detailed description of the present embodiment is omitted. Hereinafter, parts different from the second embodiment will be mainly described. Note that this embodiment is also configured to be able to perform a rest drive, as in the first and second embodiments (see FIG. 8).
- the left and right driver ICs 300L and 300R are also connected to the host 80 through the appropriate interface described above, such as an interface conforming to the MIPI-DSI standard.
- the left and right drivers according to the above interface are used to transfer data for one screen corresponding to the entire image to be displayed on the display unit (active area) 100, that is, one screen image. Transfer to IC 300L, 300R.
- two data paths for dividing the data for one screen into two half-screen data and transferring them from the host 80 to the left and right driver ICs 300L and 300R are formed based on the forming interface.
- the One of the two data paths is an odd-numbered row data DodV and an odd-numbered row data DodV among the odd-numbered row data DodV and the even-numbered row data DevV corresponding to two images obtained by dividing an image for one screen into an odd number and an even number in the vertical direction.
- odd-row data DodV corresponds to an image composed of odd-numbered pixel rows in a pixel matrix constituting an image for one screen
- even-numbered row data DevV represents even-numbered pixels in the pixel matrix.
- a “pixel row” refers to a row of pixels arranged in the horizontal direction, that is, the gate line extending direction.
- each of the driver ICs 300L and 300R receives the odd-numbered row data DodV via the odd-numbered subdata path 741, and receives the even-numbered row data DevV via the even-numbered subdata path 742, whereby Input data is given from the outside for every two line data corresponding to two pixel rows lined up along the line.
- the odd-numbered row data DodV and the even-numbered row data DevV based on the vertical division are transferred through the odd-numbered subdata path 741 and the even-numbered subdata path 742, respectively. That is, data corresponding to the odd-numbered pixel rows and data corresponding to the even-numbered pixel rows are transferred to both the left and right driver ICs 300L and 300R in parallel through the two data paths. Therefore, each of the left and right driver ICs 300L and 300R in this embodiment adjusts the timing between receiving the odd-numbered row data DodV and the even-numbered row data DevV transferred in this way and driving the source line in the active area 100.
- a line buffer for storing data for at least two pixel rows is provided (see FIGS. 27 to 31 described later).
- this embodiment is the same as the second embodiment in that data for one screen is transferred to the left and right driver ICs 300L and 300R, but two lines of data are used for transferring data for one screen. Since the paths 731 and 732 are used, there is an advantage that the operating frequency for data transfer is low.
- This embodiment has the following configuration in order to synchronize the refresh by the left driver IC 300L and the refresh by the right driver IC 300R.
- FIG. 27 is a block diagram showing a first configuration example for refresh synchronization in the present embodiment.
- the above-described two systems of data paths that is, the odd sub data path 741 and the even sub data path 742 are formed between the host 80 and the left and right driver ICs 300L and 300R.
- the left and right driver ICs 300 ⁇ / b> L are used for timing adjustment between receiving the odd-numbered row data DodV and even-numbered row data DevV transferred through the two data paths and driving the source lines in the active area 100.
- the 300R includes line buffers 307L and 307R that store data for at least one pixel row.
- this configuration example has the same configuration as the first configuration example (FIG. 15) in the second embodiment. Therefore, in this configuration example, the same portions as those in the first configuration example of the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- refresh data which is data for one screen for displaying a new image by the image update, is divided into odd-numbered row data DodV and even-numbered row data DevV, and odd-numbered sub data path 741.
- the refresh control signal RfC is transferred from the host 80 to the left and right driver ICs 300L and 300R through the even-numbered sub data path 742 and instructed to start refreshing the display image in the active area 100 by the refresh data. , 300R.
- Both the left and right driver ICs 300L and 300R receive the data for one screen including the odd-numbered row data DodV and the even-numbered row data DevV, and also receive the refresh control signal RfC.
- the present embodiment is the same as the second embodiment in that both the left and right driver ICs 300L and 300R receive data for one screen, and therefore the left and right drivers in the present configuration example thereafter.
- the operations of the ICs 300L and 300R are basically the same as those of the first configuration example (FIG. 15) of the second embodiment.
- the timing adjustment between the reception of the odd-numbered row data DodV and the even-numbered row data DevV transferred through the two-system data path based on the vertical division and the drive of the source line in the active area 100 is performed.
- the timing adjustment is performed by the line buffers 307L and 307R provided in the left and right driver ICs 300L and 300R, respectively. This is the same in other configuration examples in the present embodiment.
- the configuration for such timing adjustment is different from the first configuration example (FIG. 15) of the second embodiment.
- the same effect as that of the first configuration example of the second embodiment is achieved, and the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment.
- an abnormality such as a display shift does not occur.
- FIG. 28 is a block diagram showing a second configuration example for refresh synchronization in the present embodiment.
- the two data paths described above that is, the odd sub data path 741 and the even sub data path 742 are formed between the host 80 and the left and right driver ICs 300L and 300R.
- the left and right driver ICs 300L and 300R use the line buffers 307L and 307R to adjust the timing of receiving the odd-numbered row data DodV and the even-numbered row data DevV and driving the source lines in the active area 100, respectively.
- it has the same configuration as the second configuration example (FIG. 16) in the second embodiment. Therefore, in this configuration example, the same portions as those in the second configuration example of the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- the left and right driver ICs 300L and 300R cause the odd-numbered row data DodV and the even-numbered row data that constitute refresh data that is data for one screen for displaying a new image by the image update.
- Receive DevV the left and right driver ICs 300L and 300R cause the odd-numbered row data DodV and the even-numbered row data that constitute refresh data that is data for one screen for displaying a new image by the image update.
- Receive DevV Receive DevV.
- the present embodiment is the same as the second embodiment in that both the left and right driver ICs 300L and 300R receive data for one screen, and therefore the left and right drivers in the present configuration example thereafter.
- the operations of the ICs 300L and 300R are the same as those of the second configuration example (FIG. 16) of the second embodiment except for the timing adjustment described above by the line buffers 307L and 307R.
- the same effects as those of the second configuration example of the second embodiment can be obtained, and the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment.
- an abnormality such as a display shift does not occur.
- FIG. 29 is a block diagram showing a third configuration example for refresh synchronization in the present embodiment.
- the two data paths described above that is, the odd sub data path 741 and the even sub data path 742 are formed between the host 80 and the left and right driver ICs 300L and 300R.
- the left and right driver ICs 300L and 300R use the line buffers 307L and 307R to adjust the timing of receiving the odd-numbered row data DodV and the even-numbered row data DevV and driving the source lines in the active area 100, respectively.
- it has the same configuration as the third configuration example (FIG. 17) in the second embodiment. Therefore, in this configuration example, the same portions as those in the third configuration example of the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- the left and right driver ICs 300L and 300R cause the odd-numbered row data DodV and the even-numbered row data that constitute refresh data that is data for one screen for displaying a new image by the image update.
- Receive DevV the left and right driver ICs 300L and 300R cause the odd-numbered row data DodV and the even-numbered row data that constitute refresh data that is data for one screen for displaying a new image by the image update.
- Receive DevV Receive DevV.
- the present embodiment is the same as the second embodiment in that both the left and right driver ICs 300L and 300R receive data for one screen, and therefore the left and right drivers in the present configuration example thereafter.
- the operations of the ICs 300L and 300R are the same as those in the third configuration example (FIG. 17) of the second embodiment except for the timing adjustment described above by the line buffers 307L and 307R.
- the same effect as the third configuration example of the second embodiment is achieved, and the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment.
- an abnormality such as a display shift does not occur.
- FIG. 30 is a block diagram illustrating a fourth configuration example for refresh synchronization in the present embodiment.
- the two data paths described above that is, the odd sub data path 741 and the even sub data path 742 are formed between the host 80 and the left and right driver ICs 300L and 300R.
- the left and right driver ICs 300L and 300R use the line buffers 307L and 307R to adjust the timing of receiving the odd-numbered row data DodV and the even-numbered row data DevV and driving the source lines in the active area 100, respectively.
- it has the same configuration as the fourth configuration example (FIG. 18) in the second embodiment. Therefore, in this configuration example, the same portions as those in the fourth configuration example of the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- the left and right driver ICs 300L and 300R cause the odd-numbered row data DodV and the even-numbered row data that constitute refresh data that is data for one screen for displaying a new image by the image update.
- Receive DevV the left and right driver ICs 300L and 300R cause the odd-numbered row data DodV and the even-numbered row data that constitute refresh data that is data for one screen for displaying a new image by the image update.
- Receive DevV Receive DevV.
- the present embodiment is the same as the second embodiment in that both the left and right driver ICs 300L and 300R receive data for one screen, and therefore the left and right drivers in the present configuration example thereafter.
- the operations of the ICs 300L and 300R are the same as those in the fourth configuration example (FIG. 18) of the second embodiment except for the timing adjustment described above by the line buffers 307L and 307R.
- the same effect as that of the fourth configuration example of the second embodiment is achieved, and the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment.
- an abnormality such as a display shift does not occur.
- FIG. 31 is a block diagram showing a fifth configuration example for refresh synchronization in the present embodiment.
- the two data paths described above that is, the odd sub data path 741 and the even sub data path 742 are formed between the host 80 and the left and right driver ICs 300L and 300R.
- the left and right driver ICs 300L and 300R use the line buffers 307L and 307R to adjust the timing of receiving the odd-numbered row data DodV and the even-numbered row data DevV and driving the source lines in the active area 100, respectively.
- it has the same configuration as the fifth configuration example (FIG. 19) in the second embodiment. Therefore, in this configuration example, the same portions as those in the fifth configuration example of the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- the left and right driver ICs 300L and 300R cause the odd-numbered row data DodV and the even-numbered row data that constitute refresh data that is data for one screen for displaying a new image by the image update.
- Receive DevV the left and right driver ICs 300L and 300R cause the odd-numbered row data DodV and the even-numbered row data that constitute refresh data that is data for one screen for displaying a new image by the image update.
- Receive DevV Receive DevV.
- the present embodiment is the same as the second embodiment in that both the left and right driver ICs 300L and 300R receive data for one screen, and therefore the left and right drivers in the present configuration example thereafter.
- the operations of the ICs 300L and 300R are the same as those of the fifth configuration example (FIG. 19) of the second embodiment except for the timing adjustment described above by the line buffers 307L and 307R.
- the same effect as that of the fifth configuration example of the second embodiment is achieved, and the display unit 100 is driven by the two driver ICs 300L and 300R as in the present embodiment.
- an abnormality such as a display shift does not occur.
- the display unit (active area) 100 is driven using the two driver ICs 300L and 300R.
- three or more driver ICs are provided.
- the present invention can also be applied to the case where the display unit is driven using the display unit (see FIG. 6).
- three or more driver ICs are used in two types of configuration examples (see FIGS. 11, 17, 23, and 29) in which the driver IC that drives the display unit is identified as a master IC and a slave IC, respectively.
- the display unit (source line in the active area) is configured to be shared and driven by a plurality of driver ICs.
- the driving is not limited to a plurality of driver ICs.
- a drive circuit (SD: source driver) that includes a plurality of drive control circuits that share and drive data signal lines (source lines) in the display unit, and generates a data signal to be applied to the data signal lines in each drive control circuit
- the present invention can be applied to any display device that includes a control circuit (TCON: timing controller) that generates a signal for controlling this.
- the liquid crystal display device that performs pause driving has been described as an example.
- the present invention is not limited to this, and any organic EL (Electro-Luminescence) may be used as long as the display device performs pause driving. It can also be applied to other display devices such as display devices.
- the present invention can be applied to a display device that performs pause driving using a plurality of driver ICs and a driving method thereof.
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Abstract
Description
前記画像を表示するための表示部と、
前記入力データに基づいて前記表示部における表示画像をリフレッシュするリフレッシュ期間と前記表示部における表示画像のリフレッシュを休止する非リフレッシュ期間とが交互に現れるように前記表示部を駆動するための駆動制御部と、
前記入力データを外部から前記駆動制御部に与えるためのデータ経路と
を備え、
前記駆動制御部は、前記表示部の表示領域を分割することにより得られる複数のサブ表示領域にそれぞれ対応する複数の駆動制御回路を含み、
各駆動制御回路は、前記表示部における表示画像をリフレッシュするためのデータが前記入力データとして外部から与えられる場合に、前記入力データに基づくリフレッシュの開始タイミングに対応づけられたリフレッシュ開始情報を、前記入力データに基づき当該駆動制御回路内で取得するか、または、他の前記駆動制御回路もしくは外部から取得し、当該取得されたリフレッシュ開始情報に基づき、当該駆動制御回路に対応するサブ表示領域における表示画像のリフレッシュが他の前記駆動制御回路に対応するサブ表示領域における表示画像のリフレッシュと同期して開始されるように前記表示部を駆動することを特徴とする。
前記データ経路は、前記複数のサブ表示領域にそれぞれ対応する複数のサブデータ経路を含み、
各駆動制御回路は、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータをサブ入力データとして当該サブ表示領域に対応するサブデータ経路を介して外部から受け取り、当該サブ入力データに基づき当該サブ表示領域に画像が表示されるように前記表示部を駆動することを特徴とする。
各駆動制御回路は、前記入力データを前記データ経路を介して外部から受け取り、前記入力データに基づき対応するサブ表示領域に画像が表示されるように前記表示部を駆動することを特徴とする。
前記表示部は、複数のデータ信号線と、前記複数のデータ信号線に交差する複数の走査信号線と、前記複数のデータ信号線および前記複数の走査信号線に沿ってマトリクス状に配置された複数の画素形成部とを含み、
各画素形成部は、前記複数のデータ信号線のいずれか1つに接続されると共に前記複数の走査信号線のいずれか1つに接続され、
前記駆動制御部は、前記入力データに基づき前記複数の画素形成部によって画像が表示されるように前記複数のデータ信号線および前記複数の走査信号線を駆動し、
前記データ経路は、
前記入力データのうち、前記複数の画素形成部によって表示されるべき画像を構成する画素マトリクスにおいて前記データ信号線に沿って並ぶ画素からなる奇数番目の画素列に対応するデータを奇数列データとして外部から各駆動制御回路に転送するための奇数サブデータ経路と、
前記入力データのうち、前記画素マトリクスにおいて前記データ信号線に沿って並ぶ画素からなる偶数番目の画素列に対応するデータを偶数列データとして外部から各駆動制御回路に転送するための偶数サブデータ経路とを含み、
各駆動制御回路は、
前記奇数列データを前記奇数サブデータ経路を介して外部から受け取ると共に、前記偶数列データを前記偶数サブデータ経路を介して外部から受け取ることにより、前記画素マトリクスにおいて前記走査信号線に沿って並ぶ画素からなる1つの画素行に対応する1ラインデータずつ前記入力データを外部から与えられ、
前記奇数列データおよび前記偶数列データのうち対応するサブ表示領域に画像を表示するためのデータに基づき前記表示部の当該サブ表示領域における前記データ信号線を駆動することを特徴とする。
前記表示部は、複数のデータ信号線と、前記複数のデータ信号線に交差する複数の走査信号線と、前記複数のデータ信号線および前記複数の走査信号線に沿ってマトリクス状に配置された複数の画素形成部とを含み、
各画素形成部は、前記複数のデータ信号線のいずれか1つに接続されると共に前記複数の走査信号線のいずれか1つに接続され、
前記駆動制御部は、前記入力データに基づき前記複数の画素形成部によって画像が表示されるように前記複数のデータ信号線および前記複数の走査信号線を駆動し、
前記データ経路は、
前記入力データのうち、前記複数の画素形成部によって表示されるべき画像を構成する画素マトリクスにおいて前記走査信号線に沿って並ぶ画素からなる奇数番目の画素行に対応するデータを奇数行データとして外部から各駆動制御回路に転送するための奇数サブデータ経路と、
前記入力データのうち、前記画素マトリクスにおいて前記走査信号線に沿って並ぶ画素からなる偶数番目の画素行に対応するデータを偶数行データとして外部から各駆動制御回路に転送するための偶数サブデータ経路とを含み、
各駆動制御回路は、
前記奇数行データを前記奇数サブデータ経路を介して外部から受け取ると共に、前記偶数行データを前記偶数サブデータ経路を介して外部から受け取ることにより、前記画素マトリクスにおいて前記データ信号線に沿って並ぶ画素からなる2つの画素行に対応する2ラインデータずつ前記入力データを外部から与えられ、
前記奇数行データおよび前記偶数行データのうち対応するサブ表示領域に画像を表示するためのデータに基づき前記表示部の当該サブ表示領域における前記データ信号線を駆動することを特徴とする。
各駆動制御回路は、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき前記表示部における表示画像のリフレッシュの開始タイミングを検知するためのリフレッシュ検知部を含み、
前記複数の駆動制御回路は、マスタ駆動制御回路として識別される1つの駆動制御回路とスレーブ駆動制御回路として識別される当該マスタ駆動制御回路以外の駆動制御回路とから構成され、
前記マスタ駆動制御回路と前記スレーブ駆動制御回路との間には信号経路が設けられており、
前記スレーブ駆動制御回路は、そのリフレッシュ検知部によって前記リフレッシュの開始タイミングが検知されると、当該開始タイミングを示すリフレッシュ検知信号を前記リフレッシュ開始情報として前記信号経路を介して前記マスタ駆動制御回路に送り、
前記マスタ駆動制御回路は、そのリフレッシュ検知部によって前記リフレッシュの開始タイミングが検知されるか、または、前記スレーブ駆動制御回路から前記信号経路を介して前記リフレッシュ検知信号を受け取ると、前記リフレッシュの開始を指示するリフレッシュ制御信号を前記リフレッシュ開始情報として前記信号経路を介して前記スレーブ駆動制御回路に送ると共に、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動し、
前記スレーブ駆動制御回路は、前記マスタ駆動制御回路から前記信号経路を介して前記リフレッシュ制御信号を受け取ると、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動することを特徴とする。
前記複数の駆動制御回路は、マスタ駆動制御回路として識別される1つの駆動制御回路とスレーブ駆動制御回路として識別される当該マスタ駆動制御回路以外の駆動制御回路とから構成され、
前記マスタ駆動制御回路と前記スレーブ駆動制御回路との間には信号経路が設けられており、
前記マスタ駆動制御回路は、
前記入力データに基づき前記表示部における表示画像のリフレッシュの開始タイミングを検知するためのリフレッシュ検知部を含み、
前記リフレッシュ検知部によって前記リフレッシュの開始タイミングが検知されると、前記リフレッシュの開始を指示するリフレッシュ制御信号を前記リフレッシュ開始情報として前記信号経路を介して前記スレーブ駆動制御回路に送ると共に、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動し、
前記スレーブ駆動制御回路は、前記マスタ駆動制御回路から前記信号経路を介して前記リフレッシュ制御信号を受け取ると、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動することを特徴とする。
前記複数の駆動制御回路を相互に接続する信号経路を更に備え、
各駆動制御回路は、
前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき前記表示部における表示画像のリフレッシュの開始タイミングを検知するためのリフレッシュ検知部を含み、
前記リフレッシュ検知部によって前記リフレッシュの開始タイミングが検知されると、当該開始タイミングを示すリフレッシュ検知信号を前記リフレッシュ開始情報として前記信号経路を介して他の前記駆動制御回路に送ると共に、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動し、
他の前記駆動制御回路のいずれかから前記信号経路を介して前記リフレッシュ検知信号を受け取ると、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動することを特徴とする。
各駆動制御回路は、
前記入力データに基づき前記表示部における表示画像のリフレッシュの開始タイミングを検知するためのリフレッシュ検知部を含み、
前記リフレッシュ検知部によって前記リフレッシュの開始タイミングが検知されると、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動することを特徴とする。
前記入力データに基づき前記表示部における表示画像のリフレッシュの開始を指示するリフレッシュ制御信号を前記リフレッシュ開始情報として外部から受け取るための制御信号経路を更に備え、
各駆動制御回路は、前記リフレッシュ制御信号を前記制御信号経路を介して外部から受け取ると、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動することを特徴とする。
各駆動制御回路は単一のICチップとして構成されていることを特徴とする。
前記表示部は、表示すべき画像を構成する各画素を形成するためのスイッチング素子として、酸化物半導体によりチャネル層が形成された薄膜トランジスタを含むことを特徴とする。
<0.1 全体構成>
本発明の各実施形態について説明する前に、まず、各実施形態の基本となる構成(以下「基本構成」)について説明する。
既述のように、近年、携帯型電子機器用の液晶表示装置において使用可能な1チップドライバが提供されている。図1に示した液晶表示装置の場合、1チップドライバを使用すれば、ソースドライバ310、ゲートドライバ320、および表示制御回路200を含む回路300が1個のICで実現される。図1に示した液晶表示装置には、1チップドライバとして、例えば図2に示す構成のドライバIC300を使用することができる。
図7は、本発明の第1の実施形態に係る液晶表示装置の全体構成を示す図である。この液晶表示装置は、アクティブマトリクス型の液晶表示パネル10を備え、この液晶表示パネル100には、表示部(アクティブエリア)100が形成されると共に、2個のドライバICが左ドライバIC300Lおよび右ドライバIC300Rとして実装されている。アクティブエリア100は、ソースラインに沿った分割線で左アクティブエリア100Lと右アクティブエリア100Rとに分割されており、左アクティブエリア100Lにおけるソースラインは左ドライバIC300Lによって駆動され、右アクティブエリア100Rにおけるソースラインは右ドライバIC300Rによって駆動される。
図9は、本実施形態におけるリフレッシュの同期化のための第1の構成例を示すブロック図である。本構成例では、左および右ドライバIC300L,300Rは、いずれも、SD(ソースドライバ)およびTCON(タイミングコントローラ)を内蔵しているが、REF(リフレッシュ検知部)を有していない。本構成例では、上記画像更新のためのリフレッシュ動作の開始を指示するリフレッシュ制御信号RfCがホスト80から出力され、このリフレッシュ制御信号RfCを左および右ドライバIC300L,300Rの双方に伝達するための経路(以下「制御信号経路」という)714が形成されている。この制御信号経路714は、ホスト80と左および右ドライバIC300L,300Rとの間に専用の信号線を配設することにより実現してもよいし、これに代えて、ホスト80と左および右ドライバIC300L,300Rとの接続に使用されるインターフェース(例えばI2C規格またはSPI規格に準拠したインターフェース)に従ってホスト80から左および右ドライバIC300L,300Rにリフレッシュ制御信号RfCを転送することにより実現してもよい。
図10は、本実施形態におけるリフレッシュの同期化のための第2の構成例を示すブロック図である。本構成例では、上記画像更新のためのリフレッシュ動作の開始を指示するリフレッシュ制御信号RfCはホスト80から出力されない。
図11は、本実施形態におけるリフレッシュの同期化のための第3の構成例を示すブロック図である。本構成例は、アクティブエリア100の駆動に使用される複数のドライバICのうち1つをマスタICとし他をスレーブICとし、マスタICがスレーブICによるリフレッシュの開始タイミングを制御するという方式に基づいている。図11に示すように本構成例では、左ドライバIC300LをマスタICとし、右ドライバIC300RをスレーブICとしている。
図14は、本発明の第2の実施形態に係る液晶表示装置の全体構成を示す図である。この液晶表示装置は、ホスト80との接続に関する構成以外については、上記第1の実施形態と同様の構成を有している。このため、同一または対応する部分には同一の参照符号を付して、本実施形態に関する詳しい説明を省略し、以下では上記第1の実施形態と相違する部分を中心に説明する。なお本実施形態も、上記第1の実施形態と同様、休止駆動を行えるように構成されている(図8参照)。
図15は、本実施形態におけるリフレッシュの同期化のための第1の構成例を示すブロック図である。本構成例は、ホスト80から1画面分データDaを左および右ドライバIC300L,300Rの双方に転送するためのデータ経路720が形成される点を除き、上記第1の実施形態における第1の構成例(図9)と同様の構成を有している。そこで、本構成例のうち上記第1の実施形態の第1の構成例と同一の部分については同一の参照符号を付して詳しい説明を省略する。
図16は、本実施形態におけるリフレッシュの同期化のための第2の構成例を示すブロック図である。本構成例は、ホスト80から1画面分データDaを左および右ドライバIC300L,300Rの双方に転送するためのデータ経路720が形成される点を除き、上記第1の実施形態における第2の構成例(図10)と同様の構成を有している。そこで、本構成例のうち上記第1の実施形態の第2の構成例と同一の部分については同一の参照符号を付して詳しい説明を省略する。
図17は、本実施形態におけるリフレッシュの同期化のための第3の構成例を示すブロック図である。本構成例は、ホスト80から1画面分データDaを左および右ドライバIC300L,300Rの双方に転送するためのデータ経路720が形成される点を除き、上記第1の実施形態における第3の構成例(図11)と同様の構成を有している。そこで、本構成例のうち上記第1の実施形態における第3の構成例と同一の部分については同一の参照符号を付して詳しい説明を省略する。なお、図17に示すように本構成例では、左ドライバIC300LをマスタICとし、右ドライバIC300RをスレーブICとしている。
図18は、本実施形態におけるリフレッシュの同期化のための第4の構成例を示すブロック図である。本構成例は、上記第3の構成例(図17)の変形例と言えるものであり、マスタIC(左ドライバIC)300Lは、リフレッシュ検知部として、REF(Half)305Lに代えてREF(All)305Laを内蔵し、スレーブIC(右ドライバIC)300Rにはリフレッシュ検知部(REF(Half))を内蔵せず、リフレッシュ検知信号を伝達するための信号経路も設けられていない。本構成例は、その他の部分については上記第3の構成例(図17)と同様の構成を有している。
図19は、本実施形態におけるリフレッシュの同期化のための第5の構成例を示すブロック図である。本構成例では、左および右ドライバIC300L,300Rが、リフレッシュ検知部としてREF(All)305LaおよびREF(All)305Raをそれぞれを内蔵しており、リフレッシュ検知信号を伝達するための信号経路およびリフレッシュ制御信号を伝達するための信号経路はいずれも設けられていない。
図20は、本発明の第3の実施形態に係る液晶表示装置の全体構成を示す図である。この液晶表示装置は、ホスト80との接続に関する構成以外については、上記第2の実施形態と同様の構成を有している。このため、同一または対応する部分には同一の参照符号を付して、本実施形態に関する詳しい説明を省略し、以下では上記第2の実施形態と相違する部分を中心に説明する。なお本実施形態も、上記第1および第2の実施形態と同様、休止駆動を行えるように構成されている(図8参照)。
図21は、本実施形態におけるリフレッシュの同期化のための第1の構成例を示すブロック図である。本構成例は、ホスト80と左および右ドライバIC300L,300Rとの間に既述の2系統のデータ経路すなわち奇数サブデータ経路731および偶数サブデータ経路732が形成される点を除き、上記第2の実施形態における第1の構成例(図15)と同様の構成を有している。そこで、本構成例のうち上記第2の実施形態の第1の構成例と同一の部分については同一の参照符号を付して詳しい説明を省略する。
図22は、本実施形態におけるリフレッシュの同期化のための第2の構成例を示すブロック図である。本構成例は、ホスト80と左および右ドライバIC300L,300Rとの間に既述の2系統のデータ経路すなわち奇数サブデータ経路731および偶数サブデータ経路732が形成される点を除き、上記第2の実施形態における第2の構成例(図16)と同様の構成を有している。そこで、本構成例のうち上記第2の実施形態の第2の構成例と同一の部分については同一の参照符号を付して詳しい説明を省略する。
図23は、本実施形態におけるリフレッシュの同期化のための第3の構成例を示すブロック図である。本構成例は、ホスト80と左および右ドライバIC300L,300Rとの間に既述の2系統のデータ経路すなわち奇数サブデータ経路731および偶数サブデータ経路732が形成される点を除き、上記第2の実施形態における第3の構成例(図17)と同様の構成を有している。そこで、本構成例のうち上記第2の実施形態の第3の構成例と同一の部分については同一の参照符号を付して詳しい説明を省略する。
図24は、本実施形態におけるリフレッシュの同期化のための第4の構成例を示すブロック図である。本構成例は、ホスト80と左および右ドライバIC300L,300Rとの間に既述の2系統のデータ経路すなわち奇数サブデータ経路731および偶数サブデータ経路732が形成される点を除き、上記第2の実施形態における第4の構成例(図18)と同様の構成を有している。そこで、本構成例のうち上記第2の実施形態の第4の構成例と同一の部分には同一の参照符号を付して詳しい説明を省略する。
図25は、本実施形態におけるリフレッシュの同期化のための第5の構成例を示すブロック図である。本構成例は、1画面分データを奇数列データDodHと偶数列データDevHとに分割してホスト80から左および右ドライバIC300L,300Rに転送するために2系統のデータ経路すなわち奇数サブデータ経路731および偶数サブデータ経路732が形成される点を除き、上記第2の実施形態における第5の構成例(図19)と同様の構成を有している。そこで、本構成例のうち上記第2の実施形態の第5の構成例と同一の部分については同一の参照符号を付して詳しい説明を省略する。
図26は、本発明の第4の実施形態に係る液晶表示装置の全体構成を示す図である。この液晶表示装置は、ホスト80との接続に関連する構成以外については、上記第2の実施形態と同様の構成を有している。このため、同一または対応する部分には同一の参照符号を付して、本実施形態に関する詳しい説明を省略し、以下では上記第2の実施形態と相違する部分を中心に説明する。なお本実施形態も、上記第1および第2の実施形態と同様、休止駆動を行えるように構成されている(図8参照)。
図27は、本実施形態におけるリフレッシュの同期化のための第1の構成例を示すブロック図である。本構成例では、ホスト80と左および右ドライバIC300L,300Rとの間に既述の2系統のデータ経路すなわち奇数サブデータ経路741および偶数サブデータ経路742が形成されている。また本構成例では、当該2系統のデータ経路で転送される奇数行データDodVおよび偶数行データDevVの受け取りとアクティブエリア100におけるソースラインの駆動とのタイミング調整のために、左および右ドライバIC300L,300Rは、少なくとも1画素行分のデータを格納するラインバッファ307L,307Rをそれぞれ備えている。本構成例は、これらの点を除き、上記第2の実施形態における第1の構成例(図15)と同様の構成を有している。そこで、本構成例のうち上記第2の実施形態の第1の構成例と同一の部分については同一の参照符号を付して詳しい説明を省略する。
図28は、本実施形態におけるリフレッシュの同期化のための第2の構成例を示すブロック図である。本構成例は、ホスト80と左および右ドライバIC300L,300Rとの間に既述の2系統のデータ経路すなわち奇数サブデータ経路741および偶数サブデータ経路742が形成されている点、および、当該2系統のデータ経路で転送される奇数行データDodVおよび偶数行データDevVの受け取りとアクティブエリア100におけるソースラインの駆動とのタイミング調整のために左および右ドライバIC300L,300Rがラインバッファ307L,307Rをそれぞれ備える点を除き、上記第2の実施形態における第2の構成例(図16)と同様の構成を有している。そこで、本構成例のうち上記第2の実施形態の第2の構成例と同一の部分については同一の参照符号を付して詳しい説明を省略する。
図29は、本実施形態におけるリフレッシュの同期化のための第3の構成例を示すブロック図である。本構成例は、ホスト80と左および右ドライバIC300L,300Rとの間に既述の2系統のデータ経路すなわち奇数サブデータ経路741および偶数サブデータ経路742が形成されている点、および、当該2系統のデータ経路で転送される奇数行データDodVおよび偶数行データDevVの受け取りとアクティブエリア100におけるソースラインの駆動とのタイミング調整のために左および右ドライバIC300L,300Rがラインバッファ307L,307Rをそれぞれ備える点を除き、上記第2の実施形態における第3の構成例(図17)と同様の構成を有している。そこで、本構成例のうち上記第2の実施形態の第3の構成例と同一の部分については同一の参照符号を付して詳しい説明を省略する。
図30は、本実施形態におけるリフレッシュの同期化のための第4の構成例を示すブロック図である。本構成例は、ホスト80と左および右ドライバIC300L,300Rとの間に既述の2系統のデータ経路すなわち奇数サブデータ経路741および偶数サブデータ経路742が形成されている点、および、当該2系統のデータ経路で転送される奇数行データDodVおよび偶数行データDevVの受け取りとアクティブエリア100におけるソースラインの駆動とのタイミング調整のために左および右ドライバIC300L,300Rがラインバッファ307L,307Rをそれぞれ備える点を除き、上記第2の実施形態における第4の構成例(図18)と同様の構成を有している。そこで、本構成例のうち上記第2の実施形態の第4の構成例と同一の部分については同一の参照符号を付して詳しい説明を省略する。
図31は、本実施形態におけるリフレッシュの同期化のための第5の構成例を示すブロック図である。本構成例は、ホスト80と左および右ドライバIC300L,300Rとの間に既述の2系統のデータ経路すなわち奇数サブデータ経路741および偶数サブデータ経路742が形成されている点、および、当該2系統のデータ経路で転送される奇数行データDodVおよび偶数行データDevVの受け取りとアクティブエリア100におけるソースラインの駆動とのタイミング調整のために左および右ドライバIC300L,300Rがラインバッファ307L,307Rをそれぞれ備える点を除き、上記第2の実施形態における第5の構成例(図19)と同様の構成を有している。そこで、本構成例のうち上記第2の実施形態の第5の構成例と同一の部分については同一の参照符号を付して詳しい説明を省略する。
上記各実施形態については、休止駆動を行うことを前提とし、非リフレッシュ期間中に強制的な画像更新を行う場合の表示画像のリフレッシュに着目して説明されているが、本発明は、このようなリフレッシュ以外のリフレッシュについても適用可能である。例えば本発明は、リフレッシュ期間の途中で新たな画像を表示するために行われる強制的なリフレッシュにも本発明を適用することができ、また、定期的なリフレッシュにも適用することができる。定期的なリフレッシュにおいても何らかの原因で、表示部を駆動する例えば2個のドライバIC(上記各実施形態では左ドライバIC300Lと右ドライバIC300R)の間で当該リフレッシュのタイミングがずれた場合(例えばリフレッシュのためのデータ転送のタイミングがずれる場合)には、本発明によれば、いずれか一方のドライバICによるリフレッシュのみが行われることはなく、必ず両ドイラバICが同じタイミングでリフレッシュを開始する。
80 …ホスト
100 …表示部(アクティブエリア)
100L …左アクティブエリア(サブ表示領域)
100R …右アクティブエリア(サブ表示領域)
300L …左ドライバIC(マスタIC)
300R …右ドライバIC(スレーブIC)
305L,305R …半画面に対するリフレッシュ検知部(REF(Half))
305La,305Ra…1画面に対するリフレッシュ検知部(REF(All))
307L,307R …ラインバッファ
711 …左サブデータ経路
712 …右サブデータ経路
714 …制御信号経路
715 …第1信号経路
716 …第2信号経路
717 …第3信号経路
720 …データ経路
731,741 …奇数サブデータ経路
732,742 …偶数サブデータ経路
Da …1画面分データ
DaL …左半データ
DaR …右半データ
DodH …(水平方向分割に基づく)奇数列データ
DevH …(水平方向分割に基づく)偶数列データ
DodV …(垂直方向分割に基づく)奇数行データ
DevV …(垂直方向分割に基づく)偶数行データ
RfC …リフレッシュ制御信号(リフレッシュ開始情報)
RfD,RfDl,RfDr …リフレッシュ検知信号(リフレッシュ開始情報)
Claims (14)
- 外部から与えられる入力データに基づき画像を表示する表示装置であって、
前記画像を表示するための表示部と、
前記入力データに基づいて前記表示部における表示画像をリフレッシュするリフレッシュ期間と前記表示部における表示画像のリフレッシュを休止する非リフレッシュ期間とが交互に現れるように前記表示部を駆動するための駆動制御部と、
前記入力データを外部から前記駆動制御部に与えるためのデータ経路と
を備え、
前記駆動制御部は、前記表示部の表示領域を分割することにより得られる複数のサブ表示領域にそれぞれ対応する複数の駆動制御回路を含み、
各駆動制御回路は、前記表示部における表示画像をリフレッシュするためのデータが前記入力データとして外部から与えられる場合に、前記入力データに基づくリフレッシュの開始タイミングに対応づけられたリフレッシュ開始情報を、前記入力データに基づき当該駆動制御回路内で取得するか、または、他の前記駆動制御回路もしくは外部から取得し、当該取得されたリフレッシュ開始情報に基づき、当該駆動制御回路に対応するサブ表示領域における表示画像のリフレッシュが他の前記駆動制御回路に対応するサブ表示領域における表示画像のリフレッシュと同期して開始されるように前記表示部を駆動することを特徴とする、表示装置。 - 前記データ経路は、前記複数のサブ表示領域にそれぞれ対応する複数のサブデータ経路を含み、
各駆動制御回路は、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータをサブ入力データとして当該サブ表示領域に対応するサブデータ経路を介して外部から受け取り、当該サブ入力データに基づき当該サブ表示領域に画像が表示されるように前記表示部を駆動することを特徴とする、請求項1に記載の表示装置。 - 各駆動制御回路は、前記入力データを前記データ経路を介して外部から受け取り、前記入力データに基づき対応するサブ表示領域に画像が表示されるように前記表示部を駆動することを特徴とする、請求項1に記載の表示装置。
- 前記表示部は、複数のデータ信号線と、前記複数のデータ信号線に交差する複数の走査信号線と、前記複数のデータ信号線および前記複数の走査信号線に沿ってマトリクス状に配置された複数の画素形成部とを含み、
各画素形成部は、前記複数のデータ信号線のいずれか1つに接続されると共に前記複数の走査信号線のいずれか1つに接続され、
前記駆動制御部は、前記入力データに基づき前記複数の画素形成部によって画像が表示されるように前記複数のデータ信号線および前記複数の走査信号線を駆動し、
前記データ経路は、
前記入力データのうち、前記複数の画素形成部によって表示されるべき画像を構成する画素マトリクスにおいて前記データ信号線に沿って並ぶ画素からなる奇数番目の画素列に対応するデータを奇数列データとして外部から各駆動制御回路に転送するための奇数サブデータ経路と、
前記入力データのうち、前記画素マトリクスにおいて前記データ信号線に沿って並ぶ画素からなる偶数番目の画素列に対応するデータを偶数列データとして外部から各駆動制御回路に転送するための偶数サブデータ経路とを含み、
各駆動制御回路は、
前記奇数列データを前記奇数サブデータ経路を介して外部から受け取ると共に、前記偶数列データを前記偶数サブデータ経路を介して外部から受け取ることにより、前記画素マトリクスにおいて前記走査信号線に沿って並ぶ画素からなる1つの画素行に対応する1ラインデータずつ前記入力データを外部から与えられ、
前記奇数列データおよび前記偶数列データのうち対応するサブ表示領域に画像を表示するためのデータに基づき前記表示部の当該サブ表示領域における前記データ信号線を駆動することを特徴とする、請求項1に記載の表示装置。 - 前記表示部は、複数のデータ信号線と、前記複数のデータ信号線に交差する複数の走査信号線と、前記複数のデータ信号線および前記複数の走査信号線に沿ってマトリクス状に配置された複数の画素形成部とを含み、
各画素形成部は、前記複数のデータ信号線のいずれか1つに接続されると共に前記複数の走査信号線のいずれか1つに接続され、
前記駆動制御部は、前記入力データに基づき前記複数の画素形成部によって画像が表示されるように前記複数のデータ信号線および前記複数の走査信号線を駆動し、
前記データ経路は、
前記入力データのうち、前記複数の画素形成部によって表示されるべき画像を構成する画素マトリクスにおいて前記走査信号線に沿って並ぶ画素からなる奇数番目の画素行に対応するデータを奇数行データとして外部から各駆動制御回路に転送するための奇数サブデータ経路と、
前記入力データのうち、前記画素マトリクスにおいて前記走査信号線に沿って並ぶ画素からなる偶数番目の画素行に対応するデータを偶数行データとして外部から各駆動制御回路に転送するための偶数サブデータ経路とを含み、
各駆動制御回路は、
前記奇数行データを前記奇数サブデータ経路を介して外部から受け取ると共に、前記偶数行データを前記偶数サブデータ経路を介して外部から受け取ることにより、前記画素マトリクスにおいて前記データ信号線に沿って並ぶ画素からなる2つの画素行に対応する2ラインデータずつ前記入力データを外部から与えられ、
前記奇数行データおよび前記偶数行データのうち対応するサブ表示領域に画像を表示するためのデータに基づき前記表示部の当該サブ表示領域における前記データ信号線を駆動することを特徴とする、請求項1に記載の表示装置。 - 各駆動制御回路は、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき前記表示部における表示画像のリフレッシュの開始タイミングを検知するためのリフレッシュ検知部を含み、
前記複数の駆動制御回路は、マスタ駆動制御回路として識別される1つの駆動制御回路とスレーブ駆動制御回路として識別される当該マスタ駆動制御回路以外の駆動制御回路とから構成され、
前記マスタ駆動制御回路と前記スレーブ駆動制御回路との間には信号経路が設けられており、
前記スレーブ駆動制御回路は、そのリフレッシュ検知部によって前記リフレッシュの開始タイミングが検知されると、当該開始タイミングを示すリフレッシュ検知信号を前記リフレッシュ開始情報として前記信号経路を介して前記マスタ駆動制御回路に送り、
前記マスタ駆動制御回路は、そのリフレッシュ検知部によって前記リフレッシュの開始タイミングが検知されるか、または、前記スレーブ駆動制御回路から前記信号経路を介して前記リフレッシュ検知信号を受け取ると、前記リフレッシュの開始を指示するリフレッシュ制御信号を前記リフレッシュ開始情報として前記信号経路を介して前記スレーブ駆動制御回路に送ると共に、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動し、
前記スレーブ駆動制御回路は、前記マスタ駆動制御回路から前記信号経路を介して前記リフレッシュ制御信号を受け取ると、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動することを特徴とする、請求項2から5のいずれか1項に記載の表示装置。 - 前記複数の駆動制御回路は、マスタ駆動制御回路として識別される1つの駆動制御回路とスレーブ駆動制御回路として識別される当該マスタ駆動制御回路以外の駆動制御回路とから構成され、
前記マスタ駆動制御回路と前記スレーブ駆動制御回路との間には信号経路が設けられており、
前記マスタ駆動制御回路は、
前記入力データに基づき前記表示部における表示画像のリフレッシュの開始タイミングを検知するためのリフレッシュ検知部を含み、
前記リフレッシュ検知部によって前記リフレッシュの開始タイミングが検知されると、前記リフレッシュの開始を指示するリフレッシュ制御信号を前記リフレッシュ開始情報として前記信号経路を介して前記スレーブ駆動制御回路に送ると共に、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動し、
前記スレーブ駆動制御回路は、前記マスタ駆動制御回路から前記信号経路を介して前記リフレッシュ制御信号を受け取ると、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動することを特徴とする、請求項3から5のいずれか1項に記載の表示装置。 - 前記複数の駆動制御回路を相互に接続する信号経路を更に備え、
各駆動制御回路は、
前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき前記表示部における表示画像のリフレッシュの開始タイミングを検知するためのリフレッシュ検知部を含み、
前記リフレッシュ検知部によって前記リフレッシュの開始タイミングが検知されると、当該開始タイミングを示すリフレッシュ検知信号を前記リフレッシュ開始情報として前記信号経路を介して他の前記駆動制御回路に送ると共に、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動し、
他の前記駆動制御回路のいずれかから前記信号経路を介して前記リフレッシュ検知信号を受け取ると、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動することを特徴とする、請求項2から5のいずれか1項に記載の表示装置。 - 各駆動制御回路は、
前記入力データに基づき前記表示部における表示画像のリフレッシュの開始タイミングを検知するためのリフレッシュ検知部を含み、
前記リフレッシュ検知部によって前記リフレッシュの開始タイミングが検知されると、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動することを特徴とする、請求項3から5のいずれか1項に記載の表示装置。 - 前記入力データに基づき前記表示部における表示画像のリフレッシュの開始を指示するリフレッシュ制御信号を前記リフレッシュ開始情報として外部から受け取るための制御信号経路を更に備え、
各駆動制御回路は、前記リフレッシュ制御信号を前記制御信号経路を介して外部から受け取ると、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記表示部を駆動することを特徴とする、請求項2から5のいずれか1項に記載の表示装置。 - 各駆動制御回路は単一のICチップとして構成されていることを特徴とする、請求項2から5のいずれか1項に記載の表示装置。
- 前記表示部は、表示すべき画像を構成する各画素を形成するためのスイッチング素子として、酸化物半導体によりチャネル層が形成された薄膜トランジスタを含むことを特徴とする、請求項2から5のいずれか1項に記載の表示装置。
- 外部から与えられる入力データに基づき画像を表示するための表示部と、前記入力データに基づいて前記表示部を駆動するための複数の駆動制御回路とを備える表示装置の駆動方法であって、
前記入力データに基づいて前記表示部における表示画像をリフレッシュするリフレッシュ期間と前記表示部における表示画像のリフレッシュを休止する非リフレッシュ期間とが交互に現れるように前記表示部を駆動する駆動制御ステップを備え、
前記複数の駆動制御回路は、前記表示部の表示領域を分割することにより得られる複数のサブ表示領域にそれぞれ対応し、
前記駆動制御ステップは、
前記表示部における表示画像をリフレッシュするためのデータが前記入力データとして外部から与えられる場合に、前記入力データに基づくリフレッシュの開始タイミングに対応づけられたリフレッシュ開始情報を各駆動制御回路において取得する情報取得ステップと、
前記情報取得ステップにて取得された前記リフレッシュ開始情報に基づき、各駆動制御回路に対応するサブ表示領域における表示画像のリフレッシュが他の前記駆動制御回路に対応するサブ表示領域における表示画像のリフレッシュと同期して開始されるように各駆動制御回路により前記表示部を駆動する駆動ステップと
を含むことを特徴とする、駆動方法。 - 各駆動制御回路は、前記入力データのうち対応するサブ表示領域に画像を表示するためのデータに基づき前記表示部における表示画像のリフレッシュの開始タイミングを検知するためのリフレッシュ検知部を含み、
前記複数の駆動制御回路は、マスタ駆動制御回路として識別される1つの駆動制御回路とスレーブ駆動制御回路として識別される当該マスタ駆動制御回路以外の駆動制御回路とから構成され、
前記情報取得ステップは、
前記スレーブ駆動制御回路のリフレッシュ検知部によって前記リフレッシュの開始タイミングが検知されると、当該開始タイミングを示すリフレッシュ検知信号を前記リフレッシュ開始情報として前記マスタ駆動制御回路に送る検知信号送信ステップと、
前記マスタ駆動制御回路のリフレッシュ検知部によって前記リフレッシュの開始タイミングが検知されるか、または、前記スレーブ駆動制御回路から前記リフレッシュ検知信号を受け取ると、前記リフレッシュの開始を指示するリフレッシュ制御信号を前記リフレッシュ開始情報として前記スレーブ駆動制御回路に送る制御信号送信ステップとを含み、
前記駆動ステップは、
前記マスタ駆動制御回路のリフレッシュ検知部によって前記リフレッシュの開始タイミングが検知されるか、または、前記スレーブ駆動制御回路から前記リフレッシュ検知信号を受け取ると、前記入力データのうち前記マスタ駆動制御回路に対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記マスタ駆動制御回路により前記表示部を駆動するマスタ駆動ステップと、
前記マスタ駆動制御回路から前記リフレッシュ制御信号を受け取ると、前記入力データのうち前記スレーブ駆動制御回路に対応するサブ表示領域に画像を表示するためのデータに基づき当該サブ表示領域における表示画像のリフレッシュが開始されるように前記スレーブ駆動制御回路により前記表示部を駆動するスレーブ駆動ステップとを含むことを特徴とする、請求項13に記載の駆動方法。
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TWI564866B (zh) | 2015-07-03 | 2017-01-01 | 點晶科技股份有限公司 | 顯示器及其顯示方法 |
US10608017B2 (en) | 2017-01-31 | 2020-03-31 | Semiconductor Energy Laboratory Co., Ltd. | Display device, display module, and electronic device |
CN107978277B (zh) | 2018-01-19 | 2019-03-26 | 昆山国显光电有限公司 | 扫描驱动器及其驱动方法、有机发光显示器 |
US10832632B2 (en) | 2018-03-14 | 2020-11-10 | Samsung Display Co., Ltd. | Low power architecture for mobile displays |
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US11521542B2 (en) * | 2019-11-20 | 2022-12-06 | Novatek Microelectronics Corp. | Method for display driver system and display driver system |
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