WO2015054926A1 - Structure de mofset et son procédé de fabrication - Google Patents

Structure de mofset et son procédé de fabrication Download PDF

Info

Publication number
WO2015054926A1
WO2015054926A1 PCT/CN2013/085621 CN2013085621W WO2015054926A1 WO 2015054926 A1 WO2015054926 A1 WO 2015054926A1 CN 2013085621 W CN2013085621 W CN 2013085621W WO 2015054926 A1 WO2015054926 A1 WO 2015054926A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
region
carrier
gate stack
carrier scattering
Prior art date
Application number
PCT/CN2013/085621
Other languages
English (en)
Chinese (zh)
Inventor
尹海洲
刘云飞
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Publication of WO2015054926A1 publication Critical patent/WO2015054926A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

Definitions

  • the present invention relates to a MOSFET structure and a method of fabricating the same. More specifically, it relates to a MOSFET structure for reducing the number of hot electrons in a channel near a drain terminal and a method of fabricating the same.
  • the channel inversion layer is partially pinched, that is, the channel surface near the drain end has a small carrier concentration, and the resistance is large.
  • the channel region is Most of the voltage falls on the pinch-off region, which generates a large electric field in the pinch-off region.
  • the inversion carrier in the channel region moves to the boundary of the pinch-off region under the action of the electric field, it will be accelerated by the electric field in the pinch-off region, and will be quickly swept to the drain. In this process, the electrons will be very The large velocity is much larger than the velocity of movement in the anti-carrier region. Therefore, the velocity of electron movement in the pinch-off region is independent of the mobility, and mainly depends on the voltage on the pinch-off region.
  • the present invention provides a method for reducing the probability of hot carrier transition. Specifically, a scattering impurity, that is, a non-ionizing impurity, is implanted into a channel material near a drain end side. The probability that hot carriers are scattered in the pinch-off region increases the resistance of the carriers as they move in the pinch-off region, reducing the energy of the hot carriers, thereby reducing the entry of hot carriers into the gate dielectric layer. Number and odds. Summary of the invention
  • the present invention provides a method for reducing the number of hot electrons in a channel near a drain end.
  • the MOSFET structure and its manufacturing method effectively reduce the number and probability of hot carriers entering the gate dielectric layer and improve device performance.
  • the manufacturing method provided by the present invention includes the following steps:
  • the carrier scattering region is located within 5 nm below the surface of the substrate, and its length is less than 1/3 of the length of the gate.
  • the carrier concentration of the impurity diffusion region is greater than le20cm_ 3.
  • a semiconductor structure includes:
  • Source and drain regions located in the bottom of both sides of the gate stack
  • the carrier scattering region is located within 5 nm below the surface of the substrate and has a length less than 1/3 of the length of the gate.
  • the carrier concentration of the impurity diffusion region is greater than le20cm_ 3.
  • a method for reducing the probability of hot carrier transition specifically, injecting scattering impurities, that is, non-ionizing impurities, into a channel material near a drain end side, and increasing hot carriers
  • the probability of being scattered in the pinch-off region increases the resistance experienced by the carriers as they move in the pinch-off region, reducing the energy of the hot carriers, thereby reducing the number and probability of hot carriers entering the gate dielectric layer.
  • FIG. 1 through 5 schematically illustrate cross-sectional views of a semiconductor structure at various stages of forming a fabrication method in accordance with the present invention.
  • the present invention provides an asymmetric MOSFET structure, including: a substrate 100; a gate stack 500 located above the substrate 100; on both sides of the gate stack 500. a source/drain region 200 in the bottom of the village; a side wall 160 on both sides of the gate stack 500; an interlayer dielectric layer 300 on both sides of the side wall 160; and a village located below the gate near the drain end A carrier scattering region 400 in the bottom.
  • the carrier scattering layer 400 is located on the surface of the semiconductor structure 100 and has a depth of less than 5 nm and a length less than 1/3 of the gate length, wherein the elements forming the carrier scattering layer 400 are carbon and/or germanium. an impurity concentration greater than le20cm_ 3, by injecting a non-ionized impurities, greatly improving the probability of the scattering region, such that the device operates in the saturation region, the probability of carriers in the channel pinch-off region is scattered greatly increased, effectively reduce The energy of the hot carriers in this area.
  • the gate structure includes a gate dielectric layer, a work function adjustment layer, and a gate metal layer.
  • the preferred material for the gate dielectric layer is silicon oxynitride, which may also be silicon oxide or a high K material. Its equivalent oxidation thickness is 0.5 nm to 5 nm.
  • the gate metal layer may be only a metal gate or a metal/polysilicon composite gate with silicide on the upper surface of the polysilicon.
  • the semiconductor channel region is located on the surface of the substrate 100.
  • the preferred material is a single crystal silicon or a single crystal germanium alloy film having a thickness of 2 to 20 nm. This region is extremely lightly doped or even undoped. In the case of doping, the doping type is opposite to that of the source and drain regions.
  • the source and drain regions are respectively located on both sides of the gate stack, within the village 100.
  • the source region is symmetrical with the drain region, and its doping type is opposite to that of the village.
  • a village bottom is first provided, and a gate dielectric layer is formed on the bottom of the village.
  • the gate dielectric layer may be a thermal oxide layer, including silicon oxide or silicon oxynitride; or a high-k dielectric such as HfA10N, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, A1 2 0 3 , La One or a combination of 2 0 3 , Zr0 2 , and LaAlO, the thickness of the gate dielectric layer may be 1 nm to 10 nm, for example, 3 nm, 5 nm, or 8 nm.
  • a process such as (CVD) or atomic layer deposition (ALD) forms a gate dielectric layer.
  • a dummy gate structure 150 is formed on the gate dielectric layer.
  • the dummy gate structure 150 may be a single layer or a plurality of layers.
  • the dummy gate structure 150 may include a polymer material, amorphous silicon, polysilicon or TiN, and may have a thickness of 10 nm to 200 nm.
  • the dummy gate structure includes polysilicon and dioxide.
  • a chemical vapor deposition method is used to fill the gate vacancies with polysilicon, and then a silicon dioxide dielectric layer is formed over the polysilicon.
  • the formation method may be Epitaxial growth, oxidation, CVD, and the like.
  • the gate electrode pattern is formed by photolithography and etching of the deposited dummy gate stack by a conventional CMOS process, and then the exposed portion of the gate dielectric layer is etched away by using the gate electrode pattern as a mask. It should be noted that, unless otherwise specified, the deposition of various dielectric materials in the embodiments of the present invention may adopt the same or similar methods for forming the gate dielectric layer as described above, and thus will not be described again.
  • the village substrate 100 on both sides of the dummy gate structure is shallowly doped to form a lightly doped source and drain region, and Halo implantation may be performed to form a Halo implantation region.
  • the shallow doping impurity type is the same as the device type, and the Halo implanted impurity type is opposite to the device type.
  • sidewall spacers 160 are formed on sidewalls of the gate stack for spacing the gates. Specifically, a silicon nitride spacer layer of 40 nm to 80 nm thick is deposited by LPCVD, and then a silicon nitride spacer 160 having a width of 35 nm to 75 nm is formed on both sides of the gate electrode by a guest technique.
  • the sidewall spacers 160 may also be formed of silicon oxide, silicon oxynitride, silicon carbide, combinations thereof, and/or other suitable materials.
  • the side wall 160 may have a multi-layered structure.
  • the spacer 160 may also be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
  • a silicon dioxide dielectric layer having a thickness of 10 nm to 35 nm is deposited on the semiconductor structure to form an interlayer dielectric layer 300, and the dielectric layer is used as a buffer layer, and the ion implantation source and drain are formed.
  • Area For the P-type crystal, the dopant is boron or boron fluoride or indium or gallium.
  • the dopant is phosphorus or arsenic or antimony.
  • the doping concentration is 5el0 19 cm_ 3 ⁇ lel0 2() cm_ 3 .
  • the semiconductor structure after doping is completed as shown in FIG.
  • the dummy gate structure is removed to form dummy gate vacancies, as shown in FIG.
  • the removal of the dummy gate structure can be removed by wet etching and/or dry etching. In one embodiment, plasma etching is employed.
  • the semiconductor structure is ion-implanted to form a carrier scattering layer 400, and the impurity element forming the scattering layer 400 is carbon and/or germanium.
  • the side wall 160 is used as a mask, and oblique ion implantation is performed.
  • the angle of the ion implantation is ⁇ , and the incident angle ⁇ is adjusted according to the height of the sidewall 160 and the length of the scattering layer 400, so that the boundary of the impurity incident region is at The length of the desired scattering layer is within the range.
  • the carrier scattering layer 400 has a depth of less than 5 nm and a length less than 1/3 of the gate length.
  • the carrier scattering layer 400 has a greater scattering probability than the substrate material, that is, When the flow moves therein, the flow will be subjected to greater resistance, effectively reducing the hot carrier energy, thereby reducing the number of hot carriers that enter the gate dielectric layer and improving device performance.
  • the gate metal layer may be only a metal gate or a metal/polysilicon composite gate, wherein the polysilicon has a silicide on its upper surface.
  • a work function metal layer is deposited on the gate dielectric layer, and then a metal conductor layer is formed on the work function metal layer.
  • the work function metal layer can be made of a material such as TiN or TaN, and has a thickness ranging from 3 nm to 15 nm.
  • the metal conductor layer may be in a one-layer or multi-layer structure.
  • the material may be one of TaN, TaC, TiN, TaAlN, TiAlN, ⁇ 1 ⁇ , TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x or a combination thereof. Its thickness may range, for example, from 10 nm to 40 nm, such as 20 nm or 30 nm.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

La présente invention concerne un procédé de fabrication d'un MOSFET, qui comprend les étapes suivantes : a. fournir un substrat (100), une région de source/drain (200), un empilement (150) de pseudo-grille, une couche (300) diélectrique intermédiaire et une paroi latérale (160) ; b. retirer l'empilement (150) de pseudo-grille afin de former une vacance de pseudo-grille ; c. réaliser une injection d'ions inclinée sur la structure semi-conductrice, puis former une région (400) de dispersion de porteuse, la région (400) de dispersion de porteuse étant située sous une surface de la structure semi-conductrice sur un côté d'un drain ; et d. déposer une couche (500) d'empilement de grille dans la vacance de pseudo-grille. Selon le procédé de réduction d'une probabilité de transition de porteuse chaude de la présente invention, la dispersion d'impuretés, c'est-à-dire, les impuretés non ionisées sont injectées dans un matériau de canal à proximité d'un côté d'un drain, de sorte qu'une probabilité qu'une porteuse chaude soit dispersée dans une région de pincement est accrue, une porteuse est soumise à une résistance accrue dans le mouvement de la région de pincement, l'énergie d'une porteuse chaude est réduite et, en conséquence, la quantité et la probabilité des porteuses chaudes qui pénètrent une couche diélectrique de grille sont réduites.
PCT/CN2013/085621 2013-10-15 2013-10-22 Structure de mofset et son procédé de fabrication WO2015054926A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310479825.1 2013-10-15
CN201310479825.1A CN103606524B (zh) 2013-10-15 2013-10-15 一种mosfet结构及其制造方法

Publications (1)

Publication Number Publication Date
WO2015054926A1 true WO2015054926A1 (fr) 2015-04-23

Family

ID=50124740

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/085621 WO2015054926A1 (fr) 2013-10-15 2013-10-22 Structure de mofset et son procédé de fabrication

Country Status (2)

Country Link
CN (1) CN103606524B (fr)
WO (1) WO2015054926A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5108935A (en) * 1990-11-16 1992-04-28 Texas Instruments Incorporated Reduction of hot carrier effects in semiconductor devices by controlled scattering via the intentional introduction of impurities
US6410393B1 (en) * 1999-08-18 2002-06-25 Advanced Micro Devices, Inc. Semiconductor device with asymmetric channel dopant profile
CN102104070A (zh) * 2009-12-21 2011-06-22 中国科学院微电子研究所 半导体结构及其形成方法
CN102110609A (zh) * 2009-12-23 2011-06-29 中国科学院微电子研究所 高性能半导体器件及其形成方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482724B1 (en) * 1999-09-07 2002-11-19 Texas Instruments Incorporated Integrated circuit asymmetric transistors
US8236661B2 (en) * 2009-09-28 2012-08-07 International Business Machines Corporation Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage
CN102569394B (zh) * 2010-12-29 2014-12-03 中芯国际集成电路制造(北京)有限公司 晶体管及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5108935A (en) * 1990-11-16 1992-04-28 Texas Instruments Incorporated Reduction of hot carrier effects in semiconductor devices by controlled scattering via the intentional introduction of impurities
US6410393B1 (en) * 1999-08-18 2002-06-25 Advanced Micro Devices, Inc. Semiconductor device with asymmetric channel dopant profile
CN102104070A (zh) * 2009-12-21 2011-06-22 中国科学院微电子研究所 半导体结构及其形成方法
CN102110609A (zh) * 2009-12-23 2011-06-29 中国科学院微电子研究所 高性能半导体器件及其形成方法

Also Published As

Publication number Publication date
CN103606524B (zh) 2016-03-23
CN103606524A (zh) 2014-02-26

Similar Documents

Publication Publication Date Title
US11728219B2 (en) Method for fabricating a semiconductor device
US8927374B2 (en) Semiconductor device and fabrication method thereof
US8530316B2 (en) Method for fabricating a semiconductor device
WO2011079596A1 (fr) Structure de transistor mos et son procédé de fabrication
WO2013078882A1 (fr) Dispositif à semi-conducteurs et procédé de fabrication associé
US20110227144A1 (en) High-performance semiconductor device and method of manufacturing the same
WO2015054916A1 (fr) Structure de transistor à effet de champ (fet) à ailette et son procédé de fabrication
WO2013026243A1 (fr) Structure à semi-conducteur et son procédé de fabrication
WO2013075349A1 (fr) Structure semi-conductrice et son procédé de fabrication
CN104347707B (zh) 一种mosfet结构及其制造方法
WO2015196639A1 (fr) Procédé de fabrication de finfet
CN104576338B (zh) 一种mosfet结构及其制造方法
CN104183488A (zh) 一种FinFET半导体器件及其制备方法
CN104576378B (zh) 一种mosfet结构及其制造方法
WO2015051564A1 (fr) Structure mosfet et son procédé de fabrication
WO2015054926A1 (fr) Structure de mofset et son procédé de fabrication
WO2015054915A1 (fr) Structure de transistor mos soi ultramince asymétrique et son procédé de fabrication
CN105633151B (zh) 一种非对称FinFET结构及其制造方法
WO2015054927A1 (fr) Structure de mosfet et procédé de fabrication associé
CN104576379B (zh) 一种mosfet结构及其制造方法
WO2015051561A1 (fr) Structure de transistor à effet de champ à semi-conducteur à oxyde métallique et son procédé de fabrication
WO2015172439A1 (fr) Procédé de fabrication d'une électrode de contact et dispositif semiconducteur
WO2013163831A1 (fr) Structure de semi-conducteur et son procédé de fabrication

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13895527

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13895527

Country of ref document: EP

Kind code of ref document: A1