WO2015054926A1 - Mosfet structure and method of manufacturing same - Google Patents

Mosfet structure and method of manufacturing same Download PDF

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Publication number
WO2015054926A1
WO2015054926A1 PCT/CN2013/085621 CN2013085621W WO2015054926A1 WO 2015054926 A1 WO2015054926 A1 WO 2015054926A1 CN 2013085621 W CN2013085621 W CN 2013085621W WO 2015054926 A1 WO2015054926 A1 WO 2015054926A1
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gate
region
carrier
gate stack
carrier scattering
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PCT/CN2013/085621
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Chinese (zh)
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尹海洲
刘云飞
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中国科学院微电子研究所
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
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    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

Definitions

  • the present invention relates to a MOSFET structure and a method of fabricating the same. More specifically, it relates to a MOSFET structure for reducing the number of hot electrons in a channel near a drain terminal and a method of fabricating the same.
  • the channel inversion layer is partially pinched, that is, the channel surface near the drain end has a small carrier concentration, and the resistance is large.
  • the channel region is Most of the voltage falls on the pinch-off region, which generates a large electric field in the pinch-off region.
  • the inversion carrier in the channel region moves to the boundary of the pinch-off region under the action of the electric field, it will be accelerated by the electric field in the pinch-off region, and will be quickly swept to the drain. In this process, the electrons will be very The large velocity is much larger than the velocity of movement in the anti-carrier region. Therefore, the velocity of electron movement in the pinch-off region is independent of the mobility, and mainly depends on the voltage on the pinch-off region.
  • the present invention provides a method for reducing the probability of hot carrier transition. Specifically, a scattering impurity, that is, a non-ionizing impurity, is implanted into a channel material near a drain end side. The probability that hot carriers are scattered in the pinch-off region increases the resistance of the carriers as they move in the pinch-off region, reducing the energy of the hot carriers, thereby reducing the entry of hot carriers into the gate dielectric layer. Number and odds. Summary of the invention
  • the present invention provides a method for reducing the number of hot electrons in a channel near a drain end.
  • the MOSFET structure and its manufacturing method effectively reduce the number and probability of hot carriers entering the gate dielectric layer and improve device performance.
  • the manufacturing method provided by the present invention includes the following steps:
  • the carrier scattering region is located within 5 nm below the surface of the substrate, and its length is less than 1/3 of the length of the gate.
  • the carrier concentration of the impurity diffusion region is greater than le20cm_ 3.
  • a semiconductor structure includes:
  • Source and drain regions located in the bottom of both sides of the gate stack
  • the carrier scattering region is located within 5 nm below the surface of the substrate and has a length less than 1/3 of the length of the gate.
  • the carrier concentration of the impurity diffusion region is greater than le20cm_ 3.
  • a method for reducing the probability of hot carrier transition specifically, injecting scattering impurities, that is, non-ionizing impurities, into a channel material near a drain end side, and increasing hot carriers
  • the probability of being scattered in the pinch-off region increases the resistance experienced by the carriers as they move in the pinch-off region, reducing the energy of the hot carriers, thereby reducing the number and probability of hot carriers entering the gate dielectric layer.
  • FIG. 1 through 5 schematically illustrate cross-sectional views of a semiconductor structure at various stages of forming a fabrication method in accordance with the present invention.
  • the present invention provides an asymmetric MOSFET structure, including: a substrate 100; a gate stack 500 located above the substrate 100; on both sides of the gate stack 500. a source/drain region 200 in the bottom of the village; a side wall 160 on both sides of the gate stack 500; an interlayer dielectric layer 300 on both sides of the side wall 160; and a village located below the gate near the drain end A carrier scattering region 400 in the bottom.
  • the carrier scattering layer 400 is located on the surface of the semiconductor structure 100 and has a depth of less than 5 nm and a length less than 1/3 of the gate length, wherein the elements forming the carrier scattering layer 400 are carbon and/or germanium. an impurity concentration greater than le20cm_ 3, by injecting a non-ionized impurities, greatly improving the probability of the scattering region, such that the device operates in the saturation region, the probability of carriers in the channel pinch-off region is scattered greatly increased, effectively reduce The energy of the hot carriers in this area.
  • the gate structure includes a gate dielectric layer, a work function adjustment layer, and a gate metal layer.
  • the preferred material for the gate dielectric layer is silicon oxynitride, which may also be silicon oxide or a high K material. Its equivalent oxidation thickness is 0.5 nm to 5 nm.
  • the gate metal layer may be only a metal gate or a metal/polysilicon composite gate with silicide on the upper surface of the polysilicon.
  • the semiconductor channel region is located on the surface of the substrate 100.
  • the preferred material is a single crystal silicon or a single crystal germanium alloy film having a thickness of 2 to 20 nm. This region is extremely lightly doped or even undoped. In the case of doping, the doping type is opposite to that of the source and drain regions.
  • the source and drain regions are respectively located on both sides of the gate stack, within the village 100.
  • the source region is symmetrical with the drain region, and its doping type is opposite to that of the village.
  • a village bottom is first provided, and a gate dielectric layer is formed on the bottom of the village.
  • the gate dielectric layer may be a thermal oxide layer, including silicon oxide or silicon oxynitride; or a high-k dielectric such as HfA10N, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, A1 2 0 3 , La One or a combination of 2 0 3 , Zr0 2 , and LaAlO, the thickness of the gate dielectric layer may be 1 nm to 10 nm, for example, 3 nm, 5 nm, or 8 nm.
  • a process such as (CVD) or atomic layer deposition (ALD) forms a gate dielectric layer.
  • a dummy gate structure 150 is formed on the gate dielectric layer.
  • the dummy gate structure 150 may be a single layer or a plurality of layers.
  • the dummy gate structure 150 may include a polymer material, amorphous silicon, polysilicon or TiN, and may have a thickness of 10 nm to 200 nm.
  • the dummy gate structure includes polysilicon and dioxide.
  • a chemical vapor deposition method is used to fill the gate vacancies with polysilicon, and then a silicon dioxide dielectric layer is formed over the polysilicon.
  • the formation method may be Epitaxial growth, oxidation, CVD, and the like.
  • the gate electrode pattern is formed by photolithography and etching of the deposited dummy gate stack by a conventional CMOS process, and then the exposed portion of the gate dielectric layer is etched away by using the gate electrode pattern as a mask. It should be noted that, unless otherwise specified, the deposition of various dielectric materials in the embodiments of the present invention may adopt the same or similar methods for forming the gate dielectric layer as described above, and thus will not be described again.
  • the village substrate 100 on both sides of the dummy gate structure is shallowly doped to form a lightly doped source and drain region, and Halo implantation may be performed to form a Halo implantation region.
  • the shallow doping impurity type is the same as the device type, and the Halo implanted impurity type is opposite to the device type.
  • sidewall spacers 160 are formed on sidewalls of the gate stack for spacing the gates. Specifically, a silicon nitride spacer layer of 40 nm to 80 nm thick is deposited by LPCVD, and then a silicon nitride spacer 160 having a width of 35 nm to 75 nm is formed on both sides of the gate electrode by a guest technique.
  • the sidewall spacers 160 may also be formed of silicon oxide, silicon oxynitride, silicon carbide, combinations thereof, and/or other suitable materials.
  • the side wall 160 may have a multi-layered structure.
  • the spacer 160 may also be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
  • a silicon dioxide dielectric layer having a thickness of 10 nm to 35 nm is deposited on the semiconductor structure to form an interlayer dielectric layer 300, and the dielectric layer is used as a buffer layer, and the ion implantation source and drain are formed.
  • Area For the P-type crystal, the dopant is boron or boron fluoride or indium or gallium.
  • the dopant is phosphorus or arsenic or antimony.
  • the doping concentration is 5el0 19 cm_ 3 ⁇ lel0 2() cm_ 3 .
  • the semiconductor structure after doping is completed as shown in FIG.
  • the dummy gate structure is removed to form dummy gate vacancies, as shown in FIG.
  • the removal of the dummy gate structure can be removed by wet etching and/or dry etching. In one embodiment, plasma etching is employed.
  • the semiconductor structure is ion-implanted to form a carrier scattering layer 400, and the impurity element forming the scattering layer 400 is carbon and/or germanium.
  • the side wall 160 is used as a mask, and oblique ion implantation is performed.
  • the angle of the ion implantation is ⁇ , and the incident angle ⁇ is adjusted according to the height of the sidewall 160 and the length of the scattering layer 400, so that the boundary of the impurity incident region is at The length of the desired scattering layer is within the range.
  • the carrier scattering layer 400 has a depth of less than 5 nm and a length less than 1/3 of the gate length.
  • the carrier scattering layer 400 has a greater scattering probability than the substrate material, that is, When the flow moves therein, the flow will be subjected to greater resistance, effectively reducing the hot carrier energy, thereby reducing the number of hot carriers that enter the gate dielectric layer and improving device performance.
  • the gate metal layer may be only a metal gate or a metal/polysilicon composite gate, wherein the polysilicon has a silicide on its upper surface.
  • a work function metal layer is deposited on the gate dielectric layer, and then a metal conductor layer is formed on the work function metal layer.
  • the work function metal layer can be made of a material such as TiN or TaN, and has a thickness ranging from 3 nm to 15 nm.
  • the metal conductor layer may be in a one-layer or multi-layer structure.
  • the material may be one of TaN, TaC, TiN, TaAlN, TiAlN, ⁇ 1 ⁇ , TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x or a combination thereof. Its thickness may range, for example, from 10 nm to 40 nm, such as 20 nm or 30 nm.

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Abstract

The present invention provides a method of manufacturing a MOSFET, comprising: a. providing a substrate (100), a source/drain region (200), a pseudo-gate stack (150), an interlayer dielectric layer (300), and a sidewall (160); b. removing the pseudo-gate stack (150) to form a pseudo-gate vacancy; c. performing inclined ion injection on the semiconductor structure, and forming a carrier scattering region (400), the carrier scattering region (400) being located below a surface of the semiconductor structure on a side of a drain; and d. depositing a gate stack layer (500) in the pseudo-gate vacancy. According to the method for reducing a probability of hot carrier transition provided by the present invention, scattering impurities, that is, non-ionized impurities are injected in a channel material near a side of a drain, so that a probability that a hot carrier is scattered in a pinch-off region is increased, a carrier is subject to increased resistance in the movement in the pinch-off region, the energy of a hot carrier is reduced, and accordingly the quantity and probability of hot carriers that enter a gate dielectric layer are reduced.

Description

一种 MOSFET结构及其制造方法  MOSFET structure and manufacturing method thereof
[0001]本申请要求了 2013年 10月 15日提交的、申请号为 201310479825.1、 发明名称为"一种 MOSFET结构及其制造方法 "的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域 [0001] The present application claims priority to Chinese Patent Application No. 201310479825. filed on Jan. 15, 2013, entitled,,,,,,,,,,, In the application. Technical field
[0002】本发明涉及一种 MOSFET结构及其制造方法。 更具体而言， 涉及一 种用于减小靠近漏端的沟道中热电子数目的 MOSFET结构及其制造方法。 技术背景  The present invention relates to a MOSFET structure and a method of fabricating the same. More specifically, it relates to a MOSFET structure for reducing the number of hot electrons in a channel near a drain terminal and a method of fabricating the same. technical background
[0003】 MOSFET处于饱和区时， 沟道反型层部分夹断， 即靠近漏端的沟道 表面反型载流子浓度很小， 电阻很大， 根据串联分压关系， 此时沟道区的 电压大部分落在夹断区上， 在夹断区产生很大的电场。 当沟道区的反型载 流子在电场作用下运动到夹断区边界时， 将会被夹断区的电场加速， 很快 的被扫到漏端， 这一过程中电子将会获得很大的速度， 远大于在反型载流 子区时运动的速度， 因此， 在夹断区电子的运动速度与迁移率无关， 主要 取决于夹断区上的电压大小。  [0003] When the MOSFET is in the saturation region, the channel inversion layer is partially pinched, that is, the channel surface near the drain end has a small carrier concentration, and the resistance is large. According to the series voltage division relationship, the channel region is Most of the voltage falls on the pinch-off region, which generates a large electric field in the pinch-off region. When the inversion carrier in the channel region moves to the boundary of the pinch-off region under the action of the electric field, it will be accelerated by the electric field in the pinch-off region, and will be quickly swept to the drain. In this process, the electrons will be very The large velocity is much larger than the velocity of movement in the anti-carrier region. Therefore, the velocity of electron movement in the pinch-off region is independent of the mobility, and mainly depends on the voltage on the pinch-off region.
[0004]随着源漏之间电压的增大， 夹断区载流子所处的电场也随着增大， 因此电子能获得更高的速度和更大的能量， 产生一定数目的热载流子， 夹 断区的电场增大到一定程度时， 这些热载流子具有一定的几率越过沟道和 栅介质层之间的势垒， 进入栅介质层中， 从而在栅介质层中引入缺陷和陷 阱， 影响器件性能。  [0004] As the voltage between the source and drain increases, the electric field of the carrier in the pinch-off region also increases, so the electron can obtain higher speed and greater energy, and generate a certain number of hot loads. When the electric field of the pinch-off region is increased to a certain extent, these hot carriers have a certain probability to cross the barrier between the channel and the gate dielectric layer and enter the gate dielectric layer, thereby introducing into the gate dielectric layer. Defects and traps that affect device performance.
[0005]针对这一问题， 本发明提供了一种减小热载流子跃迁几率的方法， 具体的， 在靠近漏端一侧的沟道材料中注入散射杂质， 即非电离杂质， 增 大热载流子在夹断区被散射的概率， 使得载流子在夹断区运动时受到的阻 力增大， 降低热载流子的能量， 从而减小热载流子进入栅极介质层的数目 和几率。 发明内容 [0005] In response to this problem, the present invention provides a method for reducing the probability of hot carrier transition. Specifically, a scattering impurity, that is, a non-ionizing impurity, is implanted into a channel material near a drain end side. The probability that hot carriers are scattered in the pinch-off region increases the resistance of the carriers as they move in the pinch-off region, reducing the energy of the hot carriers, thereby reducing the entry of hot carriers into the gate dielectric layer. Number and odds. Summary of the invention
[0006]本发明提供了一种用于减小靠近漏端的沟道中热电子数目的 The present invention provides a method for reducing the number of hot electrons in a channel near a drain end.
MOSFET结构及其制造方法， 有效地减小了热载流子进入栅极介质层的数 目和几率， 提高了器件性能。 具体地， 本发明提供的制造方法包括以下步 骤： The MOSFET structure and its manufacturing method effectively reduce the number and probability of hot carriers entering the gate dielectric layer and improve device performance. Specifically, the manufacturing method provided by the present invention includes the following steps:
a. 提供村底、 源漏区、 伪栅叠层、 层间介质层和侧墙；  a. providing the bottom of the village, the source and drain areas, the pseudo gate stack, the interlayer dielectric layer and the side walls;
b. 去除伪栅叠层形成伪栅空位；  b. removing the dummy gate stack to form a dummy gate vacancy;
c 对所述半导体结构进行倾斜的离子注入， 形成载流子散射区， 所述 载流子散射区位于漏端一侧的半导体结构表面下方；  c obliquely implanting the semiconductor structure to form a carrier scattering region, the carrier scattering region being located below the surface of the semiconductor structure on the drain side;
d. 在所述伪栅空位中淀积栅极叠层。  d. depositing a gate stack in the dummy gate vacancies.
[0007】其中， 所述载流子散射区位于村底表面下方 5nm以内， 其长度小于 栅极长度的 1/3。 [0007] wherein the carrier scattering region is located within 5 nm below the surface of the substrate, and its length is less than 1/3 of the length of the gate.
[0008】其中， 形成所述载流子散射区的杂质为锗和 /或碳， 所述载流子散射 区的杂质浓度大于 le20cm_3。 [0008] wherein said forming an impurity region of carrier scattering germanium and / or carbon, the carrier concentration of the impurity diffusion region is greater than le20cm_ 3.
[0009]相应的， 一种半导体结构， 包括： Correspondingly, a semiconductor structure includes:
村底；  Village bottom
位于所述村底上方的栅极叠层；  a gate stack located above the bottom of the village;
位于所述栅极叠层两侧村底中的源漏区；  Source and drain regions located in the bottom of both sides of the gate stack;
位于所述栅极叠层两侧的侧墙；  Side walls on both sides of the gate stack;
位于所述侧墙两侧的层间介质层；  An interlayer dielectric layer on both sides of the side wall;
以及位于栅极下方靠近漏端一侧村底中的载流子散射区。  And a carrier scattering region located in the bottom of the bottom side of the gate near the drain end.
[0010】其中， 所述载流子散射区位于村底表面下方 5nm以内， 其长度小于 栅极长度的 1/3。 [0010] wherein the carrier scattering region is located within 5 nm below the surface of the substrate and has a length less than 1/3 of the length of the gate.
[0011】其中， 形成所述载流子散射区的杂质为锗和 /或碳， 所述载流子散射 区的杂质浓度大于 le20cm_3。 [0011] wherein said forming an impurity region of carrier scattering germanium and / or carbon, the carrier concentration of the impurity diffusion region is greater than le20cm_ 3.
[0012】根据本发明提供的一种减小热载流子跃迁几率的方法， 具体的， 在 靠近漏端一侧的沟道材料中注入散射杂质， 即非电离杂质， 增大热载流子 在夹断区被散射的概率， 使得载流子在夹断区运动时受到的阻力增大， 降 低热载流子的能量， 从而减小热载流子进入栅极介质层的数目和几率。 附图说明 [0012] According to the present invention, a method for reducing the probability of hot carrier transition, specifically, injecting scattering impurities, that is, non-ionizing impurities, into a channel material near a drain end side, and increasing hot carriers The probability of being scattered in the pinch-off region increases the resistance experienced by the carriers as they move in the pinch-off region, reducing the energy of the hot carriers, thereby reducing the number and probability of hot carriers entering the gate dielectric layer. DRAWINGS
[0013]图 1至图 5示意性地示出了形成根据本发明的制造方法各阶段半导 体结构的剖面图。  1 through 5 schematically illustrate cross-sectional views of a semiconductor structure at various stages of forming a fabrication method in accordance with the present invention.
具体实施方式 detailed description
[0014】为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对 本发明的实施例作详细描述。  The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0015]下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 功能的元件。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本 发明， 而不能解释为对本发明的限制。  [0015] Embodiments of the invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the drawings are intended to be illustrative of the invention and are not to be construed as limiting.
[0016]如图 5所示， 本发明提供了一种非对称 MOSFET结构， 包括： 村底 100 ; 位于所述村底 100上方的栅极叠层 500 ; 位于所述栅极叠层 500两侧 村底中的源漏区 200； 位于所述栅极叠层 500两侧的侧墙 160；位于所述侧 墙 160两侧的层间介质层 300 ;以及位于栅极下方靠近漏端一侧村底中的载 流子散射区 400。  As shown in FIG. 5, the present invention provides an asymmetric MOSFET structure, including: a substrate 100; a gate stack 500 located above the substrate 100; on both sides of the gate stack 500. a source/drain region 200 in the bottom of the village; a side wall 160 on both sides of the gate stack 500; an interlayer dielectric layer 300 on both sides of the side wall 160; and a village located below the gate near the drain end A carrier scattering region 400 in the bottom.
[0017]所述载流子散射层 400位于半导体结构 100表面，其深度小于 5nm， 长度小于栅极长度的 1/3， 其中， 形成载流子散射层 400的元素为碳和 /或 锗， 其杂质浓度大于 le20cm_3， 通过非电离杂质的注入， 大大提高了该区 域的散射概率， 使得器件在饱和区工作时， 沟道夹断区中的载流子被散射 的概率大大提高， 有效降低了该区域热载流子的能量。 The carrier scattering layer 400 is located on the surface of the semiconductor structure 100 and has a depth of less than 5 nm and a length less than 1/3 of the gate length, wherein the elements forming the carrier scattering layer 400 are carbon and/or germanium. an impurity concentration greater than le20cm_ 3, by injecting a non-ionized impurities, greatly improving the probability of the scattering region, such that the device operates in the saturation region, the probability of carriers in the channel pinch-off region is scattered greatly increased, effectively reduce The energy of the hot carriers in this area.
[0018] 目前， 对于 MOSFET, 随着源漏之间电压的增大， 夹断区载流子所 处的电场也随着增大， 因此电子能获得更高的速度和更大的能量， 产生一 定数目的热载流子， 夹断区的电场增大到一定程度时， 这些热载流子具有 一定的几率越过沟道和栅介质层之间的势垒， 进入栅介质层中， 从而在栅 介质层中引入缺陷和陷阱， 影响器件性能。 [0018] At present, for the MOSFET, as the voltage between the source and the drain increases, the electric field of the carrier in the pinch-off region also increases, so that the electron can obtain higher speed and greater energy, resulting in When a certain number of hot carriers increase the electric field in the pinch-off region to a certain extent, the hot carriers have a certain probability to cross the barrier between the channel and the gate dielectric layer and enter the gate dielectric layer, thereby Grid Defects and traps are introduced into the dielectric layer to affect device performance.
[0019]通过本发明所述的结构， 在靠近漏端一侧的沟道材料中注入散射杂 质， 即非电离杂质， 增大热载流子在夹断区被散射的概率， 使得载流子在 夹断区运动时受到的阻力增大， 降低热载流子的能量， 从而减小热载流子 进入栅极介质层的数目和几率。  [0019] With the structure of the present invention, scattering impurities, ie, non-ionizing impurities, are implanted into the channel material near the drain end side, increasing the probability that the hot carriers are scattered in the pinch-off region, so that the carriers are made. The resistance experienced during the pinch-off region increases, reducing the energy of the hot carriers, thereby reducing the number and probability of hot carriers entering the gate dielectric layer.
[0020】栅结构包括栅极介质层、 功函数调节层和栅极金属层。 栅介质层优 选材料为氮氧化硅， 也可为氧化硅或高 K 材料。 其等效氧化厚度为 0.5nm~5nm。 栅极金属层可以只为金属栅极， 也可以为金属 /多晶硅复合栅 极， 其中多晶硅上表面上具有硅化物。  [0020] The gate structure includes a gate dielectric layer, a work function adjustment layer, and a gate metal layer. The preferred material for the gate dielectric layer is silicon oxynitride, which may also be silicon oxide or a high K material. Its equivalent oxidation thickness is 0.5 nm to 5 nm. The gate metal layer may be only a metal gate or a metal/polysilicon composite gate with silicide on the upper surface of the polysilicon.
[0021]半导体沟道区位于村底 100的表面， 其优选材料为单晶硅或单晶锗合 金薄膜， 其厚度为 2~20nm。 该区域是极轻摻杂甚至未摻杂的。 在摻杂的情 况下， 其摻杂类型与源漏区摻杂相反。  [0021] The semiconductor channel region is located on the surface of the substrate 100. The preferred material is a single crystal silicon or a single crystal germanium alloy film having a thickness of 2 to 20 nm. This region is extremely lightly doped or even undoped. In the case of doping, the doping type is opposite to that of the source and drain regions.
[0022]源区和漏区分別位于栅极叠层两侧，村底 100内。源区与漏区相对称， 其摻杂类型与村底相反。  [0022] The source and drain regions are respectively located on both sides of the gate stack, within the village 100. The source region is symmetrical with the drain region, and its doping type is opposite to that of the village.
[0023]下面结合附图对本发明的制作方法进行详细说明， 包括以下步骤。 需要说明的是， 本发明各个实施例的附图仅是为了示意的目的， 因此没有 必要按比例绘制。  [0023] The manufacturing method of the present invention will be described in detail below with reference to the accompanying drawings, including the following steps. The drawings of the various embodiments of the present invention are intended to be illustrative only and are not necessarily to scale.
[0024]首先提供村底， 并在所述村底上形成栅极介质层。 所述栅极介质层 可以是热氧化层，包括氧化硅、氮氧化硅；也可为高 K介质，例如 HfA10N、 HfSiAlON, HfTaAlON, HfTiAlON, HfON、 HfSiON、 HfTaON、 HfTiON、 A1203、 La203、 Zr02、 LaAlO 中的一种或其组合， 栅极介质层的厚度可以 为 lnm -10nm, 例如 3nm、 5nm或 8nm。 可以采用热氧化、 化学气相沉积[0024] A village bottom is first provided, and a gate dielectric layer is formed on the bottom of the village. The gate dielectric layer may be a thermal oxide layer, including silicon oxide or silicon oxynitride; or a high-k dielectric such as HfA10N, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, A1 2 0 3 , La One or a combination of 2 0 3 , Zr0 2 , and LaAlO, the thickness of the gate dielectric layer may be 1 nm to 10 nm, for example, 3 nm, 5 nm, or 8 nm. Thermal oxidation, chemical vapor deposition
(CVD) 或原子层沉积 （ALD) 等工艺来形成栅极介质层。 A process such as (CVD) or atomic layer deposition (ALD) forms a gate dielectric layer.
[0025]接下来， 在所述栅极介质层上形成伪栅结构 150。 所述伪栅结构 150 可以是单层的， 也可以是多层的。 伪栅结构 150可以包括聚合物材料、 非 晶硅、 多晶硅或 TiN， 厚度可以为 10nm~200nm。 本实施例中， 伪栅结构 包括多晶硅和二氧化， 具体的， 采用化学汽相淀积的方法在栅极空位中填 充多晶硅， 接着在多晶硅上方形成一层二氧化硅介质层， 形成方法可以是 外延生长、 氧化、 CVD等。接着采用常规 CMOS工艺光刻和刻蚀所淀积的 伪栅叠层形成栅电极图形， 然后以栅电极图形为掩膜腐蚀掉栅极介质层的 棵露部分。 需说明地是， 以下若无特別说明， 本发明实施例中各种介质材 料的淀积均可采用上述所列举的形成栅介质层相同或类似的方法， 故不再 赘述。 [0025] Next, a dummy gate structure 150 is formed on the gate dielectric layer. The dummy gate structure 150 may be a single layer or a plurality of layers. The dummy gate structure 150 may include a polymer material, amorphous silicon, polysilicon or TiN, and may have a thickness of 10 nm to 200 nm. In this embodiment, the dummy gate structure includes polysilicon and dioxide. Specifically, a chemical vapor deposition method is used to fill the gate vacancies with polysilicon, and then a silicon dioxide dielectric layer is formed over the polysilicon. The formation method may be Epitaxial growth, oxidation, CVD, and the like. Then, the gate electrode pattern is formed by photolithography and etching of the deposited dummy gate stack by a conventional CMOS process, and then the exposed portion of the gate dielectric layer is etched away by using the gate electrode pattern as a mask. It should be noted that, unless otherwise specified, the deposition of various dielectric materials in the embodiments of the present invention may adopt the same or similar methods for forming the gate dielectric layer as described above, and thus will not be described again.
[0026]接下来， 对伪栅结构两侧的村底 100进行浅摻杂， 以形成轻摻杂源 漏区， 还可以进行 Halo注入， 以形成 Halo注入区。 其中浅摻杂的杂质类 型与器件类型一致， Halo注入的杂质类型与器件类型相反。  Next, the village substrate 100 on both sides of the dummy gate structure is shallowly doped to form a lightly doped source and drain region, and Halo implantation may be performed to form a Halo implantation region. Among them, the shallow doping impurity type is the same as the device type, and the Halo implanted impurity type is opposite to the device type.
[0027】可选地， 在栅极堆叠的侧壁上形成侧墙 160， 用于将栅极隔开。具体 的， 用 LPCVD淀积 40nm~80nm厚的牺牲侧墙介质层氮化硅， 接着用会客 技术再栅电极两侧形成宽度为 35nm~75nm的氮化硅侧墙 160。 侧墙 160还 可以由氧化硅、 氮氧化硅、 碳化硅及其组合， 和 /或其他合适的材料形成。 侧墙 160可以具有多层结构。侧墙 160还可以通过包括沉积刻蚀工艺形成， 其厚度范围可以是 lOnm -lOOnm, 如 30nm、 50nm或 80nm。 [0027] Optionally, sidewall spacers 160 are formed on sidewalls of the gate stack for spacing the gates. Specifically, a silicon nitride spacer layer of 40 nm to 80 nm thick is deposited by LPCVD, and then a silicon nitride spacer 160 having a width of 35 nm to 75 nm is formed on both sides of the gate electrode by a guest technique. The sidewall spacers 160 may also be formed of silicon oxide, silicon oxynitride, silicon carbide, combinations thereof, and/or other suitable materials. The side wall 160 may have a multi-layered structure. The spacer 160 may also be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
[0028】接下来，在所述半导体结构上淀积一层厚度为 10nm~35nm厚的二氧 化硅介质层， 形成层间介质层 300， 并以该介质层为緩冲层， 离子注入源漏 区。对 P型晶体而言，摻杂剂为硼或氟化硼或铟或镓等。对 N型晶体而言， 摻杂剂为磷或砷或銻等。摻杂浓度为 5el019cm_3~lel02() cm_3。完成摻杂之后 的半导体结构如图 1所示。 [0028] Next, a silicon dioxide dielectric layer having a thickness of 10 nm to 35 nm is deposited on the semiconductor structure to form an interlayer dielectric layer 300, and the dielectric layer is used as a buffer layer, and the ion implantation source and drain are formed. Area. For the P-type crystal, the dopant is boron or boron fluoride or indium or gallium. For the N-type crystal, the dopant is phosphorus or arsenic or antimony. The doping concentration is 5el0 19 cm_ 3 ~lel0 2() cm_ 3 . The semiconductor structure after doping is completed as shown in FIG.
[0029】接下来， 去除所述伪栅结构， 形成伪栅空位， 如图 2所示。 去除伪 栅结构可以采用湿刻和 /或干刻除去。在一个实施例中，采用等离子体刻蚀。  [0029] Next, the dummy gate structure is removed to form dummy gate vacancies, as shown in FIG. The removal of the dummy gate structure can be removed by wet etching and/or dry etching. In one embodiment, plasma etching is employed.
[0030】接下来， 如图 3所示， 对所述半导体结构进行离子注入， 以形成载 流子散射层 400， 形成散射层 400的杂质元素为碳和 /或锗。 具体的， 以侧 墙 160为掩膜， 进行倾斜的离子注入， 离子注入的角度为 α， 根据侧墙 160 的高度和散射层 400的长度调节入射角 α的大小， 使得杂质入射区的边界 处于所需散射层的长度范围之内。 优选的， 在本实施例中， 载流子散射层 400的深度小于 5nm， 长度小于栅极长度的 1/3。 Next, as shown in FIG. 3, the semiconductor structure is ion-implanted to form a carrier scattering layer 400, and the impurity element forming the scattering layer 400 is carbon and/or germanium. Specifically, the side wall 160 is used as a mask, and oblique ion implantation is performed. The angle of the ion implantation is α, and the incident angle α is adjusted according to the height of the sidewall 160 and the length of the scattering layer 400, so that the boundary of the impurity incident region is at The length of the desired scattering layer is within the range. Preferably, in the present embodiment, the carrier scattering layer 400 has a depth of less than 5 nm and a length less than 1/3 of the gate length.
[0031]载流子散射层 400比村底材料具有更大的散射概率， 也就是说， 载 流子在其中运动时将受到更大的阻力， 有效减小了热载流子能量， 从而降 低了跃迁进入栅介质层中的热载流子数目， 提高了器件性能。 [0031] The carrier scattering layer 400 has a greater scattering probability than the substrate material, that is, When the flow moves therein, the flow will be subjected to greater resistance, effectively reducing the hot carrier energy, thereby reducing the number of hot carriers that enter the gate dielectric layer and improving device performance.
[0032】接下来， 在栅极空位中依次形成栅极介质层、 功函数调节层和栅极 金属层。 栅极金属层可以只为金属栅极， 也可以为金属 /多晶硅复合栅极， 其中多晶硅上表面上具有硅化物。 具体的如图 5所示， 优选的， 在栅极介 质层上先沉积功函数金属层，之后再在功函数金属层之上形成金属导体层。 功函数金属层可以采用 TiN、 TaN等材料制成， 其厚度范围为 3nm~15nm。 金属导体层可以为一层或者多层结构。其材料可以为 TaN、 TaC、 TiN、 TaAlN、 TiAlN、 ΜοΑ1Ν、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax中的一种或其组合。其厚度范围例如可以为 10nm -40nm，如 20nm或 30nm。 [0032] Next, a gate dielectric layer, a work function adjusting layer, and a gate metal layer are sequentially formed in the gate vacancies. The gate metal layer may be only a metal gate or a metal/polysilicon composite gate, wherein the polysilicon has a silicide on its upper surface. Specifically, as shown in FIG. 5, preferably, a work function metal layer is deposited on the gate dielectric layer, and then a metal conductor layer is formed on the work function metal layer. The work function metal layer can be made of a material such as TiN or TaN, and has a thickness ranging from 3 nm to 15 nm. The metal conductor layer may be in a one-layer or multi-layer structure. The material may be one of TaN, TaC, TiN, TaAlN, TiAlN, ΜοΑ1Ν, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x or a combination thereof. Its thickness may range, for example, from 10 nm to 40 nm, such as 20 nm or 30 nm.
[0033]虽然关于示例实施例及其优点已经详细说明， 应当理解在不脱离本 发明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施例 进行各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当 容易理解在保持本发明保护范围内的同时， 工艺步骤的次序可以变化。  [0033] While the invention has been described in detail with reference to the preferred embodiments of the embodiments . For other examples, it will be readily understood by those of ordinary skill in the art that the order of the process steps can be varied while remaining within the scope of the invention.
[0034]此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工 艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作为本领域的普通技术人员将容易地理解， 对于目前已存在或者以后即将 开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执 行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果， 依照本发明可以对它们进行应用。 因此， 本发明所附权利要求旨在将这些 工艺、 机构、 制造、 物质组成、 手段、 方法或步骤包含在其保护范围内。 Further, the scope of application of the present invention is not limited to the process, mechanism, manufacture, composition, means, methods and steps of the specific embodiments described in the specification. From the disclosure of the present invention, it will be readily understood by those skilled in the art that the processes, mechanisms, manufactures, compositions, means, methods or steps that are presently present or later developed, The corresponding embodiments described are substantially identical in function or obtain substantially the same results, which can be applied in accordance with the present invention. Therefore, the appended claims are intended to cover such modifications, such as the

Claims

权 利 要 求 Rights request
1、 一种 MOSFET制造方法， 包括： 1. A MOSFET manufacturing method, including:
a.提供村底（100)、源漏区（200)、伪栅叠层（150)、层间介质层（300) 和侧墙 （160) ; a. Provide a bottom (100), source and drain areas (200), dummy gate stack (150), interlayer dielectric layer (300) and sidewalls (160);
b.去除伪栅叠层 （150) 形成伪栅空位； b. Remove the dummy gate stack (150) to form dummy gate vacancies;
c.对所述半导体结构进行倾斜的离子注入， 形成载流子散射区 （400)， 所述载流子散射区 （400) 位于漏端一侧的村底表面下方； c. Perform oblique ion implantation on the semiconductor structure to form a carrier scattering region (400), which is located below the bottom surface of the drain end side;
d.在所述伪栅空位中淀积栅极叠层 （500)。 d. Deposit a gate stack in the dummy gate vacancy (500).
2、根据权利要求 1所述的制造方法，其特征在于，所述载流子散射区（400) 位于所述村底 （100) 表面下方 5nm以内， 其长度小于栅极长度的 1/3。 2. The manufacturing method according to claim 1, characterized in that the carrier scattering region (400) is located within 5 nm below the surface of the bottom (100), and its length is less than 1/3 of the gate length.
3、 根据权利要求 2所述的制造方法， 其特征在于， 形成所述载流子散射区 (400) 的杂质为锗和 /或碳。 3. The manufacturing method according to claim 2, characterized in that the impurities forming the carrier scattering region (400) are germanium and/or carbon.
4、根据权利要求 1所述的制造方法，其特征在于，所述载流子散射区（400) 的杂质浓度大于 le20cm_3。 4. The manufacturing method according to claim 1, characterized in that the impurity concentration of the carrier scattering region (400) is greater than le20cm_3 .
5、 一种半导体结构， 包括： 5. A semiconductor structure, including:
村底 （100) ; Village bottom (100);
位于所述村底 （100) 上方的栅极叠层 （500) ; a gate stack (500) located above the bottom (100);
位于所述栅极叠层 （500) 两侧村底中的源漏区 （200) ; Source and drain regions (200) located in the bottom of both sides of the gate stack (500);
位于所述栅极叠层 （500) 两侧的侧墙 （160) ; Sidewalls (160) located on both sides of the gate stack (500);
位于所述侧墙 （160) 两侧的层间介质层 （300) ; Interlayer dielectric layers (300) located on both sides of the side walls (160);
以及位于栅极下方靠近漏端一侧村底中的载流子散射区 （400)。 and a carrier scattering region (400) located in the bottom of the side of the gate near the drain end.
6、根据权利要求 5所述的半导体结构，其特征在于，所述载流子散射区（400) 位于所述村底 （100) 表面下方 5nm以内， 其长度小于栅极长度的 1/3。 6. The semiconductor structure according to claim 5, characterized in that the carrier scattering region (400) is located within 5 nm below the surface of the bottom (100), and its length is less than 1/3 of the gate length.
7、 根据权利要求 5所述的半导体结构， 其特征在于， 形成所述载流子散射 区 （400) 的杂质为锗和 /或碳。 7. The semiconductor structure according to claim 5, wherein the impurities forming the carrier scattering region (400) are germanium and/or carbon.
8、根据权利要求 5所述的半导体结构，其特征在于，所述载流子散射区（400) 的杂质浓度大于 le20cm_3。 8. The semiconductor structure according to claim 5, characterized in that the impurity concentration of the carrier scattering region (400) is greater than le20cm_3 .
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