CN103606524A - Mosfet structure and manufacturing method thereof - Google Patents

Mosfet structure and manufacturing method thereof Download PDF

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Publication number
CN103606524A
CN103606524A CN201310479825.1A CN201310479825A CN103606524A CN 103606524 A CN103606524 A CN 103606524A CN 201310479825 A CN201310479825 A CN 201310479825A CN 103606524 A CN103606524 A CN 103606524A
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substrate
gate stack
region
carrier scattering
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CN103606524B (en
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尹海洲
刘云飞
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to PCT/CN2013/085621 priority patent/WO2015054926A1/en
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
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    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

Abstract

The invention provides an MOSFET manufacturing method. The MOSFET manufacturing method includes the following steps that: A. a substrate (100), source and drain regions (200), a pseudo gate stack layer (150), interlayer dielectric layers (300) and lateral walls (160) are provided; B. the pseudo gate stack layer (150) is removed, such that a pseudo gate vacancy is formed; C. tilted ion implantation is performed on a semiconductor structure, such that a carrier scattering region (400) is formed, wherein the carrier scattering region (400) is located below the surface of the semiconductor structure at one side of a drain end; and D. a gate stack layer (500) is deposited in the pseudo gate vacancy. According to a method for reducing hot carrier transition probability provided by the invention, a scattering impurity is implanted into a channel material which is adjacent to one side of the drain end, wherein the scattering impurity is a non-ionized impurity, and the probability of hot carriers of being scattered in a pinch-off region can be increased, and therefore, a resistance borne by the carriers when the carriers move in the pinch-off region can be increased, the energy of the hot carriers can be reduced, and the number of hot carriers that enter the gate dielectric layers and the probability for the hot carriers to enter the gate dielectric layers are decreased.

Description

A kind of MOSFET structure and manufacture method thereof
Technical field
The present invention relates to a kind of MOSFET structure and manufacture method thereof.More specifically, relate to a kind of for reducing raceway groove number of hot electrons object MOSFET structure and the manufacture method thereof near drain terminal.
Technical background
MOSFET when saturation region, channel inversion layer part pinch off, very little near the channel surface transoid carrier concentration of drain terminal, resistance is very large, according to series connection dividing potential drop relation, now the voltage major part of channel region drops on pinch off region, at pinch off region, produces very large electric field.When the transoid charge carrier of channel region moves to pinch off region border under electric field action, will be by the electric field acceleration of pinch off region, very fast is swept to drain terminal, in this process, electronics will obtain very large speed, much larger than in the moving speed of transoid current-carrying subarea luck, therefore, irrelevant in movement velocity and the mobility of pinch off region electronics, depend primarily on the voltage swing on pinch off region.
Increase along with voltage between the leakage of source, the residing electric field of pinch off region charge carrier is also along with increase, therefore electronic energy obtains higher speed and larger energy, produce the hot carrier of some, when the electric field of pinch off region increases to a certain degree, these hot carriers have certain probability and cross the potential barrier between raceway groove and gate dielectric layer, enter in gate dielectric layer, thereby in gate dielectric layer, introduce defect and trap, affect device performance.
For this problem, the invention provides a kind of method that reduces hot carrier transition probability, concrete, near in the channel material of drain terminal one side, injecting scatterer, be unionized impurity, increase the probability that hot carrier is scattered at pinch off region, the resistance that charge carrier is subject to when pinch off region moves is increased, reduce the energy of hot carrier, thereby reduce number and the probability that hot carrier enters gate dielectric layer.
Summary of the invention
The invention provides a kind ofly for reducing raceway groove number of hot electrons object MOSFET structure and the manufacture method thereof near drain terminal, effectively reduced number and probability that hot carrier enters gate dielectric layer, improved device performance.Particularly, manufacture method provided by the invention comprises the following steps:
A., substrate, source-drain area, pseudo-gate stack, interlayer dielectric layer and side wall are provided;
B. remove pseudo-gate stack and form pseudo-grid room;
C. the Implantation described semiconductor structure being tilted, forms carrier scattering district, and described carrier scattering district is positioned at the semiconductor structure lower face of drain terminal one side;
D. deposit gate stack in described pseudo-grid room.
Wherein, described carrier scattering district is positioned in the 5nm of substrate surface below, and its length is less than 1/3 of grid length.
Wherein, the impurity that forms described carrier scattering district is germanium and/or carbon, and the impurity concentration in described carrier scattering district is greater than 1e20cm -3.
Accordingly, a kind of semiconductor structure, comprising:
Substrate;
Be positioned at the gate stack of described substrate top;
Be arranged in the source-drain area of described gate stack both sides substrate;
Be positioned at the side wall of described gate stack both sides;
Be positioned at the interlayer dielectric layer of described side wall both sides;
And be arranged in grid below near the carrier scattering district of drain terminal one side substrate.
Wherein, described carrier scattering district is positioned in the 5nm of substrate surface below, and its length is less than 1/3 of grid length.
Wherein, the impurity that forms described carrier scattering district is germanium and/or carbon, and the impurity concentration in described carrier scattering district is greater than 1e20cm -3.
According to a kind of method that reduces hot carrier transition probability provided by the invention, concrete, near in the channel material of drain terminal one side, injecting scatterer, be unionized impurity, increase the probability that hot carrier is scattered at pinch off region, the resistance that charge carrier is subject to when pinch off region moves is increased, reduce the energy of hot carrier, thereby reduce number and the probability that hot carrier enters gate dielectric layer.
Accompanying drawing explanation
Fig. 1 to Fig. 5 schematically shows the profile that forms each stage semiconductor structure of manufacturing method according to the invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiments of the invention are described in detail.
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Below by the embodiment being described with reference to the drawings, be exemplary, only for explaining the present invention, and can not be interpreted as limitation of the present invention.
As shown in Figure 5, the invention provides a kind of asymmetric MOSFET structure, comprising: substrate 100; Be positioned at the gate stack 500 of described substrate 100 tops; Be arranged in the source-drain area 200 of described gate stack 500 both sides substrates; Be positioned at the side wall 160 of described gate stack 500 both sides; Be positioned at the interlayer dielectric layer 300 of described side wall 160 both sides; And be arranged in grid below near the carrier scattering district 400 of drain terminal one side substrate.
Described carrier scattering layer 400 is positioned at semiconductor structure 100 surfaces, and its degree of depth is less than 5nm, and length is less than 1/3 of grid length, and wherein, the element that forms carrier scattering layer 400 is carbon and/or germanium, and its impurity concentration is greater than 1e20cm -3, by the injection of unionized impurity, greatly improved the probability of scattering in this region, make device when saturation region operation, the probability that the charge carrier in raceway groove pinch off region is scattered improves greatly, effectively reduces the energy of this region hot carrier.
At present, for MOSFET, along with the increase of voltage between the leakage of source, the residing electric field of pinch off region charge carrier is also along with increase, so electronic energy obtains higher speed and larger energy, produce the hot carrier of some, when the electric field of pinch off region increases to a certain degree, these hot carriers have certain probability and cross the potential barrier between raceway groove and gate dielectric layer, enter in gate dielectric layer, thereby in gate dielectric layer, introduce defect and trap, affect device performance.
By structure of the present invention, near in the channel material of drain terminal one side, injecting scatterer, be unionized impurity, increase the probability that hot carrier is scattered at pinch off region, the resistance that charge carrier is subject to when pinch off region moves is increased, reduce the energy of hot carrier, thereby reduce number and the probability that hot carrier enters gate dielectric layer.
Grid structure comprises gate dielectric layer, work function regulating course and gate metal layer.Gate dielectric layer preferred material is silicon oxynitride, also can be silica or hafnium.Its equivalent oxide thickness is 0.5nm～5nm.Gate metal layer can be only metal gates, also can, for metal/Polysilicon Composite Structures grid, wherein on polysilicon upper surface, have silicide.
Semiconductor channel area is positioned at the surface of substrate 100, and its preferred material is monocrystalline silicon or monocrystalline germanium alloy firm, and its thickness is 2～20nm.This region is that utmost point light dope is even unadulterated.The in the situation that of doping, its doping type is contrary with source-drain area doping.
Source region and drain region lay respectively at gate stack both sides, in substrate 100.Source region and drain region are symmetrical, and its doping type is contrary with substrate.
Below in conjunction with accompanying drawing, manufacture method of the present invention is elaborated, comprises the following steps.It should be noted that, the accompanying drawing of each embodiment of the present invention is only the object in order to illustrate, is therefore not necessarily to scale.
First substrate is provided, and forms gate dielectric layer on described substrate.Described gate dielectric layer can be thermal oxide layer, comprises silica, silicon oxynitride; Also can be high K dielectric, for example HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al 2o 3, La 2o 3, ZrO 2, a kind of or its combination in LaAlO, the thickness of gate dielectric layer can be 1nm-10nm, for example 3nm, 5nm or 8nm.Can adopt the techniques such as thermal oxidation, chemical vapour deposition (CVD) (CVD) or ald (ALD) to form gate dielectric layer.
Next, on described gate dielectric layer, form pseudo-grid structure 150.Described pseudo-grid structure 150 can be individual layer, can be also multilayer.Pseudo-grid structure 150 can comprise polymeric material, amorphous silicon, polysilicon or TiN, and thickness can be 10nm～200nm.In the present embodiment, pseudo-grid structure comprises polysilicon and titanium dioxide, concrete, adopts the method for chemical vapor deposition to fill polysilicon in grid room, then above polysilicon, form layer of silicon dioxide dielectric layer, formation method can be epitaxial growth, oxidation, CVD etc.Then adopt the pseudo-gate stack of stand CMOS photoetching and the deposit of etching institute to form gate electrode figure, the gate electrode figure of then take falls the exposed part of gate dielectric layer as mask corrosion.It should be noted that, below unless otherwise noted, in the embodiment of the present invention, the deposit of various dielectric materials all can adopt the above-mentioned cited same or similar method of formation gate dielectric layer, therefore repeat no more.
Next, the substrate 100 of pseudo-grid structure both sides is carried out to shallow doping, to form lightly-doped source drain region, can also carry out Halo injection, to form Halo injection region.Wherein the dopant type of shallow doping is consistent with type of device, and the dopant type that Halo injects is contrary with type of device.
Alternatively, on the sidewall of gate stack, form side wall 160, for grid is separated.Concrete, with the thick sacrifice side wall medium layer silicon nitride of LPCVD deposit 40nm～80nm, then by the technology of receiving a visitor, form the silicon nitride side wall 160 that width is 35nm～75nm in gate electrode both sides again.Side wall 160 can also be by silica, silicon oxynitride, carborundum and combination thereof, and/or other suitable materials form.Side wall 160 can have sandwich construction.Side wall 160 can also be by comprising that deposition-etch technique forms, and its thickness range can be 10nm-100nm, as 30nm, 50nm or 80nm.
Next, on described semiconductor structure, deposit a layer thickness is the silica dioxide medium layer that 10nm～35nm is thick, forms interlayer dielectric layer 300, and take this dielectric layer as resilient coating, Implantation source-drain area.For P type crystal, dopant is boron or boron fluoride or indium or gallium etc.For N-type crystal, dopant is phosphorus or arsenic or antimony etc.Doping content is 5e10 19cm -3～1e10 20cm -3.Complete doping semiconductor structure afterwards as shown in Figure 1.
Next, remove described pseudo-grid structure, form pseudo-grid room, as shown in Figure 2.Removing pseudo-grid structure can adopt wet etching and/or dry quarter to remove.In one embodiment, using plasma etching.
Next, as shown in Figure 3, described semiconductor structure is carried out to Implantation, to form carrier scattering layer 400, the impurity element that forms scattering layer 400 is carbon and/or germanium.Concrete, take side wall 160 as mask, the Implantation tilting, the angle of Implantation is α, according to the size of the length adjustment incidence angle α of the height of side wall 160 and scattering layer 400, within the length range of the border that makes impurity incidence zone in required scattering layer.Preferably, in the present embodiment, the degree of depth of carrier scattering layer 400 is less than 5nm, and length is less than 1/3 of grid length.
Carrier scattering layer 400 has larger probability of scattering than backing material, that is to say, when charge carrier moves therein, will be subject to larger resistance, effectively reduced hot carrier energy, thereby reduced transition, enter the hot carrier number in gate dielectric layer, improved device performance.
Next, in grid room, form successively gate dielectric layer 201, work function regulating course 202 and gate metal layer 203.Gate metal layer 203 can be only metal gates, also can, for metal/Polysilicon Composite Structures grid, wherein on polysilicon upper surface, have silicide.Specifically as shown in Figure 5, preferred, on gate dielectric layer 201, first deposit workfunction layers, on workfunction layers, form again afterwards metal conductor layer.Workfunction layers can adopt the materials such as TiN, TaN to make, and its thickness range is 3nm～15nm.Metal conductor layer can be one deck or sandwich construction.Its material can be TaN, TaC, TiN, TaAlN, TiAlN, MoAlN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x, NiTa xin a kind of or its combination.Its thickness range can be for example 10nm-40nm, as 20nm or 30nm.
Although describe in detail about example embodiment and advantage thereof, be to be understood that in the situation that do not depart from the protection range that spirit of the present invention and claims limit, can carry out various variations, substitutions and modifications to these embodiment.For other examples, when those of ordinary skill in the art should easily understand within keeping protection range of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technique, mechanism, manufacture, material composition, means, method and the step of the specific embodiment of describing in specification.From disclosure of the present invention, as those of ordinary skill in the art, will easily understand, for the technique, mechanism, manufacture, material composition, means, method or the step that have existed or be about to develop at present later, wherein they carry out identical function or the identical result of acquisition cardinal principle of corresponding embodiment cardinal principle of describing with the present invention, according to the present invention, can apply them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.

Claims (8)

1. a MOSFET manufacture method, comprising:
A., substrate (100), source-drain area (200), pseudo-gate stack (150), interlayer dielectric layer (300) and side wall (160) are provided;
B. remove pseudo-gate stack (150) and form pseudo-grid room;
C. the Implantation described semiconductor structure being tilted, forms carrier scattering district (400), and described carrier scattering district (400) is positioned at the substrate surface below of drain terminal one side;
D. deposit gate stack (500) in described pseudo-grid room.
2. manufacture method according to claim 1, is characterized in that, described carrier scattering district (400) is positioned in described substrate (100) lower face 5nm, and its length is less than 1/3 of grid length.
3. manufacture method according to claim 2, is characterized in that, the impurity that forms described carrier scattering district (400) is germanium and/or carbon.
4. manufacture method according to claim 1, is characterized in that, the impurity concentration in described carrier scattering district (400) is greater than 1e20cm -3.
5. a semiconductor structure, comprising:
Substrate (100);
Be positioned at the gate stack (500) of described substrate (100) top;
Be arranged in the source-drain area (200) of described gate stack (500) both sides substrate;
Be positioned at the side wall (160) of described gate stack (500) both sides;
Be positioned at the interlayer dielectric layer (300) of described side wall (160) both sides;
And be arranged in grid below near the carrier scattering district (400) of drain terminal one side substrate.
6. semiconductor structure according to claim 5, is characterized in that, described carrier scattering district (400) is positioned in described substrate (100) lower face 5nm, and its length is less than 1/3 of grid length.
7. semiconductor structure according to claim 5, is characterized in that, the impurity that forms described carrier scattering district (400) is germanium and/or carbon.
8. semiconductor structure according to claim 5, is characterized in that, the impurity concentration in described carrier scattering district (400) is greater than 1e20cm -3.
CN201310479825.1A 2013-10-15 2013-10-15 A kind of MOSFET structure and manufacture method thereof Active CN103606524B (en)

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CN201310479825.1A CN103606524B (en) 2013-10-15 2013-10-15 A kind of MOSFET structure and manufacture method thereof
PCT/CN2013/085621 WO2015054926A1 (en) 2013-10-15 2013-10-22 Mosfet structure and method of manufacturing same

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CN103606524B CN103606524B (en) 2016-03-23

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