WO2015046791A1 - Dispositif redresseur à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif redresseur à semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2015046791A1
WO2015046791A1 PCT/KR2014/008566 KR2014008566W WO2015046791A1 WO 2015046791 A1 WO2015046791 A1 WO 2015046791A1 KR 2014008566 W KR2014008566 W KR 2014008566W WO 2015046791 A1 WO2015046791 A1 WO 2015046791A1
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Prior art keywords
substrate
forming
guard ring
layer
gate
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PCT/KR2014/008566
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English (en)
Korean (ko)
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김덕수
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주식회사 실리콘웍스
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Priority claimed from KR20130114523A external-priority patent/KR101502306B1/ko
Application filed by 주식회사 실리콘웍스 filed Critical 주식회사 실리콘웍스
Publication of WO2015046791A1 publication Critical patent/WO2015046791A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66128—Planar diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes

Definitions

  • the present invention relates to rectifying devices, and more particularly, to a semiconductor rectifying device having a low forward voltage, a low leakage current, and a fast reverse recovery characteristic, and a manufacturing method thereof.
  • Power semiconductors are semiconductor devices for high voltage or high current that are optimized for power conversion and power control.
  • the power rectifier circuit has a function of converting alternating current electricity into direct current required by electronic products.
  • Such power rectification circuits are semiconductor devices required to power all the electrical devices such as mobile devices, computer parts, communication devices, display devices, automobile parts, and industrial devices including motors, or to stably supply desired voltages and currents.
  • Typical power rectifier circuits include PIN (or PN) rectifier circuits and Schottky rectifier circuits. Since the PIN rectifier circuit uses a PN junction, the reverse leakage current is excellent, and the barrier metal is not used, so the reliability of the high temperature operation is good. However, the PIN rectifier circuit has a large forward voltage drop (VF), and a large switching time due to a slow reverse recovery time due to minority carriers.
  • VF forward voltage drop
  • the Schottky rectifier circuit is a rectifier device that uses a work function difference between the barrier metal and silicon, resulting in small forward voltage drop and fast switching time.
  • the Schottky rectifier circuit is disadvantageous for high temperature operation because of a large leakage current at off-state and a large leakage current at high temperature due to the use of a barrier metal.
  • a semiconductor rectification device using a MOS transistor is developed.
  • Semiconductor rectifier devices like PN rectifier circuits, have low leakage current and stable operation at high temperatures, and have lower forward voltage drop (V F ), higher temperature operating stability, and faster switching than Schottky rectifier circuits.
  • An object of the present invention is to provide a semiconductor rectifying device and a method for manufacturing the same, which can simplify the manufacturing process, improve the yield, and lower the manufacturing cost by improving the processes of forming the guard ring, the active region and the channel.
  • Another object of the present invention is to provide a semiconductor rectifying device having a low forward voltage, a low leakage current, and a fast reverse recovery characteristic by implementing a rectifying device using a MOS structure, and a method of manufacturing the same.
  • the semiconductor rectifying device of the present invention includes a substrate; Gate layers spaced apart on the substrate; Side walls formed on sides of the gate layer; Channels formed in the substrate below the sidewalls; Bodies formed in an open region of the substrate between the gate layers to separate the channels; An anode formed on the gate layer and the bodies to electrically connect the gate layer and the bodies; And a cathode electrode formed below the substrate.
  • the method of manufacturing a semiconductor rectifying device of the present invention comprises the steps of: forming a guard ring on a substrate; Forming gate layers in an active region of the guard ring of the substrate; Performing first ion implantation to form channels in the substrate in an open region between the gate layers; Forming sidewalls at an edge of the gate layer; Performing a second ion implantation to form bodies that limit the channels to the lower sidewalls; Forming an anode electrode electrically connecting the gate layers and the bodies; And forming a cathode at a lower portion of the substrate.
  • the method of manufacturing a semiconductor rectifying device of the present invention comprises the steps of: forming a guard ring on a substrate; Forming gate layers in an active region of the guard ring of the substrate; Performing first ion implantation to form channels in the open region between the gate layers and the substrate below the edge of the gate layers; Performing a second implantation to form bodies that confine the channels to the bottom of the edges of the gate layers; Forming an anode electrode electrically connecting the gate layers and the bodies; And forming a cathode on the bottom of the substrate.
  • the present invention can solve the complexity of the process and the difficulty of precisely controlling the process, which may occur in a process using oxide isotropic etching or pedestal used to form a channel in the semiconductor rectifying device.
  • the present invention uses sidewalls to form the channels of the semiconductor rectifying device, which simplifies the manufacturing process, thereby increasing the yield and reducing the manufacturing cost.
  • the present invention reduces the number of processes for forming the guard ring of the semiconductor rectifying device, thereby simplifying the manufacturing process, increasing the yield, and reducing the manufacturing cost.
  • the present invention has the effect of realizing a semiconductor rectifying device having a MOS structure and having a low forward voltage, low leakage current and fast reverse recovery characteristics.
  • the present invention has the effect that a semiconductor rectifying device having a diode characteristic by having a MOS structure and the gate and the source are electrically connected in common.
  • FIG. 1 is a cross-sectional view of a semiconductor rectifying device according to the present invention.
  • FIG. 2 is an equivalent circuit diagram of the semiconductor rectifying device shown in FIG. 1.
  • FIG. 3 is a cross-sectional view illustrating an internal current path of the semiconductor rectifying device illustrated in FIG. 1.
  • 4 to 15 are process diagrams illustrating a method for manufacturing the semiconductor rectifying device shown in FIG. 1.
  • FIG. 16 is a cross-sectional view of a semiconductor rectifying device according to the present invention.
  • FIG. 17 is a cross-sectional view illustrating an internal current path of the semiconductor rectifying device illustrated in FIG. 16.
  • 18 to 27 are process charts illustrating a method for manufacturing the semiconductor rectifying device shown in FIG. 16.
  • a semiconductor rectifying device includes a substrate 10, a guard ring 14, channels 22, bodies 24, gate layers 20, sidewalls 19, and electrode layers 28. ) And a back metal layer 30. Referring to FIG. 1, the structure of a semiconductor rectifying device will be described in detail.
  • the substrate 10 is a high concentration N type (N +) sub-layer (Sub Layer) (8 in Fig. 4) (N -) over the lightly doped N type epitaxial layer (Epitaxial layer) (9 of Fig. 4) structure is formed, Has
  • the active region is an area forming the semiconductor rectifying device and may be defined by the guard ring 14.
  • the guard ring region may be defined by the guard ring 14, which is intended to separate the active region from the non-active region of the outer portion.
  • An oxide film 12 may be formed on the substrate 10 in the non-active region.
  • the channels 22 formed by the first front ion implantation and the bodies 24 formed by the second front ion implantation are formed.
  • the guard ring 14 may be formed by ion implanting impurities such as boron (B), which is a P-type impurity, and driving-in the impurity, and functioning such as separating a rectifying device or blocking an electrical path from the outside.
  • impurities such as boron (B), which is a P-type impurity, and driving-in the impurity, and functioning such as separating a rectifying device or blocking an electrical path from the outside.
  • B boron
  • the bodies 24 may be formed by a well in which P-type impurities are ion-implanted, and are formed to reduce leakage current and to secure breakdown voltage.
  • the bodies 24 are between the channels 22 under the sidewalls 19 of the adjacent gate layers 20 and the channel 22 and the guard ring under the sidewalls 19 of the gate layer 20. 14) is formed between.
  • the channels 22 are for forming a current path of the rectifying device, and may be formed by implanting P-type impurities, and are charged through the gate poly 18 and the gate oxide film 16 for the rectifying operation of the rectifying device.
  • the channel characteristic may be inverted to N type by a field effect.
  • Gate layers 20 are formed on top of substrate 10 between channels 22.
  • the gate layers 20 have a structure in which the gate poly 18 is stacked on the gate oxide layer 16.
  • Side walls 19 are formed at the edges of the gate layers 20.
  • Channels 22 are formed under the side walls 19.
  • side walls 19 are formed over the substrate 10 to cover the channels 22.
  • the gate layer 20 and the bodies 24 are electrically connected to each other by an electrode layer 28 contacting the upper portion, and the electrode layer 28 may be made of a conductive metal such as aluminum.
  • the electrode layer 28 is formed on the guard ring 14 and the active region. More specifically, the electrode layer 28 is formed by depositing aluminum, which is a conductive metal, on a region including the gate layers 20 and the bodies 24. The electrode layer 28 may act as an anode electrode of the rectifying device by having a pattern by an etching process described later.
  • a conductive back metal layer 30 is formed below the substrate 10, and the back metal layer 30 has an N-sub (N ⁇ ) with respect to an N-type epitaxial layer (9 in FIG. 4). acts as a sub).
  • the back metal layer 30 may serve as a drain of the MOS while serving as a cathode of the semiconductor rectifying device of the present invention.
  • the semiconductor rectifying device configured as shown in FIG. 1 may be represented by an equivalent circuit as shown in FIG. 2 and has a characteristic of acting as a diode.
  • the semiconductor rectifying device of FIG. 1 includes a diode using an NMOS transistor, and a source (S) and a gate (G) of the NMOS transistor are electrically connected to each other to form an anode of the diode.
  • the drain D of the NMOS transistor becomes the cathode of the diode.
  • the bodies 24 serve as a source
  • the gate layer 20 serves as a gate
  • the substrate 10 and the back metal layer 30 serve as drains. It has a MOS structure that acts as a drain.
  • the semiconductor rectifying device of FIG. 1 has a gate and a source electrically connected to each other by connecting the bodies 24 and the gate layers 20 connected to the channels 22 by the electrode layer 28 in common. It has a diode characteristic that acts as an anode and the drain acts as a cathode.
  • the semiconductor rectifying device may perform the operation of rectifying the current in the path shown by the arrow of FIG. 3 due to the characteristics of the diode as shown in FIG. 2.
  • the semiconductor rectifying device shown in FIG. 1 may be manufactured by the process of FIGS. 4 to 15.
  • a method of manufacturing a semiconductor rectifying device will be described with reference to FIGS. 4 to 15.
  • an oxide film 12 is formed on the entire surface of the substrate 10.
  • the substrate 10 preferably has a structure in which a low concentration N-type (N ⁇ ) epitaxial layer 9 is formed on the high concentration N-type (N + ) sublayer 8.
  • the oxide film 12 is formed on the epitaxial layer 9.
  • the guard ring region and the active region of the substrate 10 are opened. That is, the oxide film 12 of the guard ring region where the guard ring is to be formed and the active region where the rectifying device is to be formed is removed from the oxide film 12 formed on the substrate 10.
  • a mask process may be performed. That is, after a photoresist layer (not shown) is formed on the oxide layer 12, the photoresist layer may be patterned using a first mask (not shown).
  • the patterning process includes sequentially performing an exposure process and a developing process using a first mask having a specific pattern.
  • the patterning process may include removing the photoresist layer after etching the oxide film to have a specific pattern using the photoresist layer remaining after the exposure process and the etching process.
  • the oxide film 12 formed in the guard ring region and the active region is removed, and the oxide film 12 remains on the periphery of the semiconductor rectifying device.
  • a photoresist layer 41 having an open guard ring region is formed, and boron B, which is a P-type impurity, is implanted on the substrate 10 to form the guard ring.
  • boron B which is a P-type impurity
  • a photoresist layer 41 is formed on the substrate 10 shown in FIG. 5, and the photoresist layer 41 is patterned using a second mask (not shown). . That is, as shown in FIG. 6, the photoresist layer 41 has a pattern covering the active region and the oxide film 12 and opening the guard ring region.
  • the impurity is implanted using the photoresist layer 41, the impurity is implanted only in the guard ring region and the other region is blocked by the photoresist layer 41.
  • impurity implantation is completed in the guard ring region, the photoresist layer 41 on the substrate 10 is removed.
  • the guard ring 14 is formed in the guard ring region as shown in FIG. 7 with the active region open.
  • the guard ring 14 may be formed by one oxide film etching process and may be formed by a simplified manufacturing process.
  • the gate layer 20 is formed. Referring to FIG. 8, the gate layer 20 is formed in the active region.
  • the gate layer 20 is sequentially formed by an oxidation process for forming the gate oxide layer 16, a deposition process for forming the gate poly 18, and an etching process using a photoresist layer as a mask. Can be formed.
  • the deposition of the gate poly 18 is preferably performed by a chemical vapor deposition method.
  • the gate poly 18 refers to a conductive thin film deposited with a polysilicon material, and may be formed to have a thickness of 3000 to 6000.
  • the thickness of the gate oxide layer 20 may be variously determined by the manufacturer by determining the electrical characteristics of the channels 22 of FIG. 10.
  • the gate oxide film 20 may use a natural oxide film formed naturally without undergoing a separate oxidation process.
  • the gate layer 20 is formed by forming a gate oxide film 16 and a gate poly 18 on the substrate 10, and then using a third mask (not shown) and a photoresist layer (42 in FIG. 9). And it may be formed to have a desired pattern by an etching process.
  • open regions are formed between the etched gate layers 20 as shown in FIG. 8.
  • An open region between the gate layers 20 may be formed by an etching process using a photoresist layer (42 in FIG. 9) as a mask, and the etching process may be a general photolithography process using a third mask. Therefore, detailed description thereof will be omitted.
  • front surface ion implantation is performed on the substrate 10 to form channels 22.
  • the gate layers 20, the oxide film 12, and the photoresist layer 42 are used as masks.
  • the front surface ion implantation may be performed using a P-type impurity, for example, boron (B), and the amount and energy into which the P-type impurity is implanted may be formed in the substrate under the edge of the gate layers 20. It may be determined in consideration of the width and depth of 22) of FIG.
  • the photoresist layer 42 formed on the gate layers 20 is removed.
  • the P-type impurity may be implanted into the substrate 10 in the open region in which the gate layer 20 is not formed in the active region.
  • Channels 22 may be formed in the substrate 10 between the guard ring 14, the gate layer 20, and the adjacent gate layers 20 by the front ion implantation. Since the front ion implantation is easy to control the amount and energy for forming the channels 22, the channel can be formed to the desired width and depth. That is, according to the present invention, it is possible to obtain the advantage that the process of forming the channels 22 can be easily controlled.
  • the front ion implantation is easy to implement, it is possible to use a low cost device instead of an expensive device. That is, the front ion implantation can be performed using low cost equipment. Therefore, the manufacturing cost of the semiconductor rectifying device can be lowered.
  • a poly layer 51 is formed on a substrate 10.
  • the poly layer 51 refers to a conductive thin film deposited with a polysilicon material, and is preferably formed to have a thickness of 3000 to 6000.
  • the thickness of the poly layer 51 may be variously determined by the designer in consideration of the characteristics of the process.
  • the poly layer 51 is removed by an etch-back method.
  • a spacer is formed by the poly layer 51 remaining at the edges of the gate layers 20, and the spacers serve as side walls 19 of the gate layer 20. Side walls 19 are formed to cover a portion of the channels 22.
  • front surface ion implantation using a P-type impurity is performed on the substrate 10 to form the bodies 24.
  • the front ion implantation means implantation of ions substantially perpendicular to the substrate 10.
  • the gate layers 20, the oxide film 12, and the sidewalls 19 may be used as a mask.
  • P-type impurities such as boron (B) may be used.
  • the bodies 24 are formed in the open area of the active area. In other words, the regions of the channels 22 are limited to the lower side walls 19 by the bodies 24.
  • the channels 22 formed under the side walls 19 are preserved without being affected by the front ion implantation and serve as a channel through which current flows. . That is, a separate process for forming the channels 22 on the substrate below the edge of the gate layers 20 is unnecessary. In other words, the process of forming the channels 22 in the substrate below the edge of the gate layer 20 is simplified.
  • a process using an oxide film isotropic etching or pedestal used to form the channels 22 under the gate layers 20 has a complexity of the process and difficulty in precisely controlling the process.
  • the embodiment of the present invention can solve the above-mentioned conventional difficulties by using the side walls 19.
  • the bodies 24 are formed in the open active region of the substrate 10 by the front ion implantation of FIG. 13.
  • the bodies 24 are formed in open regions between the gate layer 20 and the guard ring 14 and between the gate layers 20.
  • the channels 22 formed by the previous process are reduced and remain under the side walls 19.
  • the body 24 refers to a conventional P region or P well, and is formed to have a larger amount of dose than the channel 22 to prevent reverse bias. It is preferably formed to be equal to or deeper than the depth of channel 22 to reduce leakage current and ensure breakdown voltage.
  • the channels 22 of the adjacent gate layers 20 are separated by the body 24.
  • the drive-in may be performed to effectively form the bodies 24.
  • an annealing process may be performed to stabilize the structure of FIG. 14.
  • an electrode layer 28 for an anode electrode is formed on the gate layer 20 and the bodies 24.
  • the electrode layer 28 may be made of a conductive metal, such as aluminum metal. That is, the electrode layer 28 is formed by depositing aluminum metal on the substrate 10 and patterning the deposited aluminum metal to have a pattern as shown in FIG. 15.
  • a conductive barrier metal may be formed between the electrode layer 28 and the substrate 10, and between the electrode layer 28 and the gate layer 20. That is, the conductive barrier metal may be formed under the electrode layer 28.
  • the barrier metal may form an ohmic contact, control spike generation by the aluminum metal, and may be used as a diffusion barrier to prevent diffusion.
  • a conductive back metal layer (30 of FIG. 1) may be deposited on the lower portion of the substrate 10.
  • the material of the back metal layer (30 in Figure 1) is preferably selected to be able to act as an N-sub (N-sub) with respect to the substrate 10.
  • the back metal layer (30 in FIG. 1) serves as the cathode of the semiconductor rectifying device.
  • embodiments of the present invention can be presented to have different channel structures.
  • a semiconductor rectifying device includes a substrate 10, a guard ring 14, channels 22, bodies 24, gate layers 20, an electrode layer 28, and a back metal layer. 30 is provided.
  • FIG. 16 has a structural difference in that sidewalls 19 are not formed as compared to FIG. 1, and channels 22 are formed below edges of the gate layer 20.
  • the same components as those in the embodiment of FIG. 1 are denoted by the same reference numerals, and description of the same structures and operations will be omitted.
  • the channel 22 may be formed under the edge of the gate layer 20 by tilt ion implantation described later. Accordingly, the semiconductor rectifying device of the present invention as shown in FIG. 16 may perform the operation of rectifying the current in the path shown by the arrow of FIG. 17 by the characteristic of acting as a diode as shown in FIG. 2.
  • the semiconductor rectifying device illustrated in FIG. 16 may be manufactured by the process of FIGS. 18 to 27.
  • a method of manufacturing a semiconductor rectifying device will be described with reference to FIGS. 18 to 27.
  • FIG. 16 performs the process of forming the oxide film 12, the guard ring 14, and the gate layer 20, as shown in FIGS. 18 to 22.
  • the process of 22 is the same as that of the embodiment of FIG.
  • the gate layers 20 are formed in the active region as shown in FIG. 22.
  • the gate layer 20 is sequentially formed by an oxidation process for forming the gate oxide layer 16, a deposition process for forming the gate poly 18, and an etching process using a photoresist layer as a mask. Can be formed.
  • the gate layer 20 may be formed by forming a gate oxide film 16 and a gate poly 18 on the substrate 10 and then exposing, developing, and etching a third mask (not shown) and a photoresist layer. It may be formed to have a pattern. When a plurality of rectifying devices are formed on the substrate 10, open regions are formed between the etched gate layers 20 as shown in FIG. 22.
  • tilt ion implantation is performed on the substrate 10 to form channels (22 in FIG. 24) as shown in FIG. 23.
  • the gate layers 20 and the oxide film 12 are used as a mask.
  • the tilt ion implantation may be performed using a P-type impurity, for example, boron, and an angle, an amount, and an energy into which the P-type impurity is implanted may be formed in a substrate under the edge of the gate layers 20. It may be determined in consideration of the width and depth of the field (22 of FIG. 24).
  • the P-type impurity may be implanted into the open region where the gate layers 20 are not formed and the substrate 10 below the edge of the gate layers 20. . That is, since the P-type impurity is inclined to the substrate 10 by the tilt ion implantation, the P-type impurity may be injected into the lower portion of the edges of the gate layers 20.
  • the channels 22 may be formed between the guard ring 14, the gate layer 20, and the adjacent gate layers 20 by the tilt ion implantation. Since the tilt ion implantation is easy to control the angle, amount and energy for forming the channels 22, the channel can be formed to a desired width and depth. That is, the present invention has the advantage that the process of forming the channels 22 can be easily controlled.
  • front ion implantation means implantation of ions substantially perpendicular to the substrate 10.
  • the gate layers 20 and the oxide film 12 may be used as a mask.
  • a P-type impurity such as boron may be used.
  • the bodies 24 are formed in the open area of the active area.
  • the present invention may occur in a process using conventional oxide isotropic etching or pedestal to form the channels 22 under the gate layers 20 by using the tilt ion implantation method.
  • the complexity of the process and the difficulty of precise control of the process can be eliminated.
  • the bodies 24 are formed in the open active region of the substrate 10 by the front ion implantation of FIG. 25. That is, the bodies 24 are formed in the open region between the gate layer 20 and the guard ring 14 and between the gate layers 20. Accordingly, the channels 22 of the substrate 10 are reduced to remain under the edge of the gate layer 20. As described above, the channels 22 of the adjacent gate layers 20 are separated by the bodies 24.
  • drive-in may be performed to effectively form the bodies 24 as shown in FIG. 26.
  • an annealing process may be performed to stabilize the structure of FIG. 26.
  • an electrode layer 28 for an anode electrode is formed on the gate layer 20 and the bodies 24.
  • the electrode layer 28 may be made of a conductive metal, such as aluminum metal. That is, the electrode layer 28 is formed by depositing aluminum metal on the substrate 10 and patterning the deposited aluminum metal to have a pattern as shown in FIG. 27.
  • a barrier metal may be formed between the electrode layer 28 and the substrate 10, and between the electrode layer 28 and the gate layer 20. In this case, the barrier metal may form an ohmic contact, control spike generation by the aluminum metal, and may be used as a diffusion barrier to prevent diffusion.
  • a conductive back metal layer (30 of FIG. 16) may be deposited on the lower portion of the substrate 10.
  • the material of the back metal layer (30 in Figure 16) is preferably selected to be able to act as an N-sub (N-sub) with respect to the substrate 10.
  • the back metal layer (30 in FIG. 16) serves as the cathode of the semiconductor rectifying device.
  • the formation of the semiconductor rectification device of FIG. 16 is completed by forming the back metal layer (30 in FIG. 16).
  • embodiments of the present invention can be constructed, and by using the conventional oxide isotropic etching or pedestal to form the channels 22 in the semiconductor rectifying device according to the embodiments of the present invention.
  • the complexity of the process and the difficulty of precise control of the process can be eliminated.
  • the embodiment of the present invention may form the channels 22 by using the front ion implantation and the side walls 19, so that the manufacturing process may be performed using low-cost equipment, thereby manufacturing the semiconductor rectifying device. Can be lowered.
  • the embodiment of the present invention can improve the process of forming the channels 22 by forming the channels 22 using tilt ion implantation, thereby simplifying the manufacturing process of the semiconductor rectification device and yield Is higher.
  • the embodiment of the present invention has the advantage that the process can be accurately controlled when using the tilt ion implantation, thereby increasing the yield of the semiconductor rectifying device and the manufacturing cost is reduced.
  • the present invention reduces the number of steps of forming the guard ring 14 of the semiconductor rectifying device, thereby increasing the yield of the semiconductor rectifying device and reducing the manufacturing cost.
  • the present invention can implement a rectifier circuit having a low forward voltage, low leakage current and fast reverse recovery characteristics while having a MOS structure.
  • the present invention can implement a rectifier circuit having a diode characteristic by having the MOS structure and the gate and the source are electrically connected in common.

Abstract

La présente invention concerne un dispositif redresseur à semi-conducteur et son procédé de fabrication. Le dispositif redresseur à semi-conducteur selon la présente invention présente une tension directe faible, un faible courant de fuite, et des caractéristiques de recouvrement inverse, et peut simplifier un processus de fabrication au moyen d'un processus amélioré de formation d'un canal et peut améliorer un rendement. En outre, le dispositif redresseur à semi-conducteur selon la présente invention peut effectuer une régulation exacte en vue de former le canal.
PCT/KR2014/008566 2013-09-26 2014-09-15 Dispositif redresseur à semi-conducteur et son procédé de fabrication WO2015046791A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2013-0114527 2013-09-26
KR20130114527 2013-09-26
KR10-2013-0114523 2013-09-26
KR20130114523A KR101502306B1 (ko) 2013-09-26 2013-09-26 반도체 정류 소자 및 그의 제조 방법

Publications (1)

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WO2015046791A1 true WO2015046791A1 (fr) 2015-04-02

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080217721A1 (en) * 2007-03-09 2008-09-11 Hamerski Roman J High efficiency rectifier
KR20090083353A (ko) * 2006-11-03 2009-08-03 크리 인코포레이티드 정류 접합 션트들을 포함하는 파워 스위칭 반도체 소자들
KR20120028272A (ko) * 2010-09-13 2012-03-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 파워 다이오드 및 정류기
US20120132954A1 (en) * 2010-11-25 2012-05-31 Denso Corporation Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090083353A (ko) * 2006-11-03 2009-08-03 크리 인코포레이티드 정류 접합 션트들을 포함하는 파워 스위칭 반도체 소자들
US20080217721A1 (en) * 2007-03-09 2008-09-11 Hamerski Roman J High efficiency rectifier
KR20120028272A (ko) * 2010-09-13 2012-03-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 파워 다이오드 및 정류기
US20120132954A1 (en) * 2010-11-25 2012-05-31 Denso Corporation Semiconductor device

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