WO2014168430A1 - Procédé de fabrication de circuit redresseur - Google Patents

Procédé de fabrication de circuit redresseur Download PDF

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Publication number
WO2014168430A1
WO2014168430A1 PCT/KR2014/003115 KR2014003115W WO2014168430A1 WO 2014168430 A1 WO2014168430 A1 WO 2014168430A1 KR 2014003115 W KR2014003115 W KR 2014003115W WO 2014168430 A1 WO2014168430 A1 WO 2014168430A1
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WIPO (PCT)
Prior art keywords
ion implantation
forming
substrate
rectifier circuit
layer
Prior art date
Application number
PCT/KR2014/003115
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English (en)
Korean (ko)
Inventor
김덕수
Original Assignee
주식회사 실리콘웍스
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Priority claimed from KR20130039534A external-priority patent/KR20140123142A/ko
Application filed by 주식회사 실리콘웍스 filed Critical 주식회사 실리콘웍스
Publication of WO2014168430A1 publication Critical patent/WO2014168430A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Definitions

  • the present invention relates to rectifier circuits, and more particularly, to a method of manufacturing a rectifier circuit having low forward voltage, low leakage current and fast reverse recovery characteristics.
  • a power semiconductor is a high voltage or high current semiconductor device that is optimized for power conversion or power control.
  • the power rectifier circuit has a function of converting alternating current electricity into direct current required by electronic products.
  • Such power rectifying circuits are essential semiconductor devices required to power all the electric devices such as mobile devices, computer parts, communication devices, display devices, automotive parts, and industrial devices including motors, or to stably supply desired voltages and currents.
  • Typical power rectifier circuits include PIN (or PN) rectifier circuits and Schottky rectifier circuits.
  • the PIN rectifier circuit uses a PN junction, the reverse leakage current is excellent, and the barrier metal is not used, so the reliability of the high temperature operation is good.
  • the PIN rectifier circuit has a large forward voltage drop (VF), and a large switching time due to a slow reverse recovery time due to minority carriers.
  • the Schottky rectifier circuit is a rectifier device that uses a work function difference between the barrier metal and silicon.
  • the forward voltage drop is small and the switching time is fast.
  • the Schottky rectifier circuit is disadvantageous for high temperature operation because of a large leakage current at off-state and a large leakage current at high temperature due to the use of a barrier metal.
  • MOS Metal Oxide Semiconductor
  • MOS-controlled rectifier circuits are stable for low leakage current and high temperature operation, and have lower forward voltage drop (V F ), higher temperature operating stability, and faster switching than Schottky rectifier circuits.
  • the MOS control rectifier circuit having the above characteristics is required to present a manufacturing method capable of securing process stability while reducing process cost.
  • the channel of the MOS control rectifier circuit is generally formed by a process using oxide isotropic etching or pedestal.
  • the etching time for forming the channel must be accurately controlled. The accuracy of the adjustment of the etching time affects the yield.
  • the manufacturing method of the conventional MOS control rectifier circuit is complicated to form a channel and it is difficult to accurately control the etching process for forming the channel. Therefore, the manufacturing method of the conventional MOS control rectifier circuit has a limitation in improving the yield.
  • a conventional method of manufacturing a MOS controlled rectifier circuit includes an oxide film deposition process and a wet etching process for channel formation. Therefore, the manufacturing method of the conventional MOS control rectifier circuit has a limitation in reducing the manufacturing cost due to the cost of the oxide film deposition process and the wet etching process.
  • a rectifier circuit generally manufactured by a semiconductor process needs to provide a manufacturing method capable of securing process stability while reducing process costs. Therefore, the process of manufacturing the rectifier circuit needs to be performed simply and stably.
  • the method of manufacturing the rectifier circuit is complicated, and thus, it is difficult to control the process accurately, and many instability factors occur in the process. As a result, productivity is lowered and yield is lowered. In addition, there is a limit in reducing the manufacturing cost by increasing the cost required by the complex process.
  • An object of the present invention is to provide a method of manufacturing a rectifier circuit that can simplify the manufacturing process and improve the yield by improving the process of forming the channel.
  • an object of the present invention is to provide a method of manufacturing a rectifying circuit that can improve the yield and reduce the manufacturing cost by precisely controlling the formation of the channel using the tilt ion implantation.
  • Another object of the present invention is to provide a method of manufacturing a rectifier circuit having low forward voltage, low leakage current, and fast reverse recovery using a MOS structure.
  • Another object of the present invention is to provide a method of manufacturing a rectifier circuit that can simplify the manufacturing process, improve the yield, and lower the manufacturing cost by improving the process of forming the guard ring, the active region and the channel. .
  • another object of the present invention is to provide a method of manufacturing a rectifier circuit, which can improve the yield and reduce the cost, since the process can be stabilized and simplified while the channel length is uniformly formed.
  • the method of manufacturing the rectifier circuit of the present invention includes the steps of forming gate layers on an active region of a substrate; Performing a first ion implantation to form a channel in the substrate including an edge of the gate layers; Performing a second ion implantation to form bodies that confine the channel below an edge of the gate layers; Forming an anode electrically connecting the gate layer and the body; And forming a cathode on a rear surface of the substrate.
  • the method of manufacturing the rectifier circuit of the present invention includes: forming a guard ring for defining a region in which an MOS rectification control circuit is to be formed as an active region; Opening the active region; Forming a plurality of gate layers on the active region; Performing tilt ion implantation using the plurality of gate layers as a mask to form channels in a region including the substrate corresponding to an edge of the gate layer; Forming a body in the substrate between the gate layers to electrically separate the channel corresponding to the adjacent gate layer; And electrically connecting the body and the gate layer by forming a metal layer on the body and the gate layer.
  • the present invention can solve the complexity of the process and the difficulty of precise control of the process that may occur in the process using the oxide isotropic etching or pedestal used to form a channel in the rectifier circuit, in particular the MOS control rectifier circuit. have.
  • the present invention can simplify the manufacturing process and improve the yield by improving the process of forming the channel of the rectifier circuit.
  • the present invention has the effect of improving the yield and reduce the manufacturing cost by precisely controlling the formation of the channel of the rectifier circuit using the tilt ion implantation.
  • the present invention has the effect of realizing a rectifier circuit having a low forward voltage, low leakage current and fast reverse recovery characteristics while having a MOS structure.
  • the present invention has an effect that can realize a rectifier circuit having a diode characteristic by having the MOS structure and the gate and the source are electrically connected in common.
  • the rectifier circuit of the present invention can reduce the number of processes for forming the guide ring to simplify the manufacturing process, thereby increasing the yield and the manufacturing cost can be reduced.
  • FIG. 1 is a cross-sectional view showing a preferred embodiment of the rectifier circuit of the present invention.
  • FIG. 2 is an equivalent circuit diagram of the embodiment of FIG.
  • FIG. 3 is a cross-sectional view illustrating a current path of the embodiment of FIG. 1.
  • 4 to 11 are process charts illustrating the manufacturing method of the embodiment of FIG. 1.
  • FIG. 12 is a cross-sectional view showing another embodiment of the rectifier circuit of the present invention.
  • FIG. 13 is a cross-sectional view illustrating the current path in the embodiment of FIG. 12.
  • 14 to 23 are process diagrams illustrating a method of manufacturing the semiconductor rectifier device shown in FIG. 12.
  • An embodiment of the rectifier circuit of the present invention is configured to have a MOS structure as shown in FIG.
  • An embodiment of the present invention will be described by exemplifying a MOS controlled rectifying circuit, hereinafter, referred to as a MOS controlled rectifying circuit.
  • the rectifier circuit of FIG. 1 includes a substrate 10 including an N Type Epitaxial (N-EPI) layer.
  • N-EPI N Type Epitaxial
  • the guard ring 14 formed using the oxide film 12, the channels 22 formed by the tilt ion implantation, and the bodies 24 formed by the front ion implantation are formed on the substrate 10.
  • the guard ring 14 is formed to secure a breakdown voltage, separate an element, or block an electrical path from the outside.
  • the bodies 24 may be formed of a well implanted with P-type impurities, and are configured to reduce leakage current and secure breakdown voltage.
  • the bodies 24 have a function of electrically separating between the channels 22 formed under the edge of each gate layer 20.
  • the channels 22 are for forming a current path, and may be formed by ion implantation of P-type impurities, and supply charge through the gate poly 18 and the gate oxide 16 during the rectifying operation. Channel characteristics may be inverted to an N-type by a field effect.
  • gate layers 20 are formed on the substrate 10.
  • the gate layers 20 have a structure in which the gate oxide 16 and the gate poly 18 are sequentially stacked.
  • the channels 22 are formed on the substrate 10 at the lower edge of the gate layers 20, and the bodies 24 are formed in contact with the channels 22.
  • the body 24 is formed in the substrate 10 in the open area between the adjacent gate layers 20, and the channels 22 of the adjacent gate layers 20 are electrically separated by the body 24. .
  • the gate layer 20 and the body 24 are electrically connected by an upper layer, which may serve as an anode in an embodiment of the present invention.
  • the upper layer may include a barrier metal 26 formed by depositing a conductive metal on a region including the gate layer 20 and the body 24, and an electrode layer 28 formed by depositing aluminum. have.
  • the barrier metal 26 and the electrode layer 28 may act as an anode electrode by having a pattern by an etching process described later.
  • a back metal layer 30 is formed under the substrate 10, and the back metal layer 30 acts as an N-sub to the substrate 10.
  • the back metal layer 30 may serve as a drain of the MOS while serving as a cathode in an embodiment of the present invention.
  • the rectifier circuit implemented as shown in FIG. 1 may be represented as an equivalent circuit as shown in FIG. 2 and has a characteristic of acting as a diode.
  • the body 24 serves as a source
  • the gate layer 20 serves as a gate channel
  • the substrate 10 and the back metal layer 40 as compared to FIG. 2.
  • the gate channel and the source are anodeed by electrically connecting the body 24 and the gate layer 20 connected to the channel 22 by the barrier metal 26 and the electrode layer 28.
  • diodes act as drains and cathodes.
  • the rectifier circuit of the embodiment of the present invention may perform the operation of rectifying the current in the path as shown by the arrow of FIG. 3 due to the characteristics of the diode as shown in FIG. 2.
  • FIG. 1 may be manufactured by the process of FIGS. 4 to 11.
  • a method of manufacturing the rectifier circuit as shown in FIG. 1 will be described with reference to FIGS. 4 through 11.
  • the rectifier circuit of the embodiment of FIG. 1 is configured as a MOS control rectifier circuit.
  • a substrate 10 including an N-type epitaxial layer may be used.
  • the guard ring 14 is formed on the substrate 10 to form a rectifier circuit.
  • a mask (1st mask, not shown) is used to form the guard ring 14.
  • the oxide film 12 is formed on the substrate 10, and the region where the guard ring 14 is to be formed in the oxide film 12 is opened by an etching process using a mask (1st mask).
  • a mask (1st mask) In the etching process using a mask (1st mask), a general photolithography process may be used, and thus a detailed description thereof will be omitted.
  • the guard ring 14 as shown in FIG. 4 is formed in the region where the oxide film 12 is opened. Is formed.
  • the impurity is preferably a P-type impurity in consideration of the fact that the substrate 10 is an N-type epitaxial layer.
  • the active region is opened as shown in FIG. 5.
  • the active region may be opened by an etching process using a mask (2nd mask, not shown).
  • a mask (2nd mask) In the etching process using a mask (2nd mask), a general photolithography process may be used, and thus a detailed description thereof will be omitted.
  • gate layers 20 are formed in an active region in which the guard ring 14 is not formed.
  • the gate layers 20 are sequentially subjected to an oxidation process for forming the gate oxide 16, a deposition process for forming the gate poly 18, and an etching process using a mask (3rd mask, not shown). It can be formed by.
  • the deposition of the gate poly 18 is preferably performed by chemical vacuum deposition (CVD).
  • the gate poly 18 refers to a conductive thin film deposited with a polysilicon material, and may be formed to have a thickness of 3000 to 6000.
  • the thickness of the gate oxide 20 may be variously determined by the manufacturer to determine the electrical characteristics of the channel.
  • an open region is formed between the gate layers 20.
  • the open regions between the gate layers 20 are formed by an etching process using a mask (3rd mask), and a general photolithography process using a mask (3rd mask) may be used, so a detailed description thereof is omitted. do.
  • the tilt ion implantation of FIG. 7 may be performed using P-type impurities, and the angle, amount, and energy into which the P-type impurities are implanted may be formed in the channel 22 to be formed in the substrate 10 under the edge of the gate layers 20. Can be determined in consideration of the width and depth of the
  • the P-type impurity may be implanted into the substrate 10 in the open region where the gate layers 20 are not formed, as shown in FIG. 7.
  • the P-type impurity may be injected into the substrate 10 under the edge of the gate layers 20 by being inclined.
  • the channel 22 may be temporarily formed on the guard ring 14 by tilt ion implantation.
  • the channel 22 may be formed on the substrate 10 in the open region where the gate layers 20 are not formed, as well as on the substrate 10 below the edge of the gate layers 20. have.
  • the tilt ion implantation is easy to control the angle, amount and energy to form the channel. That is, an advantage may be provided that the channel 22 can be formed to a desired width and depth. Thus, embodiments of the present invention have the advantage of being able to easily control the process of forming channels 22.
  • front ion implantation means implantation of ions substantially perpendicular to the substrate 10.
  • Front ion implantation may also be performed using the gate layers 20 as a mask.
  • the front surface ion implantation for forming the body 24 may use P-type impurities.
  • Body 24 means a conventional well, and is formed to have a larger amount of dose than channel 22 to prevent reverse bias, and the depth of channel 22 to reduce leakage current and to ensure breakdown voltage. It is preferably formed to have the same or deeper depth.
  • the upper region of the guard ring 14 in which the channel 22 is temporarily formed in the tilt ion implantation can be restored, and the channels under the edges of the adjacent gate layers 20 ( 22 is separated by the body 24.
  • drive-in may be performed to effectively form the body 24 after the above-described front ion implantation.
  • the gate layer 20 and the body 24 may be electrically connected by the upper layer to act as an anode electrode.
  • the upper layer may include a barrier metal 26 formed by deposition of a conductive metal as shown in FIG. 9 and an electrode layer 28 formed by depositing aluminum as shown in FIG. 10.
  • FIG. 10 illustrates an anode electrode formed by etching the barrier metal 26 and the electrode layer 28 by an etching process using a mask (a 4th mask, not shown).
  • a back metal layer 30 may be formed on the lower portion of the substrate 10 as shown in FIG. 11 by deposition.
  • the material of the back metal layer 30 is preferably selected to be able to act as an N-sub (N-sub) with respect to the substrate 10.
  • FIG. 12 an embodiment of the present invention may be configured as shown in FIG. 12.
  • the same function components are denoted by the same reference numerals as in FIG. 1.
  • the rectifier circuit includes a substrate 10, a guard ring 14, channels 22, bodies 24, gate layers 20, an electrode layer 28, and a back metal layer ( 30).
  • a substrate 10 a guard ring 14
  • channels 22 bodies 24, gate layers 20, an electrode layer 28, and a back metal layer ( 30).
  • the substrate 10 has a structure in which a low concentration N-type (N ⁇ ) epitaxial layer (9 in FIG. 14) is formed on a high concentration N-type (N + ) semiconductor plate (8 in FIG. 14).
  • the active region is a region forming the rectifier circuit and may be defined by the guard ring 14.
  • the guard ring 14 is to separate the active region from the non-active region of the outer portion, and an oxide film 12 is formed on the substrate 10 of the non-active region.
  • channels 22 formed by tilt ion implantation and bodies 24 formed by front ion implantation are formed.
  • the gate layers 20 are formed to cover the top of the substrate 10 between the channels 22.
  • the gate layers 20 have a structure in which the gate poly 18 is stacked on the gate oxide 16 formed on the substrate 10.
  • the gate layer 20 and the bodies 24 are electrically connected to each other by an electrode layer 28 contacting the upper portion.
  • a conductive back metal layer 30 is formed under the substrate 10, and the back metal layer 30 acts as an N-sub to the N-type epitaxial layer 9. .
  • the bodies 24 serve as a source
  • the gate layer 20 serves as a gate
  • the substrate 10 and the back metal layer 30 serve as drains, compared to FIG. 2.
  • MOS structure in addition, in the rectifying circuit of FIG. 12, the gates and the sources electrically connected to each other are connected to the anodes by the bodies 24 and the gate layers 20 connected to the channels 22 by the electrode layer 28. And the diode acts as a cathode.
  • the rectifier circuit of FIG. 12 may perform an operation of rectifying a current in the path shown by the arrow of FIG. 13 due to the characteristics of the diode as shown in FIG. 2.
  • the rectifier circuit of FIG. 12 may be manufactured by the process of FIGS. 14 to 23. Hereinafter, a method of manufacturing the rectifier circuit will be described with reference to FIGS. 14 to 23.
  • an oxide film 12 is formed on the entire surface of the substrate 10.
  • the substrate 10 preferably has a structure in which a low concentration N-type (N ⁇ ) epitaxial layer 9 is formed on the high concentration N-type (N + ) semiconductor plate 8.
  • the oxide film 12 is formed on the epitaxial layer 9.
  • the guard ring region and the active region of the substrate 10 are opened. That is, the oxide film 12 formed in the guard ring region in which the guard ring 14 is to be formed and the active region in which the rectifier circuit is to be formed is removed from the oxide film 12 formed on the substrate 10.
  • a photoresist layer (not shown) is formed on the oxide film 12 by using a mask (1st mask, not shown), The photoresist layer is patterned.
  • the patterning process specifically includes sequentially performing an exposure process and a developing process using a mask (1st mask) having a specific pattern.
  • the patterning process may include removing the photoresist layer after etching the oxide film 12 to have a specific pattern by using the photoresist layer remaining to have a specific pattern after the exposure process and the etching process. As a result, as shown in FIG. 15, the oxide film 12 formed in the guard ring region and the active region is removed, and the oxide film 12 remains on the outer side of the rectifier circuit.
  • a photoresist layer 41 for forming the guard ring 14 is formed.
  • the guard ring 14 is formed in a region where the photoresist layer 41 is opened.
  • a photoresist layer 41 is formed on the substrate 10 shown in FIG. 15, and the photoresist is formed using a mask (2nd mask, not shown).
  • the resist layer 41 is patterned. That is, as shown in FIG. 16, the photoresist layer 41 has a pattern in which the active region and the oxide film 12 are covered and the guard ring region is open. Therefore, the photoresist layer 41 is used as a mask to implant ion boron as a P-type impurity. As a result, impurities are ion implanted only in the guard ring region, and ion implantation of impurities is blocked by the photoresist layer 41 in other regions.
  • the photoresist layer 41 on the substrate 10 is removed.
  • the guard ring 14 is formed in the guard ring region as shown in FIG. 17, and the active region is opened.
  • the oxide ring etching process may be performed only once in the guard ring 14, and as a result, the process of forming the guard ring may be simplified.
  • the gate layer 20 is formed. Referring to FIG. 18, gate layers 20 are formed in an active region.
  • the gate layer 20 is sequentially formed by an oxidation process for forming the gate oxide 16, a deposition process for forming the gate poly 18, and an etching process using a photoresist layer as a mask. Can be formed.
  • the gate layer 20 is formed by forming a gate oxide 16 and a gate poly 18 on the substrate 10 and then exposing and developing a mask (3rd mask, not shown) and a photoresist layer (not shown). And it may be formed to have a desired pattern by an etching process.
  • open regions are formed between the etched gate layers 20 as shown in FIG. 18.
  • An open region between the gate layers 20 may be formed by an etching process using a photoresist layer as a mask, and a general photo etching process using a mask (3rd mask) may be used. Is omitted.
  • tilted ion implantation using a P-type impurity, for example, boron is performed on the substrate 10 to form channels 22.
  • the gate layers 20, the oxide film 12, and the photoresist layer may be used as a mask.
  • the photoresist layer 42 means that the ones for forming the gate layers 20 are left, and may be removed after the gate layers 20 are formed. After the tilt ion implantation is completed, the photoresist layer may be removed.
  • P-type impurities may be implanted into the open region where the gate layers 20 are not formed and the substrate 10 below the edge of the gate layers 20. That is, as shown in FIG. 19, the P-type impurity is inclined to the substrate 10 by tilt ion implantation, so that the P-type impurity may be implanted under the edges of the gate layers 20. As described above, the channels 22 may be formed in the region where the P-type impurity is tilted.
  • front surface ion implantation of P-type impurities is performed on the substrate 10 to form the bodies 24.
  • the bodies 24 are formed in the open area of the active area.
  • the complexity of the process and the difficulty of precisely controlling the process may occur in a process using conventional oxide isotropic etching or pedestal to form the channels 22 under the gate layers 20.
  • the present invention can be solved by using a tilt ion implantation method.
  • the bodies 24 are formed in the open active region of the substrate 10 by the front ion implantation of FIG. 21. That is, the bodies 24 are formed in the open region between the gate layer 20 and the guard ring 14 and between the gate layers 20. Accordingly, the channels 22 formed in the active region of the substrate 10 are reduced by the bodies 24 and remain below the edge of the gate layer 20.
  • the body 24 refers to a conventional P region or P well, and is formed to have a larger amount of dose than the channel 22 to prevent reverse bias. It is preferably formed to have a depth equal to or deeper than the depth of channel 22 to reduce leakage current and ensure breakdown voltage.
  • the channels 22 of the adjacent gate layers 20 are separated by the bodies 24.
  • the drive-in may be performed to effectively form the bodies 24 of FIG. 22. And, an annealing process may be performed to stabilize the structure of FIG. 22.
  • an electrode layer 28 for an anode electrode is formed on the gate layer 20 and the bodies 24.
  • the electrode layer 28 may be made of a conductive metal, such as aluminum metal. That is, the electrode layer 28 is formed by depositing aluminum metal on the substrate 10 and patterning the deposited aluminum metal to have a pattern as shown in FIG. 23.
  • a barrier metal may be formed between the electrode layer 28 and the substrate 10, and between the electrode layer 28 and the gate layer 20. In this case, the barrier metal may form ohmic contacts, control spike generation by the aluminum metal, and may be used as a diffusion barrier.
  • a conductive back metal layer 30 may be formed under the substrate 10 by deposition.
  • embodiments of the present invention can be configured, and a process using conventional oxide isotropic etching or pedestal to form the channels 22 in the rectifying circuit according to the embodiments of the present invention.
  • the complexity of the process, the difficulty of precise control of the process can be eliminated.
  • embodiments of the present invention can improve the process of forming the channels 22 by forming the channels 22 by using the tilt ion implantation, thereby simplifying the manufacturing process of the rectifier circuit and yield Increases.
  • the tilt ion implantation when used, there is an advantage that the process can be accurately controlled. Therefore, the formation of the channels 22 of the rectifying circuit according to the present invention is precisely controlled, so that the yield is high and the manufacturing cost is reduced.
  • the embodiments of the present invention reduce the number of processes for forming the guard ring 14 of the rectifier circuit so that the yield is high and the manufacturing cost is reduced.
  • the present invention can implement a rectifier circuit having a low forward voltage, low leakage current and fast reverse recovery characteristics while having a MOS structure.
  • the present invention can implement a rectifier circuit having a diode characteristic by having the MOS structure and the gate and the source are electrically connected in common.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Cette invention concerne un procédé de fabrication d'un circuit redresseur. Ledit circuit redresseur fabriqué par le procédé selon l'invention présente une tension directe réduite, un courant de fuite réduite et un temps de recouvrement inverse réduit. De plus, ledit procédé de fabrication est simplifié grâce à un procédé amélioré de formation de canal et il assure l'amélioration du rendement. Enfin, le procédé de fabrication de circuit redresseur selon l'invention assure la commande précise de la formation d'un canal.
PCT/KR2014/003115 2013-04-10 2014-04-10 Procédé de fabrication de circuit redresseur WO2014168430A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2013-0039534 2013-04-10
KR20130039534A KR20140123142A (ko) 2013-04-10 2013-04-10 모스 제어 정류 회로 및 그의 제조 방법
KR20130114527 2013-09-26
KR10-2013-0114527 2013-09-26

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WO2014168430A1 true WO2014168430A1 (fr) 2014-10-16

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070102725A1 (en) * 2002-11-14 2007-05-10 Stmicroelectronics, S.R.L. Insulated gate planar integrated power device with co-integrated Schottky diode and process
US20080217721A1 (en) * 2007-03-09 2008-09-11 Hamerski Roman J High efficiency rectifier
KR20100057185A (ko) * 2008-11-21 2010-05-31 주식회사 동부하이텍 반도체 소자 및 그 제조 방법
US20110278642A1 (en) * 2010-05-13 2011-11-17 Great Power Semiconductor Corp. Power semiconductor structure with field effect rectifier and fabrication method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070102725A1 (en) * 2002-11-14 2007-05-10 Stmicroelectronics, S.R.L. Insulated gate planar integrated power device with co-integrated Schottky diode and process
US20080217721A1 (en) * 2007-03-09 2008-09-11 Hamerski Roman J High efficiency rectifier
KR20100057185A (ko) * 2008-11-21 2010-05-31 주식회사 동부하이텍 반도체 소자 및 그 제조 방법
US20110278642A1 (en) * 2010-05-13 2011-11-17 Great Power Semiconductor Corp. Power semiconductor structure with field effect rectifier and fabrication method thereof

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