WO2015032341A1 - 写操作方法及装置 - Google Patents

写操作方法及装置 Download PDF

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Publication number
WO2015032341A1
WO2015032341A1 PCT/CN2014/085962 CN2014085962W WO2015032341A1 WO 2015032341 A1 WO2015032341 A1 WO 2015032341A1 CN 2014085962 W CN2014085962 W CN 2014085962W WO 2015032341 A1 WO2015032341 A1 WO 2015032341A1
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Prior art keywords
bit
writing
bits
difference
difference bit
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PCT/CN2014/085962
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English (en)
French (fr)
Inventor
徐荣刚
徐君
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华为技术有限公司
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Publication of WO2015032341A1 publication Critical patent/WO2015032341A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0061—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7202—Allocation control and policies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0076—Write operation performed depending on read result

Definitions

  • Embodiments of the present invention relate to the field of communications technologies, and, more particularly, to a write operation method and apparatus.
  • an encoding process is added, and the number of 0s and 1s in the data to be written is compared, and it is determined whether the data to be written is inverted and then written to the storage information, correspondingly
  • the written data is inverted and read. For example, if the time for writing bit 1 is greater than the time for writing bit 0 and the number of 1s in the data to be written is greater than 0, the data to be written is inverted and written.
  • determining the write operation scheme only from 0 and 1 in the data to be written has certain limitations.
  • a PCM (Phase Change Memory) memory chip as an example, since the instantaneous current of write bit 0 is large and the instantaneous current of write bit 1 is small, the write operation is divided into two stages (write bit 0 stage and write bit 1 stage). In the process, there can be more bits concurrently writing bit 1 while writing bit 1 stage. Thus, judging only from the number of write bit 0 and write bit 1 does not effectively improve the efficiency of the write operation.
  • Embodiments of the present invention provide a write operation method and apparatus, which effectively improve the efficiency of a write operation.
  • a write operation method comprising: determining a first difference bit to be written according to the first data and the original data corresponding to the address to be written, and according to the second data and the address to be written Corresponding original data determines a second difference bit to be written, wherein the second data is a negation of the first data; determining a delay of writing the first difference bit and writing the second difference respectively a delay of the bit; if the delay of writing the first difference bit is greater than the delay of writing the second difference bit, writing the second difference bit to the memory chip if the second is written The delay of the difference bit is greater than the delay of writing the first difference bit, and the first difference bit is written to the memory chip.
  • the determining, by the delay of writing the first difference bit, and the delay of writing the second difference bit, respectively include:
  • the write location is determined The delay of the second difference bit is described.
  • the according to the number of writeable bits in parallel, the time of writing bit 0, and the write bit 1 Time, and the number of bits 0 and the number of bits 1 in the first difference bit determining the delay of writing the first difference bit, including: according to the number of writeable 1 in parallel, writing bit 0 Determining the delay of writing the first difference bit by time and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the first difference bit;
  • Determining the writing of the second according to the number of writeable bits in parallel, the time of writing bit 0 and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the second difference bit includes: determining the time according to the number of writes 1 in parallel, the time of writing bit 0 and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the second difference bit The delay of writing the second difference bit.
  • the determined delay of writing the first difference bit is T 1 :
  • the determined delay of writing the second difference bit is T 2 :
  • N 10 represents the number of bits 0 in the first difference bit
  • N 11 represents the number of bits 1 in the first difference bit
  • N 20 represents the number of bits 0 in the second difference bit
  • N 21 represents The number of bits 1 in the second difference bit
  • a 1 represents the number of writes 1 in parallel
  • t 0 represents the time at which bit 0 is written
  • t 1 represents the time at which bit 1 is written, and Indicates rounding up.
  • the memory chip is a phase change PCM memory chip.
  • the according to the number of writeable bits in parallel, the time of writing bit 0, and the write bit 1 Time, and the number of bits 0 and the number of bits 1 in the first difference bit determining the delay of writing the first difference bit, including: writing the bit 0 according to the number of 0s that can be written in parallel Determining the delay of writing the first difference bit by time and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the first difference bit;
  • Determining the writing of the second according to the number of writeable bits in parallel, the time of writing bit 0 and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the second difference bit includes: determining the time according to the number of writes 0 in parallel, the time of writing bit 0 and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the second difference bit The delay of writing the second difference bit.
  • the determined delay of writing the first difference bit is T 1 :
  • the determined delay of writing the second difference bit is T 2 :
  • N 10 represents the number of bits 0 in the first difference bit
  • N 11 represents the number of bits 1 in the first difference bit
  • N 20 represents the number of bits 0 in the second difference bit
  • N 21 represents The number of bits 1 in the second difference bit
  • a 0 represents the number of writes 1 in parallel
  • t 0 represents the time at which bit 0 is written
  • t 1 represents the time at which bit 1 is written, and Indicates rounding up.
  • the according to the number of writeable bits in parallel, the time of writing bit 0, and the write bit 1 determine the delay of writing the first difference bit, including: according to the number of parallel writeable 0s and parallel writes Determining the delay of writing the first difference bit, the number of 1, the time of writing bit 0, and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the first difference bit;
  • the delay of the difference bit includes: according to the number of parallel writeable 0s and the number of writes 1 in parallel, the time of writing bit 0 and the time of writing bit 1, and the number of bits 0 in the second difference bit
  • the number of bits 1 determines the delay in writing the second difference bit.
  • the determined delay of writing the first difference bit is T 1 :
  • the determined delay of writing the second difference bit is T 2 :
  • N 10 represents the number of bits 0 in the first difference bit
  • N 11 represents the number of bits 1 in the first difference bit
  • N 20 represents the number of bits 0 in the second difference bit
  • N 21 represents The number of bits 1 in the second difference bit
  • a 0 represents the number of writes 1 in parallel
  • a 1 represents the number of 0s that can be written in parallel
  • t 0 represents the time at which bit 0 is written
  • t 1 represents the bit 1 Time, and Indicates rounding up.
  • a write operation apparatus comprising: a determining unit, configured to determine a first difference bit to be written according to the first data and the original data corresponding to the address to be written, according to the second data and the The original data corresponding to the address to be written determines a second difference bit to be written, wherein the second data is an inverse of the first data, and respectively determines the first difference bit determined by the determining unit Delay of writing and writing the delay of the second difference bit determined by the determining unit; writing unit, if the determining unit determines that the delay of writing the first difference bit is greater than writing the first Transmitting the second difference bit to the memory chip, if the determining unit determines that the delay of writing the second difference bit is greater than the delay of writing the first difference bit And writing the first difference bit to the memory chip.
  • the determining unit is specifically configured to: according to the number of writeable bits in parallel, the time of writing bit 0, and the time of writing bit 1, and the foregoing Determining the delay of writing the first difference bit, and writing the time of bit 0 and the time of writing bit 1 according to the number of bits that can be written in parallel, the number of bits 0 and the number of bits 1 in a difference bit And the number of bits 0 and the number of bits 1 in the second difference bit determine a delay of writing the second difference bit.
  • the determining unit is specifically configured to: according to the number of writeable 1 in parallel, write bit 0 Time and time to write bit 1, and the number and ratio of bits 0 in the first difference bit a number of bits 1, determining a delay of writing the first difference bit, and writing a bit 0 time and a time writing bit 1 according to the number of writes 1 in parallel, and the second difference bit The number of bits 0 and the number of bits 1 determine the delay in writing the second difference bit.
  • the determining, by the determining unit, the delay of writing the first difference bit is T 1 :
  • the delay of writing the second difference bit determined by the determining unit is T 2 :
  • N 10 represents the number of bits 0 in the first difference bit
  • N 11 represents the number of bits 1 in the first difference bit
  • N 20 represents the number of bits 0 in the second difference bit
  • N 21 represents The number of bits 1 in the second difference bit
  • a 1 represents the number of writes 1 in parallel
  • t 0 represents the time at which bit 0 is written
  • t 1 represents the time at which bit 1 is written, and Indicates rounding up.
  • the memory chip is a phase change PCM memory chip.
  • the determining unit is specifically configured to: according to the number of 0s that can be written in parallel, write bit 0 Time and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the first difference bit, determining the delay of writing the first difference bit, and according to the number of 0s that can be written in parallel
  • the time at which bit 0 is written and the time at which bit 1 is written, and the number of bits 0 and the number of bits 1 in the second difference bit determine the delay in writing the second difference bit.
  • the determining, by the determining unit, the delay of writing the first difference bit is T 1 :
  • the delay of writing the second difference bit determined by the determining unit is T 2 :
  • N 10 represents the number of bits 0 in the first difference bit
  • N 11 represents the number of bits 1 in the first difference bit
  • N 20 represents the number of bits 0 in the second difference bit
  • N 21 represents The number of bits 1 in the second difference bit
  • a 0 represents the number of writes 1 in parallel
  • t 0 represents the time at which bit 0 is written
  • t 1 represents the time at which bit 1 is written, and Indicates rounding up.
  • the determining unit is specifically configured to: write parallel according to the number of parallel writeable 0s Determining the delay of writing the first difference bit, the number of 1, the time of writing bit 0, and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the first difference bit, and determining the delay of writing the first difference bit, and Determining the number according to the number of parallel writes 0 and the number of writes 1 in parallel, the time of writing bit 0, and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the second difference bit. The delay of writing the second difference bit.
  • the determining, by the determining unit, the delay of writing the first difference bit is T 1 :
  • the delay of writing the second difference bit determined by the determining unit is T 2 :
  • N 10 represents the number of bits 0 in the first difference bit
  • N 11 represents the number of bits 1 in the first difference bit
  • N 20 represents the number of bits 0 in the second difference bit
  • N 21 represents The number of bits 1 in the second difference bit
  • a 0 represents the number of writes 1 in parallel
  • a 1 represents the number of 0s that can be written in parallel
  • t 0 represents the time at which bit 0 is written
  • t 1 represents the bit 1 Time, and Indicates rounding up.
  • the writing unit is further configured to: if the delay of the second difference bit determined by the determining unit is equal to a delay of the first difference bit, then the first difference bit Writing to the memory chip or writing the second difference bit to the memory chip.
  • the embodiment of the present invention determines a first difference bit according to the first data and the original data corresponding to the to-be-written address, and determines a second difference bit according to the second data and the original data corresponding to the to-be-written address, where the second data is the first The inversion of the data.
  • FIG. 1 is a flow chart of a write operation method in accordance with an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a PCM memory chip in accordance with one embodiment of the present invention.
  • FIG. 3 is a schematic flow chart of a process of a write operation method according to an embodiment of the present invention.
  • FIG. 4 is a block diagram showing the structure of a write operation device according to an embodiment of the present invention.
  • Fig. 5 is a block diagram showing the structure of a write operation device according to another embodiment of the present invention.
  • FIG. 1 is a flow chart of a write operation method in accordance with an embodiment of the present invention.
  • the method of Figure 1 is written by A device (such as a memory chip) is executed.
  • the first data may be compared with the original data to obtain a bit different from the original data in the first data, that is, the first difference bit, and the second data is compared with the original data to obtain the first data.
  • the bit in the second data that is different from the original data that is, the second difference bit.
  • the delay in writing the first difference bit refers to the time it takes to write the first difference bit to the address to be written.
  • the delay in writing the second difference bit refers to the time it takes to write the second difference bit to the address to be written.
  • the first difference bit may be one or more bits
  • the second difference bit may be one or more bits.
  • the delay of writing the first difference bit is greater than the delay of writing the second difference bit, writing the second difference bit to the memory chip, if the delay of writing the second difference bit is greater than writing the first difference
  • the delay of the bit writes the first difference bit to the memory chip.
  • the difference bits in which the write delay is small in the first difference bit and the second difference bit can be selected to be written in the memory chip.
  • the embodiment of the present invention determines a first difference bit according to the first data and the original data corresponding to the to-be-written address, and determines a second difference bit according to the second data and the original data corresponding to the to-be-written address, where the second data is the first The inversion of the data.
  • the memory chip may be a PCM (Phase Change Memory) memory chip, or may be a memory chip of other materials, such as DRAM (Dynamic Random Access Memory). It should be understood that The material of the memory chip is not limited in the embodiment of the invention.
  • the number of bits that can be written in parallel can be written. Determining the delay of writing the first difference bit, and writing in parallel according to the time of bit 0 and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the first difference bit The number of bits, the time at which bit 0 is written, and the time at which bit 1 is written, and the number of bits 0 and the number of bits 1 in the second difference bit determine the delay in writing the second difference bit.
  • the time at which bit 0 is written refers to the time it takes to write each bit 0, and the time at which bit 1 is written refers to the time it takes to write each bit 1.
  • the memory chip is PCM
  • the number of the total current of the memory chip does not exceed the maximum current as long as a plurality of bits are transmitted in parallel.
  • the number of writeable 1s, the time of writing bit 0, and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the first difference bit may be used. Determining the delay of writing the first difference bit; and according to the number of writes 1 in parallel, the time of writing bit 0 and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the second difference bit, A delay is written to write the second difference bit.
  • the determined delay of writing the first difference bit is T 1 :
  • the determined delay for writing the second difference bit is T 2 :
  • N 10 represents the number of bits 0 in the first difference bit
  • N 11 represents the number of bits 1 in the first difference bit
  • N 20 represents the number of bits 0 in the second difference bit
  • N 21 represents the bit in the second difference bit
  • a 1 represents the number of writes 1 in parallel, for example, A 1 is an integer greater than or equal to 2
  • t 0 represents the time at which bit 0 is written
  • t 1 represents the time at which bit 1 is written
  • the memory chip is a PCM memory chip
  • the PCM memory chip since the PCM memory chip writes bits 0
  • the instantaneous current is large and the instantaneous current of writing bit 1 is small. Therefore, during the two-phase write operation (write bit 0 phase and write bit 1 phase), there may be more bits concurrently writing bit 1 during the write bit 1 phase. . Therefore, the above equations (1) and (2) can be employed to determine the delays for writing the first difference bit and the second difference bit, respectively.
  • the number of 0s that can be written in parallel, the time of writing bit 0, and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the first difference bit can be determined. Describe the delay of writing the first difference bit; and according to the number of 0s that can be written in parallel, the time of writing bit 0 and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the second difference bit are determined. The delay in writing the second difference bit.
  • the determined delay for writing the first difference bit is T 1 :
  • the determined delay for writing the second difference bit is T 2 :
  • N 10 represents the number of bits 0 in the first difference bit
  • N 11 represents the number of bits 1 in the first difference bit
  • N 20 represents the number of bits 0 in the second difference bit
  • N 21 represents the bit in the second difference bit
  • a 0 represents the number of writes 1 in parallel, for example, A 0 is an integer greater than or equal to 2
  • t 0 represents the time at which bit 0 is written
  • t 1 represents the time at which bit 1 is written, and Indicates rounding up.
  • the number of 0s that can be written in parallel, the number of 1s that can be written in parallel, the time of writing bit 0, and the time of writing bit 1 can be And determining the delay of writing the first difference bit by the number of bits 0 and the number of bits 1 in the first difference bit; and writing the number of 1 in parallel and writing the time of bit 0 according to the number of 0s that can be written in parallel And the time at which bit 1 is written, and the number of bits 0 and the number of bits 1 in the second difference bit, determine the delay in writing the second difference bit.
  • the determined delay of writing the first difference bit is T 1 :
  • the determined delay for writing the second difference bit is T 2 :
  • N 10 represents the number of bits 0 in the first difference bit
  • N 11 represents the number of bits 1 in the first difference bit
  • N 20 represents the number of bits 0 in the second difference bit
  • N 21 represents the bit in the second difference bit
  • a 0 represents the number of writes 1 in parallel
  • a 1 represents the number of 0s that can be written in parallel.
  • a 0 and A 1 are integers greater than or equal to 2
  • t 0 represents the time at which bit 0 is written.
  • t 1 represents the time at which bit 1 is written, and Indicates rounding up.
  • the first difference bit may be written to the memory chip or the second difference bit may be written to the memory chip.
  • This embodiment of the present invention is not limited thereto.
  • the PCM memory chip is taken as an example in conjunction with the schematic diagram of FIG. 2 and the flowchart of FIG. 3, and it should be understood that the embodiments of the present invention are not limited thereto.
  • the instantaneous current required to write bit 0 is large and the time is short.
  • the instantaneous current required to write bit 1 is small but long, and the current and time required for reading the pulse are higher than those of writing bit 0 and writing bit 1. less. Therefore, when writing the bit 1 stage, the manner of writing bit 1 concurrently can be employed.
  • the PCM memory chip includes a buffer, a pre-judgment circuit, a read/write control circuit, and a memory block.
  • the buffer area is used for registering the data written and read, the pre-judging circuit, and the pre-judging circuit is used for delay prediction of the difference bit to be written, which may specifically include determining A comparison circuit for writing difference bits and a delay determination circuit for determining a difference of the bit to be written, the read/write control circuit is for controlling the read and write operations of the memory block.
  • the PCM memory chip receives a read or write operation command from a CPU (Central Processing Unit) from the I/O interface to perform a read or write operation.
  • a CPU Central Processing Unit
  • Step 301 the pre-judging circuit (specifically, the comparing circuit) compares the first data registered in the buffer area with the original data corresponding to the address to be written to obtain a first difference bit, and inverts the first data registered in the buffer area to obtain The second data is compared with the original data corresponding to the address to be written to obtain a second difference bit.
  • the pre-judging circuit specifically, the comparing circuit
  • Step 302 the pre-judging circuit (specifically, the delay determining circuit) determines a delay for writing the first difference bit, and determines a delay for writing the second difference bit.
  • Step 303 the read/write control circuit writes the difference difference bit to be written to the memory block.
  • the read/write control circuit When T 1 is greater than T 2 , the read/write control circuit writes the second difference bit to the memory block; when T 1 is less than T 2 , the read/write control circuit writes the first difference bit into the memory block; when T 1 is equal to T 2 The read/write control circuit can write the first difference bit to the memory block or write the second difference bit to the memory block.
  • the difference difference bit to be written is written to the memory chip, thereby effectively improving data writing.
  • the efficiency of the operation is based on the above technical solution, by determining and comparing the delay of writing the first difference bit and the delay of writing the second difference bit, the difference difference bit to be written is written to the memory chip, thereby effectively improving data writing. The efficiency of the operation.
  • the write operation device 400 of FIG. 4 includes a determination unit 401 and a writing unit 401.
  • a determining unit 401 configured to determine, according to the first data and the original data corresponding to the to-be-written address, a first difference bit to be written, and determine a second difference bit to be written according to the second data and the original data corresponding to the to-be-written address,
  • the second data is the inverse of the first data, and the delay of the first difference bit determined by the write determination unit 401 and the delay of the second difference bit determined by the write determination unit 401 are respectively determined.
  • the Write unit 402 if the determination unit 401 determines that the delay of writing the first difference bit is greater than the write Entering the delay of the second difference bit, writing the second difference bit to the memory chip, if the delay of writing the second difference bit determined by the determining unit 401 is greater than the delay of writing the first difference bit, then the first The difference bits are written to the memory chip.
  • the memory chip may be a PCM memory chip, or may be a memory chip of other materials, such as a DRAM. It should be understood that the material of the memory chip is not limited in the embodiment of the present invention.
  • the write operation device 400 can implement the embodiments of FIGS. 1-3, and thus will not be described in detail in order to avoid redundancy.
  • the determining unit 401 may be specifically configured to: according to the number of writeable bits in parallel, the time of writing bit 0, and the time of writing bit 1, and the number and bit of bit 0 in the first difference bit. The number of ones determines the delay in writing the first difference bit. And based on the number of bits that can be written in parallel, the time at which bit 0 is written and the time at which bit 1 is written, and the number of bits 0 in the second difference bit and the number of bits 1, the delay in writing the second difference bit is determined.
  • the determining unit 401 may be specifically configured to: according to the number of writeable 1 in parallel, the time of writing bit 0, and the time of writing bit 1, and the first determined by determining unit 401 The number of bits 0 and the number of bits 1 in the difference bits determine the delay in writing the first difference bit, and the time to write bit 0 and the time to write bit 1 according to the number of writes 1 in parallel, and the determining unit 401 The number of bits 0 and the number of bits 1 in the determined second difference bit determine the delay in writing the second difference bit.
  • the delay of writing the first difference bit determined by the determining unit 401 is as in the above formula (1)
  • the delay of writing the second difference bit determined by the determining unit 401 is as shown in the above formula (2).
  • the process of the two-stage write operation (write bit 0 phase and write bit 1 phase) is performed.
  • the write bit 1 phase there may be more bits concurrently writing bit 1. Therefore, the above equations (1) and (2) can be employed to determine the delays for writing the first difference bit and the second difference bit, respectively.
  • the determining unit 401 may be specifically configured to: Writing the number of 0, the time of writing bit 0, and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the first difference bit determined by the determining unit 401, determine the delay of writing the first difference bit And, according to the number of 0s that can be written in parallel, the time of writing bit 0 and the time of writing bit 1, and the number of bits 0 and the number of bits 1 in the second difference bit determined by the determining unit 401, it is determined to write the The delay of the second difference bit. Specifically, the delay of writing the first difference bit determined by the determining unit 401 is as shown in the above formula (3), and the delay of writing the second difference bit determined by the determining unit 401 is as shown in the above formula (4).
  • the determining unit 401 may be specifically configured to: according to the number of parallel writeable 0s and the number of writes 1 in parallel, the time of writing bit 0, and the time of writing bit 1, and the determining unit
  • the number of bits 0 and the number of bits 1 in the first difference bit determined by 401 determine the delay of writing the first difference bit, and according to the number of 0s that can be written in parallel, the number of 1s can be written in parallel, and the bit 0 is written.
  • the time and the time at which bit 1 is written, and the number of bits 0 and the number of bits 1 in the second difference bit determined by the determining unit 401 determine the delay in writing the second difference bit.
  • the delay of writing the first difference bit determined by the determining unit 401 is as shown in the above formula (5)
  • the delay of writing the second difference bit determined by the determining unit 401 is as shown in the above formula (6).
  • the writing unit 402 is further configured to: if the delay of the second difference bit determined by the determining unit 401 is equal to the delay of the first difference bit, the first difference bit may be written into the memory chip or the second The difference bits are written to the memory chip.
  • This embodiment of the present invention is not limited thereto.
  • the embodiment of the present invention determines a first difference bit according to the first data and the original data corresponding to the to-be-written address, and determines a second difference bit according to the second data and the original data corresponding to the to-be-written address, where the second data is the first The inversion of the data.
  • FIG. 5 is a block diagram showing the structure of a write operation device according to still another embodiment of the present invention.
  • the device 500 includes a processor 501 and a memory 502.
  • the processor 501 controls the operation of the write operation device 500
  • the processor 501 can also be referred to as a CPU.
  • Memory 502 can include read only memory and random access memory and provides instructions and data to processor 501.
  • a portion of the memory 502 may also include non-volatile line random access memory (NVRAM).
  • NVRAM non-volatile line random access memory
  • bus system 510 The processor 501 and the memory 502 are coupled together by a bus system 510, wherein the bus system 510 includes a power bus, a control bus, and a status signal bus in addition to the data bus.
  • bus system 510 includes a power bus, a control bus, and a status signal bus in addition to the data bus.
  • various buses are labeled as bus system 510 in the figure.
  • the above-described write operation device 500 can be applied to the method disclosed in the above embodiments of the present invention.
  • the processor 501 may be an integrated circuit chip with signal processing capability. In the implementation process, each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 501 or an instruction in a form of software.
  • the memory chip performs the following operations according to the operation instruction stored by the processor 501 by calling the memory 502, which can be stored in the operating system:
  • the memory chip may be a PCM memory chip, or may be a memory chip of other materials, such as a DRAM. It should be understood that the material of the memory chip is not limited in the embodiment of the present invention.
  • the write operation device 500 can implement the embodiments of FIGS. 1-3, and thus will not be described in detail in order to avoid redundancy.
  • the processor 501 may be specifically configured to: according to the number of writeable bits in parallel, the time of writing bit 0, and the time of writing bit 1, and the number and bit of bit 0 in the first difference bit. The number of ones determines the delay in writing the first difference bit. And according to the number of bits that can be written in parallel, the time of writing bit 0 and the time of writing bit 1, and the bit 0 of the second difference bit The number of bits and the number of bits 1 determine the delay in writing the second difference bit.
  • the processor 501 is specifically configured to: according to the number of writeable 1 in parallel, the time of writing bit 0, and the time of writing bit 1, and the determined bit in the first difference bit
  • the number of 0s and the number of bits 1 determine the delay in writing the first difference bit
  • the number of bits 0 and the number of bits 1 determine the delay in writing the second difference bit.
  • the delay of writing the first difference bit determined by the processor 501 is as shown in the above formula (1)
  • the delay of writing the second difference bit determined by the processor 501 is as in the above formula (2).
  • the process of the two-stage write operation (write bit 0 phase and write bit 1 phase) is performed.
  • the write bit 1 phase there may be more bits concurrently writing bit 1. Therefore, the above equations (1) and (2) can be employed to determine the delays for writing the first difference bit and the second difference bit, respectively.
  • the processor 501 may be specifically configured to: according to the number of 0s that can be written in parallel, the time of writing bit 0, and the time of writing bit 1, and the determined bit 0 of the first difference bit.
  • the number and the number of bits 1 determine the delay of writing the first difference bit, and according to the number of 0s that can be written in parallel, the time of writing bit 0 and the time of writing bit 1, and the determined second difference bit.
  • the number of bits 0 and the number of bits 1 determine the delay in writing the second difference bit.
  • the delay of writing the first difference bit determined by the processor 501 is as shown in the above formula (3)
  • the delay of writing the second difference bit determined by the processor 501 is as shown in the above formula (4).
  • the processor 501 is specifically configured to: according to the number of parallel writeable 0s and the number of writes 1 in parallel, the time of writing bit 0, and the time of writing bit 1, and the determined The number of bits 0 and the number of bits 1 in a difference bit determine the delay of writing the first difference bit, and according to the number of 0s that can be written in parallel, the number of 1s can be written in parallel, the time and write of bit 0 are written.
  • the time of bit 1, and the determined number of bits 0 in the second difference bit and the number of bits 1, determine the delay in writing the second difference bit.
  • the processor 501 determines the first write The delay of the difference bit is as shown in the above formula (5), and the delay of writing the second difference bit determined by the processor 501 is as shown in the above formula (6).
  • the processor 501 is further configured to: if the determined delay of the second difference bit is equal to the delay of the first difference bit, write the first difference bit into the memory chip or write the second difference bit Memory chip.
  • This embodiment of the present invention is not limited thereto.
  • the embodiment of the present invention determines a first difference bit according to the first data and the original data corresponding to the to-be-written address, and determines a second difference bit according to the second data and the original data corresponding to the to-be-written address, where the second data is the first The inversion of the data.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separate.
  • the components displayed for the unit may or may not be physical units, ie may be located in one place, or may be distributed over multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present invention which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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Abstract

提供一种写操作方法及装置。该方法包括：根据第一数据和与待写地址对应的原数据确定待写的第一差异比特，并根据第二数据和所述与待写地址对应的原数据确定待写的第二差异比特，其中所述第二数据为所述第一数据的取反；分别确定写入所述第一差异比特的延时和写入所述第二差异比特的延时；如果写入所述第一差异比特的延时大于写入所述第二差异比特的延时，则将所述第二差异比特写入存储芯片，如果写入所述第二差异比特的延时大于写入所述第一差异比特的延时，则将所述第一差异比特写入存储芯片。因此，写入延时较小的待写差异比特，有效地提高数据写操作的效率。

Description

写操作方法及装置
本申请要求于2013年9月5日提交中国专利局、申请号为201310400382.2、发明名称为“写操作方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及通信技术领域，并且更具体地，涉及写操作方法及装置。
背景技术
为了提高写操作的效率，现有技术的写操作方案中，会增加一个编码处理，比较待写数据中0和1的个数，确定是否将待写数据取反后写入存储信息，相应地，在读操作过程，将写入的数据取反后读出。例如，如果写比特1的时间大于写比特0的时间且待写数据中1的个数大于0的个数，则将待写数据取反后写入。
但是，仅从待写数据中的0和1个数来确定写操作方案具有一定的局限性。以PCM(Phase Change Memory，相变存储)存储芯片为例，由于写比特0的瞬时电流大而写比特1的瞬时电流小，因此分两阶段写操作(写比特0阶段和写比特1阶段)过程中，在写比特1阶段时可以有更多的位并发的写比特1。这样，仅从写比特0和写比特1的个数来判断并不能有效地提高写操作的效率。
发明内容
本发明实施例提供一种写操作方法及装置，有效地提高写操作的效率。
第一方面，提供了一种写操作方法，该方法包括：根据第一数据和与待写地址对应的原数据确定待写的第一差异比特，并根据第二数据和所述与待写地址对应的原数据确定待写的第二差异比特，其中所述第二数据为所述第一数据的取反；分别确定写入所述第一差异比特的延时和写入所述第二差异比特的延时；如果写入所述第一差异比特的延时大于写入所述第二差异比特的延时，则将所述第二差异比特写入存储芯片，如果写入所述第二差异比特的延时大于写入所述第一差异比特的延时，则将所述第一差异比特写入存储芯片。
结合第一方面，在第一方面的另一种实现方式中，所述分别确定写入所述第一差异比特的延时和写入所述第二差异比特的延时，包括：
根据可并行写入比特的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，并根据可并行写入比特的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
结合第一方面或其上述实现方式中的任一种实现方式，在第一方面的另一种实现方式中，所述根据可并行写入比特的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，包括：根据可并行写入1的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时；
所述根据可并行写入比特的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时，包括：根据可并行写入1的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
结合第一方面或其上述实现方式中的任一种实现方式，在第一方面的另一种实现方式中，确定的所述写入所述第一差异比特的延时为T1：
Figure PCTCN2014085962-appb-000001
确定的所述写入所述第二差异比特的延时为T2：
Figure PCTCN2014085962-appb-000002
其中，N10表示所述第一差异比特中比特0的数目，N11表示所述第一差异比特中比特1的数目，N20表示所述第二差异比特中比特0的数目，N21表示所述第二差异比特中比特1的数目，A1表示可并行写入1的数目，t0表示写比特0的时间，t1表示写比特1的时间，以及
Figure PCTCN2014085962-appb-000003
表示向上取整。
结合第一方面或其上述实现方式中的任一种实现方式，在第一方面的另一种实现方式中，所述存储芯片为相变PCM存储芯片。
结合第一方面或其上述实现方式中的任一种实现方式，在第一方面的另一种实现方式中，所述根据可并行写入比特的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，包括：根据可并行写入0的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时；
所述根据可并行写入比特的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时，包括：根据可并行写入0的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
结合第一方面或其上述实现方式中的任一种实现方式，在第一方面的另一种实现方式中，确定的所述写入所述第一差异比特的延时为T1：
Figure PCTCN2014085962-appb-000004
确定的所述写入所述第二差异比特的延时为T2：
Figure PCTCN2014085962-appb-000005
其中，N10表示所述第一差异比特中比特0的数目，N11表示所述第一差异比特中比特1的数目，N20表示所述第二差异比特中比特0的数目，N21表示所述第二差异比特中比特1的数目，A0表示可并行写入1的数目，t0表示写比特0的时间，t1表示写比特1的时间，以及
Figure PCTCN2014085962-appb-000006
表示向上取整。
结合第一方面或其上述实现方式中的任一种实现方式，在第一方面的另一种实现方式中，所述根据可并行写入比特的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，包括：根据可并行写入0的数目和可并行写入1的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时；
所述根据可并行写入比特的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时，包括：根据可并行写入0的数目和可并行写入1的数目、写比特0的时间和写比特1的时间、以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
结合第一方面或其上述实现方式中的任一种实现方式，在第一方面的另一种实现方式中，确定的所述写入所述第一差异比特的延时为T1：
Figure PCTCN2014085962-appb-000007
确定的所述写入所述第二差异比特的延时为T2：
Figure PCTCN2014085962-appb-000008
其中，N10表示所述第一差异比特中比特0的数目， N11表示所述第一差异比特中比特1的数目，N20表示所述第二差异比特中比特0的数目，N21表示所述第二差异比特中比特1的数目，A0表示可并行写入1的数目，A1表示可并行写入0的数目，t0表示写比特0的时间，t1表示写比特1的时间，以及
Figure PCTCN2014085962-appb-000009
表示向上取整。
结合第一方面或其上述实现方式中的任一种实现方式，在第一方面的另一种实现方式中，如果所述第二差异比特的延时等于所述第一差异比特的延时，则将所述第一差异比特写入存储芯片或者将所述第二差异比特写入存储芯片。
第二方面，提供了一种写操作装置，该装置包括：确定单元，用于根据第一数据和与待写地址对应的原数据确定待写的第一差异比特，根据第二数据和所述与待写地址对应的原数据确定待写的第二差异比特，其中所述第二数据为所述第一数据的取反，并且分别确定写入所述确定单元确定的所述第一差异比特的延时和写入所述确定单元确定的所述第二差异比特的延时；写入单元，如果所述确定单元确定的写入所述第一差异比特的延时大于写入所述第二差异比特的延时，则将所述第二差异比特写入存储芯片，如果所述确定单元确定的写入所述第二差异比特的延时大于写入所述第一差异比特的延时，则将所述第一差异比特写入存储芯片。
结合第二方面，在第二方面的另一种实现方式中，所述确定单元具体用于：根据可并行写入比特的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，并根据可并行写入比特的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
结合第二方面或其上述实现方式中的任一种实现方式，在第二方面的另一种实现方式中，所述确定单元具体用于：根据可并行写入1的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比 特1的数目，确定所述写入所述第一差异比特的延时，并根据可并行写入1的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
结合第二方面或其上述实现方式中的任一种实现方式，在第二方面的另一种实现方式中，所述确定单元确定的所述写入所述第一差异比特的延时为T1：
Figure PCTCN2014085962-appb-000010
所述确定单元确定的所述写入所述第二差异比特的延时为T2：
Figure PCTCN2014085962-appb-000011
其中，N10表示所述第一差异比特中比特0的数目，N11表示所述第一差异比特中比特1的数目，N20表示所述第二差异比特中比特0的数目，N21表示所述第二差异比特中比特1的数目，A1表示可并行写入1的数目，t0表示写比特0的时间，t1表示写比特1的时间，以及
Figure PCTCN2014085962-appb-000012
表示向上取整。
结合第二方面或其上述实现方式中的任一种实现方式，在第二方面的另一种实现方式中，所述存储芯片为相变PCM存储芯片。
结合第二方面或其上述实现方式中的任一种实现方式，在第二方面的另一种实现方式中，所述确定单元具体用于：根据可并行写入0的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，并根据可并行写入0的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
结合第二方面或其上述实现方式中的任一种实现方式，在第二方面的另一种实现方式中，所述确定单元确定的所述写入所述第一差异比特的延时为T1：
Figure PCTCN2014085962-appb-000013
所述确定单元确定的所述写入所述第二差异比特的 延时为T2：
Figure PCTCN2014085962-appb-000014
其中，N10表示所述第一差异比特中比特0的数目，N11表示所述第一差异比特中比特1的数目，N20表示所述第二差异比特中比特0的数目，N21表示所述第二差异比特中比特1的数目，A0表示可并行写入1的数目，t0表示写比特0的时间，t1表示写比特1的时间，以及
Figure PCTCN2014085962-appb-000015
表示向上取整。
结合第二方面或其上述实现方式中的任一种实现方式，在第二方面的另一种实现方式中，所述确定单元具体用于：根据可并行写入0的数目和可并行写入1的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，并根据可并行写入0的数目和可并行写入1的数目、写比特0的时间和写比特1的时间、以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
结合第二方面或其上述实现方式中的任一种实现方式，在第二方面的另一种实现方式中，所述确定单元确定的所述写入所述第一差异比特的延时为T1：
Figure PCTCN2014085962-appb-000016
所述确定单元确定的所述写入所述第二差异比特的延时为T2：
Figure PCTCN2014085962-appb-000017
其中，N10表示所述第一差异比特中比特0的数目，N11表示所述第一差异比特中比特1的数目，N20表示所述第二差异比特中比特0的数目，N21表示所述第二差异比特中比特1的数目，A0表示可并行写入1的数目，A1表示可并行写入0的数目，t0表示写比特0的时间，t1表示写比特1的时间，以及
Figure PCTCN2014085962-appb-000018
表示向上取整。
结合第二方面或其上述实现方式中的任一种实现方式，在第二方面的另 一种实现方式中，所述写入单元还用于：如果所述确定单元确定的所述第二差异比特的延时等于所述第一差异比特的延时，则将所述第一差异比特写入存储芯片或者将所述第二差异比特写入存储芯片。
本发明实施例根据第一数据和与待写地址对应的原数据确定第一差异比特，并根据第二数据和与待写地址对应的原数据确定第二差异比特，其中第二数据为第一数据的取反。通过确定并比较写入第一差异比特的延时和写入第二差异比特的延时，将延时较小的待写差异比特写入存储芯片，从而有效地提高数据写操作的效率。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明一个实施例的写操作方法的流程图。
图2是本发明一个实施例的PCM存储芯片的示意图。
图3是本发明一个实施例的写操作方法的过程的示意性流程图。
图4是本发明一个实施例的写操作装置的结构框图。
图5是本发明另一个实施例的写操作装置的结构框图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1是本发明一个实施例的写操作方法的流程图。图1的方法由写操作 装置(如存储芯片)执行。
101，根据第一数据和与待写地址对应的原数据确定待写的第一差异比特，并根据第二数据和与待写地址对应的原数据确定待写的第二差异比特，其中第二数据为第一数据的取反。
根据本发明的实施例，可以将第一数据与原数据进行比较，得到第一数据中与原数据不同的比特，即第一差异比特，并且将第二数据与原数据地进行比较，得到第二数据中与原数据不同的比特，即第二差异比特。
102，分别确定写入第一差异比特的延时和写入第二差异比特的延时。
例如，写入第一差异比特的延时指将第一差异比特写入待写地址所花费的时间。写入第二差异比特的延时指将第二差异比特写入待写地址所花费的时间。第一差异比特可以为一个或多个比特，第二差异比特可以为一个或多个比特。
103，如果写入第一差异比特的延时大于写入第二差异比特的延时，则将第二差异比特写入存储芯片，如果写入第二差异比特的延时大于写入第一差异比特的延时，则将第一差异比特写入存储芯片。换句话说，可以选择第一差异比特和第二差异比特中写入延时较小的差异比特写入存储芯片中。
本发明实施例根据第一数据和与待写地址对应的原数据确定第一差异比特，并根据第二数据和与待写地址对应的原数据确定第二差异比特，其中第二数据为第一数据的取反。通过确定并比较写入第一差异比特的延时和写入第二差异比特的延时，将延时较小的待写差异比特写入存储芯片，从而有效地提高数据写操作的效率。
需要说明的是，存储芯片可以是PCM(Phase Change Memory，相变存储)存储芯片，也可以是其它材料的存储芯片，如DRAM(Dynamic Random Access Memory，动态随机存取存储)，应理解，本发明实施例对存储芯片的材料并不限定。
根据本发明的实施例，在102中，可以根据可并行写入比特的数目、写 比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，并根据可并行写入比特的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
写比特0的时间是指写入每个比特0所花费的时间，写比特1的时间是指写入每个比特1所花费的时间。例如，当存储芯片为PCM时，由于写比特0的电流大于写比特1的电流，因此，可以在实现写操作时，可以并行发送多个1，或者并行发送1的个数大于并行发送0的个数，只要并行发送的多个比特时存储芯片的总电流不超过最大电流即可。
可选地，作为一个实施例，在102中，可以根据可并行写入1的数目、写比特0的时间和写比特1的时间、以及第一差异比特中比特0的数目和比特1的数目，确定写入第一差异比特的延时；并根据可并行写入1的数目，写比特0的时间和写比特1的时间，以及第二差异比特中比特0的数目和比特1的数目，确定写入所述第二差异比特的延时。
具体地，确定的写第一差异比特的延时为T1：
Figure PCTCN2014085962-appb-000019
确定的写入第二差异比特的延时为T2：
Figure PCTCN2014085962-appb-000020
其中，N10表示第一差异比特中比特0的数目，N11表示第一差异比特中比特1的数目，N20表示第二差异比特中比特0的数目，N21表示第二差异比特中比特1的数目，A1表示可并行写入1的数目，例如，A1为大于等于2的整数，t0表示写比特0的时间，t1表示写比特1的时间，以及
Figure PCTCN2014085962-appb-000021
表示向上取整。
具体地，当存储芯片为PCM存储芯片时，由于PCM存储芯片写比特0 的瞬时电流大而写比特1的瞬时电流小，因此分两阶段写操作(写比特0阶段和写比特1阶段)过程中，在写比特1阶段时可以有更多的位并发的写比特1。因此，可以采用上述(1)式和(2)式来分别确定写入第一差异比特和第二差异比特的时延。
在另一种可能的实现方式下，可以根据可并行写入0的数目、写比特0的时间和写比特1的时间、以及第一差异比特中比特0的数目和比特1的数目，确定所述写入第一差异比特的延时；并根据可并行写入0的数目，写比特0的时间和写比特1的时间，以及第二差异比特中比特0的数目和比特1的数目，确定写入第二差异比特的延时。
具体地，确定的写入第一差异比特的延时为T1：
Figure PCTCN2014085962-appb-000022
确定的写入第二差异比特的延时为T2：
Figure PCTCN2014085962-appb-000023
其中，N10表示第一差异比特中比特0的数目，N11表示第一差异比特中比特1的数目，N20表示第二差异比特中比特0的数目，N21表示第二差异比特中比特1的数目，A0表示可并行写入1的数目，例如，A0为大于等于2的整数，t0表示写比特0的时间，t1表示写比特1的时间，以及
Figure PCTCN2014085962-appb-000024
表示向上取整。
在又一种可能的实现方式下，当可并行写入0和1时，可以根据可并行写入0的数目、可并行写入1的数目、写比特0的时间和写比特1的时间、以及第一差异比特中比特0的数目和比特1的数目，确定写入第一差异比特的延时；并根据可并行写入0的数目，可并行写入1的数目，写比特0的时间和写比特1的时间，以及第二差异比特中比特0的数目和比特1的数目，确定写入第二差异比特的延时。
具体地，确定的写第一差异比特的延时为T1：
Figure PCTCN2014085962-appb-000025
确定的写入第二差异比特的延时为T2：
Figure PCTCN2014085962-appb-000026
其中，N10表示第一差异比特中比特0的数目，N11表示第一差异比特中比特1的数目，N20表示第二差异比特中比特0的数目，N21表示第二差异比特中比特1的数目，A0表示可并行写入1的数目，A1表示可并行写入0的数目，例如，A0和A1均为大于等于2的整数，t0表示写比特0的时间，t1表示写比特1的时间，以及
Figure PCTCN2014085962-appb-000027
表示向上取整。
应当理解的是，上述确定待写差异比特延时的其它等价表示方式均落入本发明的保护范围内，例如，上述公式(1)也可以等价地表示为：
Figure PCTCN2014085962-appb-000028
可选地，如果在步骤102确定的第二差异比特的延时等于第一差异比特的延时，则可以将第一差异比特写入存储芯片或者将第二差异比特写入存储芯片。本发明实施例对此并不限定。
下面以PCM存储芯片为例结合图2的示意图和图3的流程图进行说明，应理解，本发明实施例并不限于。对于PCM存储芯片而言，写比特0需要的瞬时电流大、时间短，写比特1需要的瞬时电流小但时间长，读脉冲所需的电流和时间都要比写比特0和写比特1的少。因此，在写比特1阶段时，可以采用并发写比特1的方式。如图2所示，PCM存储芯片包括缓存区(buffer)、预判电路、读写控制电路和存储块。缓存区用于寄存写入和读出的数据，预判电路，预判电路用于待写差异比特的延时预判，具体可以包括用于确定待 写差异比特的比较电路和用于确定待写差异比特延时的延时确定电路，读写控制电路用于控制存储块的读写操作。PCM存储芯片从I/O接口接收到CPU(Central Processing Unit，中央处理器)的读或写操作命令，进行读或写操作。
步骤301，预判电路(具体可以是比较电路)将缓存区寄存的第一数据与待写地址对应的原数据进行比较得到第一差异比特，并将缓存区寄存的第一数据取反后得到的第二数据与待写地址对应的原数据进行比较得到第二差异比特。
步骤302，预判电路(具体可以是延时确定电路)确定写入第一差异比特的延时，并确定写入第二差异比特的延时。
具体地，分别采用上述公式(1)和(2)确定写入(也称为“传输”)第一差异比特的延时T1和写入第二差异比特的延时T2。
步骤303，读写控制电路将延时较小的待写差异比特写入存储块。
当T1大于T2时，读写控制电路将第二差异比特写入存储块；当T1小于T2时，读写控制电路将第一差异比特写入存储块；当T1等于T2时，读写控制电路可以将第一差异比特写入存储块或者将第二差异比特写入存储块。
可选地，当写入的是第二差异比特，读出时，需要取反后读出。
基于上述技术方案，通过确定并比较写入第一差异比特的延时和写入第二差异比特的延时，将延时较小的待写差异比特写入存储芯片，从而有效地提高数据写操作的效率。
图4是本发明一个实施例的写操作装置的结构框图。图4的写操作装置400包括确定单元401和写入单元401。
确定单元401，用于根据第一数据和与待写地址对应的原数据确定待写的第一差异比特，根据第二数据和与待写地址对应的原数据确定待写的第二差异比特，其中第二数据为第一数据的取反，并且分别确定写入确定单元401确定的第一差异比特的延时和写入确定单元401确定的第二差异比特的延时。
写入单元402，如果确定单元401确定的写入第一差异比特的延时大于写 入第二差异比特的延时，则将第二差异比特写入存储芯片，如果确定单元401确定的写入第二差异比特的延时大于写入第一差异比特的延时，则将第一差异比特写入存储芯片。
需要说明的是，存储芯片可以是PCM存储芯片，也可以是其它材料的存储芯片，如DRAM，应理解，本发明实施例对存储芯片的材料并不限定。
写操作装置400可实现图1-图3的实施例，因此为避免重复，不再详细描述。
可选地，作为一个实施例，确定单元401可以具体用于：根据可并行写入比特的数目、写比特0的时间和写比特1的时间、以及第一差异比特中比特0的数目和比特1的数目，确定写入第一差异比特的延时。并根据可并行写入比特的数目，写比特0的时间和写比特1的时间，以及第二差异比特中比特0的数目和比特1的数目，确定写入第二差异比特的延时。
可选地，在一种可能的实现方式下，确定单元401可以具体用于：根据可并行写入1的数目、写比特0的时间和写比特1的时间、以及确定单元401确定的第一差异比特中比特0的数目和比特1的数目，确定写入第一差异比特的延时，并根据可并行写入1的数目，写比特0的时间和写比特1的时间，以及确定单元401确定的第二差异比特中比特0的数目和比特1的数目，确定写入第二差异比特的延时。具体地，确定单元401确定的写入第一差异比特的延时如上述(1)式，确定单元401确定的写入第二差异比特的延时如上述(2)式。
具体地，当存储芯片为PCM存储芯片时，由于PCM存储芯片写比特0的瞬时电流大而写比特1的瞬时电流小，因此分两阶段写操作(写比特0阶段和写比特1阶段)过程中，在写比特1阶段时可以有更多的位并发的写比特1。因此，可以采用上述(1)式和(2)式来分别确定写入第一差异比特和第二差异比特的时延。
在另一种可能的实现方式下，确定单元401可以具体用于：根据可并行 写入0的数目、写比特0的时间和写比特1的时间、以及确定单元401确定的第一差异比特中比特0的数目和比特1的数目，确定写入所述第一差异比特的延时，并根据可并行写入0的数目，写比特0的时间和写比特1的时间，以及确定单元401确定的第二差异比特中比特0的数目和比特1的数目，确定写入所述第二差异比特的延时。具体地，确定单元401确定的写入第一差异比特的延时如上述(3)式，确定单元401确定的写入第二差异比特的延时如上述(4)式。
在又一种可能的实现方式下，确定单元401可以具体用于：根据可并行写入0的数目和可并行写入1的数目、写比特0的时间和写比特1的时间、以及确定单元401确定的第一差异比特中比特0的数目和比特1的数目，确定写入第一差异比特的延时，并根据可并行写入0的数目，可并行写入1的数目，写比特0的时间和写比特1的时间，以及确定单元401确定的第二差异比特中比特0的数目和比特1的数目，确定写入第二差异比特的延时。具体地，确定单元401确定的写入第一差异比特的延时如上述(5)式，确定单元401确定的写入第二差异比特的延时如上述(6)式。
可选地，写入单元402还可以用于：如果确定单元401确定的第二差异比特的延时等于第一差异比特的延时，则可以将第一差异比特写入存储芯片或者将第二差异比特写入存储芯片。本发明实施例对此并不限定。
本发明实施例根据第一数据和与待写地址对应的原数据确定第一差异比特，并根据第二数据和与待写地址对应的原数据确定第二差异比特，其中第二数据为第一数据的取反。通过确定并比较写入第一差异比特的延时和写入第二差异比特的延时，将延时较小的待写差异比特写入存储芯片，从而有效地提高数据写操作的效率。
本发明实施例进一步给出实现上述方法实施例中各步骤及方法的装置实施例。图5是本发明又一个实施例的写操作装置的结构框图，在该实施例中，设备500包括处理器501和存储器502。处理器501控制写操作装置500的操 作，处理器501还可以称为CPU。存储器502可以包括只读存储器和随机存取存储器，并向处理器501提供指令和数据。存储器502的一部分还可以包括非易失行随机存取存储器(NVRAM)。处理器501和存储器502通过总线系统510耦合在一起，其中总线系统510除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图中将各种总线都标为总线系统510。
上述本发明实施例揭示的方法可以应用上述的写操作装置500。其中，处理器501可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器501中的硬件的集成逻辑电路或者软件形式的指令完成。
在本发明实施例中，存储芯片根据处理器501通过调用存储器502存储的操作指令(该操作指令可存储在操作系统中)，执行如下操作：
根据第一数据和与待写地址对应的原数据确定待写的第一差异比特，并根据第二数据和与待写地址对应的原数据确定待写的第二差异比特，其中第二数据为第一数据的取反；分别确定写入第一差异比特的延时和写入第二差异比特的延时；如果写入第一差异比特的延时大于写入第二差异比特的延时，则将第二差异比特写入存储芯片，如果写入第二差异比特的延时大于写入第一差异比特的延时，则将第一差异比特写入存储芯片。
需要说明的是，存储芯片可以是PCM存储芯片，也可以是其它材料的存储芯片，如DRAM，应理解，本发明实施例对存储芯片的材料并不限定。
写操作装置500可实现图1-图3的实施例，因此为避免重复，不再详细描述。
可选地，作为一个实施例，处理器501可以具体用于：根据可并行写入比特的数目、写比特0的时间和写比特1的时间、以及第一差异比特中比特0的数目和比特1的数目，确定写入第一差异比特的延时。并根据可并行写入比特的数目，写比特0的时间和写比特1的时间，以及第二差异比特中比特0 的数目和比特1的数目，确定写入第二差异比特的延时。
可选地，在一种可能的实现方式下，处理器501具体用于：根据可并行写入1的数目、写比特0的时间和写比特1的时间、以及确定的第一差异比特中比特0的数目和比特1的数目，确定写入第一差异比特的延时，并根据可并行写入1的数目，写比特0的时间和写比特1的时间，以及确定的第二差异比特中比特0的数目和比特1的数目，确定写入第二差异比特的延时。具体地，处理器501确定的写入第一差异比特的延时如上述(1)式，处理器501确定的写入第二差异比特的延时如上述(2)式。
具体地，当存储芯片为PCM存储芯片时，由于PCM存储芯片写比特0的瞬时电流大而写比特1的瞬时电流小，因此分两阶段写操作(写比特0阶段和写比特1阶段)过程中，在写比特1阶段时可以有更多的位并发的写比特1。因此，可以采用上述(1)式和(2)式来分别确定写入第一差异比特和第二差异比特的时延。
在另一种可能的实现方式下，处理器501可以具体用于：根据可并行写入0的数目、写比特0的时间和写比特1的时间、以及确定的第一差异比特中比特0的数目和比特1的数目，确定写入所述第一差异比特的延时，并根据可并行写入0的数目，写比特0的时间和写比特1的时间，以及确定的第二差异比特中比特0的数目和比特1的数目，确定写入所述第二差异比特的延时。具体地，处理器501确定的写入第一差异比特的延时如上述(3)式，处理器501确定的写入第二差异比特的延时如上述(4)式。
在又一种可能的实现方式下，处理器501具体用于：根据可并行写入0的数目和可并行写入1的数目、写比特0的时间和写比特1的时间、以及确定的第一差异比特中比特0的数目和比特1的数目，确定写入第一差异比特的延时，并根据可并行写入0的数目，可并行写入1的数目，写比特0的时间和写比特1的时间，以及确定的第二差异比特中比特0的数目和比特1的数目，确定写入第二差异比特的延时。具体地，处理器501确定的写入第一 差异比特的延时如上述(5)式，处理器501确定的写入第二差异比特的延时如上述(6)式。
可选地，处理器501还可以用于：如果确定的第二差异比特的延时等于第一差异比特的延时，则可以将第一差异比特写入存储芯片或者将第二差异比特写入存储芯片。本发明实施例对此并不限定。
本发明实施例根据第一数据和与待写地址对应的原数据确定第一差异比特，并根据第二数据和与待写地址对应的原数据确定第二差异比特，其中第二数据为第一数据的取反。通过确定并比较写入第一差异比特的延时和写入第二差异比特的延时，将延时较小的待写差异比特写入存储芯片，从而有效地提高数据写操作的效率。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作 为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。

Claims (20)

  1. 一种写操作方法，其特征在于，包括：
    根据第一数据和与待写地址对应的原数据确定待写的第一差异比特，并根据第二数据和所述与待写地址对应的原数据确定待写的第二差异比特，其中所述第二数据为所述第一数据的取反；
    分别确定写入所述第一差异比特的延时和写入所述第二差异比特的延时；
    如果写入所述第一差异比特的延时大于写入所述第二差异比特的延时，则将所述第二差异比特写入存储芯片，如果写入所述第二差异比特的延时大于写入所述第一差异比特的延时，则将所述第一差异比特写入存储芯片。
  2. 根据权利要求1所述的方法，其特征在于，所述分别确定写入所述第一差异比特的延时和写入所述第二差异比特的延时，包括：
    根据可并行写入比特的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，并根据可并行写入比特的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
  3. 根据权利要求2所述的方法，其特征在于，所述根据可并行写入比特的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，包括：
    根据可并行写入1的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，
    其中所述根据可并行写入比特的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时，包括：
    根据可并行写入1的数目，写比特0的时间和写比特1的时间，以及所述 第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
  4. 根据权利要求3所述的方法，其特征在于，
    确定的所述写入所述第一差异比特的延时为T1：
    Figure PCTCN2014085962-appb-100001
    确定的所述写入所述第二差异比特的延时为T2：
    Figure PCTCN2014085962-appb-100002
    其中，N10表示所述第一差异比特中比特0的数目，N11表示所述第一差异比特中比特1的数目，N20表示所述第二差异比特中比特0的数目，N21表示所述第二差异比特中比特1的数目，A1表示可并行写入1的数目，t0表示写比特0的时间，t1表示写比特1的时间，以及
    Figure PCTCN2014085962-appb-100003
    表示向上取整。
  5. 根据权利要求1-4中的任一项所述的方法，其特征在于，所述存储芯片为相变PCM存储芯片。
  6. 根据权利要求2所述的方法，其特征在于，所述根据可并行写入比特的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，包括：
    根据可并行写入0的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时；
    所述根据可并行写入比特的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时，包括：
    根据可并行写入0的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
  7. 根据权利要求6所述的方法，其特征在于，
    确定的所述写入所述第一差异比特的延时为T1：
    Figure PCTCN2014085962-appb-100004
    确定的所述写入所述第二差异比特的延时为T2：
    Figure PCTCN2014085962-appb-100005
    其中，N10表示所述第一差异比特中比特0的数目，N11表示所述第一差异比特中比特1的数目，N20表示所述第二差异比特中比特0的数目，N21表示所述第二差异比特中比特1的数目，A0表示可并行写入1的数目，t0表示写比特0的时间，t1表示写比特1的时间，以及
    Figure PCTCN2014085962-appb-100006
    表示向上取整。
  8. 根据权利要求2所述的方法，其特征在于，所述根据可并行写入比特的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，包括：
    根据可并行写入0的数目和可并行写入1的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时；
    所述根据可并行写入比特的数目、写比特0的时间和写比特1的时间、以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时，包括：
    根据可并行写入0的数目和可并行写入1的数目、写比特0的时间和写比特1的时间、以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
  9. 根据权利要求8所述的方法，其特征在于，
    确定的所述写入所述第一差异比特的延时为T1：
    Figure PCTCN2014085962-appb-100007
    确定的所述写入所述第二差异比特的延时为T2：
    Figure PCTCN2014085962-appb-100008
    其中，N10表示所述第一差异比特中比特0的数目，N11表示所述第一差异比特中比特1的数目，N20表示所述第二差异比特中比特0的数目，N21表示所述第二差异比特中比特1的数目，A0表示可并行写入1的数目，A1表示可并行写入0的数目，t0表示写比特0的时间，t1表示写比特1的时间，以及
    Figure PCTCN2014085962-appb-100009
    表示向上取整。
  10. 根据权利要求1-9中的任一项所述的方法，其特征在于，所述方法还包括:
    如果所述第二差异比特的延时等于所述第一差异比特的延时，则将所述第一差异比特写入存储芯片或者将所述第二差异比特写入存储芯片。
  11. 一种写操作装置，其特征在于，包括：
    确定单元，用于根据第一数据和与待写地址对应的原数据确定待写的第一差异比特，根据第二数据和所述与待写地址对应的原数据确定待写的第二差异比特，其中所述第二数据为所述第一数据的取反，并且分别确定写入所述确定单元确定的所述第一差异比特的延时和写入所述确定单元确定的所述第二差异比特的延时；
    写入单元，如果所述确定单元确定的写入所述第一差异比特的延时大于写入所述第二差异比特的延时，则将所述第二差异比特写入存储芯片，如果所述确定单元确定的写入所述第二差异比特的延时大于写入所述第一差异比特的延时，则将所述第一差异比特写入存储芯片。
  12. 根据权利要求11所述的装置，其特征在于，所述确定单元
    具体用于：根据可并行写入比特的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，并根据可并行写入比特的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
  13. 根据权利要求12所述的装置，其特征在于，所述确定单元
    具体用于：根据可并行写入1的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，并根据可并行写入1的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
  14. 根据权利要求13所述的装置，其特征在于，
    所述确定单元确定的所述写入所述第一差异比特的延时为T1：
    Figure PCTCN2014085962-appb-100010
    所述确定单元确定的所述写入所述第二差异比特的延时为T2：
    Figure PCTCN2014085962-appb-100011
    其中，N10表示所述第一差异比特中比特0的数目，N11表示所述第一差异比特中比特1的数目，N20表示所述第二差异比特中比特0的数目，N21表示所述第二差异比特中比特1的数目，A1表示可并行写入1的数目，t0表示写比特0的时间，t1表示写比特1的时间，以及
    Figure PCTCN2014085962-appb-100012
    表示向上取整。
  15. 根据权利要求11-14中的任一项所述的装置，其特征在于，所述存储芯片为相变PCM存储芯片。
  16. 根据权利要求12所述的装置，其特征在于，所述确定单元
    具体用于：根据可并行写入0的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，并根据可并行写入0的数目，写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
  17. 根据权利要求16所述的装置，其特征在于，
    所述确定单元确定的所述写入所述第一差异比特的延时为T1：
    Figure PCTCN2014085962-appb-100013
    所述确定单元确定的所述写入所述第二差异比特的延时为T2：
    Figure PCTCN2014085962-appb-100014
    其中，N10表示所述第一差异比特中比特0的数目，N11表示所述第一差异比特中比特1的数目，N20表示所述第二差异比特中比特0的数目，N21表示所述第二差异比特中比特1的数目，A0表示可并行写入1的数目，t0表示写比特0的时间，t1表示写比特1的时间，以及
    Figure PCTCN2014085962-appb-100015
    表示向上取整。
  18. 根据权利要求12所述的装置，其特征在于，所述确定单元
    具体用于：根据可并行写入0的数目和可并行写入1的数目、写比特0的时间和写比特1的时间、以及所述第一差异比特中比特0的数目和比特1的数目，确定所述写入所述第一差异比特的延时，并根据可并行写入0的数目和可并行写入1的数目、写比特0的时间和写比特1的时间，以及所述第二差异比特中比特0的数目和比特1的数目，确定所述写入所述第二差异比特的延时。
  19. 根据权利要求18所述的装置，其特征在于，
    所述确定单元确定的所述写入所述第一差异比特的延时为T1：
    Figure PCTCN2014085962-appb-100016
    所述确定单元确定的所述写入所述第二差异比特的延时为T2：
    Figure PCTCN2014085962-appb-100017
    其中，N10表示所述第一差异比特中比特0的数目，N11表示所述第一差异比特中比特1的数目，N20表示所述第二差异比特中比特0的数目，N21表示所述第二差异比特中比特1的数目，A0表示可并行写入1的数目，A1表示可并行写入0的数目，t0表示写比特0的时间，t1表示写比特1的时间，以及
    Figure PCTCN2014085962-appb-100018
    表示向上取整。
  20. 根据权利要求11-19中的任一项所述的装置，其特征在于，
    所述写入单元还用于：如果所述确定单元确定的所述第二差异比特的延时等于所述第一差异比特的延时，则将所述第一差异比特写入存储芯片或者将所述第二差异比特写入存储芯片。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090257277A1 (en) * 2007-09-21 2009-10-15 Juhan Kim Flash memory including reduced swing amplifiers
US20100097839A1 (en) * 2008-10-19 2010-04-22 Juhan Kim High speed ferroelectric random access memory
CN101901131A (zh) * 2010-07-22 2010-12-01 上海交通大学 音频编解码比特级读写加速装置及其加速读写方法
CN102097125A (zh) * 2010-12-07 2011-06-15 清华大学 Pcm的写操作方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100819061B1 (ko) * 2007-03-06 2008-04-03 한국전자통신연구원 쓰기 전력 계산 및 데이터 반전 기능을 통한 상 변화메모리에서의 데이터 쓰기 장치 및 방법
US8116126B2 (en) * 2009-08-17 2012-02-14 International Business Machines Corporation Measurement method for reading multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition
KR101678886B1 (ko) * 2009-11-25 2016-11-23 삼성전자주식회사 멀티-레벨 상변환 메모리 장치 및 그 구동 방법
CN101783171B (zh) * 2009-12-24 2012-07-04 中国科学院上海微系统与信息技术研究所 相变存储器的猝发写方法
CN103151072B (zh) * 2013-03-28 2016-05-18 中国科学院微电子研究所 相变存储器的数据写入方法及装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090257277A1 (en) * 2007-09-21 2009-10-15 Juhan Kim Flash memory including reduced swing amplifiers
US20100097839A1 (en) * 2008-10-19 2010-04-22 Juhan Kim High speed ferroelectric random access memory
CN101901131A (zh) * 2010-07-22 2010-12-01 上海交通大学 音频编解码比特级读写加速装置及其加速读写方法
CN102097125A (zh) * 2010-12-07 2011-06-15 清华大学 Pcm的写操作方法

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