WO2015002048A1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

Info

Publication number
WO2015002048A1
WO2015002048A1 PCT/JP2014/066873 JP2014066873W WO2015002048A1 WO 2015002048 A1 WO2015002048 A1 WO 2015002048A1 JP 2014066873 W JP2014066873 W JP 2014066873W WO 2015002048 A1 WO2015002048 A1 WO 2015002048A1
Authority
WO
WIPO (PCT)
Prior art keywords
sealing sheet
sealing
semiconductor device
semiconductor
sheet
Prior art date
Application number
PCT/JP2014/066873
Other languages
French (fr)
Japanese (ja)
Inventor
豪士 志賀
浩介 盛田
智絵 飯野
石坂　剛
Original Assignee
日東電工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日東電工株式会社 filed Critical 日東電工株式会社
Publication of WO2015002048A1 publication Critical patent/WO2015002048A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device.
  • a sealing resin for example, a thermosetting resin sheet is known (see, for example, Patent Document 1).
  • the sealing body and the semiconductor device can be distinguished from each other.
  • the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that enables a sealing body and a semiconductor device to be distinguished from each other in the manufacturing process of the semiconductor device. is there.
  • the present invention is a method of manufacturing a semiconductor device, Flip-chip bonding the semiconductor chip to the circuit forming surface of the semiconductor wafer; and A step B of forming a sealing body by embedding the semiconductor chip flip-chip bonded to the semiconductor wafer in a sealing sheet; Step C for exposing the back surface of the semiconductor chip by grinding the sealing sheet of the sealing body; And a step D of dicing the sealing body exposed from the back surface of the semiconductor chip, It has a process of performing laser marking on the sealing sheet between the process B and the process C and / or between the process C and the process D.
  • the step B of forming a sealing body by embedding a semiconductor chip flip-chip bonded to a semiconductor wafer in a sealing sheet, and the sealing of the sealing body A step C of grinding the sheet to expose the back surface of the semiconductor chip; and a step D of dicing the sealing body from which the back surface of the semiconductor chip is exposed.
  • it has the process of laser-marking the said sheet
  • the sealing body and the semiconductor device are made to have mutual discrimination after the sealing sheet is ground. be able to.
  • the marking may disappear due to grinding in the process C.
  • the mutual identification between the encapsulant and the semiconductor device is performed again. It becomes possible to have.
  • the sealing body and the semiconductor device can be distinguished from each other in the manufacturing process of the semiconductor device.
  • a colorant is added to the surface of the sealing sheet opposite to the surface facing the semiconductor wafer. If a colorant is added to the surface of the sealing sheet opposite to the surface facing the semiconductor wafer, the visibility of the laser-marked portion can be improved.
  • the present invention it is possible to provide a method for manufacturing a semiconductor device that enables the sealing body and the semiconductor device to be distinguished from each other in the manufacturing process of the semiconductor device.
  • the manufacturing method of the semiconductor device is as follows: Flip-chip bonding the semiconductor chip to the circuit forming surface of the semiconductor wafer; and A step B of forming a sealing body by embedding the semiconductor chip flip-chip bonded to the semiconductor wafer in a sealing sheet; Step C for exposing the back surface of the semiconductor chip by grinding the sealing sheet of the sealing body; And a step D of dicing the sealing body exposed from the back surface of the semiconductor chip, At least a step of performing laser marking on the sealing sheet between the step B and the step C and / or between the step C and the step D is included.
  • FIG. 1 to 11 are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • the semiconductor chip 23 is flip-chip bonded to the circuit forming surface 22a of the semiconductor wafer 22 (step A).
  • a known device such as a flip chip bonder or a die bonder can be used.
  • the bumps 23b formed on the circuit formation surface 23a of the semiconductor chip 23 and the electrodes 22b formed on the circuit formation surface 22a of the semiconductor wafer 22 are electrically connected.
  • the resin sheet 24 for underfill may be affixed on the circuit formation surface 23a of the semiconductor chip 23.
  • the gap between the semiconductor chip 23 and the semiconductor wafer 22 can be resin-sealed.
  • a method for flip-chip bonding the semiconductor chip 23 to which the underfill resin sheet 24 is attached to the semiconductor wafer 22 is disclosed in, for example, Japanese Patent Application Laid-Open No. 2013-115186. Detailed description is omitted.
  • a sealing sheet 10 is prepared as shown in FIG.
  • the sealing sheet 10 may be prepared in a state of being laminated on a release liner 11 such as a polyethylene terephthalate (PET) film.
  • the release liner 11 may be subjected to a release treatment in order to easily peel the sealing sheet 10.
  • the constituent material of the sealing sheet 10 preferably includes an epoxy resin and a phenol resin as a curing agent. Thereby, favorable thermosetting is obtained.
  • the epoxy resin is not particularly limited.
  • triphenylmethane type epoxy resin, cresol novolac type epoxy resin, biphenyl type epoxy resin, modified bisphenol A type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, modified bisphenol F type epoxy resin, dicyclopentadiene type Various epoxy resins such as an epoxy resin, a phenol novolac type epoxy resin, and a phenoxy resin can be used. These epoxy resins may be used alone or in combination of two or more.
  • the epoxy equivalent is 150 to 250 and the softening point or the melting point is 50 to 130 ° C., solid at room temperature. From the viewpoint, triphenylmethane type epoxy resin, cresol novolac type epoxy resin, and biphenyl type epoxy resin are more preferable.
  • the phenol resin is not particularly limited as long as it causes a curing reaction with the epoxy resin.
  • a phenol novolac resin, a phenol aralkyl resin, a biphenyl aralkyl resin, a dicyclopentadiene type phenol resin, a cresol novolak resin, a resole resin, or the like is used.
  • These phenolic resins may be used alone or in combination of two or more.
  • phenol resin those having a hydroxyl equivalent weight of 70 to 250 and a softening point of 50 to 110 ° C. are preferably used from the viewpoint of reactivity with the epoxy resin, and phenol phenol is particularly preferable from the viewpoint of high curing reactivity.
  • a novolac resin can be suitably used. From the viewpoint of reliability, low hygroscopic materials such as phenol aralkyl resins and biphenyl aralkyl resins can also be suitably used.
  • the blending ratio of the epoxy resin and the phenol resin is blended so that the total of hydroxyl groups in the phenol resin is 0.7 to 1.5 equivalents with respect to 1 equivalent of the epoxy group in the epoxy resin from the viewpoint of curing reactivity. It is preferable to use 0.9 to 1.2 equivalents.
  • the total content of the epoxy resin and the phenol resin in the sealing sheet 10 is preferably 2.5% by weight or more, and more preferably 3.0% by weight or more. Adhesive force with respect to the semiconductor chip 23, the semiconductor wafer 22, etc. is acquired favorably as it is 2.5 weight% or more.
  • the total content of the epoxy resin and the phenol resin in the sealing sheet 10 is preferably 20% by weight or less, and more preferably 10% by weight or less. Hygroscopicity can be reduced as it is 20 weight% or less.
  • the sealing sheet 10 preferably contains a thermoplastic resin. Thereby, the handleability at the time of non-hardening and the low stress property of hardened
  • thermoplastic resin examples include natural rubber, butyl rubber, isoprene rubber, chloroprene rubber, ethylene-vinyl acetate copolymer, ethylene-acrylic acid copolymer, ethylene-acrylic acid ester copolymer, polybutadiene resin, polycarbonate resin, heat Plastic polyimide resin, polyamide resin such as 6-nylon and 6,6-nylon, phenoxy resin, acrylic resin, saturated polyester resin such as PET and PBT, polyamideimide resin, fluororesin, styrene-isobutylene-styrene block copolymer, etc. Is mentioned. These thermoplastic resins can be used alone or in combination of two or more. Of these, a styrene-isobutylene-styrene block copolymer is preferable from the viewpoint of low stress and low water absorption.
  • the content of the thermoplastic resin in the sealing sheet 10 is preferably 1.5% by weight or more, and more preferably 2.0% by weight or more. A softness
  • the content of the thermoplastic resin in the sealing sheet 10 is preferably 6% by weight or less, and more preferably 4% by weight or less. Adhesiveness with the semiconductor chip 23 and the semiconductor wafer 22 is favorable as it is 4 weight% or less.
  • the sealing sheet 10 preferably contains an inorganic filler.
  • the inorganic filler is not particularly limited, and various conventionally known fillers can be used.
  • quartz glass, talc, silica such as fused silica and crystalline silica
  • alumina aluminum nitride
  • nitriding Examples thereof include silicon and boron nitride powders. These may be used alone or in combination of two or more. Among these, silica and alumina are preferable, and silica is more preferable because the linear expansion coefficient can be satisfactorily reduced.
  • silica powder is preferable, and fused silica powder is more preferable.
  • fused silica powder examples include spherical fused silica powder and crushed fused silica powder. From the viewpoint of fluidity, spherical fused silica powder is preferable. Among these, those having an average particle diameter in the range of 10 to 30 ⁇ m are preferable, and those having a mean particle diameter in the range of 15 to 25 ⁇ m are more preferable.
  • the average particle diameter can be derived, for example, by using a sample arbitrarily extracted from the population and measuring it using a laser diffraction / scattering particle size distribution measuring apparatus.
  • the content of the inorganic filler in the sealing sheet 10 is preferably 75 to 95% by weight, and more preferably 78 to 95% by weight with respect to the entire sealing sheet 10.
  • the content of the inorganic filler is 75% by weight or more with respect to the entire sealing sheet 10
  • the mechanical expansion due to thermal shock can be suppressed by suppressing the thermal expansion coefficient low.
  • the content of the inorganic filler is 95% by weight or less with respect to the entire sealing sheet 10, flexibility, fluidity, and adhesiveness are further improved.
  • the sealing sheet 10 contains a curing accelerator.
  • the curing accelerator is not particularly limited as long as it can cure the epoxy resin and the phenol resin, and examples thereof include organophosphorus compounds such as triphenylphosphine and tetraphenylphosphonium tetraphenylborate; 2-phenyl-4, And imidazole compounds such as 5-dihydroxymethylimidazole and 2-phenyl-4-methyl-5-hydroxymethylimidazole.
  • organophosphorus compounds such as triphenylphosphine and tetraphenylphosphonium tetraphenylborate
  • 2-phenyl-4, And imidazole compounds such as 5-dihydroxymethylimidazole and 2-phenyl-4-methyl-5-hydroxymethylimidazole.
  • 2-phenyl-4,5-dihydroxymethylimidazole is preferred because the curing reaction does not proceed rapidly even when the temperature during kneading increases, and the sealing sheet 10 can be satisfactorily produced.
  • the content of the curing accelerator is preferably 0.1 to 5 parts by weight with respect to 100 parts by weight of the total of the epoxy resin and the phenol resin.
  • the sealing sheet 10 preferably contains a flame retardant component. This can reduce the expansion of combustion when ignition occurs due to component short-circuiting or heat generation.
  • a flame retardant component for example, various metal hydroxides such as aluminum hydroxide, magnesium hydroxide, iron hydroxide, calcium hydroxide, tin hydroxide, complex metal hydroxides; phosphazene flame retardants, etc. should be used. Can do.
  • the content of the phosphorus element contained in the phosphazene flame retardant is preferably 12% by weight or more.
  • the content of the flame retardant component in the sealing sheet 10 is preferably 10% by weight or more and more preferably 15% by weight or more in the total organic components (excluding the inorganic filler). A flame retardance is favorably acquired as it is 10 weight% or more.
  • the content of the thermoplastic resin in the sealing sheet 10 is preferably 30% by weight or less, and more preferably 25% by weight or less. When the content is 30% by weight or less, there is a tendency that there is little decrease in physical properties of the cured product (specifically, physical properties such as glass transition temperature and high temperature resin strength).
  • the sealing sheet 10 contains a silane coupling agent.
  • the silane coupling agent is not particularly limited, and examples thereof include 3-glycidoxypropyltrimethoxysilane.
  • the content of the silane coupling agent in the sealing sheet 10 is preferably 0.1 to 3% by weight. When the content is 0.1% by weight or more, sufficient strength of the cured product can be obtained and the water absorption rate can be lowered. If it is 3% by weight or less, the outgas amount can be lowered.
  • the sealing sheet 10 is preferably colored. Thereby, excellent marking properties and appearance can be exhibited, and a semiconductor device having an added-value appearance can be obtained. Since the colored sealing sheet 10 has excellent marking properties, it can be marked to give various information such as character information and graphic information. In particular, by controlling the coloring color, it is possible to visually recognize information (character information, graphic information, etc.) given by marking with excellent visibility. Furthermore, the sealing sheet 10 can be color-coded for each product. When the sealing sheet 10 is colored (when it is colorless and not transparent), it is not particularly limited as a color exhibited by coloring, but it is preferably a dark color such as black, blue, red, etc. It is suitable that it is black.
  • the dark basically, L * a * b * L * is defined by a color system, 60 or less (0 to 60) [preferably 50 or less (0 to 50), More preferably, it means a dark color of 40 or less (0 to 40)].
  • L * a * b * L * defined by the color system is 35 or less (0 to 35) [preferably 30 or less (0 to 30), more preferably 25 This means a blackish color which is (0 to 25) below.
  • a * and b * defined in the L * a * b * color system can be appropriately selected according to the value of L * .
  • a * and b * for example, both are preferably ⁇ 10 to 10, more preferably ⁇ 5 to 5, particularly in the range of ⁇ 3 to 3 (in particular, 0 or almost 0). Is preferred.
  • L * , a * , and b * defined in the L * a * b * color system are color difference meters (trade name “CR-200” manufactured by Minolta Co .; color difference meter). It is calculated
  • the L * a * b * color system is a color space recommended by the International Commission on Illumination (CIE) in 1976, and is a color space called the CIE 1976 (L * a * b * ) color system. It means that.
  • the L * a * b * color system is defined in JISZ 8729 in the Japanese Industrial Standard.
  • the sealing sheet 10 When the sealing sheet 10 is colored, a coloring material (coloring agent) can be used according to the target color.
  • the sealing sheet of the present invention may have a single layer structure or a plurality of layers, but at least a colorant is added to the side opposite to the surface facing the semiconductor wafer. It is preferable.
  • the entire encapsulating sheet may contain a colorant uniformly, and the colorant is present on the side opposite to the surface facing the semiconductor wafer.
  • a colorant may be contained in an unevenly distributed manner.
  • the colorant may be added to the layer on the side opposite to the surface facing the semiconductor wafer 22 and the colorant may not be added to the other layers.
  • the sealing sheet of the present invention has 10 single-layer sealing sheets
  • the case where the sealing sheet has two or more layers will be described later with reference to FIG. I decided to.
  • a color material various dark color materials such as a black color material, a blue color material, and a red color material can be suitably used, and a black color material is particularly suitable.
  • the color material any of a pigment, a dye and the like may be used. Color materials can be used alone or in combination of two or more.
  • the dye any form of dyes such as acid dyes, reactive dyes, direct dyes, disperse dyes, and cationic dyes can be used.
  • the form of the pigment is not particularly limited, and can be appropriately selected from known pigments.
  • the dye when a dye is used as the colorant, the dye is dissolved or evenly dispersed in the sealing sheet 10, so that the sealing sheet 10 having a uniform or almost uniform coloring density can be easily obtained. Can be manufactured, and marking properties and appearance can be improved.
  • the black color material is not particularly limited, and can be appropriately selected from, for example, inorganic black pigments and black dyes.
  • a black color material a color material mixture in which a cyan color material (blue-green color material), a magenta color material (red purple color material) and a yellow color material (yellow color material) are mixed. It may be.
  • Black color materials can be used alone or in combination of two or more.
  • the black color material can be used in combination with a color material other than black.
  • the black color material for example, carbon black (furnace black, channel black, acetylene black, thermal black, lamp black, etc.), graphite (graphite), copper oxide, manganese dioxide, azo pigment (azomethine) Azo black, etc.), aniline black, perylene black, titanium black, cyanine black, activated carbon, ferrite (nonmagnetic ferrite, magnetic ferrite, etc.), magnetite, chromium oxide, iron oxide, molybdenum disulfide, chromium complex, complex oxide black Examples thereof include dyes and anthraquinone organic black dyes.
  • black color material C.I. I. Solvent Black 3, 7, 22, 27, 29, 34, 43, 70, C.I. I. Direct Black 17, 19, 19, 22, 32, 38, 51, 71, C.I. I. Acid Black 1, 2, 24, 26, 31, 48, 52, 107, 109, 110, 119, 154C.
  • Black dyes such as Disperse Black 1, 3, 10, and 24;
  • Black pigments such as CI Pigment Black 1 and 7 can also be used.
  • Examples of such a black color material include a product name “OilOBlack BY”, a product name “OilBlack BS”, a product name “OilBlackHBB”, a product name “Oil Black803”, a product name “Oil Black860”, and a product name “Oil Black860”.
  • Oil Black 5970 ”, trade name“ Oil Black 5906 ”, trade name“ Oil Black 5905 ”(manufactured by Orient Chemical Co., Ltd.) and the like are commercially available.
  • color materials other than black color materials include cyan color materials, magenta color materials, and yellow color materials.
  • cyan color materials include C.I. I. Solvent Blue 25, 36, 60, 70, 93, 95; I. Cyan dyes such as Acid Blue 6 and 45; I. Pigment Blue 1, 2, 3, 15, 15: 1, 15: 2, 15: 3, 15: 3, 15: 4, 15: 5, 15: 6, 16, 16, 17 17: 1, 18, 22, 25, 56, 60, 63, 65, 66; I. Bat Blue 4; 60, C.I. I. And cyan pigments such as CI Pigment Green 7.
  • magenta dye examples include C.I. I. Solvent Red 1, 3, 8, 23, 24, 25, 27, 30, 30, 49, 52, 58, 63, 81, 82, 83, 84, the same 100, 109, 111, 121, 122; I. Disper thread 9; I. Solvent Violet 8, 13, 13, 21, and 27; C.I. I. Disperse violet 1; C.I. I. Basic Red 1, 2, 9, 9, 13, 14, 15, 17, 17, 18, 22, 23, 24, 27, 29, 32, 34, the same 35, 36, 37, 38, 39, 40; I. Basic Violet 1, 3, 7, 10, 14, 15, 21, 21, 25, 26, 27, 28 and the like.
  • magenta pigment examples include C.I. I. Pigment Red 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 21, 22, 23, 30, 31, 32, 37, 38, 39, 40, 41, 42, 48: 1, 48: 2, 48: 3, 48: 4, 49, 49: 1, 50, 51, 52, 52: 2, 53: 1, 54, 55, 56, 57: 1, 58, 60, 60: 1, 63, 63: 1, 63: 2, 64, 64: 1, 67, 68, 81, 83, etc.
  • yellow color materials include C.I. I. Solvent Yellow 19, 44, 77, 79, 81, 82, 93, 98, 103, 104, 112, 162 and the like yellow dyes; C.I. I. Pigment Orange 31 and 43; C.I. I.
  • Various color materials such as a cyan color material, a magenta color material, and a yellow color material can be used alone or in combination of two or more.
  • the mixing ratio (or blending ratio) of these color materials is not particularly limited, and each color material. It can be selected as appropriate according to the type and the target color.
  • the light transmittance (visible light transmittance) by visible light (wavelength: 380 nm to 800 nm) in the sealing sheet 10 is not particularly limited, but is preferably in the range of 20% to 0%, for example. Is from 10% to 0%, particularly preferably from 5% to 0%.
  • the visible light transmittance of the sealing sheet 10 is set to 20% or less, the print visibility can be improved. Further, it is possible to prevent an adverse effect on the semiconductor element due to the passage of light.
  • the visible light transmittance (%) of the sealing sheet 10 is such that the sealing sheet 10 having a thickness (average thickness): 10 ⁇ m is prepared, and the sealing sheet 10 (thickness: 10 ⁇ m) Using “UV-2550” (manufactured by Shimadzu Corporation), visible light having a wavelength of 380 nm to 800 nm is irradiated with a predetermined intensity.
  • the light intensity of visible light transmitted through the sealing sheet 10 by this irradiation can be measured and calculated by the following formula.
  • Visible light transmittance (%) ((light intensity of visible light after transmission through sealing sheet 10) / (initial light intensity of visible light)) ⁇ 100
  • the said calculation method of light transmittance (%) is applicable also to calculation of the light transmittance (%) of the sheet
  • the absorbance A 10 at 10 ⁇ m can be calculated as follows according to Lambert Beer's law.
  • a 10 ⁇ ⁇ L 10 ⁇ C (1) (Where L 10 is the optical path length, ⁇ is the extinction coefficient, and C is the sample concentration) Also, the absorbance A X of a thickness X ([mu] m) can be represented by the following formula (2).
  • a X ⁇ ⁇ L X ⁇ C (2)
  • the absorbance A 20 at a thickness of 20 ⁇ m can be expressed by the following formula (3).
  • the thickness (average thickness) of the sealing sheet when determining the light transmittance (%) of the sealing sheet is 10 ⁇ m.
  • the thickness of the sealing sheet is only sealed. It is the thickness at the time of obtaining the light transmittance (%) of the stop sheet, and does not mean that the sealing sheet in the present invention is 10 ⁇ m.
  • the light transmittance (%) of the sealing sheet 10 is controlled by the type and content of the resin component, the type and content of the colorant (pigment, dye, etc.), the type and content of the filler, and the like. be able to.
  • the thickness of the sealing sheet 10 is not particularly limited, but is, for example, 50 ⁇ m to 2000 ⁇ m from the viewpoint of use as a sealing sheet.
  • seat 10 for sealing is not specifically limited, The method of coating the kneaded material obtained by preparing the kneaded material of the resin composition for forming the sheet
  • a kneaded product is prepared by melt-kneading each component described below with a known kneader such as a mixing roll, a pressure kneader, or an extruder, and the obtained kneaded product is coated or plastically processed into a sheet. Shape.
  • the temperature is preferably equal to or higher than the softening point of each component described above, for example, 30 to 150 ° C., and preferably 40 to 140 ° C., more preferably 60 to 120 in consideration of the thermosetting property of the epoxy resin. ° C.
  • the time is, for example, 1 to 30 minutes, preferably 5 to 15 minutes.
  • the kneading is preferably performed under reduced pressure conditions (under reduced pressure atmosphere). Thereby, while being able to deaerate, the penetration
  • the pressure under reduced pressure is preferably 0.1 kg / cm 2 or less, more preferably 0.05 kg / cm 2 or less.
  • the lower limit of the pressure under reduced pressure is not particularly limited, but is, for example, 1 ⁇ 10 ⁇ 4 kg / cm 2 or more.
  • the kneaded material after melt-kneading is applied in a high temperature state without cooling.
  • the coating method is not particularly limited, and examples thereof include a bar coating method, a knife coating method, and a slot die method.
  • the temperature at the time of coating is preferably not less than the softening point of each component described above, and considering the thermosetting property and moldability of the epoxy resin, for example, 40 to 150 ° C., preferably 50 to 140 ° C., more preferably 70 to 120 ° C.
  • the kneaded material after melt-kneading is plastically processed in a high temperature state without cooling.
  • the plastic working method is not particularly limited, and examples thereof include a flat plate pressing method, a T-die extrusion method, a screw die extrusion method, a roll rolling method, a roll kneading method, an inflation extrusion method, a coextrusion method, and a calendar molding method.
  • the plastic working temperature is preferably not less than the softening point of each component described above, and is 40 to 150 ° C., preferably 50 to 140 ° C., more preferably 70 to 120 ° C. in consideration of the thermosetting property and moldability of the epoxy resin. is there.
  • the sealing sheet 10 can also be obtained by dissolving and dispersing a resin or the like for forming the sealing sheet 10 in an appropriate solvent to adjust the varnish and coating the varnish.
  • Step of arranging sealing sheet and laminate After the step of preparing the sealing sheet, as shown in FIG. 3, the stacked body 20 is disposed on the lower heating plate 32 with the surface on which the semiconductor chip 23 is mounted facing upward, and the semiconductor of the stacked body 20 The sealing sheet 10 is disposed on the surface on which the chip 23 is mounted.
  • the laminated body 20 may be first disposed on the lower heating plate 32, and then the sealing sheet 10 may be disposed on the laminated body 20, and the sealing sheet 10 may be disposed on the laminated body 20.
  • a laminate obtained by laminating first and then laminating the laminate 20 and the sealing sheet 10 may be disposed on the lower heating plate 32.
  • Step B the semiconductor chip 23 is embedded in the sealing sheet 10 by hot pressing with the lower heating plate 32 and the upper heating plate 34 (step B).
  • the sealing sheet 10 functions as a sealing resin for protecting the semiconductor chip 23 and its accompanying elements from the external environment. Thereby, the sealing body 28 in which the semiconductor chip 23 mounted on the semiconductor wafer 22 is embedded in the sealing sheet 10 is obtained.
  • the temperature is, for example, 40 to 100 ° C., preferably 50 to 90 ° C.
  • the pressure is, for example, 0.1 to 10 MPa, preferably Is 0.5 to 8 MPa
  • the time is, for example, 0.3 to 10 minutes, preferably 0.5 to 5 minutes.
  • the pressure reducing conditions the pressure is, for example, 0.1 to 5 kPa, preferably 0.1 to 100 Pa, and the reduced pressure holding time (the time from the start of pressure reduction to the start of pressing) is, for example, 5 to 600 seconds. Yes, preferably 10 to 300 seconds.
  • the sealing sheet 10 is thermoset. Specifically, for example, the entire sealing body 28 in which the semiconductor chip 23 mounted on the semiconductor wafer 22 is embedded in the sealing sheet 10 is heated.
  • the heating temperature is preferably 100 ° C or higher, more preferably 120 ° C or higher.
  • the upper limit of the heating temperature is preferably 200 ° C. or lower, more preferably 180 ° C. or lower.
  • the heating time is preferably 10 minutes or more, more preferably 30 minutes or more.
  • the upper limit of the heating time is preferably 180 minutes or less, more preferably 120 minutes or less.
  • you may pressurize as needed Preferably it is 0.1 Mpa or more, More preferably, it is 0.5 Mpa or more.
  • the upper limit is preferably 10 MPa or less, more preferably 5 MPa or less.
  • laser marking step 1 laser marking step before grinding sealing sheet
  • laser marking is performed on the sealing sheet 10 using a laser marking laser 36 (hereinafter also referred to as “step E-1”).
  • the conditions for laser marking are not particularly limited, but it is preferable to irradiate the sealing sheet 10 with laser [wavelength: 532 nm] under the conditions of intensity: 0.3 W to 2.0 W. Moreover, it is preferable to irradiate so that the processing depth (depth) in this case may be 2 ⁇ m or more.
  • the upper limit of the processing depth is not particularly limited, but can be selected, for example, from a range of 2 ⁇ m to 25 ⁇ m, preferably 3 ⁇ m or more (3 ⁇ m to 20 ⁇ m), more preferably 5 ⁇ m or more (5 ⁇ m to 15 ⁇ m). .
  • excellent laser marking properties are exhibited.
  • the laser workability of the sealing sheet 10 includes the type and content of the constituent resin component, the type and content of the colorant, the type and content of the crosslinking agent, the type and content of the filler, and the like. Can be controlled.
  • the place where laser marking is performed on the sealing sheet 10 is not particularly limited, and may be directly above the semiconductor chip 23, or above the place where the semiconductor chip 23 is not disposed (for example, Or the outer peripheral portion of the sealing sheet 10).
  • the information marked by the laser marking may be character information, graphic information, or the like for enabling distinction in units of sealing bodies. It may be character information, graphic information, or the like for enabling distinction.
  • the sealing sheet 10 of the sealing body 28 is ground to expose the back surface 23c of the semiconductor chip 23 (step C).
  • the method for grinding the sealing sheet 10 is not particularly limited, and examples thereof include a grinding method using a grindstone that rotates at high speed. It should be noted that the marking applied in step E-1 disappears when the thickness ground in step C is thicker than the marking depth (processing depth). On the other hand, if the thickness ground in step C is thinner than the marking depth (processing depth), the marking remains.
  • laser marking process 2 laser marking process after grinding of sealing sheet
  • laser marking is performed on the sealing sheet 10 using a laser marking laser 38 (hereinafter also referred to as “step E-2”).
  • the conditions for laser marking are not particularly limited, but it is preferable to irradiate the sealing sheet 10 with laser [wavelength: 532 nm] under the conditions of intensity: 0.3 W to 2.0 W. Moreover, it is preferable to irradiate so that the processing depth (depth) in this case may be 2 ⁇ m or more.
  • the upper limit of the processing depth is not particularly limited, but can be selected, for example, from a range of 2 ⁇ m to 25 ⁇ m, preferably 3 ⁇ m or more (3 ⁇ m to 20 ⁇ m), more preferably 5 ⁇ m or more (5 ⁇ m to 15 ⁇ m). .
  • excellent laser marking properties are exhibited.
  • the place where the laser marking is performed on the sealing sheet 10 is not particularly limited, but may be above the place where the semiconductor chip 23 is not disposed.
  • the information marked by the laser marking may be character information, graphic information, or the like for enabling distinction in units of sealing bodies. It may be character information, graphic information, or the like for enabling distinction.
  • the sealing body 28 and the semiconductor device are made to have mutual discrimination again even after the sealing sheet 10 is ground. It becomes possible. Further, the information marked by laser marking may be graphic information for alignment (alignment mark) that can be used in a dicing process described later.
  • the surface of the semiconductor wafer 22 opposite to the side on which the semiconductor chip 23 is mounted is ground to form a via (Via) 22c (see FIG. 9), and then the wiring layer 27 having the wiring 27a. (See FIG. 10).
  • the method for grinding the semiconductor wafer 22 is not particularly limited, and examples thereof include a grinding method using a grindstone that rotates at high speed.
  • bumps 27b protruding from the wiring 27a may be formed.
  • Conventionally known circuit board and interposer manufacturing techniques such as a semi-additive method and a subtractive method can be applied to the method of forming the wiring layer 27, and thus detailed description thereof is omitted here.
  • a substrate mounting step for mounting the semiconductor device 29 on a separate substrate can be performed.
  • a known device such as a flip chip bonder or a die bonder can be used.
  • the sealing body and the semiconductor device can be distinguished from each other in the manufacturing process of the semiconductor device.
  • the timing of performing the step E-1 is not limited to this example.
  • the timing of performing the step E-1 may be after the step of forming the sealing body and before the release liner peeling step. Further, it may be after the release liner peeling step and before the thermosetting step.
  • thermosetting process for thermosetting the sealing sheet of the sealing body is performed after the process B (sealing body forming process) and before the process C (sealing sheet grinding process).
  • the timing which performs the said thermosetting process is not limited to this example, You may carry out simultaneously with the process A (process which forms a sealing body). Further, the thermosetting step may be performed after step E-1 (laser marking step before grinding the sealing sheet).
  • the release liner 11 is peeled before the thermosetting process has been described.
  • the release liner 11 may be peeled after the thermosetting process.
  • this invention is not limited to embodiment mentioned above, Between the said process B and the said process C, and / or between the said process C and the said process D, the laser marking is carried out to the sheet
  • the sealing sheet of the present invention has one layer. Next, the case where the sealing sheet has two layers will be described.
  • seat for sealing of this invention is not limited to 1 layer structure or 2 layer structure, Furthermore, the other layer may be provided.
  • FIG. 12 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention.
  • the sealing sheet 110 includes a marking layer 112 and a sealing layer 114.
  • FIG. 12 shows a state where the release sheet is peeled off after the semiconductor chip 23 is embedded in the sealing sheet 110 in the stacked body 20 in which the semiconductor chip 23 is mounted on the semiconductor wafer 22.
  • the sealing sheet 110 is disposed so that the surface opposite to the surface facing the semiconductor wafer 22 becomes the marking layer 112.
  • FIG. 12 corresponds to the state of FIG. 5 except that the sealing sheet has two layers or one layer. Since the method for manufacturing the semiconductor device described with reference to FIGS. 1 to 11 is the same as that described with reference to FIGS. 1 to 11 except that the encapsulating sheet has one layer or two layers, the description other than the differences is omitted. I decided to.
  • the sealing layer 114 has a function for embedding the semiconductor chip 23.
  • the constituent material of the sealing layer 114 can be basically the same as that of the sealing sheet 10.
  • a colorant is not added. This is because a disadvantage (for example, a decrease in storage stability) due to the addition of an unnecessary colorant can be avoided.
  • the marking layer 112 is a layer on which laser marking is performed, and preferably has a configuration in which the visibility of marking by laser marking is good.
  • the constituent material of the marking layer 112 can be basically the same as that of the sealing sheet 10. However, it is preferable that a colorant is added to the marking layer 112 because laser marking is performed.
  • the light transmittance (visible light transmittance) of visible light (wavelength: 380 nm to 800 nm) in the marking layer 112 is not particularly limited, but is preferably in the range of 20% to 0%, and more preferably 10%, for example. % To 0%, particularly preferably 5% to 0%.
  • the visible light transmittance of the sealing sheet 10 By setting the visible light transmittance of the sealing sheet 10 to 20% or less, the print visibility can be improved. Further, it is possible to prevent an adverse effect on the semiconductor element due to the passage of light.
  • the visible light transmittance of the sealing layer 114 is not particularly limited, but a configuration in which a colorant is not added is preferable.
  • the thickness of the sealing layer 114 is thinner than the thickness of the semiconductor chip 23 (the total thickness of the semiconductor chip 23 and the bump 23b when bumps are provided). It can be configured. In such a configuration, the marking layer 112 is left so as to surround the semiconductor chip 23 in a plan view even after the process C. As a result, it is possible to perform laser marking on the sealing sheet 110 (marking layer 112) between the process C and the process D.
  • the present invention is not limited to the above-described example, and it is possible to make design changes as appropriate within a range that satisfies the configuration of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)

Abstract

A method for manufacturing a semiconductor device, which comprises: a step (A) wherein a semiconductor chip is flip-chip bonded to a circuit formation surface of a semiconductor wafer; a step (B) wherein a package is formed by embedding the semiconductor chip, which has been flip-chip bonded to the semiconductor wafer, in an encapsulation sheet; a step (C) wherein the back surface of the semiconductor chip is exposed to the outside by grinding the encapsulation sheet of the package; and a step (D) wherein the package, from which the back surface of the semiconductor chip is exposed, is diced. This method for manufacturing a semiconductor device also comprises a step wherein the encapsulation sheet is subjected to laser marking after the step (B) and before the step (C) and/or after the step (C) and before the step (D).

Description

半導体装置の製造方法Manufacturing method of semiconductor device
　本発明は、半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device.
　従来、半導体装置の製造方法としては、基板などに固定された１又は複数の半導体チップを封止樹脂にて封止した後、封止体を半導体装置単位のパッケージとなるようにダイシングするという方法が知られている。このような封止樹脂としては、例えば、熱硬化性樹脂シートが知られている（例えば、特許文献１参照）。 Conventionally, as a method for manufacturing a semiconductor device, one or a plurality of semiconductor chips fixed to a substrate or the like is sealed with a sealing resin, and then the sealing body is diced into a package of a semiconductor device unit. It has been known. As such a sealing resin, for example, a thermosetting resin sheet is known (see, for example, Patent Document 1).
特開２００６－１９７１４号公報JP 2006-19714 A
　半導体装置の製造においては、封止体や半導体装置を互いに識別できるようにしておくことが好ましい。 In the manufacture of a semiconductor device, it is preferable that the sealing body and the semiconductor device can be distinguished from each other.
　本発明は上述した課題に鑑みてなされたものであり、その目的は、半導体装置の製造工程において封止体や半導体装置を互いに識別することを可能とする半導体装置の製造方法を提供することにある。 The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that enables a sealing body and a semiconductor device to be distinguished from each other in the manufacturing process of the semiconductor device. is there.
　本願発明者等は、下記の構成を採用することにより、前記の課題を解決できることを見出して本発明を完成させるに至った。 The inventors of the present application have found that the above-mentioned problems can be solved by adopting the following configuration, and have completed the present invention.
　すなわち、本発明は、半導体装置の製造方法であって、
　半導体チップを半導体ウエハの回路形成面にフリップチップボンディングする工程Ａと、
　前記半導体ウエハにフリップチップボンディングされた前記半導体チップを封止用シートに埋め込んで封止体を形成する工程Ｂと、
　前記封止体の前記封止用シートを研削して前記半導体チップの裏面を表出させる工程Ｃと、
　前記半導体チップの裏面が表出している前記封止体をダイシングする工程Ｄとを有し、
　前記工程Ｂ以降前記工程Ｃまでの間、及び／又は、前記工程Ｃ以降前記工程Ｄまでの間に、前記封止用シートにレーザーマーキングを行なう工程を有することを特徴とする。 That is, the present invention is a method of manufacturing a semiconductor device,
Flip-chip bonding the semiconductor chip to the circuit forming surface of the semiconductor wafer; and
A step B of forming a sealing body by embedding the semiconductor chip flip-chip bonded to the semiconductor wafer in a sealing sheet;
Step C for exposing the back surface of the semiconductor chip by grinding the sealing sheet of the sealing body;
And a step D of dicing the sealing body exposed from the back surface of the semiconductor chip,
It has a process of performing laser marking on the sealing sheet between the process B and the process C and / or between the process C and the process D.
　本発明に係る半導体装置の製造方法によれば、半導体ウエハにフリップチップボンディングされた半導体チップを封止用シートに埋め込んで封止体を形成する工程Ｂと、前記封止体の前記封止用シートを研削して前記半導体チップの裏面を表出させる工程Ｃと、前記半導体チップの裏面が表出している前記封止体をダイシングする工程Ｄとを有する。
　そして、前記工程Ｂ以降前記工程Ｃまでの間、及び／又は、前記工程Ｃ以降前記工程Ｄまでの間に、前記封止用シートにレーザーマーキングを行なう工程を有する。
　前記工程Ｂ以降前記工程Ｃまでの間に、前記封止用シートにレーザーマーキングを行なうと、封止用シートが研削されるまでの間における、封止体や半導体装置の相互識別性を持たせることができる。
　また、前記工程Ｃ以降前記工程Ｄまでの間に、前記封止用シートにレーザーマーキングを行なうと、封止用シートが研削された後における、封止体や半導体装置の相互識別性を持たせることができる。特に、前記工程Ｂ以降前記工程Ｃまでの間に、前記封止用シートにレーザーマーキングが行なわれていたとしても、前記工程Ｃにおける研削により、マーキングは消えてしまう場合がある。しかしながら、前記工程Ｃ以降前記工程Ｄまでの間に、前記封止用シートにレーザーマーキングを行なうと、封止用シートが研削された後においても、再び、封止体や半導体装置の相互識別性を持たせることが可能となる。
　このように、前記構成によれば、半導体装置の製造工程において封止体や半導体装置を互いに識別することが可能となる。 According to the method for manufacturing a semiconductor device of the present invention, the step B of forming a sealing body by embedding a semiconductor chip flip-chip bonded to a semiconductor wafer in a sealing sheet, and the sealing of the sealing body A step C of grinding the sheet to expose the back surface of the semiconductor chip; and a step D of dicing the sealing body from which the back surface of the semiconductor chip is exposed.
And it has the process of laser-marking the said sheet | seat for sealing between the said process B and the said process C and / or between the said process C and the said process D.
When laser marking is performed on the sealing sheet between the process B and the process C, the sealing body and the semiconductor device are given mutual identification until the sealing sheet is ground. be able to.
Further, when laser marking is performed on the sealing sheet between the process C and the process D, the sealing body and the semiconductor device are made to have mutual discrimination after the sealing sheet is ground. be able to. In particular, even if laser marking is performed on the sealing sheet between the process B and the process C, the marking may disappear due to grinding in the process C. However, if laser marking is performed on the encapsulating sheet between the process C and the process D, even after the encapsulating sheet is ground, the mutual identification between the encapsulant and the semiconductor device is performed again. It becomes possible to have.
Thus, according to the above configuration, the sealing body and the semiconductor device can be distinguished from each other in the manufacturing process of the semiconductor device.
　前記構成において、前記封止用シートにおける前記半導体ウエハと対向する面とは反対の面側には、着色剤が添加されていることが好ましい。前記封止用シートにおける前記半導体ウエハと対向する面とは反対の面側に着色剤が添加されていると、レーザーマーキングされた部分の視認性を向上させることができる。 In the above configuration, it is preferable that a colorant is added to the surface of the sealing sheet opposite to the surface facing the semiconductor wafer. If a colorant is added to the surface of the sealing sheet opposite to the surface facing the semiconductor wafer, the visibility of the laser-marked portion can be improved.
　本発明によれば、半導体装置の製造工程において封止体や半導体装置を互いに識別することを可能とする半導体装置の製造方法を提供することができる。 According to the present invention, it is possible to provide a method for manufacturing a semiconductor device that enables the sealing body and the semiconductor device to be distinguished from each other in the manufacturing process of the semiconductor device.
本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の他の実施形態に係る半導体装置の製造方法を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device which concerns on other embodiment of this invention.
　以下、本発明の実施形態について、図面を参照しつつ説明する。ただし、本発明はこれらの実施形態のみに限定されるものではない。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited only to these embodiments.
　本実施形態に係る半導体装置の製造方法は、
　半導体チップを半導体ウエハの回路形成面にフリップチップボンディングする工程Ａと、
　前記半導体ウエハにフリップチップボンディングされた前記半導体チップを封止用シートに埋め込んで封止体を形成する工程Ｂと、
　前記封止体の前記封止用シートを研削して前記半導体チップの裏面を表出させる工程Ｃと、
　前記半導体チップの裏面が表出している前記封止体をダイシングする工程Ｄとを有し、
　前記工程Ｂ以降前記工程Ｃまでの間、及び／又は、前記工程Ｃ以降前記工程Ｄまでの間に、前記封止用シートにレーザーマーキングを行なう工程を少なくとも有する。 The manufacturing method of the semiconductor device according to this embodiment is as follows:
Flip-chip bonding the semiconductor chip to the circuit forming surface of the semiconductor wafer; and
A step B of forming a sealing body by embedding the semiconductor chip flip-chip bonded to the semiconductor wafer in a sealing sheet;
Step C for exposing the back surface of the semiconductor chip by grinding the sealing sheet of the sealing body;
And a step D of dicing the sealing body exposed from the back surface of the semiconductor chip,
At least a step of performing laser marking on the sealing sheet between the step B and the step C and / or between the step C and the step D is included.
　図１～図１１は、本発明の一実施形態に係る半導体装置の製造方法を説明するための断面模式図である。 1 to 11 are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.
　［準備工程］
　図１に示すように、本実施形態に係る半導体装置の製造方法では、まず、回路形成面２３ａを有する１又は複数の半導体チップ２３と、回路形成面２２ａを有する半導体ウエハ２２とを準備する。なお、以下では、複数の半導体チップを半導体ウエハにフリップチップボンディングする場合について説明する。 [Preparation process]
As shown in FIG. 1, in the method for manufacturing a semiconductor device according to this embodiment, first, one or a plurality of semiconductor chips 23 having a circuit forming surface 23a and a semiconductor wafer 22 having a circuit forming surface 22a are prepared. In the following, a case where a plurality of semiconductor chips are flip-chip bonded to a semiconductor wafer will be described.
　［半導体チップをフリップチップボンディングする工程］
　次に、図２に示すように、半導体チップ２３を半導体ウエハ２２の回路形成面２２ａにフリップチップボンディングする（工程Ａ）。半導体チップ２３の半導体ウエハ２２への搭載には、フリップチップボンダーやダイボンダーなどの公知の装置を用いることができる。具体的には、半導体チップ２３の回路形成面２３ａに形成されたバンプ２３ｂと、半導体ウエハ２２の回路形成面２２ａに形成された電極２２ｂとを電気的に接続する。これにより、複数の半導体チップ２３が半導体ウエハ２２に実装された積層体２０が得られる。この際、半導体チップ２３の回路形成面２３ａにアンダーフィル用の樹脂シート２４が貼り付けられていてもよい。この場合、半導体チップ２３を半導体ウエハ２２にフリップチップボンディングすると、半導体チップ２３と半導体ウエハ２２との間の間隙を樹脂封止することができる。なお、アンダーフィル用の樹脂シート２４が貼り付けられた半導体チップ２３を半導体ウエハ２２にフリップチップボンディングする方法については、例えば、特開２０１３－１１５１８６号公報等に開示されているため、ここでの詳細な説明は省略する。 [Process for flip chip bonding of semiconductor chip]
Next, as shown in FIG. 2, the semiconductor chip 23 is flip-chip bonded to the circuit forming surface 22a of the semiconductor wafer 22 (step A). For mounting the semiconductor chip 23 on the semiconductor wafer 22, a known device such as a flip chip bonder or a die bonder can be used. Specifically, the bumps 23b formed on the circuit formation surface 23a of the semiconductor chip 23 and the electrodes 22b formed on the circuit formation surface 22a of the semiconductor wafer 22 are electrically connected. Thereby, the stacked body 20 in which the plurality of semiconductor chips 23 are mounted on the semiconductor wafer 22 is obtained. Under the present circumstances, the resin sheet 24 for underfill may be affixed on the circuit formation surface 23a of the semiconductor chip 23. FIG. In this case, if the semiconductor chip 23 is flip-chip bonded to the semiconductor wafer 22, the gap between the semiconductor chip 23 and the semiconductor wafer 22 can be resin-sealed. Note that a method for flip-chip bonding the semiconductor chip 23 to which the underfill resin sheet 24 is attached to the semiconductor wafer 22 is disclosed in, for example, Japanese Patent Application Laid-Open No. 2013-115186. Detailed description is omitted.
　［封止用シートを準備する工程］
　また、本実施形態に係る半導体装置の製造方法では、図３に示すように、封止用シート１０を準備する。封止用シート１０は、ポリエチレンテレフタレート（ＰＥＴ）フィルムなどの剥離ライナー１１上に積層された状態で準備してもよい。この場合、剥離ライナー１１には封止用シート１０の剥離を容易に行うために離型処理が施されていてもよい。 [Step of preparing a sealing sheet]
Further, in the method for manufacturing a semiconductor device according to the present embodiment, a sealing sheet 10 is prepared as shown in FIG. The sealing sheet 10 may be prepared in a state of being laminated on a release liner 11 such as a polyethylene terephthalate (PET) film. In this case, the release liner 11 may be subjected to a release treatment in order to easily peel the sealing sheet 10.
　（封止用シート）
　封止用シート１０の構成材料は、エポキシ樹脂、及び、硬化剤としてのフェノール樹脂を含むことが好ましい。これにより、良好な熱硬化性が得られる。 (Sealing sheet)
The constituent material of the sealing sheet 10 preferably includes an epoxy resin and a phenol resin as a curing agent. Thereby, favorable thermosetting is obtained.
　前記エポキシ樹脂としては、特に限定されるものではない。例えば、トリフェニルメタン型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂、ビフェニル型エポキシ樹脂、変性ビスフェノールＡ型エポキシ樹脂、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、変性ビスフェノールＦ型エポキシ樹脂、ジシクロペンタジエン型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、フェノキシ樹脂などの各種のエポキシ樹脂を用いることができる。これらエポキシ樹脂は単独で用いてもよいし２種以上併用してもよい。 The epoxy resin is not particularly limited. For example, triphenylmethane type epoxy resin, cresol novolac type epoxy resin, biphenyl type epoxy resin, modified bisphenol A type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, modified bisphenol F type epoxy resin, dicyclopentadiene type Various epoxy resins such as an epoxy resin, a phenol novolac type epoxy resin, and a phenoxy resin can be used. These epoxy resins may be used alone or in combination of two or more.
　エポキシ樹脂の硬化後の靭性及びエポキシ樹脂の反応性を確保する観点からは、エポキシ当量１５０～２５０、軟化点もしくは融点が５０～１３０℃の常温で固形のものが好ましく、なかでも、信頼性の観点から、トリフェニルメタン型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂、ビフェニル型エポキシ樹脂がより好ましい。 From the viewpoint of ensuring the toughness of the epoxy resin after curing and the reactivity of the epoxy resin, it is preferable that the epoxy equivalent is 150 to 250 and the softening point or the melting point is 50 to 130 ° C., solid at room temperature. From the viewpoint, triphenylmethane type epoxy resin, cresol novolac type epoxy resin, and biphenyl type epoxy resin are more preferable.
　前記フェノール樹脂は、エポキシ樹脂との間で硬化反応を生起するものであれば特に限定されるものではない。例えば、フェノールノボラック樹脂、フェノールアラルキル樹脂、ビフェニルアラルキル樹脂、ジシクロペンタジエン型フェノール樹脂、クレゾールノボラック樹脂、レゾール樹脂などが用いられる。これらフェノール樹脂は単独で用いてもよいし、２種以上併用してもよい。 The phenol resin is not particularly limited as long as it causes a curing reaction with the epoxy resin. For example, a phenol novolac resin, a phenol aralkyl resin, a biphenyl aralkyl resin, a dicyclopentadiene type phenol resin, a cresol novolak resin, a resole resin, or the like is used. These phenolic resins may be used alone or in combination of two or more.
　前記フェノール樹脂としては、エポキシ樹脂との反応性の観点から、水酸基当量が７０～２５０、軟化点が５０～１１０℃のものを用いることが好ましく、なかでも硬化反応性が高いという観点から、フェノールノボラック樹脂を好適に用いることができる。また、信頼性の観点から、フェノールアラルキル樹脂やビフェニルアラルキル樹脂のような低吸湿性のものも好適に用いることができる。 As the phenol resin, those having a hydroxyl equivalent weight of 70 to 250 and a softening point of 50 to 110 ° C. are preferably used from the viewpoint of reactivity with the epoxy resin, and phenol phenol is particularly preferable from the viewpoint of high curing reactivity. A novolac resin can be suitably used. From the viewpoint of reliability, low hygroscopic materials such as phenol aralkyl resins and biphenyl aralkyl resins can also be suitably used.
　エポキシ樹脂とフェノール樹脂の配合割合は、硬化反応性という観点から、エポキシ樹脂中のエポキシ基１当量に対して、フェノール樹脂中の水酸基の合計が０．７～１．５当量となるように配合することが好ましく、より好ましくは０．９～１．２当量である。 The blending ratio of the epoxy resin and the phenol resin is blended so that the total of hydroxyl groups in the phenol resin is 0.7 to 1.5 equivalents with respect to 1 equivalent of the epoxy group in the epoxy resin from the viewpoint of curing reactivity. It is preferable to use 0.9 to 1.2 equivalents.
　封止用シート１０中のエポキシ樹脂及びフェノール樹脂の合計含有量は、２．５重量％以上が好ましく、３．０重量％以上がより好ましい。２．５重量％以上であると、半導体チップ２３、半導体ウエハ２２などに対する接着力が良好に得られる。封止用シート１０中のエポキシ樹脂及びフェノール樹脂の合計含有量は、２０重量％以下が好ましく、１０重量％以下がより好ましい。２０重量％以下であると、吸湿性を低減できる。 The total content of the epoxy resin and the phenol resin in the sealing sheet 10 is preferably 2.5% by weight or more, and more preferably 3.0% by weight or more. Adhesive force with respect to the semiconductor chip 23, the semiconductor wafer 22, etc. is acquired favorably as it is 2.5 weight% or more. The total content of the epoxy resin and the phenol resin in the sealing sheet 10 is preferably 20% by weight or less, and more preferably 10% by weight or less. Hygroscopicity can be reduced as it is 20 weight% or less.
　封止用シート１０は、熱可塑性樹脂を含むことが好ましい。これにより、未硬化時のハンドリング性や、硬化物の低応力性が得られる。 The sealing sheet 10 preferably contains a thermoplastic resin. Thereby, the handleability at the time of non-hardening and the low stress property of hardened | cured material are acquired.
　前記熱可塑性樹脂としては、天然ゴム、ブチルゴム、イソプレンゴム、クロロプレンゴム、エチレン－酢酸ビニル共重合体、エチレン－アクリル酸共重合体、エチレン－アクリル酸エステル共重合体、ポリブタジエン樹脂、ポリカーボネート樹脂、熱可塑性ポリイミド樹脂、６－ナイロンや６，６－ナイロンなどのポリアミド樹脂、フェノキシ樹脂、アクリル樹脂、ＰＥＴやＰＢＴなどの飽和ポリエステル樹脂、ポリアミドイミド樹脂、フッ素樹脂、スチレン－イソブチレン－スチレンブロック共重合体などが挙げられる。これらの熱可塑性樹脂は単独で、又は２種以上を併用して用いることができる。なかでも、低応力性、低吸水性という観点から、スチレン－イソブチレン－スチレンブロック共重合体が好ましい。 Examples of the thermoplastic resin include natural rubber, butyl rubber, isoprene rubber, chloroprene rubber, ethylene-vinyl acetate copolymer, ethylene-acrylic acid copolymer, ethylene-acrylic acid ester copolymer, polybutadiene resin, polycarbonate resin, heat Plastic polyimide resin, polyamide resin such as 6-nylon and 6,6-nylon, phenoxy resin, acrylic resin, saturated polyester resin such as PET and PBT, polyamideimide resin, fluororesin, styrene-isobutylene-styrene block copolymer, etc. Is mentioned. These thermoplastic resins can be used alone or in combination of two or more. Of these, a styrene-isobutylene-styrene block copolymer is preferable from the viewpoint of low stress and low water absorption.
　封止用シート１０中の熱可塑性樹脂の含有量は、１．５重量％以上が好ましく、２．０重量％以上がより好ましい。１．５重量％以上であると、柔軟性、可撓性が得られる。封止用シート１０中の熱可塑性樹脂の含有量は、６重量％以下が好ましく、４重量％以下がより好ましい。４重量％以下であると、半導体チップ２３や半導体ウエハ２２との接着性が良好である。 The content of the thermoplastic resin in the sealing sheet 10 is preferably 1.5% by weight or more, and more preferably 2.0% by weight or more. A softness | flexibility and flexibility are acquired as it is 1.5 weight% or more. The content of the thermoplastic resin in the sealing sheet 10 is preferably 6% by weight or less, and more preferably 4% by weight or less. Adhesiveness with the semiconductor chip 23 and the semiconductor wafer 22 is favorable as it is 4 weight% or less.
　封止用シート１０は、無機充填剤を含むことが好ましい。 The sealing sheet 10 preferably contains an inorganic filler.
　前記無機充填剤は、特に限定されるものではなく、従来公知の各種充填剤を用いることができ、例えば、石英ガラス、タルク、シリカ（溶融シリカや結晶性シリカなど）、アルミナ、窒化アルミニウム、窒化珪素、窒化ホウ素の粉末が挙げられる。これらは単独で用いてもよいし、２種以上併用してもよい。なかでも、線膨張係数を良好に低減できるという理由から、シリカ、アルミナが好ましく、シリカがより好ましい。 The inorganic filler is not particularly limited, and various conventionally known fillers can be used. For example, quartz glass, talc, silica (such as fused silica and crystalline silica), alumina, aluminum nitride, nitriding Examples thereof include silicon and boron nitride powders. These may be used alone or in combination of two or more. Among these, silica and alumina are preferable, and silica is more preferable because the linear expansion coefficient can be satisfactorily reduced.
　シリカとしては、シリカ粉末が好ましく、溶融シリカ粉末がより好ましい。溶融シリカ粉末としては、球状溶融シリカ粉末、破砕溶融シリカ粉末が挙げられるが、流動性という観点から、球状溶融シリカ粉末が好ましい。なかでも、平均粒径が１０～３０μｍの範囲のものが好ましく、１５～２５μｍの範囲のものがより好ましい。
　なお、平均粒径は、例えば、母集団から任意に抽出される試料を用い、レーザー回折散乱式粒度分布測定装置を用いて測定することにより導き出すことができる。 As silica, silica powder is preferable, and fused silica powder is more preferable. Examples of the fused silica powder include spherical fused silica powder and crushed fused silica powder. From the viewpoint of fluidity, spherical fused silica powder is preferable. Among these, those having an average particle diameter in the range of 10 to 30 μm are preferable, and those having a mean particle diameter in the range of 15 to 25 μm are more preferable.
The average particle diameter can be derived, for example, by using a sample arbitrarily extracted from the population and measuring it using a laser diffraction / scattering particle size distribution measuring apparatus.
　封止用シート１０中の前記無機充填剤の含有量は、封止用シート１０全体に対して、７５～９５重量％であることが好ましく、より好ましくは、７８～９５重量％である。前記無機充填剤の含有量が封止用シート１０全体に対して７５重量％以上であると、熱膨張率を低く抑えられることにより，熱衝撃よる機械的な破壊を抑制することができる。その結果、一方、前記無機充填剤の含有量が封止用シート１０全体に対して９５重量％以下であると、柔軟性、流動性、接着性がより良好となる。 The content of the inorganic filler in the sealing sheet 10 is preferably 75 to 95% by weight, and more preferably 78 to 95% by weight with respect to the entire sealing sheet 10. When the content of the inorganic filler is 75% by weight or more with respect to the entire sealing sheet 10, the mechanical expansion due to thermal shock can be suppressed by suppressing the thermal expansion coefficient low. As a result, on the other hand, when the content of the inorganic filler is 95% by weight or less with respect to the entire sealing sheet 10, flexibility, fluidity, and adhesiveness are further improved.
　封止用シート１０は、硬化促進剤を含むことが好ましい。 It is preferable that the sealing sheet 10 contains a curing accelerator.
　硬化促進剤としては、エポキシ樹脂とフェノール樹脂の硬化を進行させるものであれば特に限定されず、例えば、トリフェニルホスフィン、テトラフェニルホスホニウムテトラフェニルボレートなどの有機リン系化合物；２－フェニル－４，５－ジヒドロキシメチルイミダゾール、２－フェニル－４－メチル－５－ヒドロキシメチルイミダゾールなどのイミダゾール系化合物；などが挙げられる。なかでも、混練時の温度上昇によっても硬化反応が急激に進まず、封止用シート１０を良好に作製できるという理由から、２－フェニル－４，５－ジヒドロキシメチルイミダゾールが好ましい。 The curing accelerator is not particularly limited as long as it can cure the epoxy resin and the phenol resin, and examples thereof include organophosphorus compounds such as triphenylphosphine and tetraphenylphosphonium tetraphenylborate; 2-phenyl-4, And imidazole compounds such as 5-dihydroxymethylimidazole and 2-phenyl-4-methyl-5-hydroxymethylimidazole. Among these, 2-phenyl-4,5-dihydroxymethylimidazole is preferred because the curing reaction does not proceed rapidly even when the temperature during kneading increases, and the sealing sheet 10 can be satisfactorily produced.
　硬化促進剤の含有量は、エポキシ樹脂及びフェノール樹脂の合計１００重量部に対して０．１～５重量部が好ましい。 The content of the curing accelerator is preferably 0.1 to 5 parts by weight with respect to 100 parts by weight of the total of the epoxy resin and the phenol resin.
　封止用シート１０は、難燃剤成分を含むことが好ましい。これにより、部品ショートや発熱などにより発火した際の、燃焼拡大を低減できる。難燃剤組成分としては、例えば水酸化アルミニウム、水酸化マグネシウム、水酸化鉄、水酸化カルシウム、水酸化スズ、複合化金属水酸化物などの各種金属水酸化物；ホスファゼン系難燃剤などを用いることができる。 The sealing sheet 10 preferably contains a flame retardant component. This can reduce the expansion of combustion when ignition occurs due to component short-circuiting or heat generation. As the flame retardant composition, for example, various metal hydroxides such as aluminum hydroxide, magnesium hydroxide, iron hydroxide, calcium hydroxide, tin hydroxide, complex metal hydroxides; phosphazene flame retardants, etc. should be used. Can do.
　少量でも難燃効果を発揮するという観点から、ホスファゼン系難燃剤に含まれるリン元素の含有率は、１２重量％以上であることが好ましい。 From the viewpoint of exhibiting a flame retardant effect even in a small amount, the content of the phosphorus element contained in the phosphazene flame retardant is preferably 12% by weight or more.
　封止用シート１０中の難燃剤成分の含有量は、全有機成分（無機フィラーを除く）中、１０重量％以上が好ましく、１５重量％以上がより好ましい。１０重量％以上であると、難燃性が良好に得られる。封止用シート１０中の熱可塑性樹脂の含有量は、３０重量％以下が好ましく、２５重量％以下がより好ましい。３０重量％以下であると、硬化物の物性低下（具体的には、ガラス転移温度や高温樹脂強度などの物性の低下）が少ない傾向がある。 The content of the flame retardant component in the sealing sheet 10 is preferably 10% by weight or more and more preferably 15% by weight or more in the total organic components (excluding the inorganic filler). A flame retardance is favorably acquired as it is 10 weight% or more. The content of the thermoplastic resin in the sealing sheet 10 is preferably 30% by weight or less, and more preferably 25% by weight or less. When the content is 30% by weight or less, there is a tendency that there is little decrease in physical properties of the cured product (specifically, physical properties such as glass transition temperature and high temperature resin strength).
　封止用シート１０は、シランカップリング剤を含むことが好ましい。シランカップリング剤としては特に限定されず、３－グリシドキシプロピルトリメトキシシランなどが挙げられる。 It is preferable that the sealing sheet 10 contains a silane coupling agent. The silane coupling agent is not particularly limited, and examples thereof include 3-glycidoxypropyltrimethoxysilane.
　封止用シート１０中のシランカップリング剤の含有量は、０．１～３重量％が好ましい。０．１重量％以上であると、硬化物の強度が十分得られ吸水率を低くできる。３重量％以下であると、アウトガス量を低くできる。 The content of the silane coupling agent in the sealing sheet 10 is preferably 0.1 to 3% by weight. When the content is 0.1% by weight or more, sufficient strength of the cured product can be obtained and the water absorption rate can be lowered. If it is 3% by weight or less, the outgas amount can be lowered.
　封止用シート１０は、着色されていることが好ましい。これにより、優れたマーキング性及び外観性を発揮させることができ、付加価値のある外観の半導体装置とすることが可能になる。着色された封止用シート１０は、優れたマーキング性を有しているので、マーキングを施し、文字情報や図形情報などの各種情報を付与させることができる。特に、着色の色をコントロールすることにより、マーキングにより付与された情報（文字情報、図形情報など）を、優れた視認性で視認することが可能になる。更に、封止用シート１０は、製品別に色分けすることも可能である。封止用シート１０を有色にする場合（無色・透明ではない場合）、着色により呈している色としては特に制限されないが、例えば、黒色、青色、赤色などの濃色であることが好ましく、特に黒色であることが好適である。 The sealing sheet 10 is preferably colored. Thereby, excellent marking properties and appearance can be exhibited, and a semiconductor device having an added-value appearance can be obtained. Since the colored sealing sheet 10 has excellent marking properties, it can be marked to give various information such as character information and graphic information. In particular, by controlling the coloring color, it is possible to visually recognize information (character information, graphic information, etc.) given by marking with excellent visibility. Furthermore, the sealing sheet 10 can be color-coded for each product. When the sealing sheet 10 is colored (when it is colorless and not transparent), it is not particularly limited as a color exhibited by coloring, but it is preferably a dark color such as black, blue, red, etc. It is suitable that it is black.
　本実施形態において、濃色とは、基本的には、Ｌ*ａ*ｂ*表色系で規定されるＬ*が、６０以下（０～６０）［好ましくは５０以下（０～５０）、さらに好ましくは４０以下（０～４０）］となる濃い色のことを意味している。 In this embodiment, the dark, basically, L * a * b * L * is defined by a color system, 60 or less (0 to 60) [preferably 50 or less (0 to 50), More preferably, it means a dark color of 40 or less (0 to 40)].
　また、黒色とは、基本的には、Ｌ*ａ*ｂ*表色系で規定されるＬ*が、３５以下（０～３５）［好ましくは３０以下（０～３０）、さらに好ましくは２５以下（０～２５）］となる黒色系色のことを意味している。なお、黒色において、Ｌ*ａ*ｂ*表色系で規定されるａ*やｂ*は、それぞれ、Ｌ*の値に応じて適宜選択することができる。ａ*やｂ*としては、例えば、両方とも、－１０～１０であることが好ましく、より好ましくは－５～５であり、特に－３～３の範囲（中でも０又はほぼ０）であることが好適である。 Also, black and basically, L * a * b * L * defined by the color system is 35 or less (0 to 35) [preferably 30 or less (0 to 30), more preferably 25 This means a blackish color which is (0 to 25) below. In black, a * and b * defined in the L * a * b * color system can be appropriately selected according to the value of L * . As a * and b * , for example, both are preferably −10 to 10, more preferably −5 to 5, particularly in the range of −3 to 3 (in particular, 0 or almost 0). Is preferred.
　なお、本実施形態において、Ｌ*ａ*ｂ*表色系で規定されるＬ*、ａ*、ｂ*は、色彩色差計（商品名「ＣＲ－２００」ミノルタ社製；色彩色差計）を用いて測定することにより求められる。なお、Ｌ*ａ*ｂ*表色系は、国際照明委員会（ＣＩＥ）が１９７６年に推奨した色空間であり、ＣＩＥ１９７６（Ｌ*ａ*ｂ*）表色系と称される色空間のことを意味している。また、Ｌ*ａ*ｂ*表色系は、日本工業規格では、ＪＩＳＺ ８７２９に規定されている。 In this embodiment, L * , a * , and b * defined in the L * a * b * color system are color difference meters (trade name “CR-200” manufactured by Minolta Co .; color difference meter). It is calculated | required by measuring using. The L * a * b * color system is a color space recommended by the International Commission on Illumination (CIE) in 1976, and is a color space called the CIE 1976 (L * a * b * ) color system. It means that. The L * a * b * color system is defined in JISZ 8729 in the Japanese Industrial Standard.
　封止用シート１０を着色する際には、目的とする色に応じて、色材（着色剤）を用いることができる。本発明の封止用シートは、一層構成であってもよく、複数の層から構成されていてもよいが、少なくとも、半導体ウエハと対向する面とは反対の面側に、着色剤が添加されていることが好ましい。具体的に、封止用シートが１層構成の場合、封止用シート全体に均一に着色剤が含有されていてもよく、半導体ウエハと対向する面とは反対の面側に、着色剤が偏在する態様で着色剤が含有されていてもよい。また、複数の層から構成する場合、半導体ウエハ２２と対向する面とは反対の面側の層に着色剤を添加するとともに、それ以外の層には着色剤を添加しないこととしてもよい。本実施形態では、本発明の封止用シートが１層構成の封止用シートが１０である場合について説明し、封止用シートが２層以上の場合については、後に図１２を用いて説明することとする。封止用シートにおける半導体ウエハと対向する面とは反対の面側に着色剤が添加されていると、レーザーマーキングされた部分の視認性を向上させることができるからである。このような色材としては、黒系色材、青系色材、赤系色材などの各種濃色系色材を好適に用いることができ、特に黒系色材が好適である。色材としては、顔料、染料などいずれであってもよい。色材は単独で又は２種以上を組み合わせて用いることができる。なお、染料としては、酸性染料、反応染料、直接染料、分散染料、カチオン染料等のいずれの形態の染料であっても用いることが可能である。また、顔料も、その形態は特に制限されず、公知の顔料から適宜選択して用いることができる。 When the sealing sheet 10 is colored, a coloring material (coloring agent) can be used according to the target color. The sealing sheet of the present invention may have a single layer structure or a plurality of layers, but at least a colorant is added to the side opposite to the surface facing the semiconductor wafer. It is preferable. Specifically, when the encapsulating sheet has a single layer configuration, the entire encapsulating sheet may contain a colorant uniformly, and the colorant is present on the side opposite to the surface facing the semiconductor wafer. A colorant may be contained in an unevenly distributed manner. In the case of a plurality of layers, the colorant may be added to the layer on the side opposite to the surface facing the semiconductor wafer 22 and the colorant may not be added to the other layers. In the present embodiment, the case where the sealing sheet of the present invention has 10 single-layer sealing sheets will be described, and the case where the sealing sheet has two or more layers will be described later with reference to FIG. I decided to. This is because when the colorant is added to the surface of the sealing sheet opposite to the surface facing the semiconductor wafer, the visibility of the laser-marked portion can be improved. As such a color material, various dark color materials such as a black color material, a blue color material, and a red color material can be suitably used, and a black color material is particularly suitable. As the color material, any of a pigment, a dye and the like may be used. Color materials can be used alone or in combination of two or more. As the dye, any form of dyes such as acid dyes, reactive dyes, direct dyes, disperse dyes, and cationic dyes can be used. Also, the form of the pigment is not particularly limited, and can be appropriately selected from known pigments.
　特に、色材として染料を用いると、封止用シート１０中には、染料が溶解により均一又はほぼ均一に分散した状態となるため、着色濃度が均一又はほぼ均一な封止用シート１０を容易に製造することができ、マーキング性や外観性を向上させることができる。 In particular, when a dye is used as the colorant, the dye is dissolved or evenly dispersed in the sealing sheet 10, so that the sealing sheet 10 having a uniform or almost uniform coloring density can be easily obtained. Can be manufactured, and marking properties and appearance can be improved.
　黒系色材としては、特に制限されないが、例えば、無機の黒系顔料、黒系染料から適宜選択することができる。また、黒系色材としては、シアン系色材（青緑系色材）、マゼンダ系色材（赤紫系色材）およびイエロー系色材（黄系色材）が混合された色材混合物であってもよい。黒系色材は単独で又は２種以上を組み合わせて用いることができる。もちろん、黒系色材は、黒以外の色の色材と併用することもできる。 The black color material is not particularly limited, and can be appropriately selected from, for example, inorganic black pigments and black dyes. In addition, as a black color material, a color material mixture in which a cyan color material (blue-green color material), a magenta color material (red purple color material) and a yellow color material (yellow color material) are mixed. It may be. Black color materials can be used alone or in combination of two or more. Of course, the black color material can be used in combination with a color material other than black.
　具体的には、黒系色材としては、例えば、カーボンブラック（ファーネスブラック、チャンネルブラック、アセチレンブラック、サーマルブラック、ランプブラックなど）、グラファイト（黒鉛）、酸化銅、二酸化マンガン、アゾ系顔料（アゾメチンアゾブラックなど）、アニリンブラック、ペリレンブラック、チタンブラック、シアニンブラック、活性炭、フェライト（非磁性フェライト、磁性フェライトなど）、マグネタイト、酸化クロム、酸化鉄、二硫化モリブデン、クロム錯体、複合酸化物系黒色色素、アントラキノン系有機黒色色素などが挙げられる。 Specifically, as the black color material, for example, carbon black (furnace black, channel black, acetylene black, thermal black, lamp black, etc.), graphite (graphite), copper oxide, manganese dioxide, azo pigment (azomethine) Azo black, etc.), aniline black, perylene black, titanium black, cyanine black, activated carbon, ferrite (nonmagnetic ferrite, magnetic ferrite, etc.), magnetite, chromium oxide, iron oxide, molybdenum disulfide, chromium complex, complex oxide black Examples thereof include dyes and anthraquinone organic black dyes.
　本発明では、黒系色材としては、Ｃ．Ｉ．ソルベントブラック３、同７、同２２、同２７、同２９、同３４、同４３、同７０、Ｃ．Ｉ．ダイレクトブラック１７、同１９、同２２、同３２、同３８、同５１、同７１、Ｃ．Ｉ．アシッドブラック１、同２、同２４、同２６、同３１、同４８、同５２、同１０７、同１０９、同１１０、同１１９、同１５４Ｃ．Ｉ．ディスパーズブラック１、同３、同１０、同２４等のブラック系染料；Ｃ．Ｉ．ピグメントブラック１、同７等のブラック系顔料なども利用することができる。 In the present invention, as the black color material, C.I. I. Solvent Black 3, 7, 22, 27, 29, 34, 43, 70, C.I. I. Direct Black 17, 19, 19, 22, 32, 38, 51, 71, C.I. I. Acid Black 1, 2, 24, 26, 31, 48, 52, 107, 109, 110, 119, 154C. I. Black dyes such as Disperse Black 1, 3, 10, and 24; I. Black pigments such as CI Pigment Black 1 and 7 can also be used.
　このような黒系色材としては、例えば、商品名「Ｏｉｌ Ｂｌａｃｋ ＢＹ」、商品名「ＯｉｌＢｌａｃｋ ＢＳ」、商品名「ＯｉｌＢｌａｃｋＨＢＢ」、商品名「Ｏｉｌ Ｂｌａｃｋ８０３」、商品名「Ｏｉｌ Ｂｌａｃｋ８６０」、商品名「Ｏｉｌ Ｂｌａｃｋ５９７０」、商品名「Ｏｉｌ Ｂｌａｃｋ５９０６」、商品名「Ｏｉｌ Ｂｌａｃｋ５９０５」（オリエント化学工業株式会社製）などが市販されている。 Examples of such a black color material include a product name “OilＯBlack BY”, a product name “OilBlack BS”, a product name “OilBlackHBB”, a product name “Oil Black803”, a product name “Oil Black860”, and a product name “Oil Black860”. Oil Black 5970 ”, trade name“ Oil Black 5906 ”, trade name“ Oil Black 5905 ”(manufactured by Orient Chemical Co., Ltd.) and the like are commercially available.
　黒系色材以外の色材としては、例えば、シアン系色材、マゼンダ系色材、イエロー系色材などが挙げられる。シアン系色材としては、例えば、Ｃ．Ｉ．ソルベントブルー２５、同３６、同６０、同７０、同９３、同９５；Ｃ．Ｉ．アシッドブルー６、同４５等のシアン系染料；Ｃ．Ｉ．ピグメントブルー１、同２、同３、同１５、同１５：１、同１５：２、同１５：３、同１５：４、同１５：５、同１５：６、同１６、同１７、同１７：１、同１８、同２２、同２５、同５６、同６０、同６３、同６５、同６６；Ｃ．Ｉ．バットブルー４；同６０、Ｃ．Ｉ．ピグメントグリーン７等のシアン系顔料などが挙げられる。 Examples of color materials other than black color materials include cyan color materials, magenta color materials, and yellow color materials. Examples of cyan color materials include C.I. I. Solvent Blue 25, 36, 60, 70, 93, 95; I. Cyan dyes such as Acid Blue 6 and 45; I. Pigment Blue 1, 2, 3, 15, 15: 1, 15: 2, 15: 3, 15: 3, 15: 4, 15: 5, 15: 6, 16, 16, 17 17: 1, 18, 22, 25, 56, 60, 63, 65, 66; I. Bat Blue 4; 60, C.I. I. And cyan pigments such as CI Pigment Green 7.
　また、マゼンダ系色材において、マゼンダ系染料としては、例えば、Ｃ．Ｉ．ソルベントレッド１、同３、同８、同２３、同２４、同２５、同２７、同３０、同４９、同５２、同５８、同６３、同８１、同８２、同８３、同８４、同１００、同１０９、同１１１、同１２１、同１２２；Ｃ．Ｉ．ディスパースレッド９；Ｃ．Ｉ．ソルベントバイオレット８、同１３、同１４、同２１、同２７；Ｃ．Ｉ．ディスパースバイオレット１；Ｃ．Ｉ．ベーシックレッド１、同２、同９、同１２、同１３、同１４、同１５、同１７、同１８、同２２、同２３、同２４、同２７、同２９、同３２、同３４、同３５、同３６、同３７、同３８、同３９、同４０；Ｃ．Ｉ．ベーシックバイオレット１、同３、同７、同１０、同１４、同１５、同２１、同２５、同２６、同２７、２８などが挙げられる。 In the magenta color material, examples of the magenta dye include C.I. I. Solvent Red 1, 3, 8, 23, 24, 25, 27, 30, 30, 49, 52, 58, 63, 81, 82, 83, 84, the same 100, 109, 111, 121, 122; I. Disper thread 9; I. Solvent Violet 8, 13, 13, 21, and 27; C.I. I. Disperse violet 1; C.I. I. Basic Red 1, 2, 9, 9, 13, 14, 15, 17, 17, 18, 22, 23, 24, 27, 29, 32, 34, the same 35, 36, 37, 38, 39, 40; I. Basic Violet 1, 3, 7, 10, 14, 15, 21, 21, 25, 26, 27, 28 and the like.
　マゼンダ系色材において、マゼンダ系顔料としては、例えば、Ｃ．Ｉ．ピグメントレッド１、同２、同３、同４、同５、同６、同７、同８、同９、同１０、同１１、同１２、同１３、同１４、同１５、同１６、同１７、同１８、同１９、同２１、同２２、同２３、同３０、同３１、同３２、同３７、同３８、同３９、同４０、同４１、同４２、同４８：１、同４８：２、同４８：３、同４８：４、同４９、同４９：１、同５０、同５１、同５２、同５２：２、同５３：１、同５４、同５５、同５６、同５７：１、同５８、同６０、同６０：１、同６３、同６３：１、同６３：２、同６４、同６４：１、同６７、同６８、同８１、同８３、同８７、同８８、同８９、同９０、同９２、同１０１、同１０４、同１０５、同１０６、同１０８、同１１２、同１１４、同１２２、同１２３、同１３９、同１４４、同１４６、同１４７、同１４９、同１５０、同１５１、同１６３、同１６６、同１６８、同１７０、同１７１、同１７２、同１７５、同１７６、同１７７、同１７８、同１７９、同１８４、同１８５、同１８７、同１９０、同１９３、同２０２、同２０６、同２０７、同２０９、同２１９、同２２２、同２２４、同２３８、同２４５；Ｃ．Ｉ．ピグメントバイオレット３、同９、同１９、同２３、同３１、同３２、同３３、同３６、同３８、同４３、同５０；Ｃ．Ｉ．バットレッド１、同２、同１０、同１３、同１５、同２３、同２９、同３５などが挙げられる。 In the magenta color material, examples of the magenta pigment include C.I. I. Pigment Red 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 21, 22, 23, 30, 31, 32, 37, 38, 39, 40, 41, 42, 48: 1, 48: 2, 48: 3, 48: 4, 49, 49: 1, 50, 51, 52, 52: 2, 53: 1, 54, 55, 56, 57: 1, 58, 60, 60: 1, 63, 63: 1, 63: 2, 64, 64: 1, 67, 68, 81, 83, etc. 87, 88, 89, 90, 92, 101, 104, 105, 106, 108, 112, 114, 122, 123, 139, 144, 146 147, 149, 150, 151, 163, 166, 168, 170, 171, 172, 175, 176, 177, 178, 179, 184, 185 187, 190, 193, 202, 206, 207, 209, 219, 222, 224, 238, 245; I. C.I. Pigment Violet 3, 9, 19, 23, 31, 32, 33, 36, 38, 43, 50; I. Bat red 1, 2, 10, 13, 15, 23, 29, 35 and the like.
　また、イエロー系色材としては、例えば、Ｃ．Ｉ．ソルベントイエロー１９、同４４、同７７、同７９、同８１、同８２、同９３、同９８、同１０３、同１０４、同１１２、同１６２等のイエロー系染料；Ｃ．Ｉ．ピグメントオレンジ３１、同４３；Ｃ．Ｉ．ピグメントイエロー１、同２、同３、同４、同５、同６、同７、同１０、同１１、同１２、同１３、同１４、同１５、同１６、同１７、同２３、同２４、同３４、同３５、同３７、同４２、同５３、同５５、同６５、同７３、同７４、同７５、同８１、同８３、同９３、同９４、同９５、同９７、同９８、同１００、同１０１、同１０４、同１０８、同１０９、同１１０、同１１３、同１１４、同１１６、同１１７、同１２０、同１２８、同１２９、同１３３、同１３８、同１３９、同１４７、同１５０、同１５１、同１５３、同１５４、同１５５、同１５６、同１６７、同１７２、同１７３、同１８０、同１８５、同１９５；Ｃ．Ｉ．バットイエロー１、同３、同２０等のイエロー系顔料などが挙げられる。 Also, examples of yellow color materials include C.I. I. Solvent Yellow 19, 44, 77, 79, 81, 82, 93, 98, 103, 104, 112, 162 and the like yellow dyes; C.I. I. Pigment Orange 31 and 43; C.I. I. Pigment Yellow 1, 2, 3, 4, 5, 6, 7, 10, 10, 12, 13, 14, 15, 15, 16, 17, 23, 24, 34, 35, 37, 42, 53, 55, 65, 73, 74, 75, 81, 83, 93, 94, 95, 97, 98, 100, 101, 104, 108, 109, 110, 113, 114, 116, 117, 120, 128, 129, 133, 138, 139 147, 150, 151, 153, 154, 155, 156, 167, 172, 173, 180, 185, 195; I. Examples thereof include yellow pigments such as Vat Yellow 1, 3 and 20.
　シアン系色材、マゼンダ系色材、イエロー系色材などの各種色材は、それぞれ、単独で又は２種以上を組み合わせて用いることができる。なお、シアン系色材、マゼンダ系色材、イエロー系色材などの各種色材を２種以上用いる場合、これらの色材の混合割合（または配合割合）としては、特に制限されず、各色材の種類や目的とする色などに応じて適宜選択することができる。 Various color materials such as a cyan color material, a magenta color material, and a yellow color material can be used alone or in combination of two or more. When two or more kinds of various color materials such as a cyan color material, a magenta color material, and a yellow color material are used, the mixing ratio (or blending ratio) of these color materials is not particularly limited, and each color material. It can be selected as appropriate according to the type and the target color.
　封止用シート１０における可視光（波長：３８０ｎｍ～８００ｎｍ）による光線透過率（可視光透過率）としては、特に制限されないが、例えば、２０％～０％の範囲であることが好ましく、さらに好ましくは１０％～０％、特に好ましくは５％～０％である。封止用シート１０の可視光透過率を、２０％以下とすることにより、印字視認性を良好とすることができる。また光線通過による半導体素子へ悪影響を防止することができる。 The light transmittance (visible light transmittance) by visible light (wavelength: 380 nm to 800 nm) in the sealing sheet 10 is not particularly limited, but is preferably in the range of 20% to 0%, for example. Is from 10% to 0%, particularly preferably from 5% to 0%. By setting the visible light transmittance of the sealing sheet 10 to 20% or less, the print visibility can be improved. Further, it is possible to prevent an adverse effect on the semiconductor element due to the passage of light.
　封止用シート１０の可視光線透過率（％）は、厚さ（平均厚さ）：１０μｍの封止用シート１０を作製し、該封止用シート１０（厚さ：１０μｍ）に、商品名「ＵＶ－２５５０」（島津製作所製）を用いて、波長：３８０ｎｍ～８００ｎｍの可視光線を所定の強度で照射する。この照射により封止用シート１０を透過した可視光線の光強度を測定し、次式により算出することができる。
　可視光線透過率（％）＝（（封止用シート１０の透過後の可視光線の光強度）／（可視光線の初期の光強度））×１００ The visible light transmittance (%) of the sealing sheet 10 is such that the sealing sheet 10 having a thickness (average thickness): 10 μm is prepared, and the sealing sheet 10 (thickness: 10 μm) Using “UV-2550” (manufactured by Shimadzu Corporation), visible light having a wavelength of 380 nm to 800 nm is irradiated with a predetermined intensity. The light intensity of visible light transmitted through the sealing sheet 10 by this irradiation can be measured and calculated by the following formula.
Visible light transmittance (%) = ((light intensity of visible light after transmission through sealing sheet 10) / (initial light intensity of visible light)) × 100
　なお、光線透過率（％）の前記算出方法は、厚さが１０μｍでない封止用シート１０の光線透過率（％）の算出にも適用することができる。具体的には、ランベルトベールの法則により、１０μｍでの吸光度Ａ１０を下記の通り算出することができる。 In addition, the said calculation method of light transmittance (%) is applicable also to calculation of the light transmittance (%) of the sheet | seat 10 for sealing whose thickness is not 10 micrometers. Specifically, the absorbance A 10 at 10 μm can be calculated as follows according to Lambert Beer's law.
　Ａ１０＝α×Ｌ１０×Ｃ　（１）
　（式中、Ｌ１０は光路長、αは吸光係数、Ｃは試料濃度を表す）
　また、厚さＸ（μｍ）での吸光度ＡＸは下記式（２）により表すことができる。
　ＡＸ＝α×ＬＸ×Ｃ　（２）
　更に、厚さ２０μｍでの吸光度Ａ２０は下記式（３）により表すことができる。
　Ａ１０＝－ｌｏｇ１０Ｔ１０　（３）
　（式中、Ｔ１０は厚さ１０μｍでの光線透過率を表す）
　前記式（１）～（３）より、吸光度ＡＸは、
　ＡＸ＝Ａ１０×（ＬＸ／Ｌ１０）
＝－［ｌｏｇ１０（Ｔ１０）］×（ＬＸ／Ｌ１０）
と表すことができる。これにより、厚さＸ（μｍ）での光線透過率ＴＸ（％）は、下記により算出することができる。
　ＴＸ＝１０－ＡＸ
　但し、ＡＸ＝－［ｌｏｇ１０（Ｔ１０）］×（ＬＸ／Ｌ１０） A 10 = α × L 10 × C (1)
(Where L 10 is the optical path length, α is the extinction coefficient, and C is the sample concentration)
Also, the absorbance A X of a thickness X ([mu] m) can be represented by the following formula (2).
A X = α × L X × C (2)
Furthermore, the absorbance A 20 at a thickness of 20 μm can be expressed by the following formula (3).
A 10 = −log 10 T 10 (3)
(Wherein, T 10 represents a light transmittance at a thickness of 10 [mu] m)
From the equation (1) to (3), the absorbance A X is
A X = A 10 × (L X / L 10 )
= − [Log 10 (T 10 )] × (L X / L 10 )
It can be expressed as. Thereby, the light transmittance T X (%) at the thickness X (μm) can be calculated as follows.
T X = 10 -AX
However, A X = − [log 10 (T 10 )] × (L X / L 10 )
　本実施形態では、封止用シートの光線透過率（％）を求める際の封止用シートの厚さ（平均厚さ）は１０μｍであるが、この封止用シートの厚さは、あくまでも封止用シートの光線透過率（％）を求める際の厚さであり、本発明における封止用シートが１０μｍであることを意味するものではない。 In this embodiment, the thickness (average thickness) of the sealing sheet when determining the light transmittance (%) of the sealing sheet is 10 μm. However, the thickness of the sealing sheet is only sealed. It is the thickness at the time of obtaining the light transmittance (%) of the stop sheet, and does not mean that the sealing sheet in the present invention is 10 μm.
　封止用シート１０の光線透過率（％）は、樹脂成分の種類やその含有量、着色剤（顔料や染料など）の種類やその含有量、充填材の種類やその含有量などによりコントロールすることができる。 The light transmittance (%) of the sealing sheet 10 is controlled by the type and content of the resin component, the type and content of the colorant (pigment, dye, etc.), the type and content of the filler, and the like. be able to.
　なお、封止用シート１０には、上記の各成分以外に必要に応じて、他の添加剤を適宜配合できる。 In addition to the above components, other additives may be appropriately added to the sealing sheet 10 as necessary.
　封止用シート１０の厚さは、特に限定されないが、封止用シートとして使用する観点から、例えば、５０μｍ～２０００μｍである。 The thickness of the sealing sheet 10 is not particularly limited, but is, for example, 50 μm to 2000 μm from the viewpoint of use as a sealing sheet.
　封止用シート１０の製造方法は特に限定されないが、封止用シート１０を形成するための樹脂組成物の混練物を調製し、得られた混練物を塗工する方法や、得られた混練物をシート状に塑性加工する方法が好ましい。これにより、溶剤を使用せずに封止用シート１０を作製できるので、半導体チップ２３が揮発した溶剤により影響を受けることを抑制することができる。 Although the manufacturing method of the sheet | seat 10 for sealing is not specifically limited, The method of coating the kneaded material obtained by preparing the kneaded material of the resin composition for forming the sheet | seat 10 for sealing, and the obtained kneading | mixing A method of plastically processing an object into a sheet is preferable. Thereby, since the sheet | seat 10 for sealing can be produced without using a solvent, it can suppress that the semiconductor chip 23 is influenced by the solvent which volatilized.
　具体的には、後述の各成分をミキシングロール、加圧式ニーダー、押出機などの公知の混練機で溶融混練することにより混練物を調製し、得られた混練物を塗工又は塑性加工によりシート状にする。混練条件として、温度は、上述の各成分の軟化点以上であることが好ましく、例えば３０～１５０℃、エポキシ樹脂の熱硬化性を考慮すると、好ましくは４０～１４０℃、さらに好ましくは６０～１２０℃である。時間は、例えば１～３０分間、好ましくは５～１５分間である。 Specifically, a kneaded product is prepared by melt-kneading each component described below with a known kneader such as a mixing roll, a pressure kneader, or an extruder, and the obtained kneaded product is coated or plastically processed into a sheet. Shape. As the kneading conditions, the temperature is preferably equal to or higher than the softening point of each component described above, for example, 30 to 150 ° C., and preferably 40 to 140 ° C., more preferably 60 to 120 in consideration of the thermosetting property of the epoxy resin. ° C. The time is, for example, 1 to 30 minutes, preferably 5 to 15 minutes.
　混練は、減圧条件下（減圧雰囲気下）で行うことが好ましい。これにより、脱気できるとともに、混練物への気体の侵入を防止できる。減圧条件下の圧力は、好ましくは０．１ｋｇ／ｃｍ２以下、より好ましくは０．０５ｋｇ／ｃｍ２以下である。減圧下の圧力の下限は特に限定されないが、例えば、１×１０－４ｋｇ／ｃｍ２以上である。 The kneading is preferably performed under reduced pressure conditions (under reduced pressure atmosphere). Thereby, while being able to deaerate, the penetration | invasion of the gas to a kneaded material can be prevented. The pressure under reduced pressure is preferably 0.1 kg / cm 2 or less, more preferably 0.05 kg / cm 2 or less. The lower limit of the pressure under reduced pressure is not particularly limited, but is, for example, 1 × 10 −4 kg / cm 2 or more.
　混練物を塗工して封止用シート１０を形成する場合、溶融混練後の混練物は、冷却することなく高温状態のままで塗工することが好ましい。塗工方法としては特に制限されず、バーコート法、ナイフコート法，スロットダイ法等を挙げることができる。塗工時の温度としては、上述の各成分の軟化点以上が好ましく、エポキシ樹脂の熱硬化性および成形性を考慮すると、例えば４０～１５０℃、好ましくは５０～１４０℃、さらに好ましくは７０～１２０℃である。 When the kneaded material is applied to form the sealing sheet 10, it is preferable that the kneaded material after melt-kneading is applied in a high temperature state without cooling. The coating method is not particularly limited, and examples thereof include a bar coating method, a knife coating method, and a slot die method. The temperature at the time of coating is preferably not less than the softening point of each component described above, and considering the thermosetting property and moldability of the epoxy resin, for example, 40 to 150 ° C., preferably 50 to 140 ° C., more preferably 70 to 120 ° C.
　混練物を塑性加工して封止用シート１０を形成する場合、溶融混練後の混練物は、冷却することなく高温状態のままで塑性加工することが好ましい。塑性加工方法としては特に制限されず、平板プレス法、Ｔダイ押出法、スクリューダイ押出法、ロール圧延法、ロール混練法、インフレーション押出法、共押出法、カレンダー成形法などなどが挙げられる。塑性加工温度としては上述の各成分の軟化点以上が好ましく、エポキシ樹脂の熱硬化性および成形性を考慮すると、例えば４０～１５０℃、好ましくは５０～１４０℃、さらに好ましくは７０～１２０℃である。 When the kneaded material is plastically processed to form the sealing sheet 10, it is preferable that the kneaded material after melt-kneading is plastically processed in a high temperature state without cooling. The plastic working method is not particularly limited, and examples thereof include a flat plate pressing method, a T-die extrusion method, a screw die extrusion method, a roll rolling method, a roll kneading method, an inflation extrusion method, a coextrusion method, and a calendar molding method. The plastic working temperature is preferably not less than the softening point of each component described above, and is 40 to 150 ° C., preferably 50 to 140 ° C., more preferably 70 to 120 ° C. in consideration of the thermosetting property and moldability of the epoxy resin. is there.
　なお、封止用シート１０は、適当な溶剤に封止用シート１０を形成するための樹脂等を溶解、分散させてワニスを調整し、このワニスを塗工して得ることもできる。 The sealing sheet 10 can also be obtained by dissolving and dispersing a resin or the like for forming the sealing sheet 10 in an appropriate solvent to adjust the varnish and coating the varnish.
　［封止用シートと積層体とを配置する工程］
　封止用シートを準備する工程の後、図３に示すように、下側加熱板３２上に積層体２０を半導体チップ２３が実装された面を上にして配置するとともに、積層体２０の半導体チップ２３が実装された面上に封止用シート１０を配置する。この工程においては、下側加熱板３２上にまず積層体２０を配置し、その後、積層体２０上に封止用シート１０を配置してもよく、積層体２０上に封止用シート１０を先に積層し、その後、積層体２０と封止用シート１０とが積層された積層物を下側加熱板３２上に配置してもよい。 [Step of arranging sealing sheet and laminate]
After the step of preparing the sealing sheet, as shown in FIG. 3, the stacked body 20 is disposed on the lower heating plate 32 with the surface on which the semiconductor chip 23 is mounted facing upward, and the semiconductor of the stacked body 20 The sealing sheet 10 is disposed on the surface on which the chip 23 is mounted. In this step, the laminated body 20 may be first disposed on the lower heating plate 32, and then the sealing sheet 10 may be disposed on the laminated body 20, and the sealing sheet 10 may be disposed on the laminated body 20. A laminate obtained by laminating first and then laminating the laminate 20 and the sealing sheet 10 may be disposed on the lower heating plate 32.
　［封止体を形成する工程］
　次に、図４に示すように、下側加熱板３２と上側加熱板３４とにより熱プレスして、半導体チップ２３を封止用シート１０に埋め込む（工程Ｂ）。封止用シート１０は、半導体チップ２３及びそれに付随する要素を外部環境から保護するための封止樹脂として機能することとなる。これにより、半導体ウエハ２２上に実装されている半導体チップ２３が封止用シート１０に埋め込まれた封止体２８が得られる。 [Step of forming sealing body]
Next, as shown in FIG. 4, the semiconductor chip 23 is embedded in the sealing sheet 10 by hot pressing with the lower heating plate 32 and the upper heating plate 34 (step B). The sealing sheet 10 functions as a sealing resin for protecting the semiconductor chip 23 and its accompanying elements from the external environment. Thereby, the sealing body 28 in which the semiconductor chip 23 mounted on the semiconductor wafer 22 is embedded in the sealing sheet 10 is obtained.
　半導体チップ２３を封止用シート１０に埋め込む際の熱プレス条件としては、温度が、例えば、４０～１００℃、好ましくは５０～９０℃であり、圧力が、例えば、０．１～１０ＭＰａ、好ましくは０．５～８ＭＰａであり、時間が、例えば０．３～１０分間、好ましくは０．５～５分間である。これにより、半導体チップ２３が封止用シート１０に埋め込まれた半導体装置を得ることができる。また、封止用シート１０の半導体チップ２３及び半導体ウエハ２２への密着性および追従性の向上を考慮すると、減圧条件下においてプレスすることが好ましい。
　前記減圧条件としては、圧力が、例えば、０．１～５ｋＰａ、好ましくは、０．１～１００Ｐａであり、減圧保持時間（減圧開始からプレス開始までの時間）が、例えば、５～６００秒であり、好ましくは、１０～３００秒である。 As hot press conditions for embedding the semiconductor chip 23 in the sealing sheet 10, the temperature is, for example, 40 to 100 ° C., preferably 50 to 90 ° C., and the pressure is, for example, 0.1 to 10 MPa, preferably Is 0.5 to 8 MPa, and the time is, for example, 0.3 to 10 minutes, preferably 0.5 to 5 minutes. Thereby, a semiconductor device in which the semiconductor chip 23 is embedded in the sealing sheet 10 can be obtained. In view of improving the adhesion and followability of the sealing sheet 10 to the semiconductor chip 23 and the semiconductor wafer 22, it is preferable to press under reduced pressure.
As the pressure reducing conditions, the pressure is, for example, 0.1 to 5 kPa, preferably 0.1 to 100 Pa, and the reduced pressure holding time (the time from the start of pressure reduction to the start of pressing) is, for example, 5 to 600 seconds. Yes, preferably 10 to 300 seconds.
　［剥離ライナー剥離工程］
　次に、剥離ライナー１１を剥離する（図５参照）。 [Release liner peeling process]
Next, the release liner 11 is peeled (see FIG. 5).
　［熱硬化工程］
　次に、封止用シート１０を熱硬化する。具体的には、例えば、半導体ウエハ２２上に実装されている半導体チップ２３が封止用シート１０に埋め込まれた封止体２８全体を加熱する。 [Thermosetting process]
Next, the sealing sheet 10 is thermoset. Specifically, for example, the entire sealing body 28 in which the semiconductor chip 23 mounted on the semiconductor wafer 22 is embedded in the sealing sheet 10 is heated.
　熱硬化処理の条件として、加熱温度が好ましくは１００℃以上、より好ましくは１２０℃以上である。一方、加熱温度の上限が、好ましくは２００℃以下、より好ましくは１８０℃以下である。加熱時間が、好ましくは１０分以上、より好ましくは３０分以上である。一方、加熱時間の上限が、好ましくは１８０分以下、より好ましくは１２０分以下である。また、必要に応じて加圧してもよく、好ましくは０．１ＭＰａ以上、より好ましくは０．５ＭＰａ以上である。一方、上限は好ましくは１０ＭＰａ以下、より好ましくは５ＭＰａ以下である。 As the conditions for the thermosetting treatment, the heating temperature is preferably 100 ° C or higher, more preferably 120 ° C or higher. On the other hand, the upper limit of the heating temperature is preferably 200 ° C. or lower, more preferably 180 ° C. or lower. The heating time is preferably 10 minutes or more, more preferably 30 minutes or more. On the other hand, the upper limit of the heating time is preferably 180 minutes or less, more preferably 120 minutes or less. Moreover, you may pressurize as needed, Preferably it is 0.1 Mpa or more, More preferably, it is 0.5 Mpa or more. On the other hand, the upper limit is preferably 10 MPa or less, more preferably 5 MPa or less.
　［レーザーマーキング工程１（封止用シート研削前のレーザーマーキング工程）］
　次に、図６に示すように、レーザーマーキング用のレーザー３６を用いて、封止用シート１０にレーザーマーキングを行なう（以下、「工程Ｅ－１」ともいう）。レーザーマーキングの条件としては、特に限定されないが、封止用シート１０に、レーザー［波長：５３２ｎｍ］を、強度：０．３Ｗ～２．０Ｗの条件で照射することが好ましい。また、この際の加工深さ（深度）が２μｍ以上となるように照射することが好ましい。前記加工深さの上限は特に制限されないが、例えば、２μｍ～２５μｍの範囲から選択することができ、好ましくは３μｍ以上（３μｍ～２０μｍ）であり、より好ましくは５μｍ以上（５μｍ～１５μｍ）である。レーザーマーキングの条件を前記数値範囲内とすることにより、優れたレーザーマーキング性が発揮される。 [Laser marking step 1 (laser marking step before grinding sealing sheet)]
Next, as shown in FIG. 6, laser marking is performed on the sealing sheet 10 using a laser marking laser 36 (hereinafter also referred to as “step E-1”). The conditions for laser marking are not particularly limited, but it is preferable to irradiate the sealing sheet 10 with laser [wavelength: 532 nm] under the conditions of intensity: 0.3 W to 2.0 W. Moreover, it is preferable to irradiate so that the processing depth (depth) in this case may be 2 μm or more. The upper limit of the processing depth is not particularly limited, but can be selected, for example, from a range of 2 μm to 25 μm, preferably 3 μm or more (3 μm to 20 μm), more preferably 5 μm or more (5 μm to 15 μm). . By setting the laser marking conditions within the above numerical range, excellent laser marking properties are exhibited.
　なお、封止用シート１０のレーザー加工性は、構成樹脂成分の種類やその含有量、着色剤の種類やその含有量、架橋剤の種類やその含有量、充填材の種類やその含有量などによりコントロールすることができる。 In addition, the laser workability of the sealing sheet 10 includes the type and content of the constituent resin component, the type and content of the colorant, the type and content of the crosslinking agent, the type and content of the filler, and the like. Can be controlled.
　前記工程Ｅ－１において、封止用シート１０におけるレーザーマーキングを行なう箇所としては、特に限定されず、半導体チップ２３の直上であってもよく、半導体チップ２３が配置されていない箇所の上側（例えば、封止用シート１０の外周部分）であってもよい。また、レーザーマーキングによってマーキングされる情報としては、封止体単位での区別を可能とするための文字情報や図形情報等であってもよく、同一の封止体２８内において互いの半導体装置を区別可能とするための文字情報や図形情報等であってもよい。これにより、次の工程、すなわち、封止用シート１０が研削されるまでの間における、封止体２８や封止体２８内の複数の半導体チップ２３（半導体装置）の相互識別性を持たせることができる。 In the step E-1, the place where laser marking is performed on the sealing sheet 10 is not particularly limited, and may be directly above the semiconductor chip 23, or above the place where the semiconductor chip 23 is not disposed (for example, Or the outer peripheral portion of the sealing sheet 10). Further, the information marked by the laser marking may be character information, graphic information, or the like for enabling distinction in units of sealing bodies. It may be character information, graphic information, or the like for enabling distinction. Thereby, the mutual identification of the sealing body 28 and the plurality of semiconductor chips 23 (semiconductor devices) in the sealing body 28 is given until the next step, that is, until the sealing sheet 10 is ground. be able to.
　［封止用シートを研削する工程］
　次に、図７に示すように、封止体２８の封止用シート１０を研削して半導体チップ２３の裏面２３ｃを表出させる（工程Ｃ）。封止用シート１０を研削する方法としては、特に限定されず、例えば、高速回転する砥石を用いるグラインディング法を挙げることができる。なお、工程Ｅ－１により付されたマーキングは、工程Ｃにおいて研削した厚さがマーキング深さ（加工深さ）よりも厚い場合は、マーキングは消失する。一方、工程Ｃにおいて研削した厚さがマーキング深さ（加工深さ）よりも薄い場合は、マーキングは残される。 [Process of grinding sealing sheet]
Next, as shown in FIG. 7, the sealing sheet 10 of the sealing body 28 is ground to expose the back surface 23c of the semiconductor chip 23 (step C). The method for grinding the sealing sheet 10 is not particularly limited, and examples thereof include a grinding method using a grindstone that rotates at high speed. It should be noted that the marking applied in step E-1 disappears when the thickness ground in step C is thicker than the marking depth (processing depth). On the other hand, if the thickness ground in step C is thinner than the marking depth (processing depth), the marking remains.
　［レーザーマーキング工程２（封止用シート研削後のレーザーマーキング工程）］
　次に、図８に示すように、レーザーマーキング用のレーザー３８を用いて、封止用シート１０にレーザーマーキングを行なう（以下、「工程Ｅ－２」ともいう）。レーザーマーキングの条件としては、特に限定されないが、封止用シート１０に、レーザー［波長：５３２ｎｍ］を、強度：０．３Ｗ～２．０Ｗの条件で照射することが好ましい。また、この際の加工深さ（深度）が２μｍ以上となるように照射することが好ましい。前記加工深さの上限は特に制限されないが、例えば、２μｍ～２５μｍの範囲から選択することができ、好ましくは３μｍ以上（３μｍ～２０μｍ）であり、より好ましくは５μｍ以上（５μｍ～１５μｍ）である。レーザーマーキングの条件を前記数値範囲内とすることにより、優れたレーザーマーキング性が発揮される。 [Laser marking process 2 (laser marking process after grinding of sealing sheet)]
Next, as shown in FIG. 8, laser marking is performed on the sealing sheet 10 using a laser marking laser 38 (hereinafter also referred to as “step E-2”). The conditions for laser marking are not particularly limited, but it is preferable to irradiate the sealing sheet 10 with laser [wavelength: 532 nm] under the conditions of intensity: 0.3 W to 2.0 W. Moreover, it is preferable to irradiate so that the processing depth (depth) in this case may be 2 μm or more. The upper limit of the processing depth is not particularly limited, but can be selected, for example, from a range of 2 μm to 25 μm, preferably 3 μm or more (3 μm to 20 μm), more preferably 5 μm or more (5 μm to 15 μm). . By setting the laser marking conditions within the above numerical range, excellent laser marking properties are exhibited.
　前記工程Ｅ－２において、封止用シート１０におけるレーザーマーキングを行なう箇所としては、特に限定されないが、半導体チップ２３が配置されていない箇所の上側とすることができる。また、レーザーマーキングによってマーキングされる情報としては、封止体単位での区別を可能とするための文字情報や図形情報等であってもよく、同一の封止体２８内において互いの半導体装置を区別可能とするための文字情報や図形情報等であってもよい。これにより、封止用シート１０が研削された後における、封止体２８や半導体装置の相互識別性を持たせることができる。特に、前記工程Ｂ以降前記工程Ｃまでの間に、前記封止用シート１０にレーザーマーキングが行なわれていたとしても、前記工程Ｃにおける研削により、マーキングは消えてしまう場合がある。しかしながら、前記工程Ｅ－２において、封止用シート１０にレーザーマーキングを行なうと、封止用シート１０が研削された後においても、再び、封止体２８や半導体装置の相互識別性を持たせることが可能となる。また、レーザーマーキングによってマーキングされる情報としては、後述するダイシング工程において使用可能な位置合わせ用の図形情報（アライメントマーク）であってもよい。 In the step E-2, the place where the laser marking is performed on the sealing sheet 10 is not particularly limited, but may be above the place where the semiconductor chip 23 is not disposed. Further, the information marked by the laser marking may be character information, graphic information, or the like for enabling distinction in units of sealing bodies. It may be character information, graphic information, or the like for enabling distinction. Thereby, after the sheet | seat 10 for sealing is ground, the sealing body 28 and the mutual identification of a semiconductor device can be given. In particular, even if laser marking is performed on the sealing sheet 10 between the process B and the process C, the marking may disappear due to grinding in the process C. However, if laser marking is performed on the sealing sheet 10 in the step E-2, the sealing body 28 and the semiconductor device are made to have mutual discrimination again even after the sealing sheet 10 is ground. It becomes possible. Further, the information marked by laser marking may be graphic information for alignment (alignment mark) that can be used in a dicing process described later.
　［配線層を形成する工程］
　次に、半導体ウエハ２２における、半導体チップ２３が搭載されている側とは反対側の面を研削して、ビア（Ｖｉａ）２２ｃを形成した後（図９参照）、配線２７ａを有する配線層２７を形成する（図１０参照）。半導体ウエハ２２を研削する方法としては、特に限定されず、例えば、高速回転する砥石を用いるグラインディング法を挙げることができる。配線層２７には、配線２７ａから突出したバンプ２７ｂを形成してもよい。配線層２７を形成する方法には、セミアディティブ法や、サブトラクティブ法など、従来公知の回路基板やインターポーザの製造技術を適用することができるから、ここでの詳細な説明は省略する。 [Process for forming wiring layer]
Next, the surface of the semiconductor wafer 22 opposite to the side on which the semiconductor chip 23 is mounted is ground to form a via (Via) 22c (see FIG. 9), and then the wiring layer 27 having the wiring 27a. (See FIG. 10). The method for grinding the semiconductor wafer 22 is not particularly limited, and examples thereof include a grinding method using a grindstone that rotates at high speed. In the wiring layer 27, bumps 27b protruding from the wiring 27a may be formed. Conventionally known circuit board and interposer manufacturing techniques such as a semi-additive method and a subtractive method can be applied to the method of forming the wiring layer 27, and thus detailed description thereof is omitted here.
　［ダイシング工程］
　続いて、図１１に示すように、半導体チップ２３の裏面２３ｃが表出している封止体２８をダイシングする（工程Ｄ）。これにより、半導体チップ２３単位での半導体装置２９を得ることができる。 [Dicing process]
Then, as shown in FIG. 11, the sealing body 28 which the back surface 23c of the semiconductor chip 23 has exposed is diced (process D). Thereby, the semiconductor device 29 in units of the semiconductor chip 23 can be obtained.
　［基板実装工程］
　必要に応じて、半導体装置２９を別途の基板（図示せず）に実装する基板実装工程を行うことができる。半導体装置２９の前記別途の基板への実装には、フリップチップボンダーやダイボンダーなどの公知の装置を用いることができる。 [Board mounting process]
If necessary, a substrate mounting step for mounting the semiconductor device 29 on a separate substrate (not shown) can be performed. For mounting the semiconductor device 29 on the separate substrate, a known device such as a flip chip bonder or a die bonder can be used.
　以上、本実施形態に係る半導体装置の製造方法によれば、前記工程Ｅ－１において、封止用シート１０にレーザーマーキングを行なうと、封止用シート１０が研削されるまでの間における、封止体や半導体装置の相互識別性を持たせることができる。
　また、前記工程Ｅ－２において、封止用シート１０にレーザーマーキングを行なうと、封止用シート１０が研削された後における、封止体や半導体装置の相互識別性を持たせることができる。特に、前記工程Ｂ以降前記工程Ｃまでの間に、封止用シート１０にレーザーマーキングが行なわれていたとしても、前記工程Ｃにおける研削により、マーキングは消えてしまうこととなる。しかしながら、前記工程Ｅ－２において、封止用シート１０にレーザーマーキングを行なうと、封止用シート１０が研削された後においても、再び、封止体や半導体装置の相互識別性を持たせることが可能となる。
　このように、本実施形態に係る半導体装置の製造方法によれば、半導体装置の製造工程において封止体や半導体装置を互いに識別することが可能となる。 As described above, according to the method for manufacturing a semiconductor device according to the present embodiment, when laser marking is performed on the sealing sheet 10 in the step E-1, the sealing until the sealing sheet 10 is ground is performed. Mutual discrimination between the stationary body and the semiconductor device can be provided.
Further, when laser marking is performed on the sealing sheet 10 in the step E-2, the sealing body and the semiconductor device can be given mutual identification after the sealing sheet 10 is ground. In particular, even if laser marking is performed on the sealing sheet 10 between the process B and the process C, the marking disappears due to the grinding in the process C. However, when laser marking is performed on the sealing sheet 10 in the step E-2, the sealing body and the semiconductor device can have mutual discrimination again even after the sealing sheet 10 is ground. Is possible.
As described above, according to the method for manufacturing a semiconductor device according to the present embodiment, the sealing body and the semiconductor device can be distinguished from each other in the manufacturing process of the semiconductor device.
　上述した実施形態では、工程Ｅ－１（封止用シート研削前のレーザーマーキング工程）を、熱硬化工程（封止体の封止用シートを熱硬化させる工程）の後に行なう場合について説明した。しかしながら、本発明における工程Ｅ－１（封止用シート研削前のレーザーマーキング工程）を行なうタイミングはこの例に限定されない。工程Ｅ－１を行なうタイミングとしては、封止体を形成する工程の後、剥離ライナー剥離工程前であってもよい。また、剥離ライナー剥離工程の後、熱硬化工程の前であってもよい。 In the embodiment described above, the case where the step E-1 (laser marking step before grinding of the sealing sheet) is performed after the thermosetting step (step of thermally curing the sealing sheet of the sealing body) has been described. However, the timing of performing the step E-1 (laser marking step before grinding the sealing sheet) in the present invention is not limited to this example. The timing of performing the step E-1 may be after the step of forming the sealing body and before the release liner peeling step. Further, it may be after the release liner peeling step and before the thermosetting step.
　上述した実施形態では、封止体の封止用シートを熱硬化させる熱硬化工程を、工程Ｂ（封止体形成工程）の後、工程Ｃ（封止用シート研削工程）の前に行なう場合について説明した。しかしながら、本発明において、前記熱硬化工程を行なうタイミングはこの例に限定されず、工程Ａ（封止体を形成する工程）と同時に行なってもよい。また、前記熱硬化工程を、工程Ｅ－１（封止用シート研削前のレーザーマーキング工程）の後に行なってもよい。 In the embodiment described above, when the thermosetting process for thermosetting the sealing sheet of the sealing body is performed after the process B (sealing body forming process) and before the process C (sealing sheet grinding process). Explained. However, in this invention, the timing which performs the said thermosetting process is not limited to this example, You may carry out simultaneously with the process A (process which forms a sealing body). Further, the thermosetting step may be performed after step E-1 (laser marking step before grinding the sealing sheet).
　また、上述した実施形態では、剥離ライナー１１を熱硬化工程の前に剥離する場合について説明したが、熱硬化工程の後に剥離してもよい。 In the above-described embodiment, the case where the release liner 11 is peeled before the thermosetting process has been described. However, the release liner 11 may be peeled after the thermosetting process.
　また、上述した実施形態では、工程Ｅ－１（封止用シート研削前のレーザーマーキング工程）と、工程Ｅ－２（封止用シート研削後のレーザーマーキング工程）との両方を行なう場合について説明したが、本発明では、いずれか一方のみ行なうこととしてもよい。 In the above-described embodiment, the case where both the process E-1 (laser marking process before grinding the sealing sheet) and the process E-2 (laser marking process after grinding the sealing sheet) are performed is described. However, in the present invention, only one of them may be performed.
　その他、本発明は、上述した実施形態に限定されず、前記工程Ｂ以降前記工程Ｃまでの間、及び／又は、前記工程Ｃ以降前記工程Ｄまでの間に、封止用シート１０にレーザーマーキングを行なう工程さえ行なわれればよく、それ以外の工程は任意であり、行なってもよく行なわなくてもよい。また、前記工程Ｂ以降前記工程Ｃまでの間、及び／又は、前記工程Ｃ以降前記工程Ｄまでの間に、封止用シート１０にレーザーマーキングを行なう工程さえ行なわれればよく、それ以外の工程は、どのような順番で行なわれてもよい。 In addition, this invention is not limited to embodiment mentioned above, Between the said process B and the said process C, and / or between the said process C and the said process D, the laser marking is carried out to the sheet | seat 10 for sealing. It is only necessary to perform the step of performing the above steps, and other steps are optional and may or may not be performed. Further, it is only necessary to perform the laser marking process on the sealing sheet 10 between the process B and the process C and / or the process C and the process D, and other processes. May be performed in any order.
　以上、本発明の封止用シートが１層の場合の実施形態ついて説明した。次に、封止用シートが２層の場合について説明する。なお、本発明の封止用シートは、１層構成又は２層構成に限定されず、さらに他の層が設けられていても構わない。 The embodiment in the case where the sealing sheet of the present invention has one layer has been described above. Next, the case where the sealing sheet has two layers will be described. In addition, the sheet | seat for sealing of this invention is not limited to 1 layer structure or 2 layer structure, Furthermore, the other layer may be provided.
　図１２は、本発明の他の実施形態に係る半導体装置の製造方法を説明するための断面模式図である。図１２に示すように、封止用シート１１０は、マーキング層１１２と封止層１１４とを有する。図１２は、半導体チップ２３が半導体ウエハ２２に実装された積層体２０において、半導体チップ２３が封止用シート１１０に埋め込まれた後、剥離シートが剥離された状態を示す。図１２に示すように、封止用シート１１０は、半導体ウエハ２２と対向する面とは反対の面がマーキング層１１２となるように配置されている。図１２は、封止用シートが２層であるか１層であるかの点で異なる以外は、図５の状態に対応する。なお、封止用シートが１層であるか２層であるかの点以外は、図１～図１１を用いて説明した半導体装置の製造方法と同様であるから、異なる点以外の説明は省略することとする。 FIG. 12 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention. As illustrated in FIG. 12, the sealing sheet 110 includes a marking layer 112 and a sealing layer 114. FIG. 12 shows a state where the release sheet is peeled off after the semiconductor chip 23 is embedded in the sealing sheet 110 in the stacked body 20 in which the semiconductor chip 23 is mounted on the semiconductor wafer 22. As shown in FIG. 12, the sealing sheet 110 is disposed so that the surface opposite to the surface facing the semiconductor wafer 22 becomes the marking layer 112. FIG. 12 corresponds to the state of FIG. 5 except that the sealing sheet has two layers or one layer. Since the method for manufacturing the semiconductor device described with reference to FIGS. 1 to 11 is the same as that described with reference to FIGS. 1 to 11 except that the encapsulating sheet has one layer or two layers, the description other than the differences is omitted. I decided to.
　封止層１１４は、半導体チップ２３を埋め込むための機能を有する。封止層１１４の構成材料としては、基本的に封止用シート１０と同様とすることができる。ただし、封止層１１４にはレーザーマーキングが行なわれないことから、着色剤を添加しない構成とすることが好ましい。不必要な着色剤の添加による不利益（例えば、保存安定性の低下等）を回避できるからである。 The sealing layer 114 has a function for embedding the semiconductor chip 23. The constituent material of the sealing layer 114 can be basically the same as that of the sealing sheet 10. However, since laser marking is not performed on the sealing layer 114, it is preferable that a colorant is not added. This is because a disadvantage (for example, a decrease in storage stability) due to the addition of an unnecessary colorant can be avoided.
　マーキング層１１２は、レーザーマーキングが行なわれる層であり、レーザーマーキングによるマーキングの視認性が良好となる構成であることが好ましい。マーキング層１１２の構成材料も、基本的に封止用シート１０と同様とすることができる。ただし、マーキング層１１２はレーザーマーキングが行なわれることから着色剤が添加されていることが好ましい。 The marking layer 112 is a layer on which laser marking is performed, and preferably has a configuration in which the visibility of marking by laser marking is good. The constituent material of the marking layer 112 can be basically the same as that of the sealing sheet 10. However, it is preferable that a colorant is added to the marking layer 112 because laser marking is performed.
　マーキング層１１２における可視光（波長：３８０ｎｍ～８００ｎｍ）による光線透過率（可視光透過率）としては、特に制限されないが、例えば、２０％～０％の範囲であることが好ましく、さらに好ましくは１０％～０％、特に好ましくは５％～０％である。封止用シート１０の可視光透過率を、２０％以下とすることにより、印字視認性を良好とすることができる。また光線通過による半導体素子へ悪影響を防止することができる。 The light transmittance (visible light transmittance) of visible light (wavelength: 380 nm to 800 nm) in the marking layer 112 is not particularly limited, but is preferably in the range of 20% to 0%, and more preferably 10%, for example. % To 0%, particularly preferably 5% to 0%. By setting the visible light transmittance of the sealing sheet 10 to 20% or less, the print visibility can be improved. Further, it is possible to prevent an adverse effect on the semiconductor element due to the passage of light.
　なお、封止層１１４の可視光透過率は、特に限定されないが、着色剤は添加しない構成が好ましい。 Note that the visible light transmittance of the sealing layer 114 is not particularly limited, but a configuration in which a colorant is not added is preferable.
　封止用シート１１０は、図１２に示すように、封止層１１４の厚さが半導体チップ２３の厚さ（バンプを有する場合は、半導体チップ２３とバンプ２３ｂとの合計厚さ）よりも薄い構成とすることができる。このような構成とした場合、工程Ｃの後にもマーキング層１１２が平面視で半導体チップ２３を取り囲むように残される。その結果、前記工程Ｃ以降前記工程Ｄまでの間に、封止用シート１１０（マーキング層１１２）にレーザーマーキングを行なうことが可能となる。 In the sealing sheet 110, as shown in FIG. 12, the thickness of the sealing layer 114 is thinner than the thickness of the semiconductor chip 23 (the total thickness of the semiconductor chip 23 and the bump 23b when bumps are provided). It can be configured. In such a configuration, the marking layer 112 is left so as to surround the semiconductor chip 23 in a plan view even after the process C. As a result, it is possible to perform laser marking on the sealing sheet 110 (marking layer 112) between the process C and the process D.
　以上、本発明の実施形態について説明したが、本発明は、上述した例に限定されるものではなく、本発明の構成を充足する範囲内で、適宜設計変更を行うことが可能である。 As mentioned above, although the embodiment of the present invention has been described, the present invention is not limited to the above-described example, and it is possible to make design changes as appropriate within a range that satisfies the configuration of the present invention.
１０、１１０　封止用シート
２０　積層体
２２　半導体ウエハ
２３　半導体チップ
２８　封止体
２９　半導体装置 10, 110 Sealing sheet 20 Laminated body 22 Semiconductor wafer 23 Semiconductor chip 28 Sealing body 29 Semiconductor device

Claims (2)

  1. 　半導体チップを半導体ウエハの回路形成面にフリップチップボンディングする工程Ａと、
    　前記半導体ウエハにフリップチップボンディングされた前記半導体チップを封止用シートに埋め込んで封止体を形成する工程Ｂと、
    　前記封止体の前記封止用シートを研削して前記半導体チップの裏面を表出させる工程Ｃと、
    　前記半導体チップの裏面が表出している前記封止体をダイシングする工程Ｄとを有し、
    　前記工程Ｂ以降前記工程Ｃまでの間、及び／又は、前記工程Ｃ以降前記工程Ｄまでの間に、前記封止用シートにレーザーマーキングを行なう工程を有することを特徴とする半導体装置の製造方法。     Flip-chip bonding the semiconductor chip to the circuit forming surface of the semiconductor wafer; and
    A step B of forming a sealing body by embedding the semiconductor chip flip-chip bonded to the semiconductor wafer in a sealing sheet;
    Step C for exposing the back surface of the semiconductor chip by grinding the sealing sheet of the sealing body;
    And a step D of dicing the sealing body exposed from the back surface of the semiconductor chip,
    A method of manufacturing a semiconductor device comprising a step of performing laser marking on the sealing sheet between the step B and the step C and / or between the step C and the step D. .
  2. 　前記封止用シートにおける前記半導体ウエハと対向する面とは反対の面側には、着色剤が添加されていることを特徴とする請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein a colorant is added to a surface of the sealing sheet opposite to the surface facing the semiconductor wafer.
PCT/JP2014/066873 2013-07-05 2014-06-25 Method for manufacturing semiconductor device WO2015002048A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-141274 2013-07-05
JP2013141274A JP2015015369A (en) 2013-07-05 2013-07-05 Semiconductor device manufacturing method

Publications (1)

Publication Number Publication Date
WO2015002048A1 true WO2015002048A1 (en) 2015-01-08

Family

ID=52143626

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/066873 WO2015002048A1 (en) 2013-07-05 2014-06-25 Method for manufacturing semiconductor device

Country Status (3)

Country Link
JP (1) JP2015015369A (en)
TW (1) TW201513294A (en)
WO (1) WO2015002048A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106793488A (en) * 2015-11-20 2017-05-31 财团法人工业技术研究院 Flexible electronic device and manufacturing process method thereof

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI643696B (en) * 2015-11-20 2018-12-11 財團法人工業技術研究院 Bonding/debonding device and bonding method and debonding method for using the same
WO2018203487A1 (en) * 2017-05-01 2018-11-08 アルプス電気株式会社 Circuit module
JP2024015735A (en) * 2022-07-25 2024-02-06 株式会社レゾナック Film for temporary fixing, laminate for temporary fixing, manufacturing method of semiconductor device, and composition for temporary fixing

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332654A (en) * 2000-03-17 2001-11-30 Matsushita Electric Ind Co Ltd Module provided with built-in electric element and manufacturing method thereof
JP2007288170A (en) * 2006-03-20 2007-11-01 Hitachi Chem Co Ltd Die-bond dicing sheet
JP2007311416A (en) * 2006-05-16 2007-11-29 Fujifilm Corp Solid-state imaging device
JP2008109346A (en) * 2006-10-25 2008-05-08 Kyocera Corp Surface acoustic wave device, and method for manufacturing the same
JP2013093403A (en) * 2011-10-25 2013-05-16 Murata Mfg Co Ltd Method for printing on electronic component

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332654A (en) * 2000-03-17 2001-11-30 Matsushita Electric Ind Co Ltd Module provided with built-in electric element and manufacturing method thereof
JP2007288170A (en) * 2006-03-20 2007-11-01 Hitachi Chem Co Ltd Die-bond dicing sheet
JP2007311416A (en) * 2006-05-16 2007-11-29 Fujifilm Corp Solid-state imaging device
JP2008109346A (en) * 2006-10-25 2008-05-08 Kyocera Corp Surface acoustic wave device, and method for manufacturing the same
JP2013093403A (en) * 2011-10-25 2013-05-16 Murata Mfg Co Ltd Method for printing on electronic component

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106793488A (en) * 2015-11-20 2017-05-31 财团法人工业技术研究院 Flexible electronic device and manufacturing process method thereof
CN106793488B (en) * 2015-11-20 2019-04-30 财团法人工业技术研究院 Flexible electronic device and manufacturing process method thereof

Also Published As

Publication number Publication date
TW201513294A (en) 2015-04-01
JP2015015369A (en) 2015-01-22

Similar Documents

Publication Publication Date Title
JP6216180B2 (en) Sealing sheet and semiconductor device manufacturing method using the sealing sheet
JP6272690B2 (en) Sealing sheet with double-sided separator and method for manufacturing semiconductor device
CN105666976B (en) Application of the dicing tape-integrated film for semiconductor back surface in laser-marking
JP6066856B2 (en) Semiconductor device manufacturing method and sealing sheet
CN102382585B (en) Film for flip chip type semiconductor back surface, the semiconductor back surface production method of strip film and flip chip type semiconductor device
TW201729309A (en) Semiconductor package manufacturing method
WO2015002048A1 (en) Method for manufacturing semiconductor device
CN105493270A (en) Resin sheet for sealing electronic device and method for manufacturing electronic device package
WO2015098852A1 (en) Electronic component device production method and electronic component sealing sheet
WO2015037458A1 (en) Method for manufacturing semiconductor device
WO2016117268A1 (en) Sealing sheet
WO2015033867A1 (en) Method for manufacturing semiconductor device
JP2015032648A (en) Semiconductor device manufacturing method
US10074582B2 (en) Sealing sheet
JP2015220350A (en) Semiconductor device manufacturing method
WO2015053081A1 (en) Method for manufacturing semiconductor device
JP2015126060A (en) Semiconductor device manufacturing method
JP2016115741A (en) Electronic device package and sheet for sealing

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14820668

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14820668

Country of ref document: EP

Kind code of ref document: A1