WO2014198550A1 - Verfahren zur herstellung eines nitridverbindungshalbleiter-bauelements - Google Patents
Verfahren zur herstellung eines nitridverbindungshalbleiter-bauelements Download PDFInfo
- Publication number
- WO2014198550A1 WO2014198550A1 PCT/EP2014/061139 EP2014061139W WO2014198550A1 WO 2014198550 A1 WO2014198550 A1 WO 2014198550A1 EP 2014061139 W EP2014061139 W EP 2014061139W WO 2014198550 A1 WO2014198550 A1 WO 2014198550A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- buffer layer
- semiconductor layer
- layer sequence
- layer
- sequence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
- H10H20/0137—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials the light-emitting regions comprising nitride materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2902—Materials being Group IVA materials
- H10P14/2905—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
- H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
- H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
- H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/018—Bonding of wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/811—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
- H10H20/812—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/815—Bodies having stress relaxation structures, e.g. buffer layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2926—Crystal orientations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
- H10P14/3216—Nitrides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3242—Structure
- H10P14/3244—Layer structure
- H10P14/3254—Graded layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
- H10P14/3416—Nitrides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/8215—Bodies characterised by crystalline imperfections, e.g. dislocations; characterised by the distribution of dopants, e.g. delta-doping
Definitions
- the invention relates to a method for producing a nitride compound semiconductor device on a substrate having a silicon surface.
- Nitride compound semiconductors are commonly used in LEDs or
- Laser diodes are used, usually in blue
- Emit spectral range Depending on the composition of the semiconductor material, for example, an emission in the ultraviolet or green spectral range is possible. Luminescence conversion by means of phosphors, the
- Nitride compound semiconductor based LEDs are therefore of considerable importance for LED lighting systems.
- the nitride compound semiconductor layers are typically epitaxially grown on a growth substrate that conforms to the lattice constant and crystal structure of the growth factor
- Nitride compound semiconductor material is adjusted. Suitable substrate materials are in particular sapphire, GaN or SiC. However, these substrate materials are comparatively expensive. The growth of nitride compound semiconductors
- nitride compound semiconductors used growth temperature of about 1000 ° C to room temperature generated large tensile stresses in GaN.
- WO 2011/039181 A1 discloses processes for the production of nitride compound semiconductor components
- the publication WO 2013/045355 Al describes a method for producing nitride compound semiconductor components on silicon substrates, in which a layer structure is arranged between the silicon substrate and the functional layer sequence of the optoelectronic component, in which a masking layer of a silicon nitride-containing material is embedded. Embedding the masking layer achieves a reduction in dislocation density.
- the invention is based on the object, a further
- Specify nitride compound semiconductor device on a substrate with a silicon surface can be achieved by the particularly low defect densities in the semiconductor layer sequence, and which is characterized by a relatively low production cost.
- the growth substrate may in particular be a silicon substrate.
- the growth substrate may be an SOI substrate (Silicon On Insulator).
- a buffer layer having Al x In y Ga x - y N with O x 1, O x y y and x + y ⁇ 1 is applied to the silicon surface
- the buffer layer preferably has Al x Gai x N with 0 ⁇ x ⁇ 1.
- Semiconductor layer sequence is based on a nitride compound semiconductor. "On a nitride compound semiconductor based "means in this context that the semiconductor layer sequence or at least one layer thereof comprises a III-nitride compound semiconductor material, preferably Al m In y Ga m - n N, where 0 ⁇ m ⁇ 1, 0 ⁇ n ⁇ 1 and m + n ⁇ 1. This material does not necessarily have a III-nitride compound semiconductor material, preferably Al m In y Ga m - n N, where 0 ⁇ m ⁇ 1, 0 ⁇ n ⁇ 1 and m + n ⁇ 1. This material does not necessarily have a III-nitride compound semiconductor material, preferably Al m In y Ga m - n N, where 0 ⁇ m ⁇ 1, 0 ⁇ n ⁇ 1 and m + n ⁇ 1. This material does not necessarily have a III-nitride compound semiconductor material, preferably Al m In y
- the above formula contains only the essential constituents of the crystal lattice (Al, In, Ga, N), even if these may be partially replaced by small amounts of other substances.
- the nitride compound semiconductor device is according to
- the semiconductor layer sequence contains in particular an active layer of the optoelectronic component.
- Example a light-emitting diode layer sequence.
- the active layer is in particular one during operation of the component
- Radiation-emitting layer for example, as a pn junction, as a double heterostructure, as a single quantum well structure or multiple quantum well structure
- the light-emitting diode layer sequence may include, for example, an n-type semiconductor region and a p-type semiconductor region
- the buffer layer is provided with an in
- the buffer layer advantageously has one varying material composition, such that a lateral lattice constant of the buffer layer gradually or continuously increases in a first region and in a second region, that of the first region in the growth direction
- the lateral lattice constant is to be understood here and below as meaning the lattice constant in the direction perpendicular to the direction of growth.
- the buffer layer preferably consists exclusively of the first region and the second region, i. the buffer layer has no further regions apart from the first region and the second region following in the growth direction.
- the buffer layer has a smaller lateral lattice constant than a semiconductor layer of the semiconductor layer sequence adjoining the buffer layer.
- Buffer layer having such a varying lattice constant, a particularly low defect density in the
- Lattice constant of the buffer layer in the second region is gradually or continuously reduced so that they are at the interface to the subsequent
- Interface to the semiconductor layer sequence addition but end in the region of the interface.
- the buffer layer has a smaller lateral
- Lattice constant has as the adjacent semiconductor layer of the semiconductor layer sequence, the
- the spatial variation of the lattice constant of the buffer layer in the growth direction takes place in that the
- Material composition is gradually or continuously changed during growth. This is preferably realized by the fact that the aluminum content x of the material Al x In y Gai x - y N of the buffer layer decreases in the first region and increases again in the second region. Since the
- Lattice constant is reduced in this material system with increasing aluminum content, is achieved in this way that the lattice constant increases in the first region and decreases in the second region.
- the buffer layer can be
- the buffer layer advantageously has an aluminum content x.sub.0.8, preferably 0.times.0.9, at an interface with the growth substrate.
- the buffer layer has AIN at the interface with the growth substrate.
- the aluminum content x in the buffer layer advantageously has a minimum, wherein at least x ⁇ 0.6, preferably x -S 0.2, particularly preferably x -S 0.1 applies.
- the aluminum content is gradually or continuously reduced in the first range to decrease to a value of x ⁇ 0.6, preferably x-S 0.2 or even x ⁇ 0.1, and in the following second range is increased again gradually or continuously.
- Aluminum content x is thus reached at the boundary between the first region and the second region.
- the buffer layer advantageously has an aluminum content x.gtoreq.0.6, preferably x.sub.0.8 or even x.gtoreq.0.9.
- a semiconductor layer of the semiconductor layer sequence adjoining the buffer layer preferably has Al m In n Ga m - n N, where m ⁇ 0.5. Preferably, m ⁇ 0.2 or even m ⁇ 0.1.
- the adjacent to the buffer layer semiconductor layer of the semiconductor layer sequence thus advantageously has a much lower aluminum content than the buffer layer at the interface to the semiconductor layer sequence.
- the silicon surface of the growth substrate is a (111) plane.
- the (111) plane of a silicon crystal is particularly well suited for growing a hexagonal nitride compound semiconductor material due to the quasi-hexagonal crystal structure.
- the semiconductor layer sequence is advantageously connected to a carrier substrate on a surface lying opposite the growth substrate. Since the carrier substrate does not have to be suitable for growing a nitride compound semiconductor material, it can advantageously be selected on the basis of other criteria, in particular a good thermal and / or electrical conductivity. In the case of an optoelectronic nitride compound semiconductor device, before the semiconductor layer sequence is connected to the carrier substrate, a mirror layer can be applied to the semiconductor substrate
- Semiconductor layer sequence can be applied to those emitted during operation of the optoelectronic nitride compound semiconductor device in the direction of the carrier substrate
- the buffer layer can be at least partially removed, for example by an etching process.
- the remaining remainder of the buffer layer is on in this case arranged the radiation exit side of the optoelectronic component.
- Figure 1 is applied to a silicon substrate
- FIG. 3 shows a coating applied to a silicon substrate
- Figure 4 is a graph of measured
- Growth substrate 1 is provided, which has a silicon surface.
- the growth substrate 1 can
- the growth substrate 1 for example, be a silicon wafer.
- the growth substrate 1 it is also possible for the growth substrate 1 to be an SOI substrate.
- the silicon surface of the growth substrate 1 is preferably a (111) crystal plane which, because of its hexagonal symmetry, is particularly good for growing
- Nitride compound semiconductors is suitable. Then Nitride compound semiconductors is suitable. The
- Nitride compound semiconductor materials used substrates of sapphire, GaN or SiC has the advantage that it is relatively inexpensive.
- a buffer layer 2 of Al x In y Gai- x - y N is first grown in the method with O.sub.x 1, O.sub.y 1 and x + y ⁇ 1.
- the indium component y 0, ie the buffer layer has Al x Ga x -N with 0 ⁇ x ⁇ 1.
- the illustrated embodiment the
- Material composition of the buffer layer 2 during growth has been varied such that the lateral lattice constant of the buffer layer 2 in a first region 2a continuously increases and decreases continuously in a subsequent in the growth direction second region 2b.
- Embodiment is a light-emitting diode layer sequence is shown schematically in Figure 1.
- the aluminum content x of the buffer layer 2 is at the interface between the growth substrate 1 and the
- the aluminum content x initially decreases continuously in the first region 2a. This has the consequence that the lateral lattice constant of the
- Nitride compound semiconductor material continuously increased.
- the aluminum content x reaches a minimum and, correspondingly, the lattice constant of the nitride compound semiconductor material reaches a maximum.
- the aluminum component x advantageously has a
- a next step a
- the semiconductor layer sequence 3 is the light-emitting diode layer sequence of an optoelectronic component.
- Light-emitting diode layer sequence 3 is based on a nitride compound semiconductor.
- the light-emitting diode layer sequence 3 contains in particular an active layer 5 which is suitable for the emission of radiation.
- the active layer 5 may be formed, for example, as a pn junction, a double heterostructure, a single quantum well structure, or a multiple quantum well structure.
- Designation Quantum well structure includes any
- Quantum well structure no information about the dimensionality of the quantization. It thus includes quantum wells, quantum wires and quantum dots and any combination of these structures.
- the light-emitting diode layer sequence 3 contains at least one semiconductor layer 4 of a first conductivity type and at least one semiconductor layer 6 of a second
- the aluminum content of the buffer layer 2 is preferably increased continuously in the second region 2b in such a way that the aluminum content at the interface to the
- Light emitting diode layer sequence 3 is greater than that Aluminum content of the semiconductor layer 4 of
- Light-emitting diode layer sequence 3 which adjoins the buffer layer 2.
- the semiconductor layer 4 adjoining the light-emitting diode layer sequence 3 advantageously has Al m In n Ga m - n N, where m ⁇ 0.5. In particular, m ⁇ 0.2 or even m ⁇ 0.1. Due to the fact that the aluminum content of the
- Buffer layer 2 adjacent semiconductor layer 4 is smaller than the aluminum content of the buffer layer 2 at the
- the adjacent to the buffer layer 2 semiconductor layer 4 is grown with a compressive strain. This has the advantage that a tensile stress, the cooling of the
- Layer system can occur from the growth temperature to room temperature, counteracted.
- Embodiment of the method for producing a nitride compound semiconductor device shown The layer sequence differs from the embodiment of Figure 1 in that the aluminum content x in the
- Buffer layer 2 is not continuous, but varies gradually. In a first region 2a facing the growth substrate 1, the aluminum content x in the buffer layer 2 gradually decreases and decreases in one of the
- the buffer layer 2 has a plurality of partial layers in the first region 2a, wherein the aluminum content x decreases step by step from partial layer to partial layer. Furthermore, the buffer layer has a plurality of partial layers in the second region 2b, wherein the
- Aluminum content x gradually increases from partial layer to partial layer.
- the second embodiment corresponds to the first embodiment described above.
- a layer sequence on a growth substrate 1 made of silicon is not
- the buffer layer 2 at the interface with the light-emitting diode layer sequence 3 has substantially the same lattice constant as that of the buffer layer 2
- Layer sequence Sl is less than in the layer sequence S3, which was prepared according to the comparative example not according to the invention.
- Reflections in the examination by means of X-ray diffraction indicate a reduced defect density of the layer sequence in the exemplary embodiment according to the invention.
Landscapes
- Led Devices (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
Abstract
Description
Claims
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/891,924 US9660137B2 (en) | 2013-06-11 | 2014-05-28 | Method for producing a nitride compound semiconductor device |
| JP2016518909A JP6138359B2 (ja) | 2013-06-11 | 2014-05-28 | 窒化物系化合物半導体素子を製造する方法 |
| CN201480033604.4A CN105308720B (zh) | 2013-06-11 | 2014-05-28 | 用于制造氮化物化合物半导体器件的方法 |
| DE112014002779.0T DE112014002779B8 (de) | 2013-06-11 | 2014-05-28 | Verfahren zur Herstellung eines Nitrid-Verbindungshalbleiter-Bauelements |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102013106044 | 2013-06-11 | ||
| DE102013106044.7 | 2013-06-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2014198550A1 true WO2014198550A1 (de) | 2014-12-18 |
Family
ID=50897572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/EP2014/061139 Ceased WO2014198550A1 (de) | 2013-06-11 | 2014-05-28 | Verfahren zur herstellung eines nitridverbindungshalbleiter-bauelements |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9660137B2 (de) |
| JP (1) | JP6138359B2 (de) |
| CN (1) | CN105308720B (de) |
| DE (1) | DE112014002779B8 (de) |
| WO (1) | WO2014198550A1 (de) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102018119634A1 (de) * | 2018-08-13 | 2020-02-13 | Osram Opto Semiconductors Gmbh | Verfahren zur herstellung eines halbleiterbauelements und werkstück |
| US11018278B2 (en) | 2017-03-02 | 2021-05-25 | Osram Oled Gmbh | Semiconductor body |
| US20240170564A1 (en) * | 2022-11-18 | 2024-05-23 | Globalwafers Co., Ltd. | Epitaxial structure |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20210135050A1 (en) * | 2017-08-14 | 2021-05-06 | Sony Corporation | Template substrate, electronic device, light emitting device, method of manufacturing template substrate, and method of manufacturing electronic device |
| KR20190079787A (ko) * | 2017-12-28 | 2019-07-08 | 삼성전자주식회사 | 반도체 발광소자의 제조 방법 |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102006008929A1 (de) | 2006-02-23 | 2007-08-30 | Azzurro Semiconductors Ag | Nitridhalbleiter-Bauelement und Verfahren zu seiner Herstellung |
| US20100289067A1 (en) * | 2009-05-14 | 2010-11-18 | Transphorm Inc. | High Voltage III-Nitride Semiconductor Devices |
| WO2011039181A1 (de) | 2009-09-30 | 2011-04-07 | Osram Opto Semiconductors Gmbh | Verfahren zur herstellung einer leuchtdiode |
| US20110266522A1 (en) * | 2010-04-28 | 2011-11-03 | Samsung Electronics Co., Ltd. | Semiconductor device |
| WO2013045355A1 (de) | 2011-09-30 | 2013-04-04 | Osram Opto Semiconductors Gmbh | Verfahren zur herstellung eines optoelektronischen nitrid-verbindungshalbleiter-bauelements |
| US20130140525A1 (en) * | 2011-12-01 | 2013-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gallium nitride growth method on silicon substrate |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10056475B4 (de) * | 2000-11-15 | 2010-10-07 | Osram Opto Semiconductors Gmbh | Strahlungsemittierendes Halbleiterbauelement auf GaN-Basis mit verbesserter p-Leitfähigkeit und Verfahren zu dessen Herstellung |
| JP2004179452A (ja) | 2002-11-28 | 2004-06-24 | Shin Etsu Handotai Co Ltd | ヘテロエピタキシャルウエーハ |
| KR100585919B1 (ko) * | 2004-01-15 | 2006-06-01 | 학교법인 포항공과대학교 | 질화갈륨계 ⅲⅴ족 화합물 반도체 소자 및 그 제조방법 |
| KR100756841B1 (ko) * | 2006-03-13 | 2007-09-07 | 서울옵토디바이스주식회사 | AlxGa1-xN 버퍼층을 갖는 발광 다이오드 및 이의제조 방법 |
| US7655962B2 (en) | 2007-02-23 | 2010-02-02 | Sensor Electronic Technology, Inc. | Enhancement mode insulated gate heterostructure field-effect transistor with electrically isolated RF-enhanced source contact |
| JP4592742B2 (ja) * | 2007-12-27 | 2010-12-08 | Dowaエレクトロニクス株式会社 | 半導体材料、半導体材料の製造方法及び半導体素子 |
| US8227791B2 (en) | 2009-01-23 | 2012-07-24 | Invenlux Limited | Strain balanced light emitting devices |
| WO2011108519A1 (ja) * | 2010-03-02 | 2011-09-09 | Jx日鉱日石金属株式会社 | 半導体エピタキシャル基板 |
| DE102010035489A1 (de) | 2010-08-26 | 2012-03-01 | Osram Opto Semiconductors Gmbh | Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelement |
| JP5742072B2 (ja) * | 2010-10-06 | 2015-07-01 | 住友電気工業株式会社 | 半導体装置およびその製造方法 |
| JP5672926B2 (ja) * | 2010-10-08 | 2015-02-18 | 富士通株式会社 | 化合物半導体装置及びその製造方法 |
| JP5781292B2 (ja) * | 2010-11-16 | 2015-09-16 | ローム株式会社 | 窒化物半導体素子および窒化物半導体パッケージ |
| US9012939B2 (en) | 2011-08-02 | 2015-04-21 | Kabushiki Kaisha Toshiba | N-type gallium-nitride layer having multiple conductive intervening layers |
| JP5127978B1 (ja) | 2011-09-08 | 2013-01-23 | 株式会社東芝 | 窒化物半導体素子、窒化物半導体ウェーハ及び窒化物半導体層の製造方法 |
-
2014
- 2014-05-28 CN CN201480033604.4A patent/CN105308720B/zh active Active
- 2014-05-28 JP JP2016518909A patent/JP6138359B2/ja active Active
- 2014-05-28 DE DE112014002779.0T patent/DE112014002779B8/de active Active
- 2014-05-28 WO PCT/EP2014/061139 patent/WO2014198550A1/de not_active Ceased
- 2014-05-28 US US14/891,924 patent/US9660137B2/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102006008929A1 (de) | 2006-02-23 | 2007-08-30 | Azzurro Semiconductors Ag | Nitridhalbleiter-Bauelement und Verfahren zu seiner Herstellung |
| US20100289067A1 (en) * | 2009-05-14 | 2010-11-18 | Transphorm Inc. | High Voltage III-Nitride Semiconductor Devices |
| WO2011039181A1 (de) | 2009-09-30 | 2011-04-07 | Osram Opto Semiconductors Gmbh | Verfahren zur herstellung einer leuchtdiode |
| US20110266522A1 (en) * | 2010-04-28 | 2011-11-03 | Samsung Electronics Co., Ltd. | Semiconductor device |
| WO2013045355A1 (de) | 2011-09-30 | 2013-04-04 | Osram Opto Semiconductors Gmbh | Verfahren zur herstellung eines optoelektronischen nitrid-verbindungshalbleiter-bauelements |
| US20130140525A1 (en) * | 2011-12-01 | 2013-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gallium nitride growth method on silicon substrate |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11018278B2 (en) | 2017-03-02 | 2021-05-25 | Osram Oled Gmbh | Semiconductor body |
| DE102018119634A1 (de) * | 2018-08-13 | 2020-02-13 | Osram Opto Semiconductors Gmbh | Verfahren zur herstellung eines halbleiterbauelements und werkstück |
| US20240170564A1 (en) * | 2022-11-18 | 2024-05-23 | Globalwafers Co., Ltd. | Epitaxial structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105308720B (zh) | 2017-10-20 |
| JP6138359B2 (ja) | 2017-05-31 |
| JP2016530700A (ja) | 2016-09-29 |
| DE112014002779B8 (de) | 2022-12-15 |
| DE112014002779A5 (de) | 2016-02-25 |
| US20160093765A1 (en) | 2016-03-31 |
| CN105308720A (zh) | 2016-02-03 |
| DE112014002779B4 (de) | 2022-09-22 |
| US9660137B2 (en) | 2017-05-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE102011114665B4 (de) | Verfahren zur Herstellung eines optoelektronischen Nitrid-Verbindungshalbleiter-Bauelements | |
| DE112006001084B4 (de) | Licht emittierende Bauelemente mit aktiven Schichten, die sich in geöffnete Grübchen erstrecken | |
| DE112004001447B4 (de) | Nitridhalbleiter-Licht-emittierende Einrichtung | |
| DE112015000824B4 (de) | Verfahren zur Herstellung eines elektronischen Halbleiterchips | |
| DE102008026828A1 (de) | Bildung von nitrid-basierten optoelektronischen und elektronischen Bauteilstrukturen auf gitterangepassten Substraten | |
| DE112012001920B9 (de) | Strahlung emittierender Halbleiterchip mit integriertem ESD-Schutz | |
| EP2483914A1 (de) | Verfahren zur herstellung einer leuchtdiode | |
| DE112014002779B4 (de) | Verfahren zur Herstellung eines Nitrid-Verbindungshalbleiter-Bauelements | |
| DE102011115312B4 (de) | Halbleiterschichtenfolge, optoelektronischer Halbleiterchip und Verfahren zur Herstellung einer Halbleiterschichtenfolge | |
| DE112014001352T5 (de) | Lichtemitterdioden-Halbleiterstrukturen mit aktiven Gebieten, die InGaN enthalten | |
| WO2015011155A1 (de) | Optoelektronischer halbleiterchip mit einem mehrfach-quantentopf mit mindestens einer hochbarrierenschicht | |
| DE102010052727B4 (de) | Verfahren zum Herstellen eines optoelektronischen Halbleiterchips und derartiger Halbleiterchip | |
| DE102012215135A1 (de) | Lichtemittierendes Bauelement aus einem Nitridhalbleiter und Verfahren zur Herstellung desselben | |
| DE102015114478A1 (de) | Optoelektronischer Halbleiterchip und Verfahren zu dessen Herstellung | |
| WO2019145216A1 (de) | Verfahren zur herstellung eines nitrid-verbindungshalbleiter-bauelements | |
| WO2012035135A1 (de) | Halbleiterchip und verfahren zu dessen herstellung | |
| DE102011113775B4 (de) | Verfahren zur Herstellung eines optoelektronischen Bauelements | |
| EP1770767B1 (de) | Halbleitersubstrat aus GaAs und Halbleiterbauelement | |
| WO2017021301A1 (de) | Verfahren zur herstellung eines nitrid-halbleiterbauelements und nitrid-halbleiterbauelement | |
| WO2018041778A1 (de) | Optoelektronisches bauelement | |
| DE102011112713A1 (de) | Optoelektronisches Bauelement | |
| DE112019003193B4 (de) | Halbleiterbauelement mit druckverspannter schicht und verfahren zur herstellung des halbleiterbauelements mit druckverspannter schicht | |
| DE102013200507A1 (de) | Optoelektronisches Halbleiterbauelement | |
| EP1649497B1 (de) | Verfahren zur herstellung einer vielzahl von optoelektronischen halbleiterchips und optoelektronischer halbleiterchip | |
| WO2026068104A1 (de) | Optoelektronisches bauelement und optoelektronische vorrichtung |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WWE | Wipo information: entry into national phase |
Ref document number: 201480033604.4 Country of ref document: CN |
|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 14728892 Country of ref document: EP Kind code of ref document: A1 |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 14891924 Country of ref document: US |
|
| ENP | Entry into the national phase |
Ref document number: 2016518909 Country of ref document: JP Kind code of ref document: A |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 112014002779 Country of ref document: DE |
|
| REG | Reference to national code |
Ref country code: DE Ref legal event code: R225 Ref document number: 112014002779 Country of ref document: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 14728892 Country of ref document: EP Kind code of ref document: A1 |