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  • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
  • H10F10/144—Photovoltaic cells having only PN homojunction potential barriers comprising only Group III-V materials, e.g. GaAs,AlGaAs, or InP photovoltaic cells
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  • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
  • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
  • H10F10/163—Photovoltaic cells having only PN heterojunction potential barriers comprising only Group III-V materials, e.g. GaAs/AlGaAs or InP/GaInAs photovoltaic cells
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  • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
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  • H10F71/127—The active layers comprising only Group III-V materials, e.g. GaAs or InP
  • H10F71/1276—The active layers comprising only Group III-V materials, e.g. GaAs or InP comprising growth substrates not made of Group III-V materials
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  • H10F71/138—Manufacture of transparent electrodes, e.g. transparent conductive oxides [TCO] or indium tin oxide [ITO] electrodes
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  • H10F77/143—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies comprising quantum structures
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  • H10F77/10—Semiconductor bodies
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  • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
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  • H10F77/30—Coatings
  • H10F77/306—Coatings for devices having potential barriers
  • H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
  • Y02E10/543—Solar cells from Group II-VI materials
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
  • Y02E10/544—Solar cells from Group III-V materials
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
  • Y02E10/548—Amorphous silicon PV cells

Definitions

• the disclosure relates principally to a solar cell structure comprising an array of elongated nanowires made in a semiconductor material having a direct band gap.
• a solar cell is to be construed as a single diode designed for photovoltaic applications including its electrical contacts and current spreading layers.
• the Si-based solar cell may display a range of options.
• a Si-wafer can be about 200 ⁇ thick, has a textured surface and an anti-reflection coating (by e.g. SiNx).
• the wafer is frequently p-type with a shallow emitter facing the sun, and with a back- surface field generated by in-diffusion of Al or other p-type dopant.
• Large numbers of Si solar cells are typically connected in series to minimize resistive losses due to high currents.
• Cadmium-Telluride (CdTe) solar cell the most successful one to date being the Cadmium-Telluride (CdTe) solar cell.
• CdTe Cadmium-Telluride
• thin film solar cell technologies a material with stronger light absorption characteristics than silicon is deposited in a planar film on a low cost substrate (such as glass). The thickness of the film is approximately 1 % of the thickness of a conventional Si-based solar cell. Since the solar cell is created in a material that is typically deposited on top of a substrate, e.g. by Chemical Vapor Deposition (CVD) or sputtering, rather than being the substrate itself, thin film technologies are normally not limited by wafer form factors but can be made in large sheets.
• CVD Chemical Vapor Deposition
• sputtering rather than being the substrate itself
• thin film emitter is typically less conductive than the Si-emitter
• a transparent conductive oxide (TCO) has to be deposited on the sun-facing side.
• TCO transparent conductive oxide
• GaAs is the material of choice for single junction solar cells due to ideal properties of its band gap and its high photon absorption. With respect to production
• GaAs is a suitable material in single junction solar cell applications due to its low etch rate in hydrofluoric acid. GaAs is also one of the base materials for high efficiency tandem solar cells, i.e. solar cells containing several p-n junctions where each junction is tuned to a different wavelength of light. These are typically based on Ge/GaAs/lnGaP and related materials, indicating a path for bringing this technology to efficiencies well exceeding 40%. In this context, these extreme efficiency levels have already been reached for bulk planar lll-V tandem solar cells for space applications.
• nanowire elongated nanosized structure
• GaAs nanowire solar cells preferably aggregated in an array, may reduce the use of material by almost an order of magnitude compared with thin film solar cells in the same material. Diameter of such a nanowire is frequently 150-200 nm and its length spans between 1 -3 ⁇ .
• These nanowires are typically made in GaAs, but also in InP and other suitable compounds having a direct band gap.
• nanowire based solar cells provide a large number of options for tandem cell designs.
• At least two different types of nanowires for solar cell applications may be distinguished based on the position of the pn-junction.
• First type is a nanowire with an axially provided pn-junction, i.e. the pn-junction is so configured that the principal direction of current flow across the pn-junction coincides with the axial direction of the nanowire.
• Second type are nanowires with a radially provided pn-junction, i.e.
• the pn-junction is so configured that at least a portion of the current flow across the junction is perpendicular to the axial direction of the nanowire, and so that the area of the junction corresponding to said portion of the current flow is larger than the area of other parts of the junction. Further, the junction has an essentially radial symmetry. In conjunction with the above and at least when it comes to GaAs, nanowires with radially provided pn-junction are more widely spread.
• semiconductor nanowires for use in solar cells are typically grown from a costly substrate, frequently called wafer, where after remaining components of the solar cell are integrated on this substrate, rendering hereby this technology very expensive, particularly in case of a l ll-V-wafer such as GaAs.
• the nanowire material is the same, or similar to, the substrate it is grown from and integrated on.
• GaAs-nanowires are, for instance, often grown on a GaAs-wafer.
• lll-V nanowires e.g. InP or GaAs, may be grown on a substrate that is a conventional silicon wafer. It is here worth noting that silicon-based semiconductor nanowires, usually also grown on a silicon wafer, are well-known in the art, but hitherto acquired knowledge as regards their manufacture and integration into solar cells isn't readily
• wafer-based solar cell technology both silicon and GaAs-wafers
• the wafer area itself defines the cell area, which in turn relates to the current level.
• additional metallization may be needed to minimize resistive losses in conducting spreading layers such as emitters or transparent conductors.
• the final substrate is typically passive and non-conducting, e.g. glass, so that segmentation of the thin film in order to reduce current levels is enabled. This separates the physical size of the used substrate from the current level reached in the solar cell, which results in several advantages - for instance advent of the economies of scale and the possibility to tailor current levels in order to minimize resistive losses in emitter or transparent conducting layers, respectively.
• the need for metallization grids may be eliminated.
• nanowire based solar cells integrated on a semiconductor substrate Another issue with nanowire based solar cells integrated on a semiconductor substrate is that the light being transmitted through the nanowire array is wasted as heat once it is absorbed in the semiconductor substrate unless a separate, differently tuned solar cell is fabricated in the substrate itself - a considerable challenge considering known difficulties in integration of dissimilar materials.
• a crystalline wafer can be dispensed with in the final product. This can either be done by, at some point, separating the nanowires from the crystalline substrate (and preferably subsequently reusing the substrate), or by downright avoiding use of the substrate in the chain of fabrication of the structure.
• substrate-free growth techniques such as AerotaxyTM disclosed in the International Patent
• a further aspect of nanowire-based solar cells is a high surface-to-volume ratio when compared to planar solar cells belonging to the prior art. This is particularly true for many direct band-gap compound semiconductors of group- Ill and group- V, respectively.
• GaAs is of particular interest as a solar cell material, but it is well documented that its surfaces are very poor. More specifically, the high density of surface states depletes the surfaces and causes recombination of minority carriers.
• heterostructure passivation layers of AIGaAs, GalnP etc. are typically grown on the planar surface to reflect minority carriers which effectively reduce the surface induced recombination.
• nanowire arrays having nanowires with axially as well as radially provided pn-junctions, seem to be promising candidates when it comes to increasing efficiency while decreasing material usage in solar cells.
• a number of outstanding questions are still to be answered in this respect.
• some of the criteria that need to be satisfied in order to achieve a viable solution in this respect are high throughput and reliability.
• energy efficiency of the novel structures should at any rate match that of the standard solar cells currently available in the marketplace.
• a further challenge lies in maintaining the alignment of the nanowires and meeting the contacting requirements in view of the top and bottom contacts. This is particularly true in the case where the nanowires are significantly shorter than any support material used to separate the nanowires from the original substrate.
• An objective of the present invention is therefore to provide a solar cell structure that at least reduces some of the drawbacks associated with the current art.
• An overall object behind the invention is to provide a structure that combine high solar cell conversion efficiencies, e.g. of lll-V direct band gap semiconductors, with the low cost of manufacturing of thin film solar cells.
• direct band gap semiconducting nanowires can achieve the light gathering capacity approaching that of a planar film, but with nearly an order of magnitude less material.
• such demonstrations have been performed with nanowires integrated on an expensive substrate and don't capture the necessary structural elements for a low cost, high efficiency nanowire solar cell.
• one aspect of the present invention provides a solar cell structure comprising an array of elongated nanowires made in a semiconductor material having a direct band gap, wherein each nanowire has at least a first and a second sections, a first electrode layer realizing ohmic contact to at least one portion of each first section at a bottom end of each nanowire, a second, optically transparent, electrode layer realizing contact to at least one portion of each second section at a top end of each nanowire, characterized in that each nanowire comprises a minority carrier protection element for minimizing recombination of minority carriers at the contact to the second electrode layer.
• This aspect of the present invention addresses the issue of minority carrier losses in the part of the nanowire closest to the sun.
• lll-V semiconductors a majority of photons are absorbed in the first 1 00-200 nm of semiconductor material, which also holds true for properly designed arrays of nanowires made from lll-V semiconductors, such as GaAs or InP.
• the top contact facing the sun
• the top contact has a very small area compared to the entire top surface area (or junction area), so that the recombination properties of the contact can be dealt with separately from the recombination properties of most of the surface area.
• the present invention includes a functional element or structure, herein generally referred to as a minority carrier protection element, for the purpose of minimizing these losses.
• This functional element may comprise a constraint on the length of the semiconductor section extending above the top edge of the depletion region in the p-n junction diode. It may also be a graded dopant profile to provide a surface field to direct the carriers from the top surface.
• the functional element may also comprise a heterojunction barrier, either semiconducting barriers or dielectric barriers arranged such that minority carriers are reflected and see a chemically improved surface, but majority carriers do not see a barrier, or can tunnel to the transparent conductor.
• the invention relates to a solar cell structure comprising an array of elongated nanowires made in a semiconductor material having a direct band gap, wherein each nanowire has at least a first and a second sections, the first section having a first polarity and a doping level that at least exceeds 1 * 10 18 /cm 3 , wherein said structure further comprises a first electrode layer realizing ohmic contact to at least one portion of each first section, a second, optically transparent electrode layer realizing contact to at least one portion of each second section, an adhesive layer, optionally conductive, positioned underneath the first electrode layer, and an insulating layer that electrically separates the first and the second electrode layers, each nanowire further comprising a depletion region being adjacent to a top surface of the nanowire and extending at least in the longitudinal direction of the nanowire, wherein the distance between the top surface of the nanowire and the upper boundary of said depletion region is inferior to 180 nm.
• a second aspect of the present invention relates to a method for fabricating a solar cell structure comprising an array of elongated nanowires in a
• the first structure comprising the array of nanowires and a polymer matrix, said array of nanowires being completely embedded in said polymer matrix
• a third aspect of the invention relates to a solar cell structure comprising an array of elongated nanowires made in a semiconductor material having a direct band gap, wherein a first electrode layer realizing ohmic contact to at least one portion of a first section at a bottom end of each nanowire, a second, optically transparent, electrode layer realizing contact to at least one portion of a second section at a top end of each nanowire, characterized in that an upper face of the first electrode layer, facing the nanowires, has a plurality of recesses, and that said bottom ends of the nanowires are positioned in these recesses.
• the problem of providing a structure and method to maintain alignment of nanowires when transferred from one surface or matrix (for instance, a wafer or an interface between liquids, or in a polymer membrane) to another is addressed.
• the problem relates to means for performing the transfer without maintaining any of the original materials in support of alignment. This is important since the initial materials used to maintain alignment are often expensive, as in the case of a II I- V wafer, or not suitable for long term sun exposure, as in many polymer materials that may be suitable for harvesting of wires from a wafer, or even too thick relative to the nanowires, again as in many polymer materials that may be suitable for harvesting of wires from a wafer.
• the alignment is maintained by a particular structure of the conductor making ohmic contact to the section of the nanowire furthest away from the sun.
• This wrap-around back-contact structure provides mechanical support to the nanowires so that alignment is maintained through the integration even as all the original materials used to maintain alignment are replaced by other, more suitable materials (cost and function) of the final solar cell.
• nanowire solar cell concepts to date in particular those made from lll-V materials, have used active or conductive substrates
• the present invention enables integration of several connected solar cells on one single substrate, resulting in scale advantages and reduced losses from metallization layers.
• the inventive solar cell structure is achieved that is at least as energy-efficient as conventional structures. This is true for structures having an axially as well as a radially provided pn-junction. If the distance from the top surface of the nanowire to the upper boundary of the pn-junction, which more or less coincides with the extent of the high doped region, is inferior to 180 nm, Wallentin et al have showed (see in particular Fig. 3b) that the current was reduced to about 70% of the maximum current observed and even a larger proportion of the simulated peak values of current.
• the distance between the top surface of the nanowire and the upper boundary of the depletion region is controlled by the thickness of any high doped region near the top of the wire.
• This region should be kept short - in one embodiment it is less than 150 nm, in order to maintain current response.
• the thickness of the high doped region is less than 180 nm. At any rate, this thickness shouldn't exceed 240 nm. This is an important issue for wafer-free nanowire-based solar cells since layers used to maintain alignment and provide mechanical support are much thicker than the length of the nanowire, and may have non-uniformities larger than 240 nm.
• An extreme way to minimize the distance from the topmost part of the wire to the upper boundary of the photo collecting junction is to provide Schottky junction as the top contact.
• the upper boundary of the depletion region will correspond to the contact interface.
• the structure is accomplished with arbitrary spacing between the wires, i.e. tightly packed wire arrays are not indispensable in order to maintain alignment of the nanowires.
• Figs. 1 A and 1 B show an axial implementation
• Fig. 2 shows a radial implementation, of the nanowire-based solar cell according to different embodiments of the current invention.
• the axial implementations of Figs 1 A and 1 B have a 3-section nanowire 2 whereas the radial implementation of Fig. 2 also has a 3-section nanowire, the lowest section extending in the axial direction only.
• Figs. 3-15 show steps of a non-limiting method for manufacture of the solar cell structure of the present invention.
• Figs. 16-20 illustrate a way to serially connect solar cells.
• Fig. 1A shows a solar cell structure 1 according to an embodiment of the invention.
• each nanowire 2 extending substantially only in the axial direction, has a first section 3 at a back or lower end of the nanowire 2, and a second section 4 at a sun-facing end of the nanowire 2.
• the first section 3 is preferably a high doped section of a first polarity
• the second section 4 preferably is a high doped section of a second, complimentary, polarity.
• a first electrode layer 7 realizes ohmic contact to at least one portion of each first section 3 at the bottom end of each nanowire 2.
• a second, optically transparent, electrode layer 8 makes contact to at least one portion of each second section 4 at a top end of each nanowire.
• a third section 5 may be arranged between said first 3 and second 4 sections, wherein the first 3 and the second 4 sections have complementary polarities, and wherein doping level of the first 3 and second 4 section exceeds 1 * 1 0 A 18/cm3 and doping level of the third section 5 is lower than doping level of the first 3 and second 4 sections.
• the third section 5 preferably has the same polarity as the first section 3. The doping level requirement is to enable ohmic contact formation at low
• a passive, noncrystalline, supporting substrate 9 is arranged as a bottom carrier in this embodiment, attached by means of a bond matrix 1 0, e.g. an adhesive.
• the supporting substrate 9 may instead be arranged on the upper side of the structure 1 . Since Fig. 1 B shows an embodiment which in most aspects is similar to the embodiment of Fig. 1 A, the general description given with respect to Fig. 1 A is therefore also applicable to the embodiment of Fig. 1 B.
• the structure 1 further includes a minority carrier protection element at the top end of the nanowires 2 for minimizing recombination of minority carriers at the contact between the sun- facing end of the nanowire 2 and the second electrode layer 8.
• upper boundary of a hereby created traditional depleted region 6 substantially coincides with the lower limit of the high-doped second section 4 at the top of the nanowire 2 as visualized in Fig. 1A.
• the length requirement L2 for the second section 4 is that it is below 1 80 nm.
• the depletion region 6 and the structural length requirement to the contact is an example of a minority carrier protection element, aimed at minimizing losses in the emitter due to minority carrier recombination.
• the length is here to be interpreted as the axial dimension of the nanowire 2.
• an upper face of the first electrode layer 7 has a plurality of recesses 1 1 and the nanowires 2 are positioned in these recesses 1 1 .
• a lower face of the first electrode layer may also have a plurality of recesses 12, the recesses associated with the upper 1 1 and the lower 12 face of the first electrode layer 7 being uniformly and alternatingly distributed.
• Mechanical stability of the structure is hereby improved.
• the nanowires 2 are substantially vertically positioned and mutually parallel. The robustness of the structure is hereby improved as the probability of the good contact between the nanowires 2 and the first electrode layer is enhanced.
• each recess 1 1 should be 100 nm or more in order to provide sufficient stability to the nanowires 2 in a process of transferring the structure, as will be described below.
• length L2 of the second section 4 is below 180 nm and length L1 of the first section 3 exceeds length L2 of the second section 4.
• the length requirement for the wire section closest to the sun, i.e. second section 4 is to minimize losses in the emitter.
• the first section 3 one farthest away from the sun, relates to mechanical stability of the array. It also needs to be sufficiently long so as to form a back surface field layer shielding the minority carriers in the base region of the cell from the rear contacts. Moreover, the length and doping requirements of the first section 3 are such that an ohmic contact can be made without Schottky depletion layers to the entire contact surface between the wires and the conducting layer. Obviously, at least one of the first 3 and second 4 sections may comprise two different semiconductor materials creating a heterojunction. In addition to these opposite high doped sections and positioned between them, there is at least a lightly doped, third section 5. This section is optimized for carrier absorption/extraction.
• an alternative example of a minority carrier protection element is implemented.
• a heterojunction barrier is
• heterojunction barrier is configured to act as a minority carrier mirror.
• the heterojunction may comprise a semiconductor barrier, e.g. InGaP, AIGaAs, AIGaP, or it may comprise a dielectric barrier.
• a minority carrier protection element is implemented by means of a Schottky junction, preferably a p-Schottky junction, at the contact between the second section 4 of the nanowires 2 and the second electrode layer 8.
• a minority carrier protection element is implemented by means of a doping barrier of the second section 4 of the nanowires. More specifically, the second section 4 is configured with graded dopant profile, from a higher dopant level at the contact to the second electrode layer 8 to a lower dopant level downwards towards the first section 3. As visualized in Fig. 2, the nanowires 2 may be two-dimensional, i.e. extend substantially in the radial direction as well.
• nanowires 2 of the present invention are surrounded by radial passivation layers. On the general level, reduced surface
• the first electrode layer 7 is transparent such that the light may exit the solar cell structure. This renders possible the stacking of the nanowire 2 solar cell 1 on top of a further solar cell of different material, minimizing hereby thermalization losses.
• these further solar cells may be manufactured separately from the nanowire-based solar cells of the present invention.
• the first electrode layer 7 is reflective at the interface of the first section 3 and the first electrode layer 7. Said layer 7 than serves as a mirror for transmitted light, which results in a higher quantum efficiency, or alternatively gives the option to use a shorter length nanowire 2 for the same amount of absorbed light resulting in further materials savings.
• the insulating layer 13 at least radially surrounds the nanowires 2 and at least one of the nanowires 2 is recessed relative said insulating layer 13.
• the electrode 8 contact with the nanowires 2 is preferably made only to the top surface of each semiconductor nanowire 2, or with as little as possible contact to the side of the semiconductor nanowire 2, as described above.
• a benefit of allowing the insulating shell to extend above the top end of the semiconductor nanowire 2 in the final device structure reduces the influence of process variations either due to varying nanowire 2 length or to other process variations.
• the final device structure may be achieved by incorporating a metal catalyst particle, which is removed during processing.
• a passivating shell extending above the top end of the semiconductor nanowire 2 may also be used in core-shell nanowires 2.
• Figs. 3-15 show steps of a non-limiting method for manufacture of the solar cell structure 1 of the present invention.
• Figs. 3-5 have a
• FIGS. 6-1 5 are directed at the key steps of the method according to one embodiment of the present invention.
• exemplary GaAs nanowires 2 of 150-200 nm diameter grown by MOCVD on a semiconductor substrate 30, preferably a (1 1 1 )B GaAs substrate 30 are shown.
• the growth may be catalyzed by a metallic particle 31 , for instance Au.
• the nanowires 2 grow in the (1 1 1 )B orientation and thus, they are vertically aligned on the substrate 30.
• a p- type section is grown, followed by an n-type GaAs section such that the p-n junction (not shown) is located near the top of the nanowire, ideally within 180 nm from the top of the wire.
• the total length of the wire is typically 1 -3 ⁇ .
• the part of the nanowire 2 closest to the substrate 30 (the first grown layer) comprise a section of typically 500 nm worth of highly p-doped material, to later enable non-alloyed ohmic contact formation and back surface field.
• the p- doping could comprise Zn or C.
• the topmost part 31 of the wire is a sacrificial material (for instance a VLS-catalyst particle can be used here) of different material composition than the rest of the wire. Accordingly, it can be selectively removed from the nanowire 2 - a future recess is hereby created.
• the growth on the substrate 30 could be done with or without a substrate 30 masking layer.
• a polymer material 40 is deposited on the substrate 30.
• the deposition of the polymer is typically done by spray-coating. This leaves a polymer film 40 of much greater thickness (for instance > 25 ⁇ ) than the height of the nanowires 2 (1 -3 ⁇ ).
• a frame 41 may be added in order to facilitate subsequent handling. By spray-coating the film 40 over the edge of the frame 41 , the polymer film 40 may be handled more easily at later stages. After proper drying, the polymer material is removed by peeling the edges of the film 40 and gradually rolling/pulling the film 40 from the wafer. The frame 41 (or some other temporary handle) reduces the risk that the film 40 is curled up or damaged. After peeling the film 40, the intermediate structure of Fig. 5 is obtained - the nanowires 2 are embedded deep in the film 40 on the front side, while appearing at or close to the surface on the back side.
• Fig. 3-5 should not be interpreted as the only way to achieve essentially aligned nanowires 2 in a polymer film 4 or thereto similar material in such a way that the long axis of the wires 2 is perpendicular to two essentially parallel surfaces of the polymer film 40, and in such a way that the nanowires 2 are close to or at the surface of at least one of the surfaces of the polymer film 40.
• nanowires 2 could be grown by previously discussed AerotaxyTM and subsequently aligned using above-mentioned liquid based alignment techniques.
• the starting point for the method steps of the present invention is that approximately aligned nanowires 2 are available in a substrate-free polymer film 40 such as that illustrated in Fig. 5.
• An important step for the final structure, illustrated in Fig. 6, crucial for avoiding that the transferred wires fall as well as for enabling good electrical contact is a short etch step performed on the backside.
• An etch e.g. 02-ash, preferentially etches the polymer film 40 so that the nanowires 2 protrude from the film 40 by 100-500 nm once the etch is completed. It should be noted that the length of the protrusion should at most correspond to the length of the lower peripheral high doped region in the nanowire 2.
• the layer 7 may be a Ti/Au/Ti deposition, where the Ti layers may be thin adhesion layers (2-20 nm) and the Au carries most of the current (1 00-250 nm).
• the deposition is preferably not planarizing, such that coverage between the nanowires 2 is accomplished as well as partly on the side of the nanowire.
• each nanowire 2 is thereby disposed in a recess 1 1 in the first electrode layer 7, which provides excellent support and alignment to the nanowires of the solar cell structure 1 , especially these steps of production.
• the current spreading layer 7 may also be a mirror to light not absorbed in the nanowires 2.
• Other metals may also be used, or transparent conducting oxides if no mirror action is required, for instance if the cell is to be used as a top or intermediate layer in a stacked solar cell.
• the film is bonded to a supporting substrate 9 with a pre-deposited adhesive layer 10, as shown in Fig. 8.
• a pre-deposited adhesive layer 10 A range of materials could be considered for this purpose and might be appropriately selected based on other materials present in the structure. PDMS or other silicone materials could be considered.
• the adhesive layer 10 is dried or cured.
• An important step of the method according to the invention, shown in Fig. 9, is that the entire first polymer layer is subsequently dissolved, for instance in a wet solvent. As previously discussed, this solves the issue of tolerance in a thinning step and is also more cost-efficient than a vacuum etch process. This is necessitated since the polymer layer may be of much greater thickness than the nanowires 2, and not necessarily of even thickness.
• an atomic layer deposition (ALD) of silicon dioxide (S1O2) takes place (Fig. 1 0).
• This film 13 is deposited at 250C or lower, and is specifically deposited at a temperature compatible with other existing layers in the stack.
• Alternative dielectrics, or combinations of dielectrics such as AI2O3, S1O2, etc could also be deposited with ALD or other deposition methods.
• the thickness of this deposition 13 is typically around 50 nm, though other thicknesses should not be ruled out. For instance, if the dielectric is thick enough that the spacing is completely filled by dielectric 13, the structure is equivalent to the previously outlined planar option as shown in Figs 1 A, 1 B and 2.
• Various spin-on dielectrics such as spin-on glasses or BCB or even photoresist may be used in alternative embodiments.
• a photo-resist 1 00 is spin-coated on the structure to approximately the right thickness.
• An exposure (for instance by laser) may be performed for purposes of series connecting open circuit voltage of multiple cells, especially in cases where the back substrate 9 and bonding matrix 10 are insulating. This will be discussed later.
• the photo-resist thickness 100 is adjusted so that it partially covers the sacrificial top portion 31 of the nanowire 2.
• the ALD dielectric 13 is etched, ideally with a dry etch which may contain a fluorinated etchant (Fig. 12), after which the photoresist 100 is stripped (Fig. 13). If alternative dielectrics, such as spun-on dielectrics, have been used, other etch chemistries or processes could be performed, but the general concept of a short back-etch in wet or dry chemistry, with or without photoresist masking is performed.
• the sacrificial portion 31 of the nanowire 2 is thereafter removed (Fig. 14) by selective etching. If the sacrificial portion 31 of the wire is an Au particle, a potassium cyanide process could be used. Finally, in Fig. 15, a TCO (Transparent Conductive Oxide) 8 is deposited. Al- ZnO layer, for instance deposited by an ALD process can produce good conformal coverage as in Fig. 15, with complete filling of the spaces between the nanowires 2 as shown, which increases the mechanical stability of the layer and decreases the sheet resistance of the TCO 8. Alternatively, other (low- temperature) TCO films 8 may be considered, for instance sputtered ITO. To produce planar topography, this could be combined with conductive polymers.
• TCO Transparent Conductive Oxide
• the supporting substrate 9 is instead, or in addition, bonded to the upper face of the structure 1 .
• the substrate 9 must be transparent to at least the light intended to be collected by the solar cell structure 1 .
• Fig. 1 B shows an example of what such a solar cell structure 1 could look like.
• the solar cell bonding matrix 10 and substrates 9 could be conductive, which enables simple top and bottom contact formation, with the addition of top metallization grid by for instance screen printing.
• the large area cell is converted to a number of series connected cells.
• the three steps required to carry out one such series connection are shown in Figs.16-20.
• the back conductor separation A can be done by laser cut.
• the front to back conductor connection B can be accomplished by dry etching the ALD dielectric in an area cleared of photo-resist by means of a laser exposure.
• the front conductor separation C can be accomplished by a laser of which wavelength and power is tuned to burn the strongly absorbing nanowires 2 and surrounding TCO film, but leaving the metal layer intact.
• separation C can be done by applying a photoresist and etching the TCO 8. Removal of the wires is not necessary.
• FIG. 21 multiple ABC series connections are shown on a large module.
• the separation between the ABC connections is determined by the limiting sheet conductivity of either the front or back conductor.
• the sequence is finished by the edge isolation D which separates both top and bottom conductors around the edge from the active areas, i.e. it is the equivalent of an AC scribe around the edge.
• Connectors to the junction box of the module can be applied at either end of the module, for instance in the areas indicated. These areas may be screen-printed unless direct soldering can be applied to the TCO.

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• 2013
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