WO2014194719A1 - 一种sdh中支路信号的时钟数据恢复方法及装置 - Google Patents

一种sdh中支路信号的时钟数据恢复方法及装置 Download PDF

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Publication number
WO2014194719A1
WO2014194719A1 PCT/CN2014/075586 CN2014075586W WO2014194719A1 WO 2014194719 A1 WO2014194719 A1 WO 2014194719A1 CN 2014075586 W CN2014075586 W CN 2014075586W WO 2014194719 A1 WO2014194719 A1 WO 2014194719A1
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Prior art keywords
time slot
signal
time
leakage
slot
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PCT/CN2014/075586
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English (en)
French (fr)
Inventor
刘峰
徐继超
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中兴通讯股份有限公司
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Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Priority to US14/895,212 priority Critical patent/US9680585B2/en
Priority to EP14807080.8A priority patent/EP2993817A4/en
Publication of WO2014194719A1 publication Critical patent/WO2014194719A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0623—Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/22—Arrangements affording multiple use of the transmission path using time-division multiplexing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/50—Network services
    • H04L67/56—Provisioning of proxy services
    • H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors

Definitions

  • the present invention relates to the field of communications, and in particular, to a clock data recovery method and apparatus for a branch signal in an SDH (Synchronous Digital Hierarchy, Synchronous Digital Hierarchy).
  • SDH Synchronous Digital Hierarchy, Synchronous Digital Hierarchy
  • Fiber optic communications provides a low-cost, high-speed information service that quickly replaces traditional copper communications.
  • ITU has established the communication standard of SDH.
  • the frame information structure of the SDH system has a rich overhead byte, which facilitates the transmission of information and network management.
  • the unified interface parameters enable the devices of different vendors to jointly network and realize the communication network communication between regions and even the whole world.
  • SDH The basic transmission network has become the dominant direction of optical communication network construction.
  • the new network is built on the original network.
  • the new SDH network needs to be compatible with the previous PDH structure network to meet the transmission of information from the SDH architecture to the PDH architecture, so that communication information can traverse different communications.
  • Network structure When the SDH network and the original PDH network exist at the same time, when the low-speed signal needs to be transmitted through the SDH system, the simple multiplexing method of the low-speed signal to the high-speed signal in the PDH system is no longer applicable.
  • the recovery circuit is a key circuit for realizing the transmission of signals from the SDH frame structure to the PDH structure, and relates to the synchronization information and jitter indicators of the clock when the signals pass through different systems.
  • the STM-1 frame structure there are 84 T1 or 63 E1 tributary signals.
  • Embodiments of the present invention provide a clock data recovery method and apparatus for a tributary signal in an SDH, which can simultaneously recover a recovered clock and data of a multi-way tributary signal, thereby greatly saving circuit resources.
  • An embodiment of the present invention provides a clock data recovery method for a tributary signal in an SDH, including: extracting valid data of a signal from each time slot of a synchronous digital system SDH frame structure, and storing the corresponding time slot in the buffer In the space; time-multiplexing recovers the clock signal and the readout signal of each time slot; and when the readout signal of the arbitrary time slot is valid, reads from the storage space corresponding to the way slot in the buffer The data content is output and latched into the latch of the corresponding time slot.
  • the buffer includes an upstream cache and a downstream cache.
  • the valid data of the signal extracted from each time slot of the SDH frame structure is stored in a storage space corresponding to each time slot in the cache, and includes: The valid data of the extracted signal in each time slot of the SDH frame structure is first stored in the storage space corresponding to each time slot in the upstream buffer; and the read indication signal of each time slot is generated by time division multiplexing, according to the The read instruction signal uniformly reads out the data content of each time slot from the upstream buffer, and writes it into the storage space corresponding to each time slot in the downstream buffer.
  • the read indication signal of each time slot is generated by time division multiplexing, and the data content of each time slot is uniformly read out from the upstream buffer according to the read indication signal, including: including an SDH frame
  • the clock period is divided into M time segments, M is a positive integer, and the number of bits in each time slot is M-1, M or M+1, and each time segment is time-multiplexed to generate each time.
  • the read instruction signal of the slot reads out one bit of data of the corresponding time slot every time the read indication signal is generated: for each time slot with the number of bits M, a read indication of normal leakage is generated for each time segment of the M time segments a signal, reading out one bit of data; for each time slot of the number of bits M-1, generating a normal leakage read indication signal for each time segment of the M-1 time segments, and reading one bit of data; And for each time slot with the number of bits M+1, a normal leaked read indication signal is generated for each time segment of the M time segments, and a read indication signal for increasing leakage is generated in one of the time segments, and the Dividing each time slot in the SDH frame may generate a time segment of the read indication signal that increases leakage, ensuring that the number of clock cycles included in each time segment is always not less than the maximum number of read indication signals that may be generated.
  • the time-division multiplexing recovers the clock signal of each time slot, including: cyclically calculating a buffer depth deviation value of each time slot in time division multiplexing, accumulating the buffer depth deviation value, and obtaining each time interval The overflow flag of the slot; and each time slot separately recovers the clock signal of the path slot according to the overflow flag of each time slot.
  • the time-division multiplexing calculates a buffer depth deviation value of each time slot, and accumulating the buffer depth deviation value to obtain an overflow flag of each time slot, including: generating a time slot according to a frame header signal and a clock signal.
  • n is a positive integer, determined by the number of slots of the SDH frame structure; and is calculated according to the current slot number signal slot_num
  • the buffer depth deviation value of the current time slot is accumulated, and the buffer depth deviation value is accumulated. If the overflow occurs, the overflow flag of the current one time slot is generated.
  • each time slot separately recovers a clock signal of the path slot according to an overflow flag of each time slot, including: setting a counter for each time slot, when the counter is cleared, generating a clock pulse; when the overflow flag of the counter is valid, the counter is cleared to the standard value, when When the overflow flag of the counter is invalid, the counter is cleared when the standard value is +1, and then the counter restarts counting from zero.
  • the standard value is determined by the clock signal frequency of the SDH frame structure and the standard of each signal. The frequency is determined.
  • the time-division multiplexing recovers the readout signal of each time slot, including: generating a readout signal for each time slot while generating one of the time slot number signals slot_num;
  • the readout signal of the arbitrary path slot effectively includes: if the current slot number signal slot_num is generated by a counter of the current one slot in a future cycle period, the read signal is valid.
  • the embodiment of the invention further provides a clock data recovery device for the tributary signal in the SDH, comprising: a data extraction module, configured to extract valid data of the signal from each time slot of the synchronous digital system SDH frame structure, and store the data in the cache. a memory recovery space corresponding to each time slot; a clock recovery circuit configured to recover the clock signal and the read signal of each time slot in time division multiplex, and send the clock signal and the read signal to the data recovery And a data recovery module configured to receive the clock signal and the read signal, and read out from a storage space corresponding to the way slot in the buffer when a read signal of an arbitrary time slot is valid The data content is latched into the latch of the corresponding time slot.
  • the buffer includes an upstream cache and a downstream cache.
  • the data extraction module includes: an upstream data extraction circuit configured to extract valid data of a signal from each time slot of the SDH frame structure, and first deposit the data into the buffer a storage space corresponding to each time slot in the upstream buffer; and a bit leakage circuit configured to generate a read indication signal for each time slot in a time division multiplexed manner, and hooking from the upstream buffer according to the read indication signal The data content of each time slot is read and written into the storage space corresponding to each time slot in the downstream buffer.
  • the bit leak circuit generates a read indication signal for each time slot by time division multiplexing, and reads data content of each time slot from the upstream buffer according to the read indication signal:
  • the clock period included in one SDH frame is divided into M time segments, M is a positive integer, and the number of bits in each time slot is M-1, M or M+1, and each time segment is generated separately in time division multiplexing.
  • the read indication signal of the time slot reads out one bit of data of the corresponding time slot every time the read indication signal is generated; for each time slot of the number of bits M, a normal leakage reading is generated for each time segment of the M time segments.
  • the indication signal reads out one bit of data; for each time slot of the number of bits M-1, a normal leakage read indication signal is generated for each time segment of the M-1 time segments, and one bit of data is read out.
  • a normal leakage read indication signal is generated for each time segment of the M time segments, and a read indication signal for increasing leakage is generated in one of the time segments, and Pre-dividing each time slot in the SDH frame may generate a time segment of the read instruction signal for increasing leakage, ensuring that the number of clock cycles included in each time segment is always not less than the maximum number of read indication signals that may be generated.
  • the bit leak circuit further includes: one or more clock counters, the clock counter is configured to count the clock based on the frame header signal; and the time slot allocator is set according to the clock counter Outputting results, determining the normal leak in each time segment, increasing the leakage or reducing the leakage location of the leak, and the current leaked slot number; and reading and writing controllers, which are set to normal leakage, increase leakage or decrease according to each time segment The leakage location of the leak and the currently leaked slot number. In each time segment, the data is leaked from the storage space corresponding to the corresponding slot number in the upstream cache according to the currently leaked slot number, or a leaked data is added or a leak is reduced.
  • the data is sent to the storage space corresponding to the slot number in the downstream buffer, wherein a read indication signal is generated during normal leakage; a read indication signal for deducting a normal leakage is reduced when the leakage is reduced; and a read indication signal is added at the leakage position where the leakage is increased when the leakage is increased.
  • the bit leakage circuit further includes: a leakage controller configured to generate an increase leakage signal and a leakage reduction signal according to a buffer depth of a storage space corresponding to the upstream buffer corresponding time slot number, wherein the increase leakage signal indicates an increase One leakage; the leakage reduction signal indicates a decrease in one leakage; and a read/write controller configured to increase the leakage signal according to the normal leakage in each time segment, the leakage leakage or the leak reduction position, and the currently leaked time slot number.
  • a leakage controller configured to generate an increase leakage signal and a leakage reduction signal according to a buffer depth of a storage space corresponding to the upstream buffer corresponding time slot number, wherein the increase leakage signal indicates an increase One leakage; the leakage reduction signal indicates a decrease in one leakage; and a read/write controller configured to increase the leakage signal according to the normal leakage in each time segment, the leakage leakage or the leak reduction position, and the currently leaked time slot number.
  • the clock recovery circuit includes: a deviation value calculation unit and a counter set for each time slot, the counter includes an overflow flag; and the deviation value calculation unit is configured to cyclically calculate each path in time division multiplexing. a buffer depth deviation value of the time slot, accumulating the buffer depth deviation value to obtain an overflow flag of each time slot; and a counter of each time slot is set to recover a clock signal of the path time slot according to the overflow flag.
  • the clock recovery circuit further includes: an accumulated value storage unit configured to save the last accumulated value output by the offset value calculation unit of each time slot to a storage space corresponding to each of the time slots; a time slot generator configured to generate a slot number signal slot num according to a frame header signal and a clock signal, wherein the slot number signal slot_num is continuously looped from 1 to n, n being a positive integer, by the SDH frame The number of time slots of the structure is determined; the deviation value calculation unit cyclically calculates the buffer depth deviation value of each time slot by time division multiplexing, accumulating the buffer depth deviation value, and obtaining an overflow flag of each time slot: The deviation value calculation unit obtains the data buffer depth of the storage space corresponding to the current slot number and the current slot number corresponding counter from the downstream buffer according to the current slot number signal slot_num Counting the result, obtaining a buffer depth deviation value of the path slot; obtaining the last accumulated value from the storage space corresponding to the current slot number of the accumulated value
  • the counter of each time slot recovers the clock signal of the path slot according to the overflow flag by: the counter of each time slot is respectively based on the frame header signal, and is based on the clock signal from zero. Start to perform the force port 1 count; when the overflow flag of the counter is valid, the counter is cleared when the standard value is counted, and when the overflow flag of the counter is invalid, the counter is cleared to the standard value +1. And then the counter restarts counting from zero, clearing the overflow flag while clearing; the standard value is determined by the clock signal frequency of the SDH frame structure and the nominal frequency of each signal; and when the counter is clear At zero hour, a clock pulse is generated.
  • the clock recovery circuit further includes: a readout signal generator configured to generate a readout signal for each time slot while generating one of the time slot number signals slot_num;
  • the data recovery The module further includes: a latch set for each time slot, configured to store data content in a storage space corresponding to the corresponding slot number read from the downstream buffer; the latch is numbered according to the slot number And the data recovery module reads out the data content from the storage space corresponding to the path slot in the buffer when the read signal of the arbitrary path slot is valid, and latches to the corresponding time slot.
  • the latch when the readout signal of the arbitrary channel slot is valid, according to the current slot number signal slot_num and read The out signal reads out the data content in the storage space corresponding to the slot number from the downstream buffer, and latches it into the latch corresponding to the slot number; wherein, the read signal of the arbitrary path slot is valid: The current slot number signal slot_num will generate a clock pulse in the current one cycle period, and the read signal is valid.
  • FIG. 1 is a schematic diagram showing the structure of an STM-1 frame corresponding to an E1 signal
  • FIG. 2 is an STM-1 frame serial signal receiving signal diagram of an E1 signal
  • FIG. 3 is an STM-1 frame. Schematic diagram of the VC12 multiframe structure
  • FIG. 4 is a structural diagram of a clock data recovery device of a branch signal in SDH in the embodiment
  • FIG. 5 is a structural diagram of a bit leakage circuit of a clock data recovery device in an embodiment
  • FIG. 6 is a structural diagram of a clock recovery circuit and a data recovery module of the clock data recovery device in the embodiment
  • FIG. 7 is a flow chart of a method for recovering clock data of a branch signal in SDH in the embodiment
  • FIG. 8 is a structural diagram of a clock data recovery device for a branch signal in SDH in an application example
  • FIG. 9 is a clock data recovery in an application example. a bit leak circuit structure diagram of the device
  • FIG. 10 is a structural diagram of a clock recovery circuit and a data recovery module of the clock data recovery device in an application example
  • FIG. 11 is a schematic diagram of a manner in which a frame STM-1 divides a time segment in an application example
  • FIG. 12 is a schematic diagram of each E1 signal leakage position in each time segment in an application example
  • FIG. 13 is an SDH branch in an application example. Flow chart of method for clock data recovery of road signals. Preferred embodiment of the invention
  • the corresponding frame structure of the STM-1 level of the SDH synchronous digital transmission system uses a 9-line * 270-column byte frame structure, and the time slot uses a byte interleaving method to form a frame structure.
  • the E1 signal is given in FIG. Schematic diagram of the SDH frame structure of the example.
  • the first nine columns of the frame structure are the segment overhead bytes POH and the pointer bytes, where 1-3 rows are the regenerator segment overhead RSOH, 5-9 rows are the multiplex segment overhead MSOH, and the 4th row is the pointer.
  • the remaining information byte is the information payload area.
  • the STM-1 frame signal is transmitted as a serial stream in the fiber, and the clock frequency of the STM-1 frame serial signal is 155.52M.
  • receiving according to the serial code stream finding the frame header signal of the STM-1 in the received code stream, and locating all the E1 signals in the STM-1 frame according to the AU pointer and the TU pointer in the processing frame. Or the location of the T1 signal.
  • the E1 signal a signal diagram for receiving the E1 signal is given in Fig. 2
  • the ⁇ signal gives the position of the frame header of STM-1
  • PL indicates the position of all E1 signals in the frame
  • data gives the contents of all E1 signals.
  • All E1 signals are received and processed in the order of 1-63. For each E1 signal, 8 bits (1 byte) are continuously received before receiving the next E1 signal.
  • each TU12 occupies 4 columns, and each TU12 signal in an STM-1 frame has 36 bytes, one of which is the pointer byte of TU12 (VI or V2, V3, V4), and the remaining 35 words.
  • the section is the content of VC12, as shown in Figure 3.
  • each VC12 has 35 bytes, and these 35 bytes constitute one subframe, and each 4 subframes constitute a multiframe.
  • the contents of the three C1s determine whether the S1 bit carries useful data or useless data. When C1 is 0, it means that S1 carries useful data; when C1 is 1, it means that S1 carries useless data.
  • the three C1s use the majority judgment principle, that is, when at least two C1s are 0, three C1s are considered to be 0; when at least two C1s are 1, C1 is considered to be 1.
  • C2 uses a similar approach.
  • the structure of the VC12 of each channel is exactly the same.
  • the data bits of all the E1 signals or the T1 signals in the SDH frame are extracted, and the clock signals of the E1 signals or the T1 signals are restored, and the jitter of the clock signals is reduced to meet the requirements. standard requirement.
  • the T1 signal processing process is similar to the E1 signal in the SDH frame structure. Therefore, in the present embodiment, the E1 signal is taken as an example for description. The apparatus and method in this embodiment are also applicable to the T1 signal.
  • this embodiment provides a clock data recovery apparatus for a tributary signal in an SDH, including: a data extraction module configured to extract valid data of a signal from each time slot of a synchronous digital system SDH frame structure. , stored in the storage space corresponding to each time slot in the cache; taking the E1 signal as an example, the buffer can be divided according to the number of E1 slots in the SDH frame structure, and there are 63 E1s in the STM-1, then the RAM Divided into 63 independent parts, the data of each E1 time slot is stored in the corresponding storage space of the RAM.
  • the cache includes an upstream cache RAM_A and a downstream cache RAM-B, an upstream cache RAM-A is located in the data extraction module, and a downstream cache RAM-B is located in the data recovery module.
  • the data extraction module includes: an upstream data extraction circuit, The method is configured to extract valid data of the signal from each time slot of the SDH frame structure, and first store the data into a storage space corresponding to each time slot in the upstream cache; a bit leakage circuit configured to generate a read indication signal for each time slot in time division multiplexing, and read data content of each time slot from the upstream buffer according to the read indication signal, and write to the downstream buffer In the storage space corresponding to each time slot.
  • the bit leak circuit generates a read indication signal for each time slot by time division multiplexing, and uniformly reads out the data content of each time slot from the upstream buffer according to the read indication signal:
  • the included clock period is divided into M time segments, M is a positive integer, and the number of bits in each time slot is M-1, M or M+1, and each time segment is time-multiplexed to generate a read of each time slot.
  • the indication signal reads out one bit of data of the corresponding time slot every time the read indication signal is generated: for each time slot with the number of bits M, a normal leaked read indication signal is generated for each time segment of the M time segments, and the reading is performed.
  • One bit of data is generated; for each time slot of the number of bits M-1, a normal leaked read indication signal is generated for each time segment of the M-1 time segments, and one bit of data is read; For each time slot of M+1, a normal leaked read indication signal is generated for each time segment of the M time segments, and a read trigger signal for increasing leakage is generated in one of the time segments, and First dividing each time slot in the SDH frame can generate a time segment of the read indication signal for increasing leakage, ensuring that the number of clock cycles included in each time segment is always not less than the maximum number of read indication signals that may be generated.
  • the clock signal frequency is 155.52M
  • one frame time is 125us
  • the clock has 19440 clock cycles in one frame time.
  • there are 256 bits in one STM-1 period (only 256 bits when 1 S1 carries data; 257 bits when 2 S1 are carried; 255 bits when 2 S1 are not carried) .
  • the 19440 clock cycle is divided into a plurality of time segments in the manner of FIG. 4: wherein the first time segment is 75 clock cycles, and the other 15 segments (2-15 time segments) are 76 clock cycles, which are sequentially cycled.
  • the data bits are not completely equally spaced in the readout time.
  • the E1 signal has only 255 bits in an STM-1 period (Sl and S2 do not carry data)
  • there is a time segment that does not leak data in 256 time segments (the activity of not leaking data is called reducing leakage)
  • the number of bits leaking to the downstream is one less, that is, 255 bits.
  • the E1 signal has 257 bits in an STM-1 period (S1S2 carries valid data)
  • S1S2 carries valid data
  • the 256-time segment there is a time slot that leaks 2 bits (the activity name of the multi-leakage data increases the leakage).
  • the number of bits leaking downstream is one more, that is, 257 bits.
  • the bit leak circuit includes: one or more clock counters, the counter is set to count a clock based on a frame header signal; and a time slot distributor is configured to Determining, according to the output result of the counter, a normal leak in each time segment, increasing a leak or reducing a leaked leak position, and a currently leaked time slot number; a read/write controller configured to be based on a normal leak in each time segment, Increase the leak or reduce the leakage position (norm_pos, add_pos, dec_pos) and the currently leaked slot number ( leak_slot-num).
  • the corresponding time slot is buffered from the upstream according to the currently leaked slot number. Normally leaking once in the numbered storage space or adding a leak or reducing a leaked data to the storage space of the corresponding slot number in the downstream buffer, where a read indication signal is generated during normal leakage; a read indication deducting a normal leak when reducing leakage Signal; increase leakage when increasing leakage Add a read indication signal.
  • the bit leakage circuit further includes: a leakage controller configured to generate an increase leakage signal add and a decrease leakage signal dec according to a buffer depth of a storage space corresponding to the upstream buffer corresponding time slot number, wherein the increase leakage signal add indicates an increase once Leakage; the reduced leakage signal dec represents a decrease in one leak;
  • the depth of the RAM buffer indicates the amount of data.
  • a read/write controller that is set to be based on a normal leak in each time segment, increase a leak or reduce a leaked leak position, and a currently leaked time slot number, increase a leak signal add, and reduce a leak signal dec, within each time segment, Adding a leak according to the increased leak signal from the storage space of the upstream buffer RAM_A corresponding slot number according to the currently leaked slot number or reducing a leaked data to the downstream buffer RAM according to the reduced leak signal-B corresponding slot In the numbered storage space, where the leakage signal is subtracted from a normal leak when reading the leak; when the leak is increased, a read indication signal is added at the increased leak position.
  • the bit leakage circuit leaks the data of each time slot signal from the upstream buffer to the downstream buffer, and recovers the data and clock information of each time slot signal downstream.
  • the clock recovery circuit includes: a deviation value calculation unit configured to cyclically calculate a buffer depth deviation value of each time slot in time division multiplexing, and accumulate the buffer depth deviation value.
  • an overflow flag for each time slot setting a counter for each time slot, the counter is set to recover the clock signal of the time slot according to the overflow flag;
  • the counter is numbered according to the time slot number, each counter It consists of two parts: an overflow flag and a counter n (n indicates a time slot number), and for the E1 signal, there are 63 counters; an accumulated value storage unit which is set to output the deviation value calculation unit of each time slot The secondary cumulative value accumulation is saved in the storage space corresponding to each of the time slots;
  • the time slot generator is configured to generate a time slot number signal slot_num according to the frame header signal ⁇ and the clock signal clock, the time slot number signal Slot_num is continuously looped from 1 to n, and ⁇ is a positive integer, which is determined by the number of slots of the SDH frame structure (that is, the number of signal paths carried by the SDH frame structure) ;
  • the deviation value calculation unit cyclically calculates the buffer depth deviation value of each time slot by time division multiplexing
  • the value of the deviation is obtained according to the current slot number signal slot_num, and the last accumulated value accumulation is obtained from the storage space corresponding to the current slot number of the accumulated value storage unit, and the buffer depth deviation value deriviation and the last accumulated value of the path slot are used.
  • the accumulation is accumulated to obtain the accumulated result total of the time slot; according to the accumulated result total, it is determined whether the current accumulation has overflowed, and if there is an overflow, the overflow flag is marked on the counter corresponding to the current time slot number, and this time The remainder of the accumulated result is saved to the storage space corresponding to the current slot number of the accumulated value storage unit In the calculation of the cumulative value of the next operation, accumulation vide
  • slot_num continuously circulates from 1 to 63, indicating the slot number of the 63 E1 signals that need to be recovered.
  • the slot number signal slot_num indicates that the current recovery is arbitrary.
  • the clock signal of one time slot, the operation process of the overflow flag of the time slot is completed in one clock cycle.
  • the operation process of the first time slot is completed when slot_num is 1.
  • the slot_num is 2
  • the operation process of the second time slot is completed
  • the accumulation process of all time slots is continuously and cyclically completed.
  • the calculation process of the buffer depth deviation value deviation is:
  • the deviation value calculation unit subtracts the value of the data buffer depth_b from the depth reference value, and obtains the depth of the data cache deviation from the integer part of the calculated value depth_dev.
  • the count result counter is the depth deviation calculation value depth_dev a fractional part; wherein, the counter calculation result counter is a counter result of the counter after the last counter is cleared to the current reading.
  • the depth of the data buffer is deviated from the calculated value depth_dev and the fractional part and the fractional part are concatenated (the integer part is in front and the fractional part is in the back) and the reference clock standard value is added to obtain the buffer depth deviation value deviation.
  • Depth deviation calculation value depth_ dev indicates the deviation direction and size of the current cache depth: if the deviation value is positive, indicating that the amount of cache data is too large, the amount of data stored in the upstream is increasing, and the clock frequency to be recovered is faster, so as to speed up the Read data in the cache.
  • the magnitude of the offset value reflects the magnitude of the recovered clock change.
  • the deviation value is negative, it reflects that the amount of data stored in the upstream is decreasing, and the clock frequency that needs to be recovered is slowed down to slow down the speed of reading data from the cache.
  • the target reference standard value is related to the current clock and offset value bits.
  • the cache depth deviation value deriviation reflects the recovery speed at the next round of clock recovery.
  • the deviation value deviation is continuously accumulated, and if an overflow occurs during the accumulation, the margin after the overflow and the deviation value devariation are continuously accumulated. The larger the cache depth deviation value deviation, the more the number of overflows; the smaller the number of overflows, the smaller the number of overflows, so the cumulative number of overflows reflects the frequency of the recovered clock.
  • the frequency of the recovered clock can be adjusted by the number of overflows.
  • Set the overflow threshold value and judge whether the current accumulation overflows by accumulating whether the result total reaches the threshold value.
  • the overflow threshold value is related to the clock frequency and the data buffer depth depth-b.
  • the counter of each time slot recovers the recovered clock signal of the time slot according to the overflow flag by: the counter of each time slot is respectively based on the frame header signal, and is added from zero according to the clock signal.
  • the counter restarts counting from zero, and clears the overflow flag p while clearing;
  • the standard value is determined by the clock signal frequency of the SDH frame structure and the nominal frequency of each signal; when the counter is cleared, One clock pulse.
  • the clock signal frequency of one frame STM-1 is 155.52M
  • the nominal clock frequency of each E1 signal is 2.048M.
  • the frequency of the clock signal of one frame STM-1 is divided by the standard of each E1 signal.
  • the target frequency of the clock frequency to get the counter count clear is 74 (counting from 0, counting 75 times when counting to 74, that is, dividing by 75). If the counter overflow flag is invalid, the counter counts to the target value of 74+1. Cleared, that is, it is cleared when it is added to 75, and then restarts counting from zero. If this counter overflow flag is valid, it will be cleared when it counts to the target value, and then start from zero. Recount, when the counter is cleared every time, it means that the counter completes a counting period, and the counter outputs a clock pulse, which is the recovery clock pulse of this time slot.
  • the counter When there is an overflow flag, the counter will only be cleared to the target value, the counting time is short, and the generated pulse time is fast; when there is no overflow flag, the counter only counts to the target value +1 to be cleared, and the counting time is long, resulting in The pulse time is slow. Therefore, the more overflow flags, the shorter the counter counting time, the faster the pulse is generated, the more pulses are generated in a fixed time, and the recovered clock frequency is higher; conversely, the less the overflow flag, the more the counter counts. Long, the slower the pulse is generated, the less the number of pulses generated in a fixed time, and the recovered clock frequency is lower. The frequency of the recovered clock can be adjusted by the number of overflows.
  • the clock recovery circuit further includes: a readout signal generator configured to generate a readout signal for each of the time slots while generating one of the time slot number signals slot_num, and determine the readout signal Whether it is valid; the readout signal of any channel time slot is valid: if the current slot number signal slot_num is in a future cycle, the counter corresponding to the slot number will generate a recovery clock pulse, then the read signal is valid; For example, the E1 signal is cyclic.
  • the slot_num is continuously cycled from 1 to 63.
  • the counter counts one cycle and clears to generate a recovery clock pulse.
  • One count cycle is 75 or 74.
  • num_num requires 63 clock cycles per cycle. For slot 1 of the first channel, 63 clock cycles are required when slot_num is 1 to the next time again.
  • the difference between the current value of the counter and the target value of the counter is greater than 63, it means that the counter does not count to the target value during the period of one week after the slot_num cycle is equal to 1, that is, the time slot is not generated.
  • the recovery clock pulse in this case, there is no need to prepare to recover the data, so the read signal is invalid in this case; if the difference between the current value of the counter and the target value of the counter is less than 63, the meaning slot_num is cycled from 1 During the period of one week to 1 again, the counter counts to the target value, thereby generating a recovery clock of this time slot, so the read signal is effective in this case.
  • the data recovery module includes, in addition to the downstream buffer RAM-B, a latch for each time slot, and the latch is used to store the corresponding time read from the downstream buffer.
  • the data content in the slot numbered storage space; the latches are numbered according to the slot number;
  • the data recovery module reads out the data content from the storage space corresponding to the time slot in the buffer when the read signal of the arbitrary time slot is valid, and latches into the latch of the corresponding time slot. And including: when the readout signal of the arbitrary channel time slot is valid, reading the data content in the storage space corresponding to the time slot number from the downstream buffer according to the current time slot number signal slot_num and the readout signal, and latching to Corresponding to the slot number of the slot.
  • the embodiment provides a method for recovering clock data of a tributary signal in an SDH, including the following steps: S101: Extracting valid data of a signal from each time slot of a synchronous digital system SDH frame structure, and storing Entering the storage space corresponding to each time slot in the cache;
  • the cache RAM includes an upstream cache RAM_A and a downstream cache RAM-B;
  • the method further includes the following steps: extracting valid data of a signal from each time slot of the SDH frame structure, and first storing the data into a storage space corresponding to each time slot in the upstream buffer; generating each time interval in time division multiplexing
  • the read instruction signal of the slot reads the data content of each time slot uniformly from the upstream buffer according to the read indication signal, and writes the data content of each time slot in the downstream buffer.
  • the read indication signal of each time slot is generated by time division multiplexing, and the data content of each time slot is uniformly read out from the upstream buffer according to the read indication signal, including: dividing a clock period included in one SDH frame into M time segments, M is a positive integer, the number of bits in each time slot is M-1, M or M+1, and each time segment is time-multiplexed to generate a read indication signal of each time slot, each time generating The read indication signal reads out one bit of data of the corresponding time slot: For each time slot with a bit number M, a normal leak read instruction signal is generated for each time segment of the M time segments, and one bit of data is read; for each time slot with a bit number of M-1, Producing a normal leaked read indication signal for each time segment of the M-1 time segments, reading one bit of data; for each time slot of the number of bits M+1, at each time of the M time segments The segment generates a normal leaked read indication signal, generates a read indication signal for increasing leakage in one
  • step S102 the clock signal of each time slot is recovered in time division multiplexing, and further includes: cyclically calculating a buffer depth deviation value of each time slot in time division multiplexing, and accumulating the buffer.
  • the depth deviation value obtains an overflow flag for each time slot; each time slot independently recovers the clock signal of the time slot according to its overflow flag.
  • the buffer depth deviation value of each time slot is cyclically calculated in time division multiplexing, and the buffer depth deviation value is accumulated, and the overflow flag of each time slot is obtained:
  • the slot number signal slot is generated according to the frame header signal and the clock signal— Num
  • the slot number signal slot_num is continuously looped from 1 to n
  • n is a positive integer, which is determined by the number of slots of the SDH frame structure (that is, the number of signal paths carried by the SDH frame structure);
  • the current slot number signal slot_num calculates the buffer depth deviation value of the current one slot, accumulates the buffer depth offset value, and generates an overflow flag of the current one slot if the overflow occurs.
  • the method further includes: setting an accumulated value storage unit, and setting a counter for each time slot, and the accumulated value storage unit may divide according to the number of E1 slots in the SDH frame structure, The counter is numbered according to a slot number, and the counter includes an overflow flag;
  • the buffer depth deviation value of each time slot is cyclically calculated in time division multiplexing, and the buffer depth deviation value is accumulated to obtain an overflow flag of each time slot.
  • the slot generator generates a slot number signal slot num according to the frame header signal ⁇ and the clock signal clock, and the slot number signal slot_num continuously circulates from 1 to n; taking the E1 signal as an example, slot_num is from 1 to 63 cycles.
  • the data buffer depth depth_b of the storage space corresponding to the current slot number is obtained from the downstream buffer RAM_B, and the counter result counter of the current slot number corresponding counter is obtained, and the time slot is obtained by the operation.
  • the buffer depth deviation value deviation is obtained according to the current slot number signal slot_num, and the last accumulated value accumulation is obtained from the storage space corresponding to the current slot number of the accumulated value storage unit, and the buffer depth deviation value devariation of the path slot is
  • the accumulated value accumulation is accumulated to obtain the accumulated result total of the time slot; according to the accumulated result total, it is determined whether there is an overflow in the current accumulation, and if there is an overflow, an overflow flag is marked on the counter corresponding to the current time slot number.
  • the remainder of the accumulated result is saved in the storage space corresponding to the current slot number of the cumulative value storage unit, as the cumulative value of the next operation accumulation, wherein the calculation process of the cache depth deviation value devian is:
  • the data buffer depth depth—the value of b and the depth reference standard value are subtracted.
  • the depth of the data buffer deviates from the integer part of the calculated value depth_dev;
  • the counter calculation result counter is the decimal part of the depth deviation from the calculated value depth_dev.
  • the counter is calculated as the counter is cleared from the previous counter to the current read. The result of counting the counter is taken.
  • the depth of the data buffer is deviated from the integer part and the fractional part of the calculated value depth_dev (the integer part is in front and the decimal part is in the back), and the depth deviates from the calculated value depth_dev and the reference clock.
  • the standard value is added to obtain a buffer depth deviation value deriviation.
  • Each time slot is independently recovered according to its overflow flag, and the clock signal of the time slot is independently: the counter of each time slot is respectively based on the frame header signal, according to The clock signal is incremented by one from zero; when the overflow flag of the counter is valid, the counter is cleared when it reaches the standard value, and when the counter overflow flag is invalid, the counter is counted to the standard value +1.
  • the meter restarts counting from zero, and clears the overflow flag while clearing; the standard value is determined by the clock signal frequency of the SDH frame structure and the nominal frequency of each signal; when the counter is cleared, A recovery clock pulse.
  • the readout signal of each time slot is recovered in time division multiplexing in step S102, including: generating one time slot number signal slot_num and generating each time slot.
  • step S103 further comprises: when the read signal of the arbitrary time slot is valid, reading the storage space corresponding to the time slot number from the downstream buffer according to the current time slot number signal slot_num and the read signal The data content in the latch is latched into the latch corresponding to the slot number; wherein, the readout signal of the arbitrary slot is valid: if the current slot number signal slot_num is in a future cycle, The counter corresponding to the slot number generates a clock pulse, and the read signal is valid.
  • the corresponding frame structure of the STM-1 level and the E1 signal are taken as an example.
  • the clock data recovery device of the tributary signal in the SDH includes: an upstream data extraction circuit, a bit leakage circuit, a clock recovery circuit, and a data recovery module, where: upstream data
  • the extraction circuit extracts the valid data of the signal from each time slot of the SDH frame structure according to the frame header signal ⁇ , the clock signal clock and the data signal data, and stores the data into the buffer of the corresponding buffer number in the upstream buffer RAM-A;
  • the circuit determines whether the S1 and S2 bits are valid data based on the contents of the C1 and C2 bits. If the position of the S1 and S2 bits is valid data, it needs to be extracted and stored in the buffer of the time slot.
  • Cache RAM—A is divided according to the number of E1 slots in SDH.
  • STM-1 there are 63 E1s, then RAM_A is divided into 63 independent parts, and the data of each E1 slot has its corresponding space.
  • a bit leak circuit configured to generate a read indication signal for each time slot in a time division multiplex, according to The read indication signal uniformly reads out the data content of each slot number buffer from the upstream buffer RAM A, and writes it into the storage space of the downstream buffer RAM-B corresponding slot number.
  • RAM-B is divided in the same way as RAM-A. As a preferred method, as shown in FIG.
  • the bit leak circuit includes: three clock counters, a time slot allocator, a leak controller, and a read/write controller, wherein: as a preferred method, but does not exclude other
  • Figure 11 shows a way to divide time segments.
  • the 19440 clock cycle in STM-1_frame time is divided into multiple time segments: the first time segment is 75 clock cycles, and the other 15 segments (2-15 time segments) are 76.
  • One clock cycle which is cycled in turn.
  • 16 time segments of 75 clock cycles, 16*15 76 clock cycle time segments, and 256 time segments can be divided.
  • each E1 signal has 256 bits (or 255, 257 bits), within each time segment, one bit is leaked from the upstream data extraction RAM A to the data recovery RAM—B In this case, data can be leaked from the upstream RAM-A to the downstream RAM-B.
  • S1S2 does not carry data
  • the E1 signal has only 255 bits in an STM-1 period (S1S2 does not carry data)
  • S1S2 does not carry data
  • the number of bits leaking downstream is one less, that is, 255 bits.
  • the E1 signal has 257 bits in an STM-1 period (S1S2 carries valid data)
  • S1S2 carries valid data
  • the 256-time segment there is a time slot that leaks 2 bits (the activity name of the multi-leakage data increases the leakage).
  • the number of bits leaking downstream is one more, that is, 257 bits. Since a time segment has at least 75 clock cycles and a maximum of 63 E1 signals in an STM-1 frame, a time segment can satisfy the normal leakage requirement of the 63 E1 signals. In extreme cases, in an STM-1 frame, 63 E1 signals have 257 bits at the same time.
  • each E1 only leaks at most 1 bit in the STM-1 period, the activity of the 63 E1 increased leakage is artificially broken up to 256 time segments.
  • each time segment only a small number of E1 signals need to be added to leak, as shown in FIG. 12, for example, each time segment is only responsible for the increased leakage of 4 E1s, so that all E1s can be satisfied in one time segment. Normal leakage of signal Claim.
  • each time segment is only responsible for the increased leakage of 4 E1, which are 1-4, 5-8, 9-12...57-60 E1, 16th time.
  • the clip is only responsible for the increased leakage of the 61-63 E1. In this way, the first 16 time segments can complete the increased leakage requirements of all 63 E1s. No additional leaks are scheduled in other time segments.
  • the manner in which the time segments are divided and the time slot in which the leakage is added are not limited to the manner given in this embodiment.
  • each time segment is only responsible for one channel.
  • the clock counter counts the clock signal clock according to the frame header signal ⁇ of the SDH.
  • the clock counters are all cleared, and the clock is re-counted.
  • the clock counter counts as described above.
  • three clock counters are set, including: clock counter 1 (counter_low), clock counter 2 (counter middle), and clock counter 3 (counter high), but it is not excluded to set multiple clock counters in implementation. .
  • the clock counter counter-low counts from 1 to 75/76; the counters counter- middle and counter-high are used to count time segments, all counting from 1 to 16, and the combination is from 1-256.
  • Counter- middle counts a cycle, counter-high counts once.
  • Counter_ middle determines whether the maximum value of the counter-low count is 75 or 76. In Figure 7 and Figure 8, when counter_ middle is 1, the maximum value of counter-low is 75, and in other cases, counter-low counts to 76.
  • Counter high Determines if there is an increase in leakage or a decrease in leakage. In the application example, when the counter high is 1, it is possible to increase the leakage or reduce the leakage within the time segment. When the counter-high is other values, only the normal leakage, no increase of leakage and reduction of leakage.
  • the time slot allocator in the bit leakage circuit determines the leakage location of each E1 signal.
  • the clock counter counter_low when the clock counter counter_low is in the range of 1-63, it indicates a normal leakage or a decrease in leakage of each signal. For example, when counter_low is 1, it indicates that the first E1 signal leaks normally or reduces the leak position, and each signal corresponds to each time slot; when counter-low is other content, it indicates an idle leak position. No leaks are made.
  • each E1 signal (or each time slot) reduces leakage at most once, so that the leakage reduction can be implemented in one time segment, in this application example, the leakage is reduced.
  • the 63 E1 increase leakage activity is artificially broken up into 256 time segments, and only a small amount of E1 signal needs to be added to leak in each time segment.
  • counter-low For 64, 65, 66, 67, the increased leakage position of the E1 signal is indicated. For example: In the first time segment, counter- low is 64.
  • 65, 66, 67 indicate the increased leakage position of the 1, 2, 3, and 4 E1 signals; in the second time segment, counter-low is 64, 65, 66, and 67 indicates the 5th, 6th, 7th, and 8th roads. The E1 signal increases the leakage position, and so on. In the 16th time segment, counter-low is 64, 65, and 66 indicates the increased leakage position of the 61st, 62nd, and 63th E1 signals. According to the output results of the above three clock counters, the time slot distributor generates a leak slot number signal leak_slot-num, a normal leak position signal norm_pos, and a boosting force according to a mechanism of normal leakage, increased leakage, and reduced leakage.
  • leak position signal add_pos and the leak position signal dec_pos are reduced. These leak location signals indicate the type of leak that can be made at that location.
  • Leak_slot — num indicates the slot number of the current leak.
  • the leak-slot-num effective range is from 1-63.
  • the leaked slot number is from 1 to 63; when counter_low is 64, 65,
  • the leakage controller gives a leakage operation signal: generating an increase leakage signal add and a decrease leakage signal dec according to a depth depth_a of the storage space corresponding to the slot number of the upstream cache RAM A, the increase leakage signal add indicating an increase in leakage;
  • the reduced leakage signal dec represents a decrease in leakage;
  • the read/write controller according to the current leaked slot number signal leak_slot-num, leakage operation signal (increased leakage add, reduced leakage dec), leakage position signal (normal leakage position signal norm_pos
  • the leakage position signal add_pos is increased, the leakage position signal dec_pos is decreased, the read instruction signal of the upstream RAM_A is generated, the data content of the corresponding time slot is read out from the buffer, and the read data is written to the downstream RAM—B corresponds to The slot number is in the storage space.
  • a normal leak produces a read indication signal; If there is a decrease in leakage, a read indication signal of a normal leak is deducted; if there is an increase in leakage, a read indication signal is added at the increased leak position.
  • the bit leak circuit generates a read indication signal for each signal (corresponding to each time slot), reads data from the upstream data buffer, and stores it in the downstream data recovery buffer RAM-B, and controls each signal by controlling the number of read operations. It leaks evenly into the downstream cache RAM-B, and recovers the data and clock information of each signal downstream.
  • the clock recovery circuit includes: a deviation value calculation unit, a time slot generator, a read signal generator, a counter for each time slot, and a cumulative value storage unit, wherein:
  • the time slot generator continuously generates the slot number signal slot_num according to the frame header signal ⁇ and the clock signal clock. For the El signal, slot_num continually loops from 1 to 63, indicating the 63 E1 signal slot number to be recovered.
  • the deviation value calculation unit obtains the buffered data buffer depth_b corresponding to the current slot number and the count result counter of the current slot number corresponding counter from the downstream buffer RAM_B according to the current slot number signal slot_num, and the operation result is obtained.
  • the buffer depth deviation value deviation of the road slot for example, the current slot number slot_num is 1, and the data buffer depth depth_b of the first time slot is obtained from the buffer RAM-B, and the first time slot is obtained at the same time.
  • the current counting result of the counter 1 counter, the deviation value calculating unit calculates the buffer deviation value deviation of the first time slot according to the buffer depth depth_b of the slot 1 and the counter calculation result counter, wherein the buffer depth deviation value derivation calculation process is The deviation value calculation unit subtracts the value of the data buffer depth_b from the depth reference value to obtain a deviation of the cache depth, where the difference is an integer part of the depth deviation calculation value depth_dev; The count result counter is used as the decimal part of the depth deviation calculation value depth_dev.
  • the counter of the counter is the count result of the counter after the last counter is cleared to the current read.
  • the depth of the data buffer is deviated from the integer part and the decimal part of the calculated value depth_dev (the integer part is in front and the decimal part is in the back), and the reference clock standard value is added to obtain a slow
  • the depth deviation value deviation mousse the deviation value calculation unit acquires the last accumulated value accumulation from the accumulated value storage unit corresponding to the current slot number according to the current slot number signal slot_num, and the buffer depth deviation value devariation of the path slot And accumulating the last accumulated value accumulation to obtain the cumulative result total of the time slot; according to the accumulated result total, determining whether the current accumulation overflow occurs, if the overflow occurs during the addition operation, the overflow flag is stored in the current time slot number.
  • the flag position of the corresponding counter is p, and the remainder of the accumulated result is saved to the accumulated value storage unit corresponding to the current slot number, and the calculation result of the next calculation is the cumulative value of the accumulating value calculation unit.
  • the overflow flag operation process of the first time slot is completed when slot_num is 1.
  • slot_num is 2, when the second path is completed.
  • the operation of the slot, and so on, does not cyclically complete the accumulation process of all time slots.
  • each counter consists of two parts: overflow flag p and counter n (n indicates the slot number), and 63 counters for the E1 signal.
  • the overflow flag indicates whether the adder appears during the last accumulation operation of the time slot.
  • Counter n continuously counts from zero. If this counter overflow flag p is invalid, that is, there is no overflow, the counter counts to the target value (the system clock is 155.52M, and for the E1 signal, the target value is 74) Cleared when +1, that is, it is cleared when it is added to 75, and then restarts counting from zero. If this counter overflow flag p is valid, it will be cleared when it counts to the target value, and then count again from zero. When clearing, it needs to clear the overflow flag p.
  • the counter of each time slot is counted independently. When the counter is cleared every time, it means that the counter completes a counting cycle, and the counter outputs a clock pulse. a recovery clock pulse of a time slot.
  • a readout signal generator for generating a slot number signal slot Num simultaneously generates a read signal read_b for each time slot; and determines whether the read signal read-b is valid, and the read signal of any time slot is valid: if the current time slot number signal slot_num In the next cycle, the counter corresponding to the slot number will generate a recovery clock pulse, and the read signal is valid; the clock recovery circuit simultaneously gives the readout of each slot data when restoring each E1 signal clock.
  • the signal read_b and the slot number slot_num are used to prepare the data for each time slot.
  • the counter does not count to the target value during the period of one week after the slot-num cycle is again equal to 1, that is, the time slot is not generated.
  • the recovery clock pulse in this case, does not need to be prepared to recover data, so in this case the read signal read-b is invalid. If the difference between the current value of the counter and the target value of the counter is less than 63, the counter will count to the target value during the period of one cycle from 1 to 1 again, thereby generating the recovery clock of this time slot.
  • the read signal read-b is valid
  • the data recovery module reads data from the downstream buffer RAM-B in advance, and latches it into the latch corresponding to the slot number for recovery.
  • the clock pulse is like this.
  • the data recovery module is valid according to the slot number slot_num and the read signal read-b, and reads the recovery data of the storage space corresponding to the slot number from the RAM-B, and latches it into the latch corresponding to the slot number. , for recovery clock pulses. In this way, the clock and data of the local E1 signal (the local time slot) are all recovered.
  • the recovery process for other time slots is also completely similar.
  • a clock data recovery method for a branch signal in SDH which includes the following steps:
  • the upstream data extraction module extracts valid data of each signal from each time slot of the SDH frame structure according to the frame header signal ⁇ , the clock signal clock, and the data signal data, and stores the valid data in the storage space corresponding to each time slot of the upstream cache RAM A. ;
  • the upstream data extracting circuit determines whether the S1 and S2 bits are valid data based on the contents of the C1 and C2 bits. If the position of the S1 and S2 bits is valid data, it needs to be extracted and stored in the buffer of the time slot.
  • Cache RAM—A is divided according to the number of E1 slots in SDH. In STM-1, there are 63 E1s, then RAM_A is divided into 63 independent parts, and the data of each E1 slot has its corresponding space.
  • S502 The bit leak circuit generates a read indication signal for each time slot in a time division multiplexing manner, and uniformly reads out the data content of each time slot from the upstream buffer RAM_A according to the read indication signal, and writes the data content to the downstream buffer.
  • the storage space corresponding to each time slot of the RAM-B includes the following steps: S5021: The clock counter counts the clock clock based on the frame header signal ⁇ , and generates various types of count values required by the time slot allocator; The clock counter counter-low counts from 1 to 75/76; the counters counter- middle and counter-high are used to count time segments, all counting from 1 to 16, and the counter-high counts once when the counter-middle counts a loop.
  • Counter_ middle determines whether the maximum value of the counter-low count is 75 or 76. In Figure 8 and Figure 9, when counter-middle is 1, the maximum value of counter-low is 75, and in other cases, counter-low counts to 76.
  • Counter—high determines if there is an increase in leakage or a decrease in leakage. In this application example, when counter-high is 1, it is possible to increase leakage or reduce leakage in the time segment. When counter-high is other values, only normal leakage, no boosting port leakage and leakage reduction.
  • the time slot distributor generates a bit leak circuit time-division leaking time slot number signal leak_slot_num, a normal leakage time position signal norm_pos, a leakage time position signal add_pos, and a leakage reduction according to the count value of the above clock counter.
  • S5023 The leakage controller according to the current leaked slot number signal leak_slot_num, the buffer depth depth_a of the storage space corresponding to the current slot number in the upstream buffer RAM A, and the current leak position signals norm_pos, add_pos, dec_pos, Generating a boosting read operation signal add or reducing a read operation signal dec;
  • the read/write controller signals the leak_slot_num according to the current leaked slot number, and the leak position
  • the signals norm_pos, add_pos, dec_pos, and the boosting port leak add signal reduce the leakage dec signal, generate the read buffer signal read_a of the upstream buffer RAM_A, and read out the data content corresponding to each time slot from the buffer, and at the same time
  • the read data is written to the downstream RAM-B in the storage space corresponding to the slot number.
  • the deviation value calculation unit cyclically calculates the buffer depth deviation value of each time slot in a time division multiplexing manner, and accumulates the buffer depth deviation value to obtain an overflow flag of each time slot; specifically, the following steps are included:
  • the time slot generator 4 continuously generates the time slot number signal slot num according to the frame header signal ⁇ and the clock signal clock; for the E1 signal, the slot_num continuously circulates from 1 to 63, indicating the 63 E1 signals that need to be recovered. Time slot number.
  • the deviation value calculation unit obtains, according to the current slot number signal slot_num, the data buffer depth depth_b of the storage space corresponding to the current slot number and the counter result counter of the current slot number corresponding counter from the downstream buffer RAM_B, The operation obtains the buffer depth deviation value deviation of the time slot; for example, the current time slot number slot_num is 1, and the data buffer depth depth_b of the first time slot is obtained from the buffer RAM-B, and the deviation value calculation unit The data buffer depth depth—b is subtracted from the depth reference value, and the difference is the integer part of the depth deviation from the calculated value depth_dev. At the same time, the current count result counter of the counter 1 of the first time slot is taken as the decimal part of the depth deviation calculation value depth_dev.
  • the deviation value calculation unit calculates the buffer deviation value deviation of the first time slot according to the depth deviation calculation value of the time slot 1 and the reference clock standard value.
  • the calculation process of the E1 signal is 2.048 M, and the system clock is 155.52 M.
  • the system clock 155.52M performs the following frequency division method: In every 1024 frequency division, the frequency division of 76 is 960 times, and the frequency division of 75 is 64 times. According to this method, the frequency division is continuously performed, and the frequency division is performed.
  • the average frequency of the clock signal is 2.048M, which is the standard clock of the E1 signal.
  • the reference clock standard value is continuously accumulated, and the accumulated value exceeds the overflow threshold, and the remainder continues to accumulate with the reference clock reference value.
  • the reference clock standard value is every 1024 In the second accumulation, there will be 64 overflows. If the current data depth of the sampled data stream is 7-bit data (binary), the middle position of the data buffer depth is 7 100-0000, and the intermediate position is used as the depth reference value.
  • the current cache depth value is 7'bOOOO-0000, it means that the cache is fast; if the current cache depth is 7'bl ll-1111, it means that the cache is almost full. Therefore, the difference between the current cache depth value and the intermediate position (depth reference value) is the cache depth deviation state, and the difference is used as the integer part of the depth deviation calculation value depth_dev.
  • the counter counter is the fractional part of the depth deviation from the calculated value depth_dev.
  • the base clock standard value base is the buffer depth deviation value derivation.
  • the depth deviation calculation value depth_dev is 0, it means that there is no deviation in the buffer depth, and only the reference clock standard value base is left.
  • the result of the constant accumulation of the reference clock standard value is that every 1024 accumulations, there will be 64 overflows, 960 times without overflow, and the ratio of the number of overflows and the number of non-overflows is just the number of times the frequency division control is required.
  • the cache depth deviation value deviation is not equal to the reference clock standard value, which means that there is a deviation between the frequency of the data clock and the standard frequency, and the deviation deviates from the calculated value depth_dev. Reflects the deviation of the clock frequency. If the depth deviation from the calculated value depth_dev is too large, the cache depth deviation value deviation is greater than the reference clock standard value, then the cumulative overflow number is increased, and the frequency recovery result is accelerated, and vice versa.
  • the deviation value calculation unit acquires the last accumulated value accumulation from the storage space corresponding to the current slot number of the accumulated value storage unit according to the current slot number signal slot_num, and the buffer depth deviation value deriviation of the path slot and the upper slot The cumulative value accumulation is accumulated to obtain an accumulated result total of the time slot of the road;
  • the deviation value calculation unit determines whether the accumulation has overflowed according to the accumulated result total, and if there is an overflow, puts an overflow flag on the counter corresponding to the current time slot number, and saves the remainder of the accumulated result to the accumulated value.
  • the storage space corresponding to the current slot number of the storage unit is used as the cumulative value accumulation of the next operation. All of the above calculations are done in one clock cycle.
  • S504 the counter of each time slot independently recovers the clock signal of the time slot according to the overflow flag thereof, and the read signal generator generates a read signal read_b for each time slot;
  • the counter of each time slot recovers the clock signal of the time slot according to the overflow flag thereof, and specifically includes the following steps:
  • S5041 The counter of each time slot is respectively based on the frame header signal, and is incremented by one according to the clock signal from the start of the clock;
  • S5042 When the overflow flag ⁇ of the counter is valid, the counter is cleared when the standard value is 74. For the E1 signal, the standard value is 74; when the counter overflow flag ⁇ is invalid, the counter counts to the standard value 74+1, that is, it is cleared at 75, and then the counter restarts counting from zero. Clearing the overflow flag ⁇ while clearing;
  • the read signal generator generates a read signal read_b for each time slot while generating one of the time slot number signals slot_num; and determines whether the read signal read-b is valid or not.
  • the readout signal of the slot is valid: if the current slot number signal slot_num is in a future cycle, and the counter corresponding to the slot number generates a recovery clock pulse, the read signal is valid;
  • the data recovery module reads the recovery data of the storage space corresponding to the slot number from the RAM-B according to the slot number slot_num and the valid read signal read-b, and latches the latch to the corresponding slot number. In the device, the recovery clock pulse is sampled.
  • the above-described method and apparatus using the E1 signal as an example of the application are also applicable to the T1 signal.
  • T1 signal 84 T1 signals per STM-1, the nominal frequency of each T1 is 1.5M.
  • the revision of FIG. 4 and FIG. 5 according to the frame structure of T1 can be applied to T1.
  • the clock signal for the data is 155.52M, the frame time is 125us, and the clock has 19440 clock cycles in one frame.
  • there are 193 bits in one STM-1 period normally only 1 S1 carries 193 bits of data; when 2 S1s are carried, it is 194 bits; when 2 S1 are not carried, it is 192 bits).
  • each time segment has 100 clock cycles, and in the last 140 time segments, each time segment has 101 clock cycles.
  • 84 normal adjustment positions are set (the normal adjustment position also has the reduction adjustment function), and an adjustment adjustment position is set (because there are only 84 time slots, if only one adjustment position is set in one time segment, In the 193 time segments, only 84 time segment settings are required.
  • each time segment of the first 84 time segments is set to an increase adjustment position, and the remaining positions are set as idle adjustment positions.
  • the clock data recovery method and device for the branch signal in the SDH system use a set of clock recovery circuits for multi-channel E1 or T1 signals.
  • the method of sub-multiplexing can simultaneously recover the recovered clock and data of the branch signals with different clock frequencies, and greatly save circuit resources.
  • the clock data recovery method and device for the tributary signal in the SDH provided by the embodiment of the invention adopts a set of clock recovery circuit for the multi-channel E1 or T1 signal, and adopts the time division multiplexing method to recover the multi-way tributary signal at the same time. Restore clock and data, and greatly save circuit resources.

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Abstract

一种SDH中支路信号的时钟数据恢复方法及装置，其中，所述方法包括：从同步数字体系SDH帧结构每路时隙中提取信号的有效数据，存入缓存中各路时隙对应的存储空间中；时分复用地恢复出每路时隙的时钟信号和读出信号；当任意路时隙的读出信号有效时，从所述缓存中所述路时隙对应的存储空间读出数据内容，并锁存到对应时隙的锁存器中；所述装置包括：数据提取模块、时钟恢复电路以及数据恢复模块。

Description

一种 SDH中支路信号的时钟数据恢复方法及装置
技术领域
本发明涉及通信领域， 尤其涉及一种 SDH ( Synchronous Digital Hierarchy 简称， 同步数字体系） 中支路信号的时钟数据恢复方法及装置。
背景技术
随着信息技术的发展和人们对通讯带宽的巨大需求， 通讯网络已经从模 拟网络向数字网络转变， 光纤技术的发展大大推动了数字通讯技术的发展，满 足人们对通讯带宽的需求。 光纤通讯提供了低成本、 高速的信息服务， 迅速 代替了传统的铜缆通讯。 为适应光纤技术的发展， 统一各通讯厂商的产品， 实现传输信息的互通， 国际电联制定了 SDH的通讯标准。 SDH体系的帧信息 结构有丰富的开销字节,方便信息的传输和网络管理， 统一的接口参数能使不 同厂商的设备联合组网，实现跨地域甚至全球的通讯网络互通， 这些优点使得 以 SDH为基础的传输网成为光通讯网建设的主导方向。但新的网络是在原有 的网络基础上建设起来的， 新的 SDH网络需要兼容以前的 PDH结构网络， 满足信息从 SDH体系结构到 PDH体系结构之间的传输， 实现通讯信息可以 穿越不同的通讯网络结构。 当 SDH网络和原有的 PDH网络同时存在时， 低 速信号需要穿过 SDH体系传输时， PDH体系中低速信号到高速信号的简单 复用方式不再适用。 对于 El、 T1等信号在 SDH帧结构中进行传输时， 需要 釆用塞入调节位和固定塞入位，加上通道开销字节，复用到 SDH帧结构中去； 同样当信号从 SDH帧结构到 PDH结构的恢复时， 需要解出虚容器信号， 去 掉开销字节、 固定塞入比特和调节比特， 恢复出 El、 T1信号。 恢复电路是实 现信号从 SDH帧结构到 PDH结构传输的关键电路， 关系到信号穿过不同体 系时时钟的同步信息和抖动 (jitter)指标。 在 STM-1帧结构中包含有 84路 T1 或 63路 E1支路信号， 由于支路信号之间独立， 每路之间的时钟都不相同， 一般实现上是每个支路单独进行恢复， 如中国专利 CN1638283: 实现 E1T1 去抖动的单晶振数字锁相环装置。这些专利实现了单个支路信号的时钟恢复， 对于 STM-1帧， 有 63路 E1支路信号， 应用该专利时需要 63个单独的电路 恢复时钟。 相比单路 El信号， 63路 E1信号需要 63个时钟恢复电路， 消耗 63倍的时钟资源。 在 STM-1帧有 84路 T1支路信号， 应用该专利时需要 84 个单独的恢复电路。对于 STM-16, 有 1008路 E1信号， 需要消耗 1008资源， 资源消耗非常大。 发明内容 本发明实施例提供一种 SDH中支路信号的时钟数据恢复方法及装置，能 同时恢复出多路支路信号的恢复时钟和数据， 大幅度地节约电路资源。 本发明实施例提供了一种 SDH中支路信号的时钟数据恢复方法， 包括： 从同步数字体系 SDH帧结构每路时隙中提取信号的有效数据，存入緩存 中各路时隙对应的存储空间中； 时分复用地恢复出每路时隙的时钟信号和读出信号； 以及 当任意路时隙的读出信号有效时， 从所述緩存中的所述路时隙对应的存 储空间读出数据内容， 并锁存到对应时隙的锁存器中。 可选地， 所述緩存包括上游緩存和下游緩存； 所述从 SDH帧结构每路时隙中提取信号的有效数据，存入緩存中各路时 隙对应的存储空间中， 包括： 从所述 SDH帧结构每路时隙中提取信号的有效数据，先存入到所述上游 緩存中各路时隙对应的存储空间中； 以及 时分复用地产生每路时隙的读指示信号， 根据所述读指示信号从上游緩 存中均匀地读出每路时隙的数据内容， 并写入到下游緩存中各路时隙对应的 存储空间中。 可选地， 所述时分复用地产生每路时隙的读指示信号， 根据所述读指示 信号从上游緩存中均匀地读出每路时隙的数据内容， 包括： 将一个 SDH帧包含的时钟周期划分为 M个时间片段， M为正整数， 每 路时隙的比特数为 M-1、 M或 M+1 , 在每个时间片段时分复用地产生各路时 隙的读指示信号， 每产生一次读指示信号读出相应时隙的一比特数据： 对比特数为 M的每一路时隙， 在 M个时间片段的每一时间片段产生一 次正常泄漏的读指示信号， 读出一比特的数据； 对比特数为 M-1的每一路时隙，在 M-1个时间片段的每一时间片段产生 一次正常泄漏的读指示信号， 读出一比特的数据； 以及 对比特数为 M+1的每一路时隙， 在 M个时间片段的每一时间片段产生 一次正常泄漏的读指示信号， 在其中的一个时间片段产生一次增加泄漏的读 指示信号，且预先划分 SDH帧中各路时隙可产生增加泄漏的读指示信号的时 间片段， 保证各时间片段包含的时钟周期数总是不小于可能产生的最大读指 示信号数。 可选地， 所述时分复用地恢复出每路时隙的时钟信号， 包括： 时分复用地循环计算每路时隙的緩存深度偏差值， 累加所述緩存深度偏 差值， 得到每路时隙的溢出标志； 以及 每路时隙分别根据每路时隙的溢出标志， 独立地恢复出所述路时隙的时 钟信号。 可选地， 所述时分复用地循环计算每路时隙的緩存深度偏差值， 累加所 述緩存深度偏差值得到每路时隙的溢出标志， 包括： 根据帧头信号和时钟信号生成时隙编号信号 slot— num, 所述时隙编号信 号 slot— num从 1到 n不断循环 , n为正整数， 由所述 SDH帧结构的时隙数确 定； 以及 根据当前时隙编号信号 slot— num计算当前一路时隙的緩存深度偏差值， 累加所述緩存深度偏差值，如果累加有溢出则生成当前一路时隙的溢出标志。 可选地， 每路时隙分别根据每路时隙的溢出标志， 独立地恢复出所述路 时隙的时钟信号， 包括： 每路时隙设置一个计数器， 当所述计数器清零时， 产生一个时钟脉冲； 当所述计数器的溢出标志有效时， 所述计数器计数到标准值时清零， 当 所述计数器的溢出标志无效时， 所述计数器计数到标准值 +1时清零， 然后所 述计数器从零重新开始计数，所述标准值由 SDH帧结构的时钟信号频率和每 路信号的标称频率确定。 可选地， 所述时分复用地恢复出每路时隙的读出信号， 包括： 在生成一个所述时隙编号信号 slot— num的同时为每路时隙生成一个读出 信号；
所述任意路时隙的读出信号有效包括： 如果当前时隙编号信号 slot— num 在未来一个循环周期内， 当前一路时隙的计数器会产生时钟脉冲， 则读出信 号有效。
本发明实施例还提供了一种 SDH 中支路信号的时钟数据恢复装置， 包 括： 数据提取模块，其设置成从同步数字体系 SDH帧结构每路时隙中提取信 号的有效数据， 存入緩存中各路时隙对应的存储空间中； 时钟恢复电路， 其设置成时分复用地恢复出每路时隙的时钟信号和读出 信号， 并将所述时钟信号和读出信号发送至数据恢复模块； 以及 数据恢复模块， 其设置成接收所述时钟信号和读出信号， 并且当任意路 时隙的读出信号有效时， 从所述緩存中的所述路时隙对应的存储空间读出数 据内容， 并锁存到对应时隙的锁存器中。 可选地， 所述緩存包括上游緩存和下游緩存； 所述数据提取模块包括： 上游数据提取电路，其设置成从所述 SDH帧结构每路时隙中提取信号的 有效数据， 先存入到所述上游緩存中各路时隙对应的存储空间中； 以及 比特泄露电路， 其设置成时分复用地产生每路时隙的读指示信号， 根据 所述读指示信号从上游緩存中均勾地读出每路时隙的数据内容， 并写入到下 游緩存中各路时隙对应的存储空间中。 可选地， 所述比特泄露电路通过如下方式时分复用地产生每路时隙的读 指示信号， 根据所述读指示信号从上游緩存中均勾地读出每路时隙的数据内 容：
将一个 SDH帧包含的时钟周期划分为 M个时间片段， M为正整数， 每 路时隙的比特数为 M-1、 M或 M+1 , 在每个时间片段时分复用地产生各路时 隙的读指示信号， 每产生一次读指示信号读出相应时隙的一比特数据； 对比特数为 M的每一路时隙， 在 M个时间片段的每一时间片段产生一 次正常泄漏的读指示信号， 读出一比特的数据； 对比特数为 M-1的每一路时隙，在 M-1个时间片段的每一时间片段产生 一次正常泄漏的读指示信号， 读出一比特的数据； 以及 对比特数为 M+1的每一路时隙， 在 M个时间片段的每一时间片段产生 一次正常泄漏的读指示信号， 在其中的一个时间片段产生一次增加泄漏的读 指示信号，且预先划分 SDH帧中各路时隙可产生增加泄漏的读指示信号的时 间片段， 保证各时间片段包含的时钟周期数总是不小于可能产生的最大读指 示信号数。 可选地， 所述比特泄露电路还包括： 一个或多个时钟计数器， 所述时钟计数器设置成以帧头信号为基准对时 钟进行计数； 时隙分配器， 其设置成根据所述时钟计数器的输出结果， 确定每个时间 片段中正常泄漏、 增加泄漏或者减少泄漏的泄露位置以及当前泄露的时隙编 号； 以及 读写控制器， 其设置成根据每个时间片段中正常泄漏、 增加泄漏或者减 少泄漏的泄露位置以及当前泄露的时隙编号， 在每个时间片段内， 根据当前 泄露的时隙编号从上游緩存对应时隙编号的存储空间中正常泄露一次数据或 者增加一次泄露数据或者减少一次泄露数据到下游緩存对应时隙编号的存储 空间中， 其中， 正常泄漏时产生一个读指示信号； 减少泄漏时扣除一个正常 泄漏的读指示信号；增加泄漏时在增加泄漏的泄露位置增加一个读指示信号。 可选地， 所述比特泄露电路还包括： 泄露控制器， 其设置成根据所述上游緩存对应时隙编号的存储空间的緩 存深度产生增加泄漏信号和减少泄漏信号， 所述增加泄漏信号表示增加一次 泄漏； 所述减少泄漏信号表示减少一次泄漏； 以及 读写控制器， 其设置成根据每个时间片段中正常泄漏、 增加泄漏或者减 少泄漏的泄露位置以及当前泄露的时隙编号、增加泄漏信号和减少泄漏信号， 在每个时间片段内， 根据当前泄露的时隙编号从上游緩存对应时隙编号的存 储空间中根据所述增加泄露信号增加一次泄露数据或者根据所述减少泄露信 号减少一次泄露数据到下游緩存对应时隙编号的存储空间中， 其中， 减少泄 漏时扣除一个正常泄漏的读指示信号； 增加泄漏时在增加泄漏位置增加一个 读指示信号。 可选地， 所述时钟恢复电路包括： 偏差值计算单元和为每路时隙设置的 一个计数器， 所述计数器包括一个溢出标志； 所述偏差值计算单元设置成时分复用地循环计算每路时隙的緩存深度偏 差值， 累加所述緩存深度偏差值， 得到每路时隙的溢出标志； 以及 每路时隙的计数器设置成根据所述溢出标志恢复出所述路时隙的时钟信 号。
可选地， 所述时钟恢复电路还包括： 累计值存储单元， 其设置成将每路时隙所述偏差值计算单元输出的上次 累计值保存到其各路时隙对应的存储空间中； 时隙生成器， 其设置成根据帧头信号和时钟信号 ， 生成时隙编号信号 slot num, 所述时隙编号信号 slot— num从 1到 n不断循环， n为正整数， 由所 述 SDH帧结构的时隙数确定； 所述偏差值计算单元通过如下方式时分复用地循环计算每路时隙的緩存 深度偏差值， 累加所述緩存深度偏差值， 得到每路时隙的溢出标志： 所述偏差值计算单元根据当前时隙编号信号 slot— num, 从下游緩存获取 当前时隙编号对应的存储空间的数据緩存深度和当前时隙编号对应计数器的 计数结果， 运算得到所述路时隙的緩存深度偏差值； 根据当前时隙编号信号 slot— num, 从所述累计值存储单元当前时隙编号 对应的存储空间中获取上次累计值， 将所述路时隙的緩存深度偏差值和所述 上次累计值进行累加， 得到所述路时隙的累加结果； 以及 根据所述累加结果判断本次累加是否出现溢出， 如果有溢出则在当前时 隙编号对应的计数器上打上溢出标志， 同时将本次累加结果的余数保存到所 述累计值存储单元当前时隙编号对应的存储空间中， 作为下一次运算的累计 值。 可选地， 每路时隙的计数器通过如下方式根据所述溢出标志恢复出所述 路时隙的时钟信号： 所述每路时隙的计数器分别以帧头信号为基准， 根据时钟信号从零开始 进行力口 1计数； 当所述计数器的溢出标志有效时， 所述计数器计数到标准值时清零， 当 所述计数器的溢出标志无效时， 所述计数器计数到标准值 +1时清零， 然后所 述计数器从零重新开始计数， 在清零的同时清除所述溢出标志； 所述标准值 由 SDH帧结构的时钟信号频率和每路信号的标称频率确定； 以及 当所述计数器清零时， 产生一个时钟脉冲。 可选地， 所述时钟恢复电路还包括： 读出信号生成器， 其设置成在生成一个所述时隙编号信号 slot— num的同 时为每路时隙生成一个读出信号； 所述数据恢复模块， 还包括： 为每路时隙设置的锁存器， 其设置成保存 从下游緩存中读出的对应时隙编号的存储空间中的数据内容； 所述锁存器按 照时隙编号进行编号； 以及 所述数据恢复模块通过如下方式当任意路时隙的读出信号有效时， 从所 述緩存中的所述路时隙对应的存储空间读出数据内容， 并锁存到对应时隙的 锁存器中： 当任意路时隙的读出信号有效时， 根据当前时隙编号信号 slot— num和读 出信号从下游緩存中读出对应时隙编号的存储空间中的数据内容， 并锁存到 对应时隙编号的锁存器中； 其中， 所述任意路时隙的读出信号有效包括： 如 果当前时隙编号信号 slot— num在未来一个循环周期内， 当前一路时隙的的计 数器会产生时钟脉冲， 则读出信号有效。
与相关技术相比，本发明实施例提供的 SDH中支路信号的时钟数据恢复 方法及装置， 将多路 E1或 T1信号釆用一套时钟恢复电路， 釆用时分复用的 办法， 能同时恢复出多路支路信号的恢复时钟和数据， 大幅度地节约电路资 源。 附图概述 图 1 是以 E1信号为例的 STM-1等级相应的 SDH帧结构示意图； 图 2 是以 E1信号为例的 STM-1帧串行信号接收信号图； 图 3是 STM-1帧的 VC12复帧结构示意图；
图 4是实施例中 SDH中支路信号的时钟数据恢复装置结构图；
图 5是实施例中时钟数据恢复装置的比特泄露电路结构图；
图 6是实施例中时钟数据恢复装置的时钟恢复电路及数据恢复模块的结 构图；
图 7是实施例中 SDH中支路信号的时钟数据恢复的方法流程图； 图 8是一个应用示例中 SDH中支路信号的时钟数据恢复装置结构图； 图 9是一个应用示例中时钟数据恢复装置的比特泄露电路结构图； 图 10 是一个应用示例中时钟数据恢复装置的时钟恢复电路以及数据恢 复模块的结构图；
图 11是一个应用示例中一帧 STM-1划分时间片段的方式示意图； 图 12是一个应用示例中在每个时间片段中每路 E1信号泄露位置示意图； 图 13是一个应用示例中 SDH中支路信号的时钟数据恢复的方法流程图。 本发明的较佳实施方式
下文中将结合附图对本发明的实施例进行详细说明。 需要说明的是， 在 不冲突的情况下， 本申请中的实施例及实施例中的特征可以相互任意组合。
实施例：
SDH同步数字传送体系的 STM-1等级相应的帧结构釆用 9行 *270列字 节帧结构， 时隙釆用字节间插方式组成帧结构，在图 1中给出了以 E1信号为 例的 SDH帧结构示意图。 在一帧中， 帧结构的前 9列是段开销字节 POH和 指针字节， 其中的 1-3行是再生段开销 RSOH、 5-9行是复用段开销 MSOH、 第 4行是指针字节， 余下信息字节是信息净负荷区域。 在 STM-1帧中可以承 载 63路 E1信号， 每一路 E1信号在 STM-1帧中占 4列位置， 63路 E1共占 63*4=252列, 63路 E1信号分别间插排列， 按照 1-63、 1-63、 1-63、 1-63的 顺序排列。在 STM-1帧中，也可以承载 84路 T1信号，每一路 T1信号在 STM-1 帧中占 3列位置， 84路 T1共占 84*3=252列， 84路 T1信号分别间插排列， 按照 1-84、 1-84、 1-84、 1-84的顺序排列。
STM-1帧信号在光纤中以串行码流的方式传递， STM-1帧串行信号的时 钟频率为 155.52M。 在接收时， 按照串行码流的方式进行接收， 在接收码流 中找到 STM-1 的帧头信号， 按照处理帧中的 AU指针和 TU指针， 定位出 STM-1帧中的所有 E1信号或 T1信号的位置。 以 E1信号为例， 在图 2中给 出了接收 E1信号的信号图， φ信号给出 STM-1的帧头位置， PL指示帧中所 有 E1信号的位置， data给出所有 E1信号内容。 所有 E1信号按照 1-63的顺 序接收和处理， 对每个 E1信号， 8个比特（1个字节）连续接收完后才开始 接收下一个 E1信号。
在 STM-1帧中， E1信号是先放在 VC12中， VC12放在 TU12中， TU12 最后放在 SDH帧中进行传送。 在 SDH帧， 每个 TU12占据 4列位置， 一个 STM-1帧中每路 TU12信号有 36字节，其中一个字节是 TU12的指针字节（ VI 或 V2、 V3、 V4 ) , 其余 35字节是 VC12的内容， 如图 3所示。 对于 VC12, 每个 VC12有 35个字节， 这 35个字节组成一个子帧， 每 4个子帧组成一个 复帧。 在 VC12复帧中， 有 4个开销字节 V5、 J2、 Z6、 Z7, 也有固定塞入字 节或塞入比特 R, 以及通讯比特 0。 在 VC12复帧中， 同时还有控制比特 C1、 C2和调整比特 Sl、 S2, 剩余的就是数据字节或数据比特。 3个 C1的内容决 定 S1比特是承载有用数据还是无用数据。 当 C1为 0时， 表示 S1承载有用 数据； 当 C1为 1时， 表示 S1承载无用数据。 3个 C1釆用多数判断原则， 即 至少有 2个 C1为 0时， 则认为 3个 C1为 0; 当至少 2个 C1为 1时， 则认为 C1为 1。 同理， C2釆用类似方式。 每一路的 VC12的结构完全一样， 本发明 实施例就是将 SDH帧中所有 E1信号或 T1信号的数据比特提取出来，并恢复 这些 E1信号或 T1信号的时钟信号， 降低时钟信号的抖动， 以满足标准要求。 在 SDH帧结构中 T1信号处理过程和 E1信号类似， 因此在本实施例中以 E1 信号为例进行说明， 本实施例中的装置及方法同样适应于 T1信号。
如图 4所示，本实施例提供了一种 SDH中支路信号的时钟数据恢复装置， 包括： 数据提取模块，其设置成从同步数字体系 SDH帧结构每路时隙中提取信 号的有效数据， 存入緩存中各路时隙对应的存储空间中； 以 E1信号为例， 緩存可以按照 SDH帧结构中的 E1的时隙数进行划分， 在 STM-1中有 63个 E1 , 则将 RAM划分成 63个独立部分， 每个 E1时隙的 数据保存在 RAM各自对应的存储空间中。 时钟恢复电路， 其设置成时分复用地恢复出每路时隙的时钟信号和读出 信号， 并将所述时钟信号和读出信号发送至数据恢复模块； 数据恢复模块， 其设置成接收所述时钟信号和读出信号， 并且当任意路 时隙的读出信号有效时， 从所述緩存中该路时隙对应的存储空间读出数据内 容， 并锁存到对应时隙的锁存器中。 其中， 所述緩存包括上游緩存 RAM— A和下游緩存 RAM— B, 上游緩存 RAM— A位于数据提取模块， 下游緩存 RAM— B位于数据恢复模块； 所述数据 提取模块包括： 上游数据提取电路，其设置成从所述 SDH帧结构每路时隙中提取信号的 有效数据， 先存入到所述上游緩存中各路时隙对应的存储空间中； 比特泄露电路， 其设置成时分复用地产生每路时隙的读指示信号， 根据 所述读指示信号从上游緩存中均勾地读出每路时隙的数据内容， 并写入到下 游緩存中各路时隙对应的存储空间中。
其中， 所述比特泄露电路通过如下方式时分复用地产生每路时隙的读指 示信号，根据所述读指示信号从上游緩存中均匀地读出每路时隙的数据内容： 将一个 SDH帧包含的时钟周期划分为 M个时间片段， M为正整数， 每 路时隙的比特数为 M-1、 M或 M+1 , 在每个时间片段时分复用地产生各路时 隙的读指示信号， 每产生一次读指示信号读出相应时隙的一比特数据： 对比特数为 M的每一路时隙， 在 M个时间片段的每一时间片段产生一 次正常泄漏的读指示信号， 读出一比特的数据； 对比特数为 M-1的每一路时隙，在 M-1个时间片段的每一时间片段产生 一次正常泄漏的读指示信号， 读出一比特的数据； 对比特数为 M+1的每一路时隙， 在 M个时间片段的每一时间片段产生 一次正常泄漏的读指示信号， 在其中的一个时间片段产生一次增加泄漏的读 指示信号，且预先划分 SDH帧中各路时隙可产生增加泄漏的读指示信号的时 间片段， 保证各时间片段包含的时钟周期数总是不小于可能产生的最大读指 示信号数。
以 E1信号为例， 对于 STM-1 串行数据流， 时钟信号频率是 155.52M, 一帧时间是 125us, 在一帧时间中时钟有 19440个时钟周期。 对于一路 E1信 号， 在一个 STM-1周期内共有 256比特（只有 1个 S1承载数据时是 256比 特； 当 2个 S1都承载时是 257比特； 当 2个 S1都不承载时是 255比特 ) 。 将 19440时钟周期按照图 4的方式划分成多个时间片段:其中第 1个时间片段 是 75个时钟周期， 另外 15段（第 2-15个时间片段）是 76个时钟周期， 依 次循环划分。 这样在 19440个时钟周期中， 可以划分出 16个 75时钟周期的 时间片段， 16*15个 76时钟周期的时间片段，共 256个时间片段。在一个 STM-1 周期中， 当每路 E1信号有 256个比特（或 255、 257个比特 ) , 在每个时间 片段内， 从上游緩存中泄漏一个比特到下游緩存中， 就可以均勾地将数据从 上游緩存的数据泄漏到下游緩存中。相对于每路时隙数据在 SDH帧结构中集 中分布在固定时隙位置， 此处的均勾泄漏， 即从上游緩存中均勾地读出每路 时隙的数据内容，表示每路时隙的数据比特在读出时间间隔上已经均匀分布， 但因存在减少泄漏或增加泄漏的现象， 数据比特在读出时间上并非完全等间 隔。 当一个 STM-1周期中 E1信号只有 255个比特（ Sl、 S2都不承载数据 ) 时， 则在 256个时间片段中， 有一个时间片段不泄漏数据（不泄漏数据的活 动称为减少泄漏） ， 这样泄漏到下游的比特数就少 1个， 即 255个比特。 当 一个 STM-1周期中 E1信号有 257个比特时（ S1S2都承载有效数据 ) , 则在 256时间片段中， 有一个时间片段中泄漏 2个比特（多泄漏数据的活动称谓 增加泄漏） ， 这样泄漏到下游的比特数就多 1个， 即 257个比特。 时间片段 的划分方式可以包括多种， 只要保证每个时间片包括的时钟周期大于 63 , 且 将 19440时钟周期划分为 256个时间片段。 如图 5所示， 在一个应用示例中， 所述比特泄露电路包括： 一个或多个时钟计数器， 所述计数器设置成以帧头信号为基准对时钟进 行计数； 时隙分配器， 其设置成根据所述计数器的输出结果， 确定每个时间片段 中正常泄漏、 增加泄漏或者减少泄漏的泄露位置以及当前泄露的时隙编号； 读写控制器， 其设置成根据每个时间片段中正常泄漏、 增加泄漏或者减 少泄漏的泄露位置（norm_pos、 add_pos、 dec_pos ) 以及当前泄露的时隙编号 ( leak— slot— num ) , 在每个时间片段内， 根据当前泄露的时隙编号从上游緩 存对应时隙编号的存储空间中正常泄露一次或者增加一次泄露或者减少一次 泄露数据到下游緩存对应时隙编号的存储空间中， 其中， 正常泄漏时产生一 个读指示信号； 减少泄漏时扣除一个正常泄漏的读指示信号； 增加泄漏时在 增加泄漏的泄露位置增加一个读指示信号。 其中， 比特泄露电路还包括： 泄露控制器， 其设置成根据所述上游緩存对应时隙编号的存储空间的緩 存深度产生增加泄漏信号 add和减少泄漏信号 dec,所述增加泄漏信号 add表 示增加一次泄漏； 所述减少泄漏信号 dec表示减少一次泄漏； RAM緩存深度表示数据的多少， 当数据过多时需要增加泄露速度，数据 越多， 增加泄露的频率也越大； 当数据过少时需要减少泄露， 数据越少， 泄 漏的频率也越少。 例如， 在 leak slot num等于对应时隙号时, 在 norm_pos 或 add_pos位置时， 当对应时隙的数据过多时才生成 add,在 dec_pos位置时， 当数据过少时才生成 dec。 读写控制器， 其设置成根据每个时间片段中正常泄漏、 增加泄漏或者减 少泄漏的泄露位置以及当前泄露的时隙编号、 增加泄漏信号 add和减少泄漏 信号 dec, 在每个时间片段内， 根据当前泄露的时隙编号从上游緩存 RAM— A 对应时隙编号的存储空间中根据所述增加泄露信号增加一次泄露或者根据所 述减少泄露信号减少一次泄露数据到下游緩存 RAM— B对应时隙编号的存储 空间中， 其中， 减少泄漏时扣除一个正常泄漏的读信号； 增加泄漏时在增加 泄漏位置增加一个读指示信号。 比特泄漏电路通过控制读操作次数， 将每路时隙信号的数据从上游緩存 中比较均匀地泄露到下游緩存中， 在下游恢复出每路时隙信号的数据和时钟 信息。 如图 6所示， 在一个应用示例中， 所述时钟恢复电路包括： 偏差值计算单元， 其设置成时分复用地循环计算每路时隙的緩存深度偏 差值， 累加所述緩存深度偏差值， 得到每路时隙的溢出标志； 每路时隙设置一个计数器， 该计数器设置成根据所述溢出标志恢复出该 路时隙的时钟信号； 所述计数器按照时隙编号进行编号， 每个计数器由两个 部分组成： 溢出标志和计数器 n ( n表示时隙编号）， 对于 E1信号， 有 63个 计数器； 累计值存储单元， 其设置成将每路时隙所述偏差值计算单元输出的上次 累计值 accumulation保存到其各路时隙对应的存储空间中； 时隙生成器， 其设置成根据帧头信号 φ和时钟信号 clock, 生成时隙编 号信号 slot— num,所述时隙编号信号 slot— num从 1到 n不断循环，η为正整数， 由所述 SDH帧结构的时隙数 (即， 所述 SDH帧结构承载的信号路数 )确定； 偏差值计算单元通过如下方式时分复用地循环计算每路时隙的緩存深度 偏差值， 累加所述緩存深度偏差值， 得到每路时隙的溢出标志： 所述偏差值计算单元根据当前时隙编号信号 slot— num , 从下游緩存 RAM— B获取当前时隙编号对应的存储空间的数据緩存深度 depth— b和当前时 隙编号对应计数器的计数结果 counter, 运算得到该路时隙的緩存深度偏差值 deviation; 根据当前时隙编号信号 slot— num, 从累计值存储单元当前时隙编号对应 的存储空间中获取上次累计值 accumulation, 将该路时隙的緩存深度偏差值 deviation和上次累计值 accumulation进行累加 ,得到该路时隙的累加结果 total; 根据所述累加结果 total, 判断本次累加是否出现溢出， 如果有溢出则在 当前时隙编号对应的计数器上打上溢出标志， 同时将本次累加结果的余数保 存到累计值存储单元当前时隙编号对应的存储空间中， 作为下一次运算的累 计值 accumulation„ 对于 E1信号， slot— num从 1到 63不断循环,表示需要恢复的 63路 E1信 号的时隙编号。 时隙编号信号 slot— num表示当前正在恢复任意一路时隙的时 钟信号， 该路时隙的溢出标志的运算过程都在一个时钟周期内完成。 例如， 对于第 1路时隙， 在 slot— num为 1时完成第 1路时隙的运算过程， 下个时钟 周期时， slot— num为 2, 完成第 2路时隙的运算过程， 以此类推不断循环地完 成所有时隙的累加运算过程。 其中， 緩存深度偏差值 deviation计算过程是： 所述偏差值计算单元将所述数据緩存深度 depth— b 的值和深度参考值相 减，得到数据緩存的深度偏离计算值 depth— dev的整数部分。计数结果 counter 是深度偏离计算值 depth— dev 的小数部分； 其中， 所述计数器的计算结果 counter为上一次计数器清零后到当前读取时计数器的计数结果。 将所述数据緩存的深度偏离计算值 depth— dev整数部分和小数部分拼接 起来（整数部分在前， 小数部分在后）和基准时钟标准值相加得到緩存深度 偏差值 deviation„ 深度偏离计算值 depth— dev表示当前緩存深度的偏差方向和大小：如果偏 差值为正， 表示緩存数据量偏大， 上游存入的数据量在增加， 需要恢复的时 钟频率加快些， 以便加快从緩存中读出数据。 偏差值的大小反映出恢复时钟 变化的大小。 如果偏差值为负， 反映上游存入的数据量在减少， 需要恢复的 时钟频率减慢些， 以减慢从緩存中读出数据的速度。 目标参考标准值与当前 时钟、 偏差值位有关。 緩存深度偏差值 deviation反映下一轮时钟恢复时的恢复速度大小。 对偏 差值 deviation不间断地进行累加， 累加时如果出现溢出现象， 则将溢出后的 余量和偏差值 deviation不断进行累计。 緩存深度偏差值 deviation越大， 则溢 出次数越多； 越小， 则溢出次数越少， 因此累计溢出的次数反映出恢复时钟 的频率大小。 通过溢出次数可以调节恢复时钟的频率大小。 设置溢出门限值， 通过累加结果 total是否达到门限值来判断本次累加是 否出现溢出， 溢出门限值与时钟频率以及数据緩存深度 depth— b有关。 其中， 所述每路时隙的计数器通过如下方式根据所述溢出标志恢复出该 时隙的恢复时钟信号： 每路时隙的计数器分别以帧头信号为基准， 根据时钟信号从零开始进行 加 1计数； 当所述计数器的溢出标志 p有效时， 该计数器计数到标准值时清零， 当 所述计数器的溢出标志 p无效时， 该计数器计数到标准值 +1时清零， 然后所 述计数器从零重新开始计数， 在清零的同时清除所述溢出标志 p; 所述标准 值由 SDH帧结构的时钟信号频率和每路信号的标称频率确定； 当所述计数器清零时， 产生一个时钟脉冲。 以 E1信号为例， 一帧 STM-1的时钟信号频率是 155.52M, 每路 E1信号 的标称时钟频率是 2.048M, 用一帧 STM-1的时钟信号频率除以每路 E1信号 的标称时钟频率得到计数器计数清零的目标值为 74 (从 0开始计数， 计数到 74时共计数 75次， 即 75分频） ， 如果本计数器溢出标志无效， 计数器计数 到目标值 74+1时清零， 也就是累加到 75时清零， 然后从零重新开始计数， 如果本计数器溢出标志有效， 则本次计数到目标值时才清零， 然后从零开始 重新计数， 当计数器每次清零时， 表示计数器完成一个计数周期， 计数器就 输出一个时钟脉冲， 该脉冲就是本时隙的恢复时钟脉冲。 当有溢出标志时， 计数器只计数到目标值就清零， 计数时间短， 产生的 脉冲时间快； 当没有溢出标志时， 计数器只计数到目标值 +1才清零， 计数时 间长， 产生的脉冲时间慢。 因此溢出标志越多， 计数器计数的时间越短， 产 生脉冲越快， 固定时间内产生的脉冲数量就越多， 恢复的时钟频率就偏高； 反之， 溢出标志越少， 计数器计数的时间就越长， 产生脉冲越慢， 固定时间 内产生的脉冲数量就越少， 恢复的时钟频率就偏低。 通过溢出次数可以调节 恢复时钟的频率大小， 通过这种方式就可以根据数据緩存量的大小均匀地恢 复出业务的时钟信号。 此外， 所述时钟恢复电路还包括： 读出信号生成器， 其设置成在生成一个所述时隙编号信号 slot— num的同 时为每路时隙生成一个读出信号， 并判断该读出信号是否有效； 任意路时隙 的读出信号有效是指： 如果当前时隙编号信号 slot— num在未来一个循环周期 内， 对应时隙编号的计数器会产生恢复时钟脉冲， 则读出信号有效； 以 E1信号为例， slot— num从 1到 63不断循环， 计数器计数一个周期清 零产生一个恢复时钟脉冲， 一个计数周期为 75或 74, 读出信号有效的原则 是： 当系统需要恢复 63路时隙时， slot— num每循环一次需要 63个时钟周期， 对于第 1路时隙， 在 slot— num为 1到下次再次为 1时， 需要 63个时钟周期。 当计数器的当前值和计数器的目标值之差大于 63时，意味着 slot— num循环一 周后到再次等于 1的这段时间中， 计数器不会计数到目标值， 也就是不会产 生本时隙的恢复时钟脉冲， 这种情况下不需要准备恢复数据， 因此这种情况 下读出信号就无效； 如果计数器的当前值和计数器目标值之差小于 63时， 意 味者 slot— num从 1开始循环一周到再次为 1的这段时间中， 计数器会计数到 目标值， 从而产生本时隙的恢复时钟脉冲， 因此这种情况下读出信号就有效。 如图 6所示， 所述数据恢复模块除了下游緩存 RAM— B之外， 还包括： 为每路时隙设置的一个锁存器， 该锁存器用于保存从下游緩存中读出的对应 时隙编号的存储空间中的数据内容； 所述锁存器按照时隙编号进行编号； 所述数据恢复模块通过如下方式当任意路时隙的读出信号有效时， 从所 述緩存中该路时隙对应的存储空间读出数据内容， 并锁存到对应时隙的锁存 器中， 包括： 当任意路时隙的读出信号有效时， 根据当前时隙编号信号 slot— num和读 出信号从下游緩存中读出对应时隙编号的存储空间中的数据内容， 并锁存到 对应时隙编号的锁存器中。
如图 7所示，本实施例提供了一种 SDH中支路信号的时钟数据恢复的方 法， 包括以下步骤： S101 : 从同步数字体系 SDH帧结构每路时隙中提取信号的有效数据，存 入緩存中各路时隙对应的存储空间中；
S102: 时分复用地恢复出每路时隙的时钟信号和读出信号；
S103: 当任意路时隙的读出信号有效时， 从所述緩存中该路时隙对应的 存储空间读出数据内容， 并锁存到对应时隙的锁存器中。 其中， 所述緩存 RAM包括上游緩存 RAM— A和下游緩存 RAM— B; 步骤
S101还包括以下步骤： 从所述 SDH帧结构每路时隙中提取信号的有效数据，先存入到所述上游 緩存中各路时隙对应的存储空间中； 时分复用地产生每路时隙的读指示信号， 根据所述读指示信号从上游緩 存中均匀地读出每路时隙的数据内容， 并写入到下游緩存中各路时隙对应的 存储空间中。
其中， 时分复用地产生每路时隙的读指示信号， 根据所述读指示信号从 上游緩存中均匀地读出每路时隙的数据内容， 包括： 将一个 SDH帧包含的时钟周期划分为 M个时间片段， M为正整数， 每 路时隙的比特数为 M-1、 M或 M+1 , 在每个时间片段时分复用地产生各路时 隙的读指示信号， 每产生一次读指示信号读出相应时隙的一比特数据： 对比特数为 M的每一路时隙， 在 M个时间片段的每一时间片段产生一 次正常泄漏的读指示信号， 读出一比特的数据； 对比特数为 M-1的每一路时隙，在 M-1个时间片段的每一时间片段产生 一次正常泄漏的读指示信号， 读出一比特的数据； 对比特数为 M+1的每一路时隙， 在 M个时间片段的每一时间片段产生 一次正常泄漏的读指示信号， 在其中的一个时间片段产生一次增加泄漏的读 指示信号，且预先划分 SDH帧中各路时隙可产生增加泄漏的读指示信号的时 间片段， 保证各时间片段包含的时钟周期数总是不小于可能产生的最大读指 示信号数。 其中，作为一种较佳的方式， 步骤 S102中时分复用地恢复出每路时隙的 时钟信号， 还包括： 时分复用地循环计算每路时隙的緩存深度偏差值， 累加所述緩存深度偏 差值， 得到每路时隙的溢出标志； 每路时隙分别根据其溢出标志， 独立地恢复出该路时隙的时钟信号。 其中， 时分复用地循环计算每路时隙的緩存深度偏差值， 累加所述緩存 深度偏差值， 得到每路时隙的溢出标志包括： 根据帧头信号和时钟信号生成时隙编号信号 slot— num, 所述时隙编号信 号 slot— num从 1到 n不断循环， n为正整数，由所述 SDH帧结构的时隙数（即， 所述 SDH帧结构承载的信号路数） 决定； 根据当前时隙编号信号 slot— num计算当前一路时隙的緩存深度偏差值， 累加所述緩存深度偏差值，如果累加有溢出则生成当前一路时隙的溢出标志。 作为一种较佳的方式， 所述方法还包括： 设置一个累计值存储单元， 并 为每路时隙设置一个计数器， 累计值存储单元可以按照 SDH帧结构中的 E1 的时隙数进行划分， 按照时隙编号为所述计数器进行编号， 所述计数器包括 溢出标志；
时分复用地循环计算每路时隙的緩存深度偏差值， 累加所述緩存深度偏 差值， 得到每路时隙的溢出标志还包括： 时隙生成器根据帧头信号 φ 和时钟信号 clock , 生成时隙编号信号 slot num, 所述时隙编号信号 slot— num从 1到 n不断循环； 以 E1信号为例， slot— num从 1到 63循环。 根据当前时隙编号信号 slot— num, 从下游緩存 RAM— B获取当前时隙编 号对应的存储空间的数据緩存深度 depth— b和当前时隙编号对应计数器的计 数结果 counter, 运算得到该路时隙的緩存深度偏差值 deviation; 根据当前时隙编号信号 slot— num, 从累计值存储单元当前时隙编号对应 的存储空间中获取上次累计值 accumulation, 将该路时隙的緩存深度偏差值 deviation和上次累计值 accumulation进行累加 ,得到该路时隙的累加结果 total; 根据所述累加结果 total, 判断本次累加是否出现溢出， 如果有溢出则在 当前时隙编号对应的计数器上打上溢出标志， 同时将本次累加结果的余数保 存到累计值存储单元当前时隙编号对应的存储空间中， 作为下一次运算的累 计值 accumulation„ 其中， 所述緩存深度偏差值 deviation的计算过程是： 将所述数据緩存深度 depth— b 的值和深度参考标准值相减， 得到数据緩 存的深度偏离计算值 depth— dev的整数部分； 计数器的计算结果 counter是深 度偏离计算值 depth— dev的小数部分。 其中， 所述计数器的计算结果 counter 为上一次计数器清零后到当前读取时计数器的计数结果。 将所述数据緩存的深度偏离计算值 depth— dev的整数部分和小数部分拼 接起来（整数部分在前， 小数部分在后）， 深度偏离计算值 depth— dev和基准 时钟标准值相加得到緩存深度偏差值 deviation 其中， 每路时隙分别根据其溢出标志， 独立地恢复出该路时隙的时钟信 号包括： 每路时隙的计数器分别以帧头信号为基准， 根据时钟信号从零开始进行 加 1计数； 当所述计数器的溢出标志有效时， 该计数器计数到标准值时清零， 当所 述计数器的溢出标志无效时， 该计数器计数到标准值 +1时清零， 然后所述计 数器从零重新开始计数,在清零的同时清除所述溢出标志；所述标准值由 SDH 帧结构的时钟信号频率和每路信号的标称频率确定； 当所述计数器清零时， 产生一个恢复时钟脉冲。 其中，作为一种较佳的方式， 步骤 S102中时分复用地恢复出每路时隙的 读出信号， 包括： 在生成一个所述时隙编号信号 slot— num的同时为每路时隙生成一个读出 信号； 其中， 步骤 S103还包括： 当任意路时隙的读出信号有效时， 根据当前时隙编号信号 slot— num和读 出信号从下游緩存中读出对应时隙编号的存储空间中的数据内容， 并锁存到 对应时隙编号的锁存器中； 其中， 所述任意路时隙的读出信号有效包括： 如 果当前时隙编号信号 slot— num在未来一个循环周期内， 对应时隙编号的计数 器会产生时钟脉冲， 则读出信号有效。
在一个应用示例中以 STM-1等级相应的帧结构、 E1信号为例， 结合图
8-10对本发明实施例作详细描述， 如图 8所示， SDH中支路信号的时钟数据 恢复装置包括： 上游数据提取电路、 比特泄露电路、 时钟恢复电路和数据恢 复模块， 其中： 上游数据提取电路，根据帧头信号 φ、 时钟信号 clock以及数据信号 data 从 SDH帧结构每路时隙中提取信号的有效数据，存入到上游緩存 RAM— A对 应时隙编号的緩存中； 上游数据提取电路根据 C1和 C2比特的内容，判断 S1和 S2比特是否是 有效数据。 如果 Sl、 S2比特的位置是有效数据， 也需要提取出来存放在该时 隙的緩存中。 緩存 RAM— A按照 SDH中的 E1的时隙数进行划分， 在 STM-1 中有 63个 E1 , 则将 RAM— A划分成 63个独立部分， 每个 E1时隙的数据存 在各自对应空间。 比特泄露电路， 其设置成时分复用地产生每路时隙的读指示信号， 根据 所述读指示信号从上游緩存 RAM A中均匀地读出每个时隙编号緩存的数据 内容， 并写入到下游緩存 RAM— B对应时隙编号的存储空间中。 RAM— B的划 分方式与 RAM— A相同。 作为一种较佳方式， 如图 9所示， 比特泄露电路包括： 3个时钟计数器、 时隙分配器、 泄露控制器和读写控制器， 其中： 作为一种较佳方式， 但不排除其他划分时间片段的方式， 图 11给出了一 种划分时间片段的方式。 如图 11所示， 将 STM-1—帧时间中的 19440时钟 周期分成多个时间片段:其中第 1个时间片段是 75个时钟周期，另外 15段（第 2-15个时间片段 )是 76个时钟周期， 依次循环划分。 这样在 19440个时钟周 期中， 可以划分出 16个 75时钟周期的时间片段， 16*15个 76时钟周期的时 间片段， 共 256个时间片段。 在一个 STM-1周期中， 当每路 E1信号有 256 个比特（或 255、 257个比特 ) ,在每个时间片段内，从上游的数据提取 RAM A 中泄漏一个比特到数据恢复 RAM— B中，就可以均勾地将数据从上游 RAM— A 泄漏到下游 RAM— B中。当一个 STM-1周期中 E1信号只有 255个比特（ S1S2 都不承载数据 )时， 则在 256个时间片段中，有一个时间片段不泄漏数据 (不 泄漏数据的活动称为减少泄漏 ) , 这样泄漏到下游的比特数就少 1个， 即 255 个比特。 当一个 STM-1周期中 E1信号有 257个比特时（ S1S2都承载有效数 据） ， 则在 256时间片段中， 有一个时间片段中泄漏 2个比特（多泄漏数据 的活动称谓增加泄漏）， 这样泄漏到下游的比特数就多 1个， 即 257个比特。 由于一个时间片段至少有 75个时钟周期，一个 STM-1帧中最多只有 63路 E1 信号， 因此一个时间片段可以满足 63路 E1信号的正常泄漏要求。 在极端情 况下， 在 STM-1帧中， 63路 E1信号都同时有 257个比特， 如果所有 E1都 要求在同一个时间片段中泄漏 2个比特 (一次正常泄漏和一次增加泄漏）时， 一个时间片段共需要泄漏 2*63=126个比特， 但一个时间片段内只有 75或 76 个时钟周期，无法泄漏 126比特。由于一个 STM-1帧中共有 256个时间片段， 而每路 E1在 STM-1周期内最多只会多泄漏 1个比特， 因此将 63路 E1增加 泄漏的活动人为地打散到 256个时间片段中， 每个时间片段中只需要对少量 的 E1信号进行增加泄漏， 如图 12所示， 例如， 每个时间片段中最多只负责 4路 E1的增加泄漏， 这样一个时间片段内可以满足所有 E1信号的正常泄漏 要求。 将一个时间片段划分成 3部分， 正常 /减少泄漏部分， 增加泄漏部分和 空闲泄漏部分。 在正常泄漏中， 如果需要减少泄漏， 则扣除正常泄漏， 就减 少一个比特的泄漏， 实现减少泄漏功能。 在图 12中前 15个时间片段中， 每 个时间片段只负责 4路 E1的增加泄漏， 分别是 1-4、 5-8、 9-12...57-60路 E1 , 第 16个时间片段只负责 61 -63路 E1的增加泄漏。 这样前 16个时间片段就可 以完成所有 63路 E1的增加泄漏要求。 其他时间片段中不再安排增加泄漏活 动。 在具体实现时， 时间片段的划分方式以及增加泄漏放在哪个时间片段中 实现并不限于本实施例给出的方式， 例如， 可以在前 63个时间片段中， 每个 时间片段只负责 1路 E1的增加泄漏。 如图 9所示， 时钟计数器根据 SDH的帧头信号 φ对时钟信号 clock进行 计数， 帧头信号 φ到来时计数器全部清零， 重新对 clock进行计数。 对于 E1 信号， 时钟计数器按照上面划分片段的方式进行计数。 在本应用示例中设置 3个时钟计数器，包括：时钟计数器 1( counter— low )、 时钟计数器 2 ( counter middle )和时钟计数器 3 ( counter high ) , 但在实现 时并不排除设置多个时钟计数器。 时钟计数器 counter— low从 1 计数到 75/76; 计数器 counter— middle和 counter— high用于计数时间片段，都是从 1计数到 16,组合起来就是从 1-256。 counter— middle计数一个循环时, counter— high才计数一次。 counter— middle决 定了 counter— low计数的最大值是 75还是 76。在图 7和图 8中， counter— middle 为 1时， counter— low计数最大值为 75 , 其余情况下 counter— low都是计数到 76。 counter high 决定是否存在增加泄漏或减少泄漏。 在本应用示例中 counter high 为 1 时， 时间片段内才可能有增加泄漏或减少泄漏， 在 counter— high为其他值时， 只有正常泄漏， 没有增加泄漏和减少泄漏。 这样保 证在 STM-1的周期内 19440个时钟下，可以划分出 16个 75时间片段， 16*15 个 76时间片段， 共 256个时间片段。 比特泄漏电路中的时隙分配器确定每路 E1信号的泄漏位置。在图 12中， 时钟计数器 counter— low在 1-63范围时， 表示每路信号的正常泄漏或减少泄 漏。 如 counter— low为 1时表示第 1路 E1信号的正常泄漏或减少泄漏位置， 每路信号与每路时隙对应； counter— low为其他内容时， 表示空闲泄漏位置， 不进行泄漏。 由于在一个 STM-1帧内， 每路 E1信号 （或者说每路时隙 )最 多一次减少泄漏， 这样减少泄漏只要在一个时间片段内实现即可， 在本应用 示例中将减少泄漏放在第一个时间片段。 将 63路 E1增加泄漏活动人为地打 散到 256个时间片段中，每个时间片段中只需要对少量的 E1信号进行增加泄 漏， 在本应用示例中在前 15个时间片段内， counter— low为 64、 65、 66、 67 表示 E1信号的增加泄漏位置。 例如： 第一个时间片段内， counter— low为 64、
65、 66、 67表示第 1、 2、 3、 4路 E1信号的增加泄漏位置； 第二个时间片段 内， counter— low为 64、 65、 66、 67表示第 5、 6、 7、 8路 E1信号的增加泄 漏位置， 依次类推。 在第 16个时间片段内， counter— low为 64、 65、 66表示 第 61路、 62路、 63路 E1信号的增加泄漏位置。 依据上述 3个时钟计数器的输出结果， 时隙分配器根据正常泄漏、 增加 泄漏、 减少泄漏的产生机制， 产生泄漏时隙编号信号 leak— slot— num, 正常泄 漏位置信号 norm_pos、 增力。泄漏位置信号 add_pos 以及减少泄漏位置信号 dec_pos。 这些泄漏位置信号指示在该位置上可以进行的泄漏类型。 leak— slot— num指示当前泄漏的时隙编号。对于 E 1信号， leak— slot— num有效范 围是从 1-63。例如，在图 12中，第一个时间片段内，当时钟计数器 counter— low 在 1-63范围时， 表示每路信号的正常泄漏或减少泄漏， leak— slot— num对应当 前正常泄露或当前减少泄露的时隙编号， 从 1 -63； 当 counter— low为 64、 65、
66、 67表示第 1、 2、 3、 4路 E1信号的增加泄漏位置， leak— slot— num对应 1、 2、 3、 4。 泄漏控制器给出泄漏操作信号： 根据所述上游緩存 RAM A对应时隙编 号的存储空间的深度 depth— a产生增加泄漏信号 add和减少泄漏信号 dec, 所 述增加泄漏信号 add表示增加一次泄漏； 所述减少泄漏信号 dec表示减少一 次泄漏； 读写控制器根据当前泄露时隙编号信号 leak— slot— num、泄漏操作信号（增 加泄漏 add、 减少泄漏 dec ) 、 泄露位置信号 （正常泄漏位置信号 norm_pos、 增加泄漏位置信号 add_pos、 减少泄漏位置信号 dec_pos )产生上游 RAM— A 的读指示信号， 从緩存中读出对应时隙的数据内容， 同时将读出的数据写入 到下游 RAM— B对应时隙编号的存储空间中。正常泄漏产生一个读指示信号； 如果有减少泄漏， 则扣除一个正常泄漏的读指示信号； 如果有增加泄漏， 则 在增加泄漏位置增加一个读指示信号。 比特泄露电路产生每路信号 （对应每个时隙） 的读指示信号， 从上游数 据緩存中读出数据， 存入到下游数据恢复緩存 RAM— B中， 通过控制读操作 次数， 将每路信号比较均匀地泄露到下游緩存 RAM— B中， 在下游恢复出每 路信号的数据和时钟信息。 作为一种较佳方式，如图 10所示，时钟恢复电路包括：偏差值计算单元、 时隙生成器、 读出信号生成器、 每路时隙分配一个计数器和一个累计值存储 单元， 其中：
时隙产生器才艮据帧头信号 φ和时钟信号 clock不断循环地产生时隙编号 信号 slot— num。 对于 El信号， slot— num从 1到 63不断循环,表示需要恢复的 63路 E1信号时隙编号。 偏差值计算单元根据当前时隙编号信号 slot— num, 从下游緩存 RAM— B 获取当前时隙编号对应的緩存的数据緩存深度 depth— b和当前时隙编号对应 计数器的计数结果 counter, 运算得到该路时隙的緩存深度偏差值 deviation; 例如， 当前时隙编号 slot— num为 1 , 从緩存 RAM— B中得到第 1路时隙 的数据緩存深度 depth— b, 同时得到第一路时隙的计数器 1 的当前计数结果 counter,偏差值计算单元根据时隙 1的緩存深度 depth— b和计数器的计算结果 counter计算出第 1路时隙的緩存偏差值 deviation 其中， 緩存深度偏差值 deviation计算过程是： 所述偏差值计算单元将所述数据緩存深度 depth— b 的值和深度参考值相 减，得到緩存深度的偏离状况， 差值就是深度偏离计算值 depth— dev的整数部 分； 所述计数器的计数结果 counter作为深度偏离计算值 depth— dev的小数部 分。 其中， 所述计数器的计算结果 counter为上一次计数器清零后到当前读取 时计数器的计数结果。 将所述数据緩存的深度偏离计算值 depth— dev的整数部分和小数部分拼 接起来（整数部分在前， 小数部分在后） ， 和基准时钟标准值相加， 得到緩 存深度偏差值 deviation„ 偏差值计算单元根据当前时隙编号信号 slot— num, 从当前时隙编号对应 的累计值存储单元中获取上次累计值 accumulation,将该路时隙的緩存深度偏 差值 deviation和上次累计值 accumulation进行累加 , 得到该路时隙的累加结 果 total; 根据所述累加结果 total, 判断本次累加是否出现溢出， 如果加法运算时 有溢出则将溢出标志存到当前时隙编号对应的计数器的标志位置 p, 同时将 本次累加结果的余数保存到当前时隙编号对应的累计值存储单元中， 作为下 一次运算的累计值 accumulation 偏差值计算单元上述的所有计算过程都在一个时钟周期中完成。 例如， 对于第 1路时隙， 在 slot— num为 1时完成第 1路时隙的溢出标志运算过程。 下个时钟周期时， slot— num为 2, 完成第 2路时隙的运算过程， 以此类推不循 环地完成所有时隙的累加运算过程。 每路时隙都有一个计数器， 每个计数器由两个部分组成： 溢出标志 p和 计数器 n ( n表示时隙编号）， 对于 E1信号有 63个计数器。 溢出标志指示该 时隙在上次累加运算时， 加法器是否出现溢出现象。 计数器 n则不断地从零 开始计数， 如果本计数器溢出标志 p无效， 也就是没有出现溢出， 则计数器 计数到目标值（在系统时钟为 155.52M, 对于 E1信号， 目标值是 74 ) +1时 清零， 也就是累加到 75时清零， 然后从零重新开始计数； 如果本计数器溢出 标志 p有效， 则本次计数到目标值时才清零， 然后从零开始重新计数， 计数 器在清零的同时需要清除溢出标志 p。 每一路时隙的计数器都是独立地进行 计数， 当计数器每次清零时， 表示计数器完成一个计数周期， 计数器就输出 一个时钟脉冲， 该脉冲就是本时隙的恢复时钟脉冲。 读出信号生成器， 用于在生成一个所述时隙编号信号 slot— num的同时为 每路时隙生成一个读出信号 read— b; 并判断该读出信号 read— b是否有效， 任 意路时隙的读出信号有效是指： 如果当前时隙编号信号 slot— num在未来一个 循环周期内， 对应时隙编号的计数器会产生恢复时钟脉冲， 则读出信号有效； 时钟恢复电路在恢复每路 E1信号时钟时，同时给出每路时隙数据的读出 信号 read— b和时隙编号 slot— num,准备好每路时隙的数据。 例如： 当恢复第 1 路时隙的时钟时， 也就是在 slot— num为 1时， 需要根据计数器 1的计数结果 判断数据恢复緩存 RAM— B的读出信号 read— b是否有效， 当读出信号 read— b 有效时， 从 RAM— B中读出第 1路时隙的数据， 准备好第 1路时隙的恢复数 据。 读出信号 read— b有效的原则是： 如果当前时隙编号信号 slot— num在未来 一个循环周期内， 对应时隙编号的计数器会产生恢复时钟脉冲， 则读出信号 有效。 以 E1信号为例， 当系统需要恢复 63路时隙时， slot— num每循环一次 需要 63个时钟周期， 对于第 1路时隙， 在 slot— num为 1到下次再次为 1时， 需要 63个时钟周期。 当计数器的当前值和计数器的目标值之差大于 63时， 意味者 slot— num循环一周后到再次等于 1的这段时间中， 计数器不会计数到 目标值， 也就是不会产生本时隙的恢复时钟脉冲， 这种情况下不需要准备恢 复数据， 因此这种情况下读出信号 read— b就无效。 如果计数器的当前值和计 数器目标值之差小于 63时， 意味者 slot— num从 1开始循环一周到再次为 1 的这段时间中， 计数器会计数到目标值， 从而产生本时隙的恢复时钟脉冲， 在这种情况下需要准备恢复数据， 读出信号 read— b有效， 数据恢复模块提前 从下游緩存 RAM— B中读出数据， 锁存到对应时隙编号的锁存器中， 供恢复 时钟脉冲釆样。 数据恢复模块根据时隙号 slot— num和读出信号 read— b有效， 从 RAM— B 中读出对应时隙编号的存储空间的恢复数据， 并锁存到对应时隙编号的锁存 器中， 供恢复时钟脉冲釆样。 这样本路 E1信号 (本路时隙）的时钟和数据就全部恢复出来了。 其他时 隙的恢复过程也完全类似。
如图 13所示， 釆用上述应用示例中的装置， 还提供了一种 SDH中支路 信号的时钟数据恢复方法包括以下步骤：
S501 : 上游数据提取模块根据帧头信号 φ、 时钟信号 clock 以及数据信 号 data从 SDH 帧结构每路时隙中提取信号的有效数据， 存入到上游緩存 RAM A各路时隙对应的存储空间中； 上游数据提取电路根据 C1和 C2比特的内容，判断 S1和 S2比特是否是 有效数据。 如果 Sl、 S2比特的位置是有效数据， 也需要提取出来存放在该时 隙的緩存中。 緩存 RAM— A按照 SDH中的 E1的时隙数进行划分， 在 STM-1 中有 63个 E1 , 则将 RAM— A划分成 63个独立部分， 每个 E1时隙的数据存 在各自对应空间。
S502: 比特泄露电路时分复用地产生每路时隙的读指示信号， 根据所述 读指示信号从上游緩存 RAM— A中均匀地读出每路时隙的数据内容， 并写入 到下游緩存 RAM— B各路时隙对应的存储空间中； 具体包括以下步骤： S5021 : 时钟计数器以帧头信号 φ为基准， 对时钟 clock进行计数， 生成 时隙分配器需要的各类计数值； 其中， 时钟计数器 counter— low从 1计数到 75/76; 计数器 counter— middle 和 counter— high用于计数时间片段， 都是从 1计数到 16, counter— middle计数 一个循环时, counter— high才计数一次, counter— middle决定了 counter— low计 数的最大值是 75还是 76。在图 8和图 9中， counter— middle为 1时， counter— low 计数最大值为 75 , 其余情况下 counter— low都是计数到 76。 counter— high决定 是否存在增加泄漏或减少泄漏。在本应用示例中 counter— high为 1时， 时间片 段内才可能有增加泄漏或减少泄漏，在 counter— high为其他值时，只有正常泄 漏， 没有增力口泄漏和减少泄漏。 S5022: 时隙分配器根据上面的时钟计数器的计数值， 生成比特泄漏电路 时分复用的泄露时隙编号信号 leak— slot— num、 正常泄漏时间位置信号 norm_pos , 增加泄漏时间位置信号 add_pos 以及减少泄漏时间位置信号 dec_pos, 其中 , leak— slot— num从 1-63有效；
S5023: 泄漏控制器根据当前泄露时隙编号信号 leak— slot— num、上游緩存 RAM A中当前时隙编号对应的存储空间的緩存深度 depth— a , 以及当前的泄 漏位置信号 norm_pos、 add_pos、 dec_pos, 生成增力口读操作信号 add或减少 读操作信号 dec;
S5024: 读写控制器根据当前泄露时隙编号信号 leak— slot— num、泄露位置 信号 norm_pos、 add_pos、 dec_pos, 以及增力口泄漏 add信号、 减少泄漏 dec 信号， 产生上游緩存 RAM— A的读指示信号 read— a, 从緩存中读出对应各路 时隙的数据内容， 同时将读出的数据写入到下游 RAM— B对应时隙编号的存 储空间中。 S503:偏差值计算单元时分复用地循环计算每路时隙的緩存深度偏差值， 累加所述緩存深度偏差值， 得到每路时隙的溢出标志； 具体包括以下步骤：
S5031 :时隙产生器 4艮据帧头信号 φ和时钟信号 clock不断循环地产生时 隙编号信号 slot num; 对于 E1信号， slot— num从 1到 63不断循环,表示需要恢复的 63路 E1信 号时隙编号。
S5032: 偏差值计算单元根据当前时隙编号信号 slot— num, 从下游緩存 RAM— B获取当前时隙编号对应的存储空间的数据緩存深度 depth— b和当前时 隙编号对应计数器的计数结果 counter, 运算得到该路时隙的緩存深度偏差值 deviation; 例如， 当前时隙编号 slot— num为 1 , 从緩存 RAM— B中得到第 1路时隙 的数据緩存深度 depth— b, 偏差值计算单元将数据緩存深度 depth— b和深度参 考值相减，其差值就是深度偏离计算值 depth— dev的整数部分。 同时将第一路 时隙的计数器 1的当前计数结果 counter作为深度偏离计算值 depth— dev的小 数部分。 偏差值计算单元根据时隙 1的深度偏离计算值和基准时钟标准值计 算出第 1路时隙的緩存偏差值 deviation 计算过程如下： E1信号的标准时钟 是 2.048M,在系统时钟为 155.52M情况下， 系统时钟 155.52M进行如下分频 方式： 在每 1024次的分频中， 76分频为 960次, 75分频为 64次， 按照这种方 式不断地进行循环分频， 则分频出的时钟信号平均频率为 2.048M, 也就是 E1 信 号 的 标 准 时钟 。 设 置 2 进制 的 基 准 时钟 标 准值 base=17'b0— 0010— 0000— 0000— 0000 , 设置 累 加 器 累 加溢 出 门 限是 17'bl— 1111— 1111— 1111— 1111。 对基准时钟标准值不断累加， 累计值超过溢出 门限则溢出，余数继续和基准时钟参考标注值累加。基准时钟标准值在每 1024 次累加中， 会出现 64次溢出。 如果釆样到的数据緩存当前深度 depth是 7位 数据（二进制） ， 则数据緩存深度的中间位置是 7 100— 0000, 将中间位置作 为深度参考值。 如果当前緩存深度釆样值 depth为 7'bOOO— 0000, 表示緩存快 空； 如果当前釆样的緩存深度 depth为 7'bl l l— 1111 , 表示緩存快满。 因此将 当前緩存深度釆样值 depth和中间位置 (深度参考值 )之差就是緩存深度偏离 状态， 将该差值作为深度偏离计算值 depth— dev的整数部分。 计数器 counter 作为深度偏离计算值 depth— dev的小数部分。 深度偏离计算值 depth— dev的整 数部分和深度偏离计算值 depth— dev的小数部分拼接起来（整数部分在前， 小 数部分在后） ， 就是深度偏离计算值 depth— dev, 将 depth— dev加上基准时钟 标准值 base就是緩存深度偏差值 deviation当深度偏离计算值 depth— dev为 0 时， 表示緩存深度没有偏差， 只剩下基准时钟标准值 base。 基准时钟标准值 不断累计的结果就是每 1024次累加中， 会出现 64次溢出， 960次不溢出， 溢出次数和不溢出次数的比例刚好是分频控制要求的次数。 当深度偏离计算 值 depth— dev不等于零的话， 则緩存深度偏差值 deviation就不等于基准时钟 标准值， 意味者数据时钟的频率和标准频率之间有偏差， 深度偏离计算值 depth— dev 的偏差大小反映出时钟频率的偏差大小。 如果深度偏离计算值 depth— dev偏大， 则緩存深度偏差值 deviation大于基准时钟标准值， 则累加溢 出次数就加大， 频率恢复结果就加快， 反之依然。
S5033: 偏差值计算单元根据当前时隙编号信号 slot— num, 从累计值存储 单元当前时隙编号对应的存储空间中获取上次累计值 accumulation,将该路时 隙的緩存深度偏差值 deviation和上次累计值 accumulation进行累加， 得到该 路时隙的累加结果 total;
S5034: 偏差值计算单元根据所述累加结果 total, 判断本次累加是否出现 溢出， 如果有溢出则在当前时隙编号对应的计数器上打上溢出标志， 同时将 本次累加结果的余数保存到累计值存储单元当前时隙编号对应的存储空间 中， 作为下一次运算的累计值 accumulation。 上述的所有计算过程都在一个时钟周期中完成。
S504: 每路时隙的计数器分别根据其溢出标志， 独立地恢复出该路时隙 的时钟信号， 读出信号生成器为每路时隙生成读出信号 read— b; 其中，每路时隙的计数器分别根据其溢出标志恢复出该时隙的时钟信号 , 具体包括以下步骤：
S5041 : 每路时隙的计数器分别以帧头信号为基准，根据时钟信号从零开 始进行加 1计数； S5042: 当所述计数器的溢出标志 ρ有效时， 该计数器计数到标准值 74 时清零， 对于 E1信号来说， 标准值为 74; 当所述计数器的溢出标志 ρ无效 时， 该计数器计数到标准值 74+1 , 即 75时才清零， 然后所述计数器从零重 新开始计数， 在清零的同时清除所述溢出标志 ρ;
S5043: 当所述计数器清零时， 产生一个恢复时钟脉冲。 每一路时隙的计数器都是独立地进行计数， 当计数器每次清零时， 表示 计数器完成一个计数周期， 计数器就输出一个时钟脉冲， 该脉冲就是本时隙 的恢复时钟脉冲。
其中， 读出信号生成器在生成一个所述时隙编号信号 slot— num的同时为 每路时隙生成一个读出信号 read— b; 并判断该读出信号 read— b是否有效， 任 意路时隙的读出信号有效是指： 如果当前时隙编号信号 slot— num在未来一个 循环周期内， 对应时隙编号的计数器会产生恢复时钟脉冲， 则读出信号有效；
S505: 数据恢复模块根据时隙号 slot— num和有效读出信号 read— b, 从 RAM— B中读出对应时隙编号的存储空间的恢复数据，并锁存到对应时隙编号 的锁存器中， 供恢复时钟脉冲釆样。
上述以 E1信号为例的应用示例的方法及装置也同样适用于 T1信号。 对 于 T1信号， 每个 STM-1中 84路 T1信号， 每路 T1的标称频率是 1.5M。 将 图 4和图 5按照 T1的帧结构进行修订就可以适用于 Tl。 对于 STM-1串行数 据流， 数据的时钟信号是 155.52M, —帧时间是 125us, 在一帧时间中时钟有 19440个时钟周期。对于一路 T1信号，在一个 STM-1周期内共有 193比特（正 常情况下只有 1个 S1承载数据时是 193比特； 当 2个 S1都承载时是 194比 特； 当 2个 S1都不承载时是 192比特）。 这样在 19440个时钟周期中， 可以 划分出 53个 100时间片段， 140个 101时间片段， 共 193个时间片段， 如图 7。 前 53个时间片段中 （时间片段 1-53 ) , 每个时间片段有 100个时钟周期， 后 140个时间片段中， 每个时间片段有 101个时钟周期。 在每个时间片段中， 设置 84个正常调整位置（正常调整位置也同时具备减少调整功能）， 设置一 个增加调整位置 (因为只有 84路时隙， 如果一个时间片段中只设置一个增加 调整位置， 在 193个时间片段中只需要 84个时间片段设置就可以， 在本事例 中前 84个时间片段中每个时间片段设置一个增加调整位置）， 其余位置设置 为空闲调整位置。 上述内容仅为本发明实施例的一个应用示例， 在具体实施时不排除其他 方式， 如恢复时隙容量大小， 时间片段的其他划分方式， 时隙编号的其他编 码方式。
从上述实施例可以看出， 相对于相关技术， 上述实施例中提供的 SDH体 系中支路信号的时钟数据恢复方法及装置， 将多路 E1或 T1信号釆用一套时 钟恢复电路， 釆用时分复用的办法， 能同时恢复出多路时钟频率不同的支路 信号的恢复时钟和数据， 大幅度地节约电路资源。
本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序 来指令相关硬件完成， 所述程序可以存储于计算机可读存储介质中， 如只读 存储器、 磁盘或光盘等。 可选地， 上述实施例的全部或部分步骤也可以使用 一个或多个集成电路来实现。 相应地， 上述实施例中的各模块 /单元可以釆用 硬件的形式实现， 也可以釆用软件功能模块的形式实现。 本发明不限制于任 何特定形式的硬件和软件的结合。
以上所述仅为本发明的较佳实施例而已， 并非用于限定本发明的保护范 围。 根据本发明的发明内容， 还可有其他多种实施例， 在不背离本发明精神 改变和变形， 凡在本发明的精神和原则之内， 所作的任何修改、 等同替换、 改进等， 均应包含在本发明的保护范围之内。 14 075586
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工业实用性
本发明实施例提供的 SDH中支路信号的时钟数据恢复方法及装置，将多 路 E1或 T1信号采用一套时钟恢复电路， 采用时分复用的办法， 能同时恢复 出多路支路信号的恢复时钟和数据， 大幅度地节约电路资源。

Claims

权 利 要 求 书
1、 一种 SDH中支路信号的时钟数据恢复方法， 包括： 从同步数字体系 SDH帧结构每路时隙中提取信号的有效数据，存入緩存 中各路时隙对应的存储空间中； 时分复用地恢复出每路时隙的时钟信号和读出信号； 以及 当任意路时隙的读出信号有效时， 从所述緩存中的所述路时隙对应的存 储空间读出数据内容， 并锁存到对应时隙的锁存器中。
2、 如权利要求 1所述的方法， 其中： 所述緩存包括上游緩存和下游緩存； 所述从 SDH帧结构每路时隙中提取信号的有效数据，存入緩存中各路时 隙对应的存储空间中， 包括： 从所述 SDH帧结构每路时隙中提取信号的有效数据，先存入到所述上游 緩存中各路时隙对应的存储空间中； 以及 时分复用地产生每路时隙的读指示信号， 根据所述读指示信号从上游緩 存中均匀地读出每路时隙的数据内容， 并写入到下游緩存中各路时隙对应的 存储空间中。
3、 如权利要求 2所述的方法， 其中： 所述时分复用地产生每路时隙的读指示信号， 根据所述读指示信号从上 游緩存中均匀地读出每路时隙的数据内容， 包括： 将一个 SDH帧包含的时钟周期划分为 M个时间片段， M为正整数， 每 路时隙的比特数为 M-1、 M或 M+1 , 在每个时间片段时分复用地产生各路时 隙的读指示信号， 每产生一次读指示信号读出相应时隙的一比特数据； 对比特数为 M的每一路时隙， 在 M个时间片段的每一时间片段产生一 次正常泄漏的读指示信号， 读出一比特的数据； 对比特数为 M-1的每一路时隙，在 M-1个时间片段的每一时间片段产生 一次正常泄漏的读指示信号， 读出一比特的数据； 以及 对比特数为 M+l的每一路时隙， 在 M个时间片段的每一时间片段产生 一次正常泄漏的读指示信号， 在其中的一个时间片段产生一次增加泄漏的读 指示信号，且预先划分 SDH帧中各路时隙可产生增加泄漏的读指示信号的时 间片段， 保证各时间片段包含的时钟周期数总是不小于可能产生的最大读指 示信号数。
4、 如权利要求 2所述的方法， 其中： 所述时分复用地恢复出每路时隙的时钟信号， 包括： 时分复用地循环计算每路时隙的緩存深度偏差值， 累加所述緩存深度偏 差值， 得到每路时隙的溢出标志； 以及 每路时隙分别根据每路时隙的溢出标志， 独立地恢复出所述路时隙的时 钟信号。
5、 如权利要求 4所述的方法， 其中： 所述时分复用地循环计算每路时隙的緩存深度偏差值， 累加所述緩存深 度偏差值得到每路时隙的溢出标志， 包括： 根据帧头信号和时钟信号生成时隙编号信号 slot— num, 所述时隙编号信 号 slot— num从 1到 n不断循环 , n为正整数， 由所述 SDH帧结构的时隙数确 定； 以及 根据当前时隙编号信号 slot— num计算当前一路时隙的緩存深度偏差值， 累加所述緩存深度偏差值，如果累加有溢出则生成当前一路时隙的溢出标志。
6、 如权利要求 5所述的方法， 其中： 每路时隙分别根据每路时隙的溢出标志， 独立地恢复出所述路时隙的时 钟信号， 包括： 每路时隙设置一个计数器， 当所述计数器清零时， 产生一个时钟脉冲； 以及 当所述计数器的溢出标志有效时， 所述计数器计数到标准值时清零， 当 所述计数器的溢出标志无效时， 所述计数器计数到标准值 +1时清零， 然后所 述计数器从零重新开始计数，所述标准值由 SDH帧结构的时钟信号频率和每 路信号的标称频率确定。
7、 如权利要求 6所述的方法， 其中： 所述时分复用地恢复出每路时隙的读出信号， 包括： 在生成一个所述时隙编号信号 slot— num的同时为每路时隙生成一个读出 信号； 以及 所述任意路时隙的读出信号有效包括： 如果当前时隙编号信号 slot— num 在未来一个循环周期内， 当前一路时隙的计数器会产生时钟脉冲， 则读出信 号有效。
8、 一种 SDH中支路信号的时钟数据恢复装置， 包括： 数据提取模块，其设置成从同步数字体系 SDH帧结构每路时隙中提取信 号的有效数据， 存入緩存中各路时隙对应的存储空间中； 时钟恢复电路， 其设置成时分复用地恢复出每路时隙的时钟信号和读出 信号， 并将所述时钟信号和读出信号发送至数据恢复模块； 以及 数据恢复模块， 其设置成接收所述时钟信号和读出信号， 并且当任意路 时隙的读出信号有效时， 从所述緩存中的所述路时隙对应的存储空间读出数 据内容， 并锁存到对应时隙的锁存器中。
9、 如权利要求 8所述的装置， 其中： 所述緩存包括上游緩存和下游緩存； 所述数据提取模块包括： 上游数据提取电路，其设置成从所述 SDH帧结构每路时隙中提取信号的 有效数据， 先存入到所述上游緩存中各路时隙对应的存储空间中； 以及 比特泄露电路， 其设置成时分复用地产生每路时隙的读指示信号， 根据 所述读指示信号从上游緩存中均勾地读出每路时隙的数据内容， 并写入到下 游緩存中各路时隙对应的存储空间中。
10、 如权利要求 9所述的装置， 其中： 所述比特泄露电路通过如下方式时分复用地产生每路时隙的读指示信 号， 根据所述读指示信号从上游緩存中均匀地读出每路时隙的数据内容： 将一个 SDH帧包含的时钟周期划分为 M个时间片段， M为正整数， 每 路时隙的比特数为 M-1、 M或 M+1 , 在每个时间片段时分复用地产生各路时 隙的读指示信号， 每产生一次读指示信号读出相应时隙的一比特数据； 对比特数为 M的每一路时隙， 在 M个时间片段的每一时间片段产生一 次正常泄漏的读指示信号， 读出一比特的数据； 对比特数为 M-1的每一路时隙，在 M-1个时间片段的每一时间片段产生 一次正常泄漏的读指示信号， 读出一比特的数据； 以及 对比特数为 M+1的每一路时隙， 在 M个时间片段的每一时间片段产生 一次正常泄漏的读指示信号， 在其中的一个时间片段产生一次增加泄漏的读 指示信号，且预先划分 SDH帧中各路时隙可产生增加泄漏的读指示信号的时 间片段， 保证各时间片段包含的时钟周期数总是不小于可能产生的最大读指 示信号数。
11、 如权利要求 10所述的装置， 其中： 所述比特泄露电路还包括： 一个或多个时钟计数器， 所述时钟计数器设置成以帧头信号为基准对时 钟进行计数； 时隙分配器， 其设置成根据所述时钟计数器的输出结果， 确定每个时间 片段中正常泄漏、 增加泄漏或者减少泄漏的泄露位置以及当前泄露的时隙编 号； 以及 读写控制器， 其设置成根据每个时间片段中正常泄漏、 增加泄漏或者减 少泄漏的泄露位置以及当前泄露的时隙编号， 在每个时间片段内， 根据当前 泄露的时隙编号从上游緩存对应时隙编号的存储空间中正常泄露一次数据或 者增加一次泄露数据或者减少一次泄露数据到下游緩存对应时隙编号的存储 空间中， 其中， 正常泄漏时产生一个读指示信号； 减少泄漏时扣除一个正常 泄漏的读指示信号；增加泄漏时在增加泄漏的泄露位置增加一个读指示信号。
12、 如权利要求 11所述的装置， 其中： 所述比特泄露电路还包括： 泄露控制器， 其设置成根据所述上游緩存对应时隙编号的存储空间的緩 存深度产生增加泄漏信号和减少泄漏信号， 所述增加泄漏信号表示增加一次 泄漏； 所述减少泄漏信号表示减少一次泄漏； 以及 读写控制器， 其设置成根据每个时间片段中正常泄漏、 增加泄漏或者减 少泄漏的泄露位置以及当前泄露的时隙编号、增加泄漏信号和减少泄漏信号， 在每个时间片段内， 根据当前泄露的时隙编号从上游緩存对应时隙编号的存 储空间中根据所述增加泄露信号增加一次泄露数据或者根据所述减少泄露信 号减少一次泄露数据到下游緩存对应时隙编号的存储空间中， 其中， 减少泄 漏时扣除一个正常泄漏的读指示信号； 增加泄漏时在增加泄漏位置增加一个 读指示信号。
13、 如权利要求 9所述的装置， 其中： 所述时钟恢复电路包括： 偏差值计算单元和为每路时隙设置的一个计数 器， 所述计数器包括一个溢出标志； 所述偏差值计算单元设置成时分复用地循环计算每路时隙的緩存深度偏 差值， 累加所述緩存深度偏差值， 得到每路时隙的溢出标志； 以及 每路时隙的计数器设置成根据所述溢出标志恢复出所述路时隙的时钟信 号。
14、 如权利要求 13所述的装置， 其中： 所述时钟恢复电路还包括： 累计值存储单元， 其设置成将每路时隙所述偏差值计算单元输出的上次 累计值保存到各路时隙对应的存储空间中； 时隙生成器， 其设置成根据帧头信号和时钟信号， 生成时隙编号信号 slot num, 所述时隙编号信号 slot— num从 1到 n不断循环， n为正整数， 由所 述 SDH帧结构的时隙数确定； 所述偏差值计算单元通过如下方式时分复用地循环计算每路时隙的緩存 深度偏差值， 累加所述緩存深度偏差值， 得到每路时隙的溢出标志： 所述偏差值计算单元根据当前时隙编号信号 slot— num, 从下游緩存获取 当前时隙编号对应的存储空间的数据緩存深度和当前时隙编号对应计数器的 计数结果， 运算得到所述路时隙的緩存深度偏差值； 根据当前时隙编号信号 slot— num, 从所述累计值存储单元当前时隙编号 对应的存储空间中获取上次累计值， 将所述路时隙的緩存深度偏差值和所述 上次累计值进行累加， 得到所述路时隙的累加结果； 以及 根据所述累加结果判断本次累加是否出现溢出， 如果有溢出则在当前时 隙编号对应的计数器上打上溢出标志， 同时将本次累加结果的余数保存到所 述累计值存储单元当前时隙编号对应的存储空间中， 作为下一次运算的累计 值。
15、 如权利要求 13所述的装置， 其中： 每路时隙的计数器通过如下方式根据所述溢出标志恢复出所述路时隙的 时钟信号： 所述每路时隙的计数器分别以帧头信号为基准， 根据时钟信号从零开始 进行力口 1计数； 当所述计数器的溢出标志有效时， 所述计数器计数到标准值时清零， 当 所述计数器的溢出标志无效时， 所述计数器计数到标准值 +1时清零， 然后所 述计数器从零重新开始计数， 在清零的同时清除所述溢出标志； 所述标准值 由 SDH帧结构的时钟信号频率和每路信号的标称频率确定； 以及 当所述计数器清零时， 产生一个时钟脉冲。
16、 如权利要求 14所述的装置， 其中： 所述时钟恢复电路还包括： 读出信号生成器， 其设置成在生成一个所述时隙编号信号 slot— num的同 时为每路时隙生成一个读出信号； 所述数据恢复模块， 还包括： 为每路时隙设置的锁存器， 其设置成保存 从下游緩存中读出的对应时隙编号的存储空间中的数据内容； 所述锁存器按 照时隙编号进行编号； 以及 所述数据恢复模块通过如下方式当任意路时隙的读出信号有效时， 从所 述緩存中的所述路时隙对应的存储空间读出数据内容， 并锁存到对应时隙的 锁存器中： 当任意路时隙的读出信号有效时， 根据当前时隙编号信号 slot— num和读 出信号从下游緩存中读出对应时隙编号的存储空间中的数据内容， 并锁存到 对应时隙编号的锁存器中； 其中， 所述任意路时隙的读出信号有效包括： 如 果当前时隙编号信号 slot— num在未来一个循环周期内， 当前一路时隙的的计 数器会产生时钟脉冲， 则读出信号有效。
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