WO2014194199A1 - Procédés d'intégration de nitrure de manganèse - Google Patents

Procédés d'intégration de nitrure de manganèse Download PDF

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Publication number
WO2014194199A1
WO2014194199A1 PCT/US2014/040239 US2014040239W WO2014194199A1 WO 2014194199 A1 WO2014194199 A1 WO 2014194199A1 US 2014040239 W US2014040239 W US 2014040239W WO 2014194199 A1 WO2014194199 A1 WO 2014194199A1
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Prior art keywords
layer
depositing
film
deposition
manganese nitride
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PCT/US2014/040239
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English (en)
Inventor
Paul F. Ma
Jennifer Meng TSENG
Mei Chang
Annamalai Lakshmanan
Jing Tang
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Applied Materials, Inc.
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Priority claimed from US13/905,932 external-priority patent/US9076661B2/en
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Publication of WO2014194199A1 publication Critical patent/WO2014194199A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments of the present invention relate generally to barrier layers in semiconductor devices, and their integration into semiconductor devices. More particularly, embodiments of the invention relate to films comprising manganese nitride integration.
  • Microelectronic devices such as semiconductors or integrated circuits, can include millions of electronic circuit devices such as transistors, capacitors, etc.
  • electronic circuit devices such as transistors, capacitors, etc.
  • the size of conductive lines, vias, and interconnects, gates, etc. must be reduced.
  • Reliable formation of multilevel interconnect structures is also necessary to increase circuit density and quality.
  • Advances in fabrication techniques have enabled use of copper for conductive lines, interconnects, vias, and other structures.
  • electromigration in interconnect structures becomes a greater hurdle to overcome, with decreased feature size and the increased use of copper for interconnections.
  • Tantalum nitride is a copper barrier at film thicknesses greater than 10A, where the film is continuous.
  • TaN is a copper barrier at film thicknesses greater than 10A, where the film is continuous.
  • TaN films around 5 A thick are not continuous.
  • TaN by itself may be a discontinuous film, thus limiting its copper barrier properties.
  • Current methods include a Ta layer on top of a TaN layer, which acts as a wetting layer for copper and provides the continuity of a barrier film. For smaller nodes (less than 32 nm), however, this method leads to larger line resistance and hence is not an adequate solution.
  • PVD tantalum nitride is a standard material for diffusion barriers in copper interconnections. Due to poor adhesion of copper to the TaN, a tantalum liner is also used to enhance the durability of the interconnect structures. As the dimension of copper interconnections are being reduced to sub-20 nm, the non-conformal nature of PVD TaN barrier plus Ta liner has caused issues, such as copper gap fill voiding and high line resistance.
  • Atomic layer deposition (ALD) TaN is being used as an advanced technology with better conformality; however, the film quality of ALD TaN still needs significant improvements.
  • One aspect of the invention pertains to a method of forming a semiconductor device, the method comprising: depositing a film comprising manganese nitride over a dielectric; depositing a copper seed layer over the film; and depositing a copper fill layer over the copper seed layer.
  • Various embodiments are listed below. It will be understood that the embodiments listed below may be combined not only as listed below, but in other suitable combinations in accordance with the scope of the invention.
  • the dielectric is a low-k dielectric.
  • the method further comprises depositing a pore sealant over the dielectric prior to depositing the film comprising manganese nitride.
  • depositing a copper seed layer comprises chemical vapor deposition, atomic layer deposition, physical vapor deposition or electrochemical deposition.
  • the manganese nitride is deposited by atomic layer deposition.
  • the method further comprises treating the manganese nitride film with an ammonia plasma post treatment.
  • the manganese nitride and copper seed layer are deposited in the same chamber.
  • the manganese nitride has a formula of Mn 3 N 2 .
  • a second aspect of the invention pertains to a method of forming a semiconductor device, the method comprising: depositing a film comprising manganese nitride over a dielectric; depositing a film comprising cobalt or ruthenium over the film comprising manganese nitride or doping the manganese nitride layer with cobalt or ruthenium; depositing a copper seed layer; and depositing a copper fill layer over the copper seed layer.
  • the dielectric is a low-k dielectric.
  • the method further comprises depositing a pore sealant over the low-k dielectric prior to depositing the film comprising manganese nitride.
  • depositing a copper seed layer comprises chemical vapor deposition, atomic layer deposition, physical vapor deposition or electrochemical deposition.
  • the manganese nitride is deposited by atomic layer deposition.
  • the method further comprises treating the manganese nitride film with a ammonia plasma post treatment.
  • the manganese nitride and copper seed layer are deposited in the same chamber.
  • depositing the manganese nitride and depositing the film comprising cobalt or ruthenium occurs without a vacuum break.
  • the manganese nitride has a formula of ⁇ 3 ⁇ 2 .
  • Yet another aspect of the invention pertains to a semiconductor device comprising: a low-k dielectric layer; a manganese nitride layer overlying the low-k dielectric layer; a seed layer selected from a copper seed layer or electrochemical deposition seed layer overlying the manganese nitride layer; a copper layer overlying the copper seed layer.
  • the semiconductor device further comprises a cobalt- or ruthenium-containing layer overlying the manganese nitride layer but under the seed layer.
  • the seed layer comprises a copper seed layer.
  • FIGS. 1A and IB illustrate a dielectric layer before and after deposition of a barrier layer and conductive fill material in accordance with one or more embodiments of the invention.
  • FIG. 2 illustrates a semiconductor dev ice in accordance with one or more embodiments of the invention.
  • Embodiments of the invention relate to the integration of films comprising manganese nitride for back end of the line interconnects. Such films may be useful as a copper barrier and/or copper wetting material during the fabrication of semiconductor devices.
  • one aspect of the invention pertains to method of forming a semiconductor device, the method comprising: depositing a film comprising manganese nitride over a dielectric; depositing a copper seed layer over the film; and depositing a copper fill layer over the copper seed layer.
  • a dielectric material comprising manganese nitride is deposited over a dielectric material.
  • the dielectric layer may be provided using methods known in the art.
  • the dielectric layer may overly other layers, as the situation calls for.
  • the dielectric may comprise a low-k dielectric.
  • low-k dielectric refers a dielectric material having a k value of less than about 4.
  • the dielectric may be porous.
  • the method may further comprise depositing a pore sealant over the dielectric prior to depositing the film comprising manganese nitride.
  • manganese nitride may be referred to as "MnN x .”
  • Deposition of a film comprising manganese nitride may be carried out by any suitable method.
  • the deposition methods can be atomic layer deposition (ALD) or chemical vapor deposition (CVD).
  • the amount of manganese to nitride may be expressed as a ratio.
  • the atomic ratio of Mn:N ranges from about 90: 10 to about 20:80.
  • suitable manganese nitride film phases include, but are not limited to Mn 4 N, Mn 3 N 2 , Mn 6 N5.
  • the Mn:N ratio is about 60:40 and/or the phase is Mn 3 N 2 .
  • the manganese nitride layer may be formed by any appropriate deposition process.
  • the manganese layer can be deposited by an alternating layer deposition (ALD) process or a plasma enhanced atomic layer deposition (PEALD).
  • the dopant can then be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD) or ALD.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • the dopant is then diffused into the manganese-containing layer to form an integrated manganese-containing dopant layer.
  • the dopant may be diffused into the manganese- containing layer through various processes, including by plasma treatment and by heating.
  • MnN x is deposited using an organometallic precursor.
  • the precursor of some embodiments can generate a high purity manganese film by CVD and high purity MnN x films by ALD with smooth morphology.
  • the organometallic precursor may include a manganese silyl amido complex.
  • ALD of ⁇ from trimethyl silyl amido manganese complexes of some embodiments has been performed on standard ALD chambers.
  • the substrate is exposed to a first precursor and a reactant.
  • the exposure to these precursors can be substantially simultaneously, as in a CVD reaction, or sequentially, as in an ALD reaction.
  • the manganese nitride is deposited via ALD.
  • substantially simultaneously means that the precursor and reactant gases are flowed into the chamber to react with each other and the substrate surface together. It will be understood by those skilled in the art that there may be areas of the substrate which are briefly exposed to one of the precursor and reactant gas only until the other diffuses to the same area.
  • Each A is independently selected from carbon or silicon and each R is independently selected from hydrogen, methyl, substituted or un- substituted alkanes, branched or un-branched alkanes, substituted or un- substituted alkenes, branched or un-branched alkenes, substituted or un-substituted alkynes, branched or un-branched alkynes or substituted or un-substituted aromatics.
  • the oxidation state of the manganese can be in any suitable oxidation state capable of reacting with the substrate or the reactant. In some embodiments, the manganese is Mn(II) or Mn(III).
  • the deposition of the manganese-containing film can be performed on a bare substrate surface or on a film already present on the substrate surface.
  • the manganese-containing film can be deposited on a dielectric film present on the surface.
  • the dielectric film can have various structures (e.g., trenches) formed therein which have tops, bottoms and sidewalls.
  • the bottom can be either the dielectric or a surface under the dielectric (e.g., bare substrate or another material).
  • the deposition of the manganese- containing film can be selective for the difference surfaces.
  • the deposition of the manganese-containing film is selective for the dielectric layer or the underlying layer.
  • each A is a nitrogen atom.
  • each R group is a methyl.
  • the manganese-containing organometallic compound comprises manganese bis[bis(trimethylsilyl)amide].
  • the reactant is one or more of ammonia. Without being bound by any particular theory of operation, it is believed that the Mn-N bonds are broken during film formation. Therefore, as an example, if ammonia is used, a manganese nitride film can be formed.
  • the dielectric may be porous and may require a pore sealant.
  • suitable methods include ALD of Si0 2 and exposure to an N 2 0 plasma.
  • the copper seed layer may be deposited over the film comprising manganese nitride using methods known in the art. Such methods include, but are not limited to chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) and/or electrochemical deposition (ECD).
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • ECD electrochemical deposition
  • the manganese nitride and copper seed layer are deposited in the same chamber. In further embodiments, such chambers would contain at least two ampoules for the various chemicals needed during deposition. In alternative embodiments, the manganese nitride and copper seed layer are deposited in different chambers. In one or more embodiments, deposition of the manganese nitride and the film comprising cobalt or ruthenium occurs without a vacuum break. [0030] Following deposition of the copper seed layer, a copper fill layer is deposited over the copper seed layer. This can be carried out via methods known in the art, including, but not limited to, chemical vapor deposition and physical vapor deposition.
  • the methods described herein further comprise treating a manganese nitride film with an ammonia (NH 3 ) plasma post treatment.
  • NH 3 ammonia
  • the surface of the substrate may need to be polished.
  • Post treatment with a plasma comprising ammonia helps to prevent degradation during chemical mechanical polishing techniques.
  • the Mn:N ratio is modulated towards a nitrogen-rich ratio. Increase of the nitrogen content in the MnN helps to prevent CMP corrosion.
  • Suitable conditions for the ammonia plasma treatment may be selected for the particular films, precursors, etc. used. Suitable temperatures during exposure to the plasma will generally range from about 150°C to about 300 °C.
  • Pressures will generally range from about 0.5 Torr to 10 Torr. Spacing will generally range form about lOOmils to about 500mils.
  • RF Power at 40MHz will generally range from about 100W to about 1000W.
  • the NH 3 flow rate generally will range from about 500 to about 5000 seem.
  • a noble gas plasma may also be used in the process. For example, argon may be flowed at a rate of about 500 to about 5,000 seem.
  • the methods described herein further comprise depositing a film comprising cobalt or ruthenium over the film comprising manganese nitride. This can be accomplished by methods known in the art.
  • the cobalt or ruthenium may not be a separate and distinct layer, but a dopant in the manganese nitride film.
  • the barrier layer comprises manganese nitride and a dopant selected from Mn, Co, Ru, Ta, Al, Mg, Cr, Nb, Ti and V.
  • the manganese and the dopant can be deposited in alternating layers.
  • a first manganese-containing layer such as a manganese monolayer, is deposited on a dielectric film.
  • the underlying layer can be any suitable layer including, but not limited to, a metal layer or a base substrate.
  • a first dopant layer such as a layer of dopant, dopant alloy or other dopant-containing compound, may then be deposited on top of the first manganese- containing layer. This first dopant layer can also be a monolayer.
  • a second manganese- containing layer is then deposited on top of the first dopant layer. This process is repeated until a doped manganese-containing film of the desired thickness is produced.
  • the ratio of manganese-containing layers to dopant layers can be any suitable combination and is not limited to 1: 1. For example, there can be ten manganese-containing layers deposited for every one dopant layer.
  • a manganese- containing precursor and a cobalt precursor can be flowed into the chamber together to react with the surface.
  • the reactant employed can be specific for one of the precursor species or common to both species.
  • the substrate or surface is exposed to a first precursor followed by a first reactant and to a second precursor different from the first precursor followed by either the first reactant or by a second reactant different from the first reactant.
  • an appropriate metal-containing precursor may be used for depositing the dopant metal.
  • suitable precursors include metal complexes containing the desired dopant, such as dopant metals coordinated with organic or carbonyl ligands.
  • a suitable dopant precursor should have sufficient vapor pressure to be deposited in the appropriate process, such as ALD, CVD and PVD.
  • a co-reactant may be used to deposit the dopant.
  • reducing gases such as hydrogen and ammonia can be used as co-reactants for depositing some dopants.
  • the doped manganese-containing film is treated with a plasma prior to depositing the conductive material.
  • the plasma comprises one or more of He, Ar, NH 3 , H 2 and N 2 .
  • the conductive material may be deposited in a variety of ways, including by an electroless deposition process, an electroplating (ECP) process, a CVD process or a PVD process.
  • ECP electroplating
  • a first seed layer is deposited upon the barrier layer, and a bulk conductive layer is then formed upon the seed layer.
  • the barrier layer comprises 0.1 to 10 % dopant, based on the weight of the manganese layer.
  • the barrier layer comprises 0.2 to 8 wt. % dopant.
  • the barrier layer comprises 0.5 to 5 wt. % dopant.
  • Another aspect of the invention pertains to the semiconductor devices produced by one or more of the methods described herein.
  • the device will depend on how the method employed. For example, where the method comprises depositing a film comprising manganese nitride over a dielectric; depositing a copper seed layer over the film; and depositing a copper fill layer over the copper seed layer, the semiconductor device will comprise a copper fill layer over a copper seed layer over a film comprising manganese nitride layer overlaying a dielectric.
  • the semiconductor device comprises a low-k dielectric layer; a manganese nitride layer overlying the low-k dielectric layer; a seed layer selected from a copper seed layer or electrochemical deposition seed layer overlying the manganese nitride layer; and a copper layer overlying the copper seed layer.
  • the semiconductor device will further comprise a cobalt- or ruthenium-containing layer overlying the manganese nitride layer but under the seed layer.
  • the semiconductor device will further comprise a copper seed layer.
  • the seed layer comprises an electrochemical deposition seed layer.
  • the semiconductor device further comprises a pore sealant overlying the low-k dielectric layer but under the manganese nitride layer.
  • the method may comprise manganese nitride deposition, followed by ammonia post treatment, copper seed deposition, followed by conventional copper plating.
  • the method may comprise deposition of manganese nitride, cobalt or ruthenium deposition or doping, followed by electrochemical seed deposition, followed by electrochemical plating.
  • the method comprises manganese nitride deposition, followed by deposition or doping of cobalt or ruthenium, followed by copper seed and electrochemical plating.
  • the method may comprise manganese nitride deposition, followed by cobalt or ruthenium deposition or doping, followed by copper seed and electrochemical chemical deposition seed, and then electrochemical plating. Any of the above could be preceded by pore sealing of a porous dielectric. Certain parts of the method (e.g. , electrochemical plating and electrochemical deposition) may take place after vacuum break.
  • FIG. 1A depicts an embodiment of a microelectronic device 100 comprising a substrate 105 and a dielectric layer 110.
  • the dielectric layer 110 is disposed upon the substrate 105, and the dielectric layer 110 has a trench 150 defined by a trench bottom 120, sidewalls 115, and opening 160.
  • the dielectric layer 110 is a low-k dielectric layer.
  • the dielectric layer comprises SiO x .
  • the dielectric layer comprises porous carbon-doped SiO x .
  • the dielectric layer is a porous carbon-doped SiO x layer with a k value less than 3.
  • FIG. IB shows the same microelectronic device 100 after deposition of a barrier layer 130, which covers at least a portion of the sidewall 115 and/or trench bottom 120.
  • the barrier layer 130 may cover the entirety of the sidewall 115 and trench bottom 120.
  • the barrier layer 130 may comprise MnN x and one or more dopants such as Co, M n, Ru, Ta, Al, Mg, Cr, Nb, Ti or V.
  • the barrier layer comprises 0.1 to 10 % dopant, based on the weight of the manganese layer. In some embodiments, the barrier layer comprises 0.2 to 8 wt. % dopant. In particular embodiments, the barrier layer comprises 0.5 to 5 wt. % dopant.
  • barrier layer refers to a discrete layer formed by depositing TaN and one or more dopants, and excludes a region in which a second element or dopant diffuses into only a portion of the barrier layer. In other words, the dopant is present throughout the entire thickness of the TaN layer, and not only at a surface portion thereof.
  • a conductive fill material 140 fills at least a portion of the trench 150 lined with barrier layer 130.
  • the conductive fill material comprises copper or a copper alloy.
  • the conductive fill material further comprises Al.
  • the microelectronic device further comprises an adhesion layer comprising one or more of Ru and Co, Mn.
  • the adhesion layer may comprise one or more dopants such as Ta, Al, Mg, Cr, Nb, Ti or V.
  • the adhesion layer comprises Ru and Mn.
  • manganese and manganese nitride can be used as liners. For example, when PVD Cu is replaced by CVD Cu, manganese nitride may be a promising liner. Also, manganese nitride can be reduced to Mn to act as a liner to promote the adhesion with Cu.
  • a seeding layer is deposited on top of the barrier layer.
  • the seeding layer comprises an alloy of copper, such as a Cu-Mn alloy.
  • the seeding layer comprises less than about 5 wt. % Mn, less than about 4 wt. % Mn, less than about 3 wt. % Mn, or less than about 2 wt. % Mn.
  • the seeding layer comprises about 1 wt. % Mn.
  • the line resistance of copper alloys containing 1 wt. % Mn is expected to be the same as or similar to the line resistance of pure copper.
  • the dopant can selectively diffuse through the barrier layer 130 to the dielectric layer 110 and form a complex with the dielectric material that will be resistant to electromigration.
  • the Mn can diffuse through the barrier layer and form MnSiO x .
  • This self- forming barrier layer of MnSiO x can then prevent copper electromigration from the conductive material 140 to the dielectric layer 110.
  • doped manganese may also be a barrier to oxygen diffusing from the dielectric layer 110 to the conductive material 140.
  • Oxygen diffusion from the dielectric layer 110 to the conductive material 140 can result in oxygen reacting with components in the conductive material and/or seed layer. For example, oxygen can react with the layer at the interface of the barrier layer 130 and the conductive material 140, thus "pinning" the Mn to the barrier layer/conductive material interface. Similarly, if a seed layer comprising Mn is present, then oxygen can react with the Mn in the seed layer at the seed layer/barrier layer interface and pin the Mn to the interface.
  • FIG. 2 is another illustration that shows a device according to one or more embodiments of the invention.
  • FIG. 2 shows low-k dielectric 200, which has several features (i.e., Damascene patterning). As mentioned above, such low-k dielectrics may be porous. As a result, deposited over low-k dielectric 200 can be pore sealant 210. Overlying pore sealant 210 is manganese nitride film 220. This manganese nitride film 220 can be any of the ones described herein. A copper seed layer 230 may be deposited over manganese nitride film 220. Following this, copper fill 240 may be deposited, for example, via a chemical vapor deposition process.
  • the methods described herein may, in one or more embodiments, be followed with chemical mechanical polishing of the deposited copper.
  • the deposited manganese or MnN x film can be used as an alternative diffusion barrier in the back-end-of-line copper interconnections to replace currently used PVD TaN or ALD TaN.
  • the deposition approach can be integrated with the ALD TaN deposition to generate manganese doped TaN or tantalum doped with MnN x .
  • TaN and MnN layers can be combined.
  • a “substrate surface,” as used herein, refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process.
  • a substrate surface on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application.
  • Barrier layers, metals or metal nitrides on a substrate surface include titanium, titanium nitride, tungsten nitride, tantalum and tantalum nitride, aluminum, copper, or any other conductor or conductive or non-conductive barrier layer useful for device fabrication.
  • Substrates may have various dimensions, such as 200 mm or 300 mm diameter wafers, as well as, rectangular or square panes.
  • Substrates on which embodiments of the invention may be useful include, but are not limited to semiconductor wafers, such as crystalline silicon (e.g., Si ⁇ 100> or Si ⁇ l l l>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, III-V materials such as GaAs, GaN, InP, etc. and patterned or non-patterned wafers.
  • Substrates may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal and/or bake the substrate surface.
  • a processing chamber is configured to expose the substrate to a sequence of gases and/or plasmas during the vapor deposition process.
  • the processing chamber would include separate supplies of reactants, along with any supply of carrier, purge and inert gases such as argon and nitrogen in fluid communication with gas inlets for each of the reactants and gases.
  • Each inlet may be controlled by an appropriate flow controller such as a mass flow controller or volume flow controller in communication with a central processing unit (CPU) that allows flow of each of the reactants to the substrate to perform a deposition process as described herein.
  • CPU central processing unit
  • the central processing unit may be one of any forms of a computer processor that can be used in an industrial setting for controlling various chambers and sub-processors.
  • the CPU can be coupled to a memory and may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), flash memory, compact disc, floppy disk, hard disk, or any other form of local or remote digital storage.
  • Support circuits can be coupled to the CPU to support the CPU in a conventional manner. These circuits include cache, power supplies, clock circuits, input/output circuitry, subsystems, and the like.
  • Temporal ALD also referred to as time-domain ALD
  • time-domain ALD is a traditional process in which the first precursor flows into the chamber to react (e.g., chemisorption) with the surface. The first precursor is purged from the chamber before flowing the reactant into the chamber.
  • spatial ALD both the first precursor and reactant gases are simultaneously flowed to the chamber but are separated spatially so that there is a region between the flows that prevents mixing of the precursors.
  • a gas curtain e.g., purge gases, vacuum ports or combinations thereof
  • the substrate can be processed in single substrate deposition chambers, where a single substrate is loaded, processed and unloaded before another substrate is processed.
  • the substrate can also be processed in a continuous manner, like a conveyer system, in which multiple substrate are individually loaded into a first part of the chamber, move through the chamber and are unloaded from a second part of the chamber.
  • the shape of the chamber and associated conveyer system can form a straight path or curved path.
  • the processing chamber may be a carousel in which multiple substrates are moved about a central axis and exposed to the deposition gases at different positions.
  • the co-reactants are typically in vapor or gas form.
  • the reactants may be delivered with a carrier gas.
  • a carrier gas, a purge gas, a deposition gas, or other process gas may contain nitrogen, hydrogen, argon, neon, helium, or combinations thereof.
  • the various plasmas described herein, such as the nitrogen plasma or the inert gas plasma, may be ignited from and/or contain a plasma co-reactant gas.
  • the various gases for the process may be pulsed into an inlet, through a gas channel, from various holes or outlets, and into a central channel.
  • the deposition gases may be sequentially pulsed to and through a showerhead.
  • the gases can flow simultaneously through gas supply nozzle or head and the substrate and/or the gas supply head can be moved so that the substrate is sequentially exposed to the gases.
  • the apparatus comprises a deposition chamber for deposition of a film on a substrate.
  • the chamber comprises a process area for supporting a substrate.
  • the apparatus includes a precursor inlet in fluid communication with a supply of a manganese precursor, such as manganese [bis(bis(trimethylsilyl)amide].
  • the apparatus also includes a reactant gas inlet in fluid communication with a supply of nitrogen-containing precursor, such as ammonia.
  • the apparatus also includes a reactant gas inlet in fluid communication with a supply of dopant precursor, such as a dopant-containing metal complex.
  • the apparatus further includes a purge gas inlet in fluid communication with a purge gas.
  • the apparatus can further include a vacuum port for removing gas from the deposition chamber.
  • the apparatus can further include an auxiliary gas inlet for supplying one or more auxiliary gases such as inert gases to the deposition chamber.
  • the deposition can further include a means for heating the substrate by radiant and/or resistive heat.
  • a plasma system and processing chambers or systems which may be used during methods described here for depositing or forming the films can be performed on either PRODUCER ® , CENTURA ® , or ENDURA ® systems, all available from Applied Materials, Inc., located in Santa Clara, Calif.
  • a detailed description of an ALD processing chamber may be found in commonly assigned U.S. Pat. Nos. 6,821,563, 6,878,206, 6,916,398, and 7,780,785.
  • one or more layers may be formed during a plasma enhanced atomic layer deposition (PEALD) process.
  • PEALD plasma enhanced atomic layer deposition
  • the use of plasma provides sufficient energy to promote a species into the excited state where surface reactions become favorable and likely.
  • Introducing the plasma into the process can be continuous or pulsed.
  • sequential pulses of precursors (or reactive gases) and plasma are used to process a layer.
  • the reagents may be ionized either locally (i.e., within the processing area) or remotely (i.e., outside the processing area). In some embodiments, remote ionization can occur upstream of the deposition chamber such that ions or other energetic or light emitting species are not in direct contact with the depositing film.
  • the plasma is generated external from the processing chamber, such as by a remote plasma generator system.
  • the plasma may be generated via any suitable plasma generation process or technique known to those skilled in the art.
  • plasma may be generated by one or more of a microwave (MW) frequency generator or a radio frequency (RF) generator.
  • MW microwave
  • RF radio frequency
  • the frequency of the plasma may be tuned depending on the specific reactive species being used. Suitable frequencies include, but are not limited to, 2 MHz, 13.56 MHz, 40 MHz, 60 MHz and 100 MHz.
  • plasmas may be used during the deposition processes disclosed herein, it should be noted that plasmas may not be required. Indeed, other embodiments relate to deposition processes under very mild conditions without a plasma.
  • the substrate is subjected to processing prior to and/or after forming the layer.
  • This processing can be performed in the same chamber or in one or more separate processing chambers.
  • the substrate is moved from the first chamber to a separate, second chamber for further processing.
  • the substrate can be moved directly from the first chamber to the separate processing chamber, or it can be moved from the first chamber to one or more transfer chambers, and then moved to the desired separate processing chamber.
  • the processing apparatus may comprise multiple chambers in communication with a transfer station. An apparatus of this sort may be referred to as a "cluster tool" or "clustered system", and the like.
  • a cluster tool is a modular system comprising multiple chambers which perform various functions including substrate center-finding and orientation, degassing, annealing, deposition and/or etching.
  • a cluster tool includes at least a first chamber and a central transfer chamber.
  • the central transfer chamber may house a robot that can shuttle substrates between and among processing chambers and load lock chambers.
  • the transfer chamber is typically maintained at a vacuum condition and provides an intermediate stage for shuttling substrates from one chamber to another and/or to a load lock chamber positioned at a front end of the cluster tool.
  • processing chambers which may be used include, but are not limited to, cyclical layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etch, pre-clean, chemical clean, thermal treatment such as RTP, plasma nitridation, degas, orientation, hydroxylation and other substrate processes.
  • CLD cyclical layer deposition
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • etch pre-clean
  • thermal treatment such as RTP, plasma nitridation, degas, orientation, hydroxylation and other substrate processes.
  • the substrate is continuously under vacuum or "load lock” conditions, and is not exposed to ambient air when being moved from one chamber to the next.
  • the transfer chambers are thus under vacuum and are "pumped down” under vacuum pressure.
  • Inert gases may be present in the processing chambers or the transfer chambers.
  • an inert gas is used as a purge gas to remove some or all of the reactants after forming the layer on the surface of the substrate.
  • a purge gas is injected at the exit of the deposition chamber to prevent reactants from moving from the deposition chamber to the transfer chamber and/or additional processing chamber. Thus, the flow of inert gas forms a curtain at the exit of the chamber.
  • the substrate can be processed in single substrate deposition chambers, where a single substrate is loaded, processed and unloaded before another substrate is processed.
  • the substrate can also be processed in a continuous manner, like a conveyer system, in which multiple substrate are individually loaded into a first part of the chamber, move through the chamber and are unloaded from a second part of the chamber.
  • the shape of the chamber and associated conveyer system can form a straight path or curved path.
  • the processing chamber may be a carousel in which multiple substrates are moved about a central axis and are exposed to deposition, etch, annealing, cleaning, etc. processes throughout the carousel path.
  • the substrate can be heated or cooled.
  • Such heating or cooling can be accomplished by any suitable means including, but not limited to, changing the temperature of the substrate support and flowing heated or cooled gases to the substrate surface.
  • the substrate support includes a heater/cooler which can be controlled to change the substrate temperature conductively.
  • the gases (either reactive gases or inert gases) being employed are heated or cooled to locally change the substrate temperature.
  • a heater/cooler is positioned within the chamber adjacent the substrate surface to convectively change the substrate temperature.
  • the substrate can also be stationary or rotated during processing.
  • a rotating substrate can be rotated continuously or in discreet steps.
  • a substrate may be rotated throughout the entire process, or the substrate can be rotated by a small amount between exposure to different reactive or purge gases.
  • Rotating the substrate during processing may help produce a more uniform deposition or etch by minimizing the effect of, for example, local variability in gas flow geometries.
  • the substrate In atomic layer deposition type chambers, the substrate can be exposed to the first and second precursors either spatially or temporally separated processes.
  • Temporal ALD is a traditional process in which the first precursor flows into the chamber to react with the surface. The first precursor is purged from the chamber before flowing the second precursor.
  • both the first and second precursors are simultaneously flowed to the chamber but are separated spatially so that there is a region between the flows that prevents mixing of the precursors.
  • the substrate In spatial ALD, the substrate must be moved relative to the gas distribution plate, or vice-versa.

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Abstract

L'invention concerne des procédés pour former un dispositif à semi-conducteur. Certains procédés consistent à déposer sur un diélectrique un film comprenant du nitrure de manganèse ; à déposer une couche d'ensemencement de cuivre sur le film ; et à déposer une couche de remplissage de cuivre sur la couche d'ensemencement de cuivre. Des dispositifs à semi-conducteur sont également décrits. Certains dispositifs à semi-conducteur comprennent une couche diélectrique à faible valeur k ; une couche de nitrure de manganèse recouvrant la couche diélectrique à faible valeur k ; une couche d'ensemencement, choisie entre une couche d'ensemencement de cuivre et une couche d'ensemencement de dépôt électrochimique recouvrant la couche de nitrure de manganèse ; une couche de cuivre recouvrant la couche d'ensemencement de cuivre.
PCT/US2014/040239 2013-05-30 2014-05-30 Procédés d'intégration de nitrure de manganèse WO2014194199A1 (fr)

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