WO2014185254A1 - Method for manufacturing chip resistor - Google Patents

Method for manufacturing chip resistor Download PDF

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Publication number
WO2014185254A1
WO2014185254A1 PCT/JP2014/061704 JP2014061704W WO2014185254A1 WO 2014185254 A1 WO2014185254 A1 WO 2014185254A1 JP 2014061704 W JP2014061704 W JP 2014061704W WO 2014185254 A1 WO2014185254 A1 WO 2014185254A1
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resistor
electrode
masking
forming
overcoat
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PCT/JP2014/061704
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French (fr)
Japanese (ja)
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岡 直人
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コーア株式会社
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C17/00Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/28Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals
    • H01C17/281Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals by thick film techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C17/00Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/22Apparatus or processes specially adapted for manufacturing resistors adapted for trimming
    • H01C17/24Apparatus or processes specially adapted for manufacturing resistors adapted for trimming by removing or adding resistive material

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  • the present invention relates to a method of manufacturing a chip resistor that is surface-mounted on a circuit board by soldering.
  • This type of chip resistor includes an insulating substrate having a rectangular shape in plan view, a pair of electrode portions provided on the insulating substrate at a predetermined interval, and a resistor that bridges the paired electrode portions,
  • the resistor is mainly composed of an insulating protective coat or the like covering the resistor, and a trimming groove for adjusting a resistance value is formed in the resistor.
  • the electrode portion includes a front electrode, a back electrode, and an end face electrode that bridges both electrodes, and a pair of surface electrodes are bridged by a resistor on the surface side of the insulating substrate.
  • an overcoat (protective coat) is formed so as to cover the entire resistor including the trimming groove.
  • the large-sized substrate is primarily divided into strips along the dividing grooves, and a plurality of the strip-shaped substrates are overlapped.
  • the strip-shaped substrate is secondarily formed. Dividing (secondary break processing) into individual chips is obtained.
  • a standardized chip size chip resistor is completed by forming a plating layer on the base electrode layer (surface electrode, back electrode, and end electrode) continuous in a U-shape of a single chip.
  • the sputtered film wraps around the overcoat when stacking a plurality of strip-shaped substrates and forming an end face electrode by sputtering, and such sputtering is performed. Since the dimensions and linearity of the electrodes vary due to the wraparound of the film, there is a problem that the mounting state of the chip resistor mounted on the circuit board cannot be correctly inspected.
  • the masking material is formed on the overcoat in the previous step of forming the end face electrode, and this masking material is removed after the sputtering of the end face electrode. Can be prevented, and the state of the sputter end can be made linear.
  • the overcoat is formed so as to cover the entire resistor including the trimming groove. Therefore, the surface of the overcoat does not become a flat surface but has a recess having the same shape as the trimming groove. For this reason, when the masking material is formed on the entire surface of the overcoat as in the prior art disclosed in Patent Document 1, the masking material enters the concave portion of the overcoat, and the masking material is washed after sputtering of the end face electrodes. In some cases, it becomes difficult to remove the masking material that has entered the recess.
  • the present invention has been made in view of the actual situation of the prior art, and an object of the present invention is to provide a chip resistor manufacturing method capable of reliably preventing spattering of a sputter on a protective coat with a simple manufacturing process. Is to provide.
  • a resistor forming step for forming, a trimming forming step for forming a trimming groove for adjusting a resistance value in the resistor, and a protective coat forming step for forming a protective coat so as to cover the entire resistor after the trimming forming step A masking process for masking the protective coat so as to avoid the trimming groove forming part, and an end face electrode forming process for forming an end face electrode connected to the electrode by a sputtering method on the end face of the insulating substrate; And a masking removal step of removing the masking by washing after the end face electrode forming step.
  • the mask formed on the protective coat may be frame-shaped so as to surround the portion where the trimming groove is formed. Forming masking at a predetermined position of the protective coat formed on the large-sized substrate before the primary division when the trimming groove forming portion is sandwiched between the pair of masking formed on both ends. Is preferable.
  • the manufacturing method of the chip resistor according to the present invention in the pre-process for forming the end face electrode by sputtering, masking is performed on the protective coat so as to avoid the formation site of the trimming groove, and this masking is removed after the sputtering of the end face electrode.
  • the spattering of the sputter on the protective coating can be prevented by masking, and the sputter end state can be made linear.
  • FIG. 2 is a cross-sectional view taken along the line II-II in FIG. It is explanatory drawing which shows the manufacturing process of this chip resistor. It is explanatory drawing which shows the manufacturing process of this chip resistor. It is explanatory drawing which shows the end surface electrode formation process in this manufacturing process. It is explanatory drawing which shows the manufacturing process of the multiple chip resistor which concerns on the example of 2nd Embodiment of this invention.
  • the chip resistor 1 includes a rectangular parallelepiped insulating substrate 2 and longitudinal ends of the surface of the insulating substrate 2 (upper surface in FIG. 2).
  • a pair of front surface electrodes 3 provided, a pair of back surface electrodes 4 provided at both ends in the longitudinal direction of the back surface of the insulating substrate 2 (the lower surface in FIG. 2), and a pair of surface electrodes 3 are overlapped and insulated.
  • FIG. 1 A resistor 5 provided on the surface of the substrate 2, an undercoat 6 covering the resistor 5, an overcoat 7 covering the undercoat 6, and a pair of bridges between the surface electrode 3 and the back electrode 4 It is mainly comprised by the end surface electrode 8, and the plating layer 9 which coat
  • the insulating substrate 2 is made of ceramic or the like, and this insulating substrate 2 is obtained by dividing a large-sized substrate, which will be described later, along a vertical and horizontal dividing groove and taking a large number of them.
  • the front electrode 3 is obtained by screen-printing a silver paste, dried and fired, and the back electrode 4 is also obtained by screen-printing a silver paste, dried and fired.
  • the resistor 5 is a resistor paste such as ruthenium oxide that is screen-printed, dried and fired.
  • a trimming groove 10 is formed in the resistor 5 to adjust the resistance value.
  • the undercoat 6 is obtained by screen-printing and baking a glass paste. The undercoat 6 is formed so as to cover the resistor 5 before the trimming groove 10 is formed.
  • the overcoat 7 is obtained by screen-printing and curing an epoxy resin paste, and this overcoat 7 is formed after the trimming groove 10 is formed in the resistor 5.
  • the end face electrode 8 is formed by sputtering so as to cover the end face of the insulating substrate 2 and the surface electrode 3, and the end face electrode 8 is a sputter containing adhesion chromium (Cr) to the insulating substrate 2 and a barrier layer material. It consists of a membrane.
  • the barrier layer functions as a cushioning material against thermal stress (heat shock), and nickel (Ni) or copper (Cu) is used.
  • the plating layer 9 is formed by electrolytic plating so as to cover the end face electrode 8, and this plating layer 9 is made of tin (Sn) -lead (Pb), lead-free Sn, or the like.
  • an unfired back electrode 4 is formed by screen-printing and drying Ag paste on the back surface of a large substrate 20 on which a large number of insulating substrates 2 are taken.
  • an unfired surface electrode 3 is formed by screen-printing and drying an Ag / Pd paste on the surface of the large substrate 20 (electrode formation step).
  • the large-sized substrate 20 is provided with a primary dividing groove and a secondary dividing groove (both not shown) in advance in a lattice shape, and each of the squares divided by both the dividing grooves is equivalent to one. This is the chip area.
  • a ruthenium oxide resistor paste is screened on the surface of the large substrate 20 as a fourth step.
  • an unfired resistor 5 is formed in each chip region as shown in FIG. 3B (resistor forming step). At that time, both ends in the longitudinal direction of the resistor 5 are overlapped with the surface electrodes 3 provided at both ends in the longitudinal direction of each chip region.
  • the resistor 5 is fired at a high temperature of about 850 ° C. Note that the firing of the third step described above may be omitted, and the front electrode 3, the back electrode 4 and the resistor 5 may be fired simultaneously in this fifth step. In this case, the firing step is reduced to reduce the cost. Is possible.
  • the glass paste is screen-printed on the region covering the resistor 5 and dried in the sixth step, the glass paste is baked at a high temperature of about 600 ° C. in the seventh step, so that FIG. As shown in FIG. 2, an undercoat 6 is formed on the resistor 5.
  • This undercoat 6 is for preventing the vicinity of the trimming groove 10 of the resistor 5 from being damaged by the heat of the laser beam irradiated in the next step.
  • the trimming groove 10 is formed by irradiating the resistor 5 covered with the undercoat 6 with a laser beam (trimming forming step). At that time, probes not shown are brought into contact with the surface electrodes 3 existing on both sides in the longitudinal direction of the resistor 5 to be trimmed, and laser trimming is performed while measuring the resistance value through these probes. When the laser beam irradiation is started and the trimming groove 10 becomes longer, the resistance value increases accordingly. Therefore, when the resistance value of the resistor 5 to be trimmed reaches a desired value, the laser beam irradiation is performed. Turn off.
  • an epoxy resin paste is screen-printed in a region covering the undercoat 6 and then heat-cured at about 200 ° C., so that the resistor 5 is shown in FIG.
  • an overcoat 7 covering the undercoat 6 and the trimming groove 10 is formed (protective coat forming step).
  • the surface of the overcoat 7 after heat curing is not a flat surface, and the trimming groove 10 is located near the center of the overcoat 7.
  • the overcoat 7 is for protecting the resistor 5 from the external environment.
  • a water-soluble epoxy resin is screen-printed in a region avoiding the recess 7a on the overcoat 7 and dried, thereby forming the recess 7a on the overcoat 7 as shown in FIG.
  • a pair of strip-shaped masking materials 11 that are opposed to each other are formed (masking forming step).
  • the end portions on the surface electrode 3 side of these masking materials 11 are parallel to the longitudinal end portions of the overcoat 7, and the masking material 11 is removed in the completed state of the chip resistor 1 as will be described later.
  • the process up to this point is a batch process for the large-sized substrate 20 for taking a large number of pieces, but in the next eleventh step, a primary break process is performed in which the large-sized substrate 20 is divided into strips along the first dividing groove. . Thereby, a strip-shaped substrate 30 provided with a plurality of chip regions is obtained.
  • a plurality of strip-shaped substrates 30 are stacked in the vertical direction, and Cr / Ni is sputtered on the end surfaces of the strip-shaped substrates 30 in this state, as shown in FIG.
  • the end face electrode 8 that bridges the front electrode 3 and the back face electrode 4 is formed (end face electrode forming step).
  • the masking material 11 on the overcoat 7 of the lower strip-shaped substrate 30 is sputtered in a state of being in contact with the lower surface of the upper strip-shaped substrate 30, and a sputtered film is also formed between the strip-shaped substrates 30 overlapping vertically.
  • the end surface electrode 8 is formed from the end surface of the strip-shaped substrate 30 to the end portion of the overcoat 7 and the end portion of the masking material 11 beyond the surface electrode 3.
  • the sputtered film does not reach the recess 7 a beyond the masking material 11.
  • FIG. 5 shows an end face electrode forming process when five strip-shaped substrates 30 are stacked and sputtered, and one of them corresponds to the strip-shaped substrate 30 shown in FIG.
  • a secondary break process is performed in which the strip-shaped substrate 30 is divided along the second divided grooves, and a piece (chip alone) having the same size as the chip resistor 1 is obtained.
  • the masking material 11 formed on the overcoat 7 is removed as shown in FIG. (Masking removal process). At this time, since the masking material 11 does not enter the recess 7a on the overcoat 7, the masking material 11 can be easily cleaned and removed without applying a strong ultrasonic wave for a long time.
  • the plating is performed so as to cover the back surface electrode 4 and the end surface electrode 8 as shown in FIG. Layer 9 is formed to complete the chip resistor 1 as shown in FIGS.
  • the masking material 11 is formed on the overcoat (protective coat) 7 in the previous step of forming the end face electrode 8. Since the masking material 11 is removed by ultrasonic cleaning after sputtering of the end face electrode 8, the masking material 11 can prevent the sputtering film from wrapping around the overcoat 7, and the state of the sputter end can be made linear. can do. In addition, since the masking material 11 is formed on the overcoat 7 so as to avoid the recess 7a, which is the formation site of the trimming groove 10, when the masking material 11 is removed by ultrasonic cleaning after the end face electrode 8 is sputtered, bother. It can be easily removed without applying a strong ultrasonic wave for a long time, and the troublesome masking removal work is not necessary, thereby simplifying the manufacturing process.
  • a pair of masking materials 11 are formed in a strip shape at the longitudinal ends of the overcoat 7 covering the connection portion between the surface electrode 3 and the resistor 5, and the center sandwiched between the masking materials 11 is formed. Since the formation site (recess 7a) of the trimming groove 10 is located in the region, the masking material 11 is easily and accurately formed at a predetermined position of the overcoat 7 formed on the large substrate 20 before the primary division. Can do.
  • both the split surface of the strip-shaped substrate 30 and the surface electrode 3 are covered with the end face electrode 8 and the end face electrode 8 is formed by sputtering.
  • the front face electrode 3 is covered. Only a portion may be formed by a sputtered film, and a thick film may be formed on the divided surface of the strip-shaped substrate 30 using transfer printing or the like.
  • the surface electrode 3 and the back electrode 4 are formed as end faces 8 that are continuous in a U-shape, and these are all formed of a sputtered film, or only the portion covering the front electrode 3 and the back electrode 4 is formed of a sputtered film. You may do it.
  • the multiple chip resistor according to the present embodiment is a quadruple type chip resistor that is integrally provided in a state where four resistance elements are separated on an insulating substrate. 20 is provided with a number of chip formation regions.
  • FIG. 6 is an explanatory diagram corresponding to the plan view on the right side of FIG.
  • the process until the overcoat 7 is formed on the large substrate 20 is the same as that of the first embodiment example, but is formed in the next masking formation process.
  • the shape of the masking material 11 is different from that of the first embodiment. As shown in FIG. 6, the masking material 11 is formed in a comb-like shape so as to protrude between the adjacent surface electrodes 3. Yes.

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  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

In order to enable the wraparound of sputtering material on a protective coat to be reliably prevented in a simple manufacturing step, a method for manufacturing a chip resistor (1) involves a previous step in which end surface electrodes (8) are formed, wherein a masking material (11) is formed on an overcoat (a protective coat) (7) in such a manner as to avoid a recess (7a), which is where a trimming groove (10) is formed, and the masking material (11) is removed by ultrasonic cleaning after the sputtering of the end surface electrodes (8).

Description

チップ抵抗器の製造方法Manufacturing method of chip resistor
 本発明は、回路基板上に半田付けによって面実装されるチップ抵抗器の製造方法に関する。 The present invention relates to a method of manufacturing a chip resistor that is surface-mounted on a circuit board by soldering.
 この種のチップ抵抗器は、平面視矩形状の絶縁基板と、絶縁基板上に所定間隔を存して設けられた一対の電極部と、対をなす電極部どうしを橋絡する抵抗体と、抵抗体を被覆する絶縁性の保護コート等によって主に構成されており、抵抗体には抵抗値調整用のトリミング溝が形成されている。電極部は表面電極と裏面電極および両電極を橋絡する端面電極とからなり、絶縁基板の表面側で一対の表面電極が抵抗体によって橋絡されている。 This type of chip resistor includes an insulating substrate having a rectangular shape in plan view, a pair of electrode portions provided on the insulating substrate at a predetermined interval, and a resistor that bridges the paired electrode portions, The resistor is mainly composed of an insulating protective coat or the like covering the resistor, and a trimming groove for adjusting a resistance value is formed in the resistor. The electrode portion includes a front electrode, a back electrode, and an end face electrode that bridges both electrodes, and a pair of surface electrodes are bridged by a resistor on the surface side of the insulating substrate.
 通常、このようなチップ抵抗器を製造する場合、予め分割溝が設けられた大判基板を準備し、この大判基板上に銀ペースト等を印刷して焼成することにより、大判基板の表裏両面にそれぞれ複数対の表面電極と裏面電極を形成する。次に、大判基板上に抵抗体ペーストを印刷して焼成することにより、各対の表面電極に跨がるように複数の抵抗体を形成した後、抵抗体を覆う領域にガラスペーストを印刷して焼成することにより、各抵抗体の上にアンダーコートを形成する。次に、抵抗体の抵抗値を調整するために、アンダーコートに覆われている抵抗体に対してレーザビームを照射してトリミング溝を形成した後、抵抗体を外部環境から保護するために、トリミング溝を含めた抵抗体全体を覆うようにオーバーコート(保護コート)を形成する。次に、大判基板を分割溝に沿って短冊状に1次分割し、複数の短冊状基板を重ね合わせた状態で、その端面全体にスパッタリングにより端面電極を形成した後、短冊状基板を2次分割(2次ブレイク加工)して個片化されたチップ単体を得る。最後に、チップ単体のコ字状に連続する下地電極層(表面電極と裏面電極および端面電極)に対してめっき層を形成することにより、規格化されたチップサイズのチップ抵抗器が完成する。 Usually, when manufacturing such a chip resistor, prepare a large-sized substrate provided with dividing grooves in advance, print and paste silver paste etc. on this large-sized substrate, respectively, on both sides of the large-sized substrate A plurality of pairs of front and back electrodes are formed. Next, a resistor paste is printed on a large substrate and baked to form a plurality of resistors so as to straddle each pair of surface electrodes, and then a glass paste is printed on a region covering the resistors. By baking, an undercoat is formed on each resistor. Next, in order to adjust the resistance value of the resistor, after forming the trimming groove by irradiating the resistor covered with the undercoat with a laser beam, in order to protect the resistor from the external environment, An overcoat (protective coat) is formed so as to cover the entire resistor including the trimming groove. Next, the large-sized substrate is primarily divided into strips along the dividing grooves, and a plurality of the strip-shaped substrates are overlapped. After forming end face electrodes on the entire end surface by sputtering, the strip-shaped substrate is secondarily formed. Dividing (secondary break processing) into individual chips is obtained. Finally, a standardized chip size chip resistor is completed by forming a plating layer on the base electrode layer (surface electrode, back electrode, and end electrode) continuous in a U-shape of a single chip.
 しかしながら、このような各工程を経て製造されるチップ抵抗器においては、複数の短冊状基板を重ね合わせてスパッタリングにより端面電極を形成する際に、スパッタ膜がオーバーコートに回り込んでしまい、かかるスパッタ膜の回り込みに起因して電極の寸法や直線性がばらついてしまうため、回路基板上に実装されたチップ抵抗器の実装状態を正しく検査できなくなるという問題がある。 However, in a chip resistor manufactured through each of these processes, the sputtered film wraps around the overcoat when stacking a plurality of strip-shaped substrates and forming an end face electrode by sputtering, and such sputtering is performed. Since the dimensions and linearity of the electrodes vary due to the wraparound of the film, there is a problem that the mounting state of the chip resistor mounted on the circuit board cannot be correctly inspected.
 そこで従来より、保護コートであるオーバーコート上にペースト状のマスキング材を印刷・乾燥し、端面電極をスパッタリングにより形成した後、超音波洗浄によってマスキング材を除去するようにしたチップ抵抗器の製造方法が提案されている(例えば、特許文献1参照)。かかる従来技術によれば、端面電極を形成する前工程でオーバーコート上にマスキング材を形成しておき、このマスキング材を端面電極のスパッタリング後に除去するようにしたので、オーバーコート上におけるスパッタの回り込みを阻止することができると共に、スパッタ端の状態を直線状にすることができる。 Therefore, a conventional method of manufacturing a chip resistor in which a masking material in a paste form is printed and dried on an overcoat that is a protective coating, and after forming an end face electrode by sputtering, the masking material is removed by ultrasonic cleaning. Has been proposed (see, for example, Patent Document 1). According to such a conventional technique, the masking material is formed on the overcoat in the previous step of forming the end face electrode, and this masking material is removed after the sputtering of the end face electrode. Can be prevented, and the state of the sputter end can be made linear.
特開2004-128218号公報JP 2004-128218 A
 ところで、この種のチップ抵抗器においては、オーバーコート形成前の抵抗体にトリミング溝を形成して抵抗値を調整した後、そのトリミング溝を含めた抵抗体全体を覆うようにオーバーコートが形成されるため、オーバーコートの表面は平坦面とならずにトリミング溝と同形状の凹部を有することになる。このため、特許文献1に開示された従来技術のように、オーバーコートの表面全体にマスキング材を形成すると、マスキング材がオーバーコートの凹部に入り込んでしまい、端面電極のスパッタリング後にマスキング材を洗浄するとき、凹部に入り込んだマスキング材を除去しにくくなるという問題が発生する。なお、超音波洗浄を長時間続けたり超音波の周波数を高めてパワーを上げれば、凹部に入り込んだマスキング材でも洗浄することは可能となるが、その場合、製造コストが高騰したり、スパッタ膜の損傷によって歩留まりが悪くなるという別の問題が発生する。 By the way, in this type of chip resistor, after the trimming groove is formed in the resistor before the overcoat formation and the resistance value is adjusted, the overcoat is formed so as to cover the entire resistor including the trimming groove. Therefore, the surface of the overcoat does not become a flat surface but has a recess having the same shape as the trimming groove. For this reason, when the masking material is formed on the entire surface of the overcoat as in the prior art disclosed in Patent Document 1, the masking material enters the concave portion of the overcoat, and the masking material is washed after sputtering of the end face electrodes. In some cases, it becomes difficult to remove the masking material that has entered the recess. If the ultrasonic cleaning is continued for a long time or the power of the ultrasonic wave is increased to increase the power, it is possible to clean even the masking material that has entered the recess. However, in that case, the manufacturing cost increases, the sputtered film Another problem arises in that the yield is poor due to damage.
 本発明は、このような従来技術の実情に鑑みてなされたもので、その目的は、保護コート上におけるスパッタの回り込みを簡単な製造工程で確実に阻止することが可能なチップ抵抗器の製造方法を提供することにある。 The present invention has been made in view of the actual situation of the prior art, and an object of the present invention is to provide a chip resistor manufacturing method capable of reliably preventing spattering of a sputter on a protective coat with a simple manufacturing process. Is to provide.
 上記の目的を達成するために、本発明によるチップ抵抗器の製造方法では、矩形状の絶縁基板上に一対の電極を形成する電極形成工程と、前記電極間に跨がるように抵抗体を形成する抵抗体形成工程と、前記抵抗体に抵抗値調整用のトリミング溝を形成するトリミング形成工程と、前記トリミング形成工程後に前記抵抗体の全体を覆うように保護コートを形成する保護コート形成工程と、前記トリミング溝の形成部位を避けるように前記保護コート上にマスキングを施すマスキング形成工程と、前記絶縁基板の端面にスパッタリング法によって前記電極と接続する端面電極を形成する端面電極形成工程と、前記端面電極形成工程後に前記マスキングを洗浄によって除去するマスキング除去工程と、を含むこととした。 In order to achieve the above object, in the method of manufacturing a chip resistor according to the present invention, an electrode forming step of forming a pair of electrodes on a rectangular insulating substrate, and a resistor so as to straddle the electrodes. A resistor forming step for forming, a trimming forming step for forming a trimming groove for adjusting a resistance value in the resistor, and a protective coat forming step for forming a protective coat so as to cover the entire resistor after the trimming forming step A masking process for masking the protective coat so as to avoid the trimming groove forming part, and an end face electrode forming process for forming an end face electrode connected to the electrode by a sputtering method on the end face of the insulating substrate; And a masking removal step of removing the masking by washing after the end face electrode forming step.
 このように端面電極をスパッタリングによって形成する前工程において、保護コート上にトリミング溝の形成部位を避けるようにマスキングを施しておき、このマスキングを端面電極のスパッタリング後に除去するようにしたので、保護コート上におけるスパッタの回り込みをマスキングによって阻止することができると共に、スパッタ端の状態を直線状にすることができる。ここで、保護コートの表面にはトリミング溝と同形状の凹部が存在するが、この凹部を避けた位置でマスキングが保護コート上に形成されているので、端面電極のスパッタリング後にマスキングを除去するとき、超音波洗浄等を用いてマスキングを簡単に除去することができ、面倒なマスキング除去作業が不要になって製造工程を簡略化することができる。 Thus, in the pre-process for forming the end face electrode by sputtering, masking was performed on the protective coat so as to avoid the formation of the trimming groove, and this masking was removed after sputtering of the end face electrode. It is possible to prevent the spattering of the upper part from being masked by masking and to make the state of the sputter end straight. Here, there is a recess with the same shape as the trimming groove on the surface of the protective coat, but masking is formed on the protective coat at a position avoiding this recess, so when removing the mask after sputtering of the end face electrode The masking can be easily removed using ultrasonic cleaning or the like, and the troublesome masking removal work is not required, and the manufacturing process can be simplified.
 かかるチップ抵抗器の製造方法において、保護コート上に形成されるマスキングはトリミング溝の形成部位を包囲するように枠状であっても良いが、このマスキングが電極との接続箇所である抵抗体の両端側にそれぞれ形成されており、トリミング溝の形成部位がこれら一対のマスキングによって挟まれていると、1次分割前の大判基板に形成された保護コートの所定位置にマスキングを簡単に形成することができて好ましい。 In such a chip resistor manufacturing method, the mask formed on the protective coat may be frame-shaped so as to surround the portion where the trimming groove is formed. Forming masking at a predetermined position of the protective coat formed on the large-sized substrate before the primary division when the trimming groove forming portion is sandwiched between the pair of masking formed on both ends. Is preferable.
 本発明によるチップ抵抗器の製造方法は、端面電極をスパッタリングによって形成する前工程において、保護コート上にトリミング溝の形成部位を避けるようにマスキングを施しておき、このマスキングを端面電極のスパッタリング後に除去するようにしたので、保護コート上におけるスパッタの回り込みをマスキングによって阻止することができると共に、スパッタ端の状態を直線状にすることができる。また、保護コートの表面にはトリミング溝と同形状の凹部が存在するが、この凹部を避けた位置でマスキングが保護コート上に形成されているので、端面電極のスパッタリング後にマスキングを除去するとき、超音波洗浄等を用いてマスキングを簡単に除去することができ、面倒なマスキング除去作業が不要になって製造工程を簡略化することができる。 In the manufacturing method of the chip resistor according to the present invention, in the pre-process for forming the end face electrode by sputtering, masking is performed on the protective coat so as to avoid the formation site of the trimming groove, and this masking is removed after the sputtering of the end face electrode. As a result, the spattering of the sputter on the protective coating can be prevented by masking, and the sputter end state can be made linear. In addition, there is a recess having the same shape as the trimming groove on the surface of the protective coat, but since masking is formed on the protective coat at a position avoiding this recess, when removing the masking after sputtering of the end face electrode, Masking can be easily removed using ultrasonic cleaning or the like, and a troublesome mask removing operation is not necessary, thereby simplifying the manufacturing process.
本発明の第1実施形態例に係るチップ抵抗器の平面図である。It is a top view of the chip resistor concerning the example of a 1st embodiment of the present invention. 図1のII-II線に沿う断面図である。FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 該チップ抵抗器の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of this chip resistor. 該チップ抵抗器の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of this chip resistor. 該製造工程中の端面電極形成工程を示す説明図である。It is explanatory drawing which shows the end surface electrode formation process in this manufacturing process. 本発明の第2実施形態例に係る多連チップ抵抗器の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the multiple chip resistor which concerns on the example of 2nd Embodiment of this invention.
 以下、発明の実施の形態を図面を参照しながら説明する。図1と図2に示すように、発明の第1実施形態例に係るチップ抵抗器1は、直方体形状の絶縁基板2と、絶縁基板2の表面(図2では上面)の長手方向両端部に設けられた一対の表面電極3と、絶縁基板2の裏面(図2では下面)の長手方向両端部に設けられた一対の裏面電極4と、一対の表面電極3に両端部を重ね合わせて絶縁基板2の表面に設けられた抵抗体5と、抵抗体5を被覆するアンダーコート6と、アンダーコート6を被覆するオーバーコート7と、表面電極3と裏面電極4を橋絡している一対の端面電極8と、各裏面電極4と端面電極8を被覆するめっき層9とによって主に構成されている。 Hereinafter, embodiments of the invention will be described with reference to the drawings. As shown in FIGS. 1 and 2, the chip resistor 1 according to the first embodiment of the present invention includes a rectangular parallelepiped insulating substrate 2 and longitudinal ends of the surface of the insulating substrate 2 (upper surface in FIG. 2). A pair of front surface electrodes 3 provided, a pair of back surface electrodes 4 provided at both ends in the longitudinal direction of the back surface of the insulating substrate 2 (the lower surface in FIG. 2), and a pair of surface electrodes 3 are overlapped and insulated. A resistor 5 provided on the surface of the substrate 2, an undercoat 6 covering the resistor 5, an overcoat 7 covering the undercoat 6, and a pair of bridges between the surface electrode 3 and the back electrode 4 It is mainly comprised by the end surface electrode 8, and the plating layer 9 which coat | covers each back surface electrode 4 and the end surface electrode 8. FIG.
 絶縁基板2はセラミック等からなり、この絶縁基板2は後述する大判基板を縦横の分割溝に沿って分割して多数個取りされたものである。表面電極3は銀ペーストをスクリーン印刷して乾燥・焼成させたものであり、同じく裏面電極4も銀ペーストをスクリーン印刷して乾燥・焼成させたものである。抵抗体5は酸化ルテニウム等の抵抗体ペーストをスクリーン印刷して乾燥・焼成させたものであり、この抵抗体5には抵抗値を調整するためにトリミング溝10が形成されている。アンダーコート6はガラスペーストをスクリーン印刷して焼成させたものであり、このアンダーコート6はトリミング溝10を形成する前に抵抗体5を覆うように形成されている。オーバーコート7はエポキシ系樹脂ペーストをスクリーン印刷して加熱硬化させたものであり、このオーバーコート7は抵抗体5にトリミング溝10を形成した後に形成されている。 The insulating substrate 2 is made of ceramic or the like, and this insulating substrate 2 is obtained by dividing a large-sized substrate, which will be described later, along a vertical and horizontal dividing groove and taking a large number of them. The front electrode 3 is obtained by screen-printing a silver paste, dried and fired, and the back electrode 4 is also obtained by screen-printing a silver paste, dried and fired. The resistor 5 is a resistor paste such as ruthenium oxide that is screen-printed, dried and fired. A trimming groove 10 is formed in the resistor 5 to adjust the resistance value. The undercoat 6 is obtained by screen-printing and baking a glass paste. The undercoat 6 is formed so as to cover the resistor 5 before the trimming groove 10 is formed. The overcoat 7 is obtained by screen-printing and curing an epoxy resin paste, and this overcoat 7 is formed after the trimming groove 10 is formed in the resistor 5.
 端面電極8は絶縁基板2の端面と表面電極3を覆うようにスパッタリングによって形成されたものであり、この端面電極8は絶縁基板2に対する密着性クロム(Cr)とバリヤー層の材料を含有するスパッタ膜からなる。バリヤー層は熱応力(ヒートショック)に対するクッション材として機能するものであり、ニッケル(Ni)または銅(Cu)が用いられている。めっき層9は端面電極8を覆うように電解メッキによって形成されたものであり、このめっき層9は錫(Sn)-鉛(Pb)や鉛フリーのSn等からなる。 The end face electrode 8 is formed by sputtering so as to cover the end face of the insulating substrate 2 and the surface electrode 3, and the end face electrode 8 is a sputter containing adhesion chromium (Cr) to the insulating substrate 2 and a barrier layer material. It consists of a membrane. The barrier layer functions as a cushioning material against thermal stress (heat shock), and nickel (Ni) or copper (Cu) is used. The plating layer 9 is formed by electrolytic plating so as to cover the end face electrode 8, and this plating layer 9 is made of tin (Sn) -lead (Pb), lead-free Sn, or the like.
 次に、上記の如く構成されたチップ抵抗器1の製造方法について、図3と図4を参照しながら説明する。なお、第1工程から第10工程までは図3を参照して説明し、第11工程から第15工程までは図4を参照して説明する。 Next, a method for manufacturing the chip resistor 1 configured as described above will be described with reference to FIGS. The first to tenth steps will be described with reference to FIG. 3, and the eleventh to fifteenth steps will be described with reference to FIG.
 まず、第1工程として、図3(a)に示すように、絶縁基板2が多数個取りされる大判基板20の裏面にAgペーストをスクリーン印刷して乾燥させることによって未焼成の裏面電極4を形成した後、第2工程として、大判基板20の表面にAg/Pdペーストをスクリーン印刷して乾燥させることによって未焼成の表面電極3を形成する(電極形成工程)。なお、大判基板20には予め1次分割溝と2次分割溝(いずれも図示せず)が格子状に設けられており、両分割溝によって区切られたマス目の1つ1つが1個分のチップ領域となる。 First, as a first step, as shown in FIG. 3A, an unfired back electrode 4 is formed by screen-printing and drying Ag paste on the back surface of a large substrate 20 on which a large number of insulating substrates 2 are taken. After the formation, as a second step, an unfired surface electrode 3 is formed by screen-printing and drying an Ag / Pd paste on the surface of the large substrate 20 (electrode formation step). The large-sized substrate 20 is provided with a primary dividing groove and a secondary dividing groove (both not shown) in advance in a lattice shape, and each of the squares divided by both the dividing grooves is equivalent to one. This is the chip area.
 次に、第3工程として、これら未焼成の表面電極3と裏面電極4を850℃程度の高温で焼成した後、第4工程として、大判基板20の表面に酸化ルテニウム系の抵抗体ペーストをスクリーン印刷して乾燥させることにより、図3(b)に示すように、各チップ領域に未焼成の抵抗体5を形成する(抵抗体形成工程)。その際、抵抗体5の長手方向両端部は、各チップ領域の長手方向両端部に設けられている表面電極3に重ね合わせておく。そして、次なる第5工程で、この抵抗体5を850℃程度の高温で焼成する。なお、前述した第3工程の焼成を省略し、この第5工程で表面電極3と裏面電極4および抵抗体5を同時に焼成しても良く、その場合は焼成工程を減らしてコストダウンを図ることが可能となる。 Next, after firing the unfired front electrode 3 and back electrode 4 at a high temperature of about 850 ° C. as a third step, a ruthenium oxide resistor paste is screened on the surface of the large substrate 20 as a fourth step. By printing and drying, an unfired resistor 5 is formed in each chip region as shown in FIG. 3B (resistor forming step). At that time, both ends in the longitudinal direction of the resistor 5 are overlapped with the surface electrodes 3 provided at both ends in the longitudinal direction of each chip region. In the next fifth step, the resistor 5 is fired at a high temperature of about 850 ° C. Note that the firing of the third step described above may be omitted, and the front electrode 3, the back electrode 4 and the resistor 5 may be fired simultaneously in this fifth step. In this case, the firing step is reduced to reduce the cost. Is possible.
 次に、第6工程として、抵抗体5を覆う領域にガラスペーストをスクリーン印刷して乾燥した後、第7工程でこのガラスペーストを600℃程度の高温で焼成することにより、図3(c)に示すように、抵抗体5の上にアンダーコート6を形成する。このアンダーコート6は、次工程で照射されるレーザビームの熱で抵抗体5のトリミング溝10近傍が損傷しないようにするためのものである。 Next, after the glass paste is screen-printed on the region covering the resistor 5 and dried in the sixth step, the glass paste is baked at a high temperature of about 600 ° C. in the seventh step, so that FIG. As shown in FIG. 2, an undercoat 6 is formed on the resistor 5. This undercoat 6 is for preventing the vicinity of the trimming groove 10 of the resistor 5 from being damaged by the heat of the laser beam irradiated in the next step.
 次に、第8工程として、図3(d)に示すように、アンダーコート6に覆われている抵抗体5に対してレーザビームを照射してトリミング溝10を形成する(トリミング形成工程)。その際、トリミング対象となる抵抗体5の長手方向の両側に存する表面電極3に図示せぬプローブをそれぞれ接触させ、これらプローブを介して抵抗値を測定しながらレーザトリミングを行う。レーザビームの照射が開始されてトリミング溝10が長くなると、それに伴って抵抗値が増大していくので、トリミング対象の抵抗体5の抵抗値が所望の値に達した時点でレーザビームの照射をオフにする。 Next, as an eighth step, as shown in FIG. 3D, the trimming groove 10 is formed by irradiating the resistor 5 covered with the undercoat 6 with a laser beam (trimming forming step). At that time, probes not shown are brought into contact with the surface electrodes 3 existing on both sides in the longitudinal direction of the resistor 5 to be trimmed, and laser trimming is performed while measuring the resistance value through these probes. When the laser beam irradiation is started and the trimming groove 10 becomes longer, the resistance value increases accordingly. Therefore, when the resistance value of the resistor 5 to be trimmed reaches a desired value, the laser beam irradiation is performed. Turn off.
 次に、第9工程として、アンダーコート6を覆う領域にエポキシ系樹脂ペーストをスクリーン印刷した後、これを200℃程度で加熱硬化させることにより、図3(e)に示すように、抵抗体5とアンダーコート6およびトリミング溝10を覆うオーバーコート7を形成する(保護コート形成工程)。その際、アンダーコート6上に印刷された樹脂ペーストはトリミング溝10の内部にも入り込むため、加熱硬化後のオーバーコート7の表面は平坦面とならず、オーバーコート7の中央付近にトリミング溝10と同形状の凹部7aができる。なお、このオーバーコート7は抵抗体5を外部環境から保護するためのものである。 Next, as a ninth step, an epoxy resin paste is screen-printed in a region covering the undercoat 6 and then heat-cured at about 200 ° C., so that the resistor 5 is shown in FIG. Then, an overcoat 7 covering the undercoat 6 and the trimming groove 10 is formed (protective coat forming step). At this time, since the resin paste printed on the undercoat 6 also enters the trimming groove 10, the surface of the overcoat 7 after heat curing is not a flat surface, and the trimming groove 10 is located near the center of the overcoat 7. A concave portion 7a having the same shape as that is formed. The overcoat 7 is for protecting the resistor 5 from the external environment.
 次に、第10工程として、オーバーコート7上の凹部7aを避ける領域に水溶性エポキシ樹脂をスクリーン印刷して乾燥させることにより、図3(f)に示すように、オーバーコート7上に凹部7aを挟んで対向する一対の帯状のマスキング材11を形成する(マスキング形成工程)。これらマスキング材11の表面電極3側の端部はオーバーコート7の長手方向端部と平行であり、後述するように、チップ抵抗器1の完成状態でマスキング材11は除去されている。 Next, as a tenth step, a water-soluble epoxy resin is screen-printed in a region avoiding the recess 7a on the overcoat 7 and dried, thereby forming the recess 7a on the overcoat 7 as shown in FIG. A pair of strip-shaped masking materials 11 that are opposed to each other are formed (masking forming step). The end portions on the surface electrode 3 side of these masking materials 11 are parallel to the longitudinal end portions of the overcoat 7, and the masking material 11 is removed in the completed state of the chip resistor 1 as will be described later.
 ここまでの工程は多数個取り用の大判基板20に対する一括処理であるが、次なる第11工程では、大判基板20を第1分割溝に沿って短冊状に分割するという1次ブレイク加工を行う。これにより、複数個分のチップ領域が設けられた短冊状基板30を得る。 The process up to this point is a batch process for the large-sized substrate 20 for taking a large number of pieces, but in the next eleventh step, a primary break process is performed in which the large-sized substrate 20 is divided into strips along the first dividing groove. . Thereby, a strip-shaped substrate 30 provided with a plurality of chip regions is obtained.
 そして、次なる第12工程で、複数枚の短冊状基板30を上下方向に重ね合わせ、この状態で短冊状基板30の端面にCr/Niをスパッタリングすることにより、図4(a)に示すように、表面電極3と裏面電極4とを橋絡する端面電極8を形成する(端面電極形成工程)。この場合、下側の短冊状基板30のオーバーコート7上のマスキング材11が上側の短冊状基板30の下面に接した状態でスパッタリングされ、上下に重なる短冊状基板30の間にもスパッタ膜が回り込むため、端面電極8は短冊状基板30の端面から表面電極3を越えてオーバーコート7の端部やマスキング材11の端部位置まで形成される。ただし、図5に示すように、マスキング材11が上側の短冊状基板30の下面に接しているため、スパッタ膜がマスキング材11を越えて凹部7aまで達することはない。なお、図5は5枚の短冊状基板30を重ね合わせてスパッタリングしたときの端面電極形成工程を示しており、そのうちの1枚が図4(a)に示す短冊状基板30に相当する。 Then, in the next twelfth step, a plurality of strip-shaped substrates 30 are stacked in the vertical direction, and Cr / Ni is sputtered on the end surfaces of the strip-shaped substrates 30 in this state, as shown in FIG. Next, the end face electrode 8 that bridges the front electrode 3 and the back face electrode 4 is formed (end face electrode forming step). In this case, the masking material 11 on the overcoat 7 of the lower strip-shaped substrate 30 is sputtered in a state of being in contact with the lower surface of the upper strip-shaped substrate 30, and a sputtered film is also formed between the strip-shaped substrates 30 overlapping vertically. In order to wrap around, the end surface electrode 8 is formed from the end surface of the strip-shaped substrate 30 to the end portion of the overcoat 7 and the end portion of the masking material 11 beyond the surface electrode 3. However, as shown in FIG. 5, since the masking material 11 is in contact with the lower surface of the upper strip-shaped substrate 30, the sputtered film does not reach the recess 7 a beyond the masking material 11. FIG. 5 shows an end face electrode forming process when five strip-shaped substrates 30 are stacked and sputtered, and one of them corresponds to the strip-shaped substrate 30 shown in FIG.
 しかる後、第13工程として、短冊状基板30を第2分割溝に沿って分割するという2次ブレイク加工を行い、チップ抵抗器1と同等の大きさの個片(チップ単体)を得る。 Thereafter, as a thirteenth step, a secondary break process is performed in which the strip-shaped substrate 30 is divided along the second divided grooves, and a piece (chip alone) having the same size as the chip resistor 1 is obtained.
 次に、第14工程として、個片化されたチップ単体に対して超音波洗浄を行うことにより、図4(b)に示すように、オーバーコート7上に形成されたマスキング材11を除去する(マスキング除去工程)。その際、マスキング材11はオーバーコート7上の凹部7aに入り込んでいないため、長時間や強い超音波をかけることなく簡単にマスキング材11を洗浄・除去することができる。 Next, as a fourteenth step, the masking material 11 formed on the overcoat 7 is removed as shown in FIG. (Masking removal process). At this time, since the masking material 11 does not enter the recess 7a on the overcoat 7, the masking material 11 can be easily cleaned and removed without applying a strong ultrasonic wave for a long time.
 最後に、第15工程として、個片化されたチップ単体の絶縁基板2に対して電解メッキを施すことにより、図4(c)に示すように、裏面電極4と端面電極8を被覆するめっき層9を形成し、図1と図2に示すようなチップ抵抗器1が完成する。 Finally, as a fifteenth step, the plating is performed so as to cover the back surface electrode 4 and the end surface electrode 8 as shown in FIG. Layer 9 is formed to complete the chip resistor 1 as shown in FIGS.
 以上説明したように、本実施形態例に係るチップ抵抗器1の製造方法においては、端面電極8を形成する前工程でオーバーコート(保護コート)7上にマスキング材11を形成しておき、このマスキング材11を端面電極8のスパッタリング後に超音波洗浄によって除去するようにしたので、オーバーコート7上におけるスパッタ膜の回り込みをマスキング材11によって阻止することができると共に、スパッタ端の状態を直線状にすることができる。また、マスキング材11がトリミング溝10の形成部位である凹部7aを避けるようにオーバーコート7上に形成されているので、端面電極8のスパッタリング後にマスキング材11を超音波洗浄によって除去するとき、わざわざ長時間や強い超音波をかけなくても簡単に除去することができ、面倒なマスキング除去作業が不要になって製造工程を
簡略化することができる。
As described above, in the method of manufacturing the chip resistor 1 according to this embodiment, the masking material 11 is formed on the overcoat (protective coat) 7 in the previous step of forming the end face electrode 8. Since the masking material 11 is removed by ultrasonic cleaning after sputtering of the end face electrode 8, the masking material 11 can prevent the sputtering film from wrapping around the overcoat 7, and the state of the sputter end can be made linear. can do. In addition, since the masking material 11 is formed on the overcoat 7 so as to avoid the recess 7a, which is the formation site of the trimming groove 10, when the masking material 11 is removed by ultrasonic cleaning after the end face electrode 8 is sputtered, bother. It can be easily removed without applying a strong ultrasonic wave for a long time, and the troublesome masking removal work is not necessary, thereby simplifying the manufacturing process.
 また、本実施形態例では、表面電極3と抵抗体5との接続箇所を覆うオーバーコート7の長手方向端部に一対のマスキング材11を帯状に形成し、これらマスキング材11に挟まれた中央領域にトリミング溝10の形成部位(凹部7a)が位置しているので、1次分割前の大判基板20に形成されたオーバーコート7の所定位置にマスキング材11を簡単かつ高精度に形成することができる。 Further, in this embodiment, a pair of masking materials 11 are formed in a strip shape at the longitudinal ends of the overcoat 7 covering the connection portion between the surface electrode 3 and the resistor 5, and the center sandwiched between the masking materials 11 is formed. Since the formation site (recess 7a) of the trimming groove 10 is located in the region, the masking material 11 is easily and accurately formed at a predetermined position of the overcoat 7 formed on the large substrate 20 before the primary division. Can do.
 なお、上記実施形態例では、端面電極8によって短冊状基板30の分割面と表面電極3の両方を覆い、この端面電極8をスパッタリングによって形成するようにしているが、例えば、表面電極3を覆う部分だけをスパッタ膜によって形成し、短冊状基板30の分割面については転写印刷等を用いて厚膜形成するようにしても良い。あるいは、表面電極3と裏面電極4とをコ字状に連続する端面電極8となし、これらを全てスパッタ膜によって形成したり、表面電極3と裏面電極4を覆う部分だけをスパッタ膜によって形成するようにしても良い。 In the above embodiment, both the split surface of the strip-shaped substrate 30 and the surface electrode 3 are covered with the end face electrode 8 and the end face electrode 8 is formed by sputtering. For example, the front face electrode 3 is covered. Only a portion may be formed by a sputtered film, and a thick film may be formed on the divided surface of the strip-shaped substrate 30 using transfer printing or the like. Alternatively, the surface electrode 3 and the back electrode 4 are formed as end faces 8 that are continuous in a U-shape, and these are all formed of a sputtered film, or only the portion covering the front electrode 3 and the back electrode 4 is formed of a sputtered film. You may do it.
 次に、本発明を多連チップ抵抗器に適用した第2実施形態例について図6を参照して説明する。本実施形態例に係る多連チップ抵抗器は、絶縁基板上に4つの抵抗素子がセパレートされた状態で一体的に設けられている4連タイプチップ抵抗器であり、多数個取り用の大判基板20には多数個分のチップ形成領域が設けられている。 Next, a second embodiment in which the present invention is applied to a multiple chip resistor will be described with reference to FIG. The multiple chip resistor according to the present embodiment is a quadruple type chip resistor that is integrally provided in a state where four resistance elements are separated on an insulating substrate. 20 is provided with a number of chip formation regions.
 図6は図3(f)の右側の平面図に対応する説明図である。本実施形態例に係る多連チップ抵抗器の製造方法において、大判基板20に対してオーバーコート7を形成するまでの工程は第1実施形態例と同じであるが、次のマスキング形成工程で形成されるマスキング材11の形状が第1実施形態例と相違しており、図6に示すように、このマスキング材11は隣接する表面電極3の間に突出するように櫛歯状に形成されている。これにより、1次ブレイク後の短冊状基板の分割面にスパッタリングによって端面電極を形成するとき、スパッタ膜がマスキング材11の突部11aを覆うように形成されるため、マスキング材11の印刷パターンを工夫するという簡単な構成によって、隣接する表面電極3間の短絡を確実に防止することができる。 FIG. 6 is an explanatory diagram corresponding to the plan view on the right side of FIG. In the manufacturing method of the multiple chip resistor according to the present embodiment example, the process until the overcoat 7 is formed on the large substrate 20 is the same as that of the first embodiment example, but is formed in the next masking formation process. The shape of the masking material 11 is different from that of the first embodiment. As shown in FIG. 6, the masking material 11 is formed in a comb-like shape so as to protrude between the adjacent surface electrodes 3. Yes. As a result, when the end face electrode is formed by sputtering on the divided surface of the strip-shaped substrate after the primary break, the sputtered film is formed so as to cover the protrusion 11a of the masking material 11, so that the printing pattern of the masking material 11 is changed. With a simple configuration that is devised, it is possible to reliably prevent a short circuit between adjacent surface electrodes 3.
 1 チップ抵抗器
 2 絶縁基板
 3 表面電極
 4 裏面電極
 5 抵抗体
 6 アンダーコート
 7 オーバーコート(保護コート)
 7a 凹部(トリミング溝の形成部位)
 8 端面電極
 9 めっき層
 10 トリミング溝
 11 マスキング材
 11a 突部
 20 大判基板
 30 短冊状基板
DESCRIPTION OF SYMBOLS 1 Chip resistor 2 Insulating substrate 3 Front surface electrode 4 Back surface electrode 5 Resistor 6 Undercoat 7 Overcoat (protective coat)
7a Concavity (formation part of trimming groove)
8 End face electrode 9 Plating layer 10 Trimming groove 11 Masking material 11a Protrusion 20 Large format substrate 30 Strip substrate

Claims (2)

  1.  矩形状の絶縁基板上に一対の電極を形成する電極形成工程と、
     前記電極間に跨がるように抵抗体を形成する抵抗体形成工程と、
     前記抵抗体に抵抗値調整用のトリミング溝を形成するトリミング形成工程と、
     前記トリミング形成工程後に前記抵抗体の全体を覆うように保護コートを形成する保護コート形成工程と、
     前記トリミング溝の形成部位を避けるように前記保護コート上にマスキングを施すマスキング形成工程と、
     前記絶縁基板の端面にスパッタリング法によって前記電極と接続する端面電極を形成する端面電極形成工程と、
     前記端面電極形成工程後に前記マスキングを洗浄によって除去するマスキング除去工程と、
    を含むことを特徴とするチップ抵抗器の製造方法。
    An electrode forming step of forming a pair of electrodes on a rectangular insulating substrate;
    Forming a resistor so as to straddle between the electrodes; and
    A trimming formation step of forming a trimming groove for adjusting a resistance value in the resistor;
    A protective coat forming step of forming a protective coat so as to cover the entire resistor after the trimming forming step;
    Masking forming step of masking on the protective coat so as to avoid the formation site of the trimming groove;
    An end face electrode forming step of forming an end face electrode connected to the electrode by a sputtering method on the end face of the insulating substrate;
    A masking removal step of removing the masking by washing after the end face electrode forming step;
    A method of manufacturing a chip resistor, comprising:
  2.  請求項1の記載において、前記マスキングが前記電極との接続箇所である前記抵抗体の両端側にそれぞれ形成されており、前記トリミング溝の形成部位がこれら一対のマスキングによって挟まれていることを特徴とするチップ抵抗器の製造方法。 2. The mask according to claim 1, wherein the masking is formed on both ends of the resistor, which is a connection portion with the electrode, and the trimming groove forming portion is sandwiched between the pair of masking. A manufacturing method of a chip resistor.
PCT/JP2014/061704 2013-05-16 2014-04-25 Method for manufacturing chip resistor WO2014185254A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107705944A (en) * 2017-11-15 2018-02-16 江苏苏杭电子有限公司 High stability thermistor processing technology

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JP2022024701A (en) * 2020-07-28 2022-02-09 住友金属鉱山株式会社 Manufacturing method of chip resistor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004128218A (en) * 2002-10-02 2004-04-22 Koa Corp Method of manufacturing small electronic component and chip resistor
JP2004259773A (en) * 2003-02-24 2004-09-16 Koa Corp Method for manufacturing chip resistor
JP2006013025A (en) * 2004-06-24 2006-01-12 Koa Corp Resistor and its manufacturing method
JP2011211022A (en) * 2010-03-30 2011-10-20 Panasonic Corp Method of manufacturing resistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004128218A (en) * 2002-10-02 2004-04-22 Koa Corp Method of manufacturing small electronic component and chip resistor
JP2004259773A (en) * 2003-02-24 2004-09-16 Koa Corp Method for manufacturing chip resistor
JP2006013025A (en) * 2004-06-24 2006-01-12 Koa Corp Resistor and its manufacturing method
JP2011211022A (en) * 2010-03-30 2011-10-20 Panasonic Corp Method of manufacturing resistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107705944A (en) * 2017-11-15 2018-02-16 江苏苏杭电子有限公司 High stability thermistor processing technology
CN107705944B (en) * 2017-11-15 2019-03-05 昆山苏杭电路板有限公司 High stability thermistor processing technology

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