WO2014185085A1

WO2014185085A1 - Semiconductor storage device

Info

Publication number: WO2014185085A1
Application number: PCT/JP2014/051221
Authority: WO
Inventors: 小野　瑞城
Original assignee: 株式会社東芝
Priority date: 2013-05-14
Filing date: 2014-01-22
Publication date: 2014-11-20
Also published as: JP2014222740A; TW201444027A

Abstract

A semiconductor device comprises: first and second p-type field-effect transistors (Tp1, Tp2), and first and second n-type field-effect transistors (Tn1, Tn2) formed on a semiconductor substrate; an insulating film formed on each transistor; and third and fourth n-type field-effect transistors (Tn3, Tn4) formed on the insulating film. An SRAM is composed of these six transistors. In addition, the transistors (Tn3, Tn4) have a planar structure; at least a portion of a channel region of the transistor (Tn3) is formed on at least a portion of gate electrodes of the transistors (Tp2, Tn2) in such a manner as to overlap when viewed from the normal direction of the semiconductor substrate; and at least a portion of a channel region of the transistor (Tn4) is formed on at least a portion of gate electrodes of the transistors (Tp1, Tn1) in such a manner as to overlap when viewed from the normal direction of the semiconductor substrate.

Description

Semiconductor memory device

Embodiments described herein relate generally to a semiconductor memory device, and more particularly, to an SRAM (Static Random Access).
The present invention relates to a semiconductor memory device having a three-dimensional structure.

In a semiconductor integrated circuit, a low power supply voltage is being promoted in order to reduce power consumption. One of the barriers to accomplishing this is the static noise margin of an SRAM (Static Noise Margin, Hereinafter, there is a problem of abbreviated as SNM). SNM represents the upper limit of the magnitude of noise that is not lost in stored information. If the SNM is zero, the upper limit of the magnitude of the noise that is not lost in the stored information is zero, that is, the stored information is lost in any noise. That means that no noise is allowed, so such SRAM cannot be used. In general, the SNM decreases as the power supply voltage decreases. Therefore, the reduction of the power supply voltage has been restricted due to the decrease of the SNM accompanying the reduction of the power supply voltage.

Conventionally, there is a trade-off between increasing the SNM in the SRAM and reducing the power supply voltage. Therefore, there is a restriction on lowering the power supply voltage, and there is a demand for increasing the SNM particularly under a constant power supply voltage.

The problem to be solved by the present invention is to provide a semiconductor memory device capable of increasing the SNM under a constant power supply voltage in an SRAM structure.

A semiconductor memory device according to an embodiment is formed on a semiconductor substrate, first and second p-type field effect transistors and first and second n-type field effect transistors formed on the semiconductor substrate, and the respective transistors. And the third and fourth n-type field effect transistors formed on the insulating film. Each source region and each substrate electrode of the first and second p-type field effect transistors are connected to a wiring whose potential is maintained at a power supply voltage, and each of the first and second n-type field effect transistors is The source region and each substrate electrode are connected to a wiring whose potential is maintained at the ground potential, and each drain region of the first p-type field effect transistor and the first n-type field effect transistor and the second p-type The gate electrodes of the n-type field effect transistor and the second n-type field effect transistor and the drain region of the third n-type field effect transistor are connected to each other, and the second p-type field effect transistor and the second n-type field effect transistor Each n-type field effect transistor drain region, the first p-type field effect transistor, each gate electrode of the first n-type field effect transistor, and the fourth n-type. A drain region of the field effect transistor is connected to each other, gate electrodes of the third and fourth n-type field effect transistors are connected to a word line, and a source region of the third n-type field effect transistor is a bit And a source region of the fourth n-type field effect transistor is connected to an inverted bit line. The third and fourth n-type field effect transistors have a planar structure, and at least a part of the channel region of the third n-type field effect transistor is a gate of the second p-type field effect transistor. An electrode and a wiring connected to the gate electrode overlap with at least a part of the gate electrode of the second n-type field effect transistor and the wiring connected to the gate electrode when viewed from the normal direction of the semiconductor substrate. And at least a part of the channel region of the fourth n-type field effect transistor includes a gate electrode of the first p-type field effect transistor, a wiring connected to the gate electrode, and the first n-type field effect transistor. Formed so as to overlap at least a part of the gate electrode of the type field effect transistor and the wiring connected to the gate electrode when viewed from the normal direction of the semiconductor substrate It has been.

In the present invention, at least one of the field effect transistors constituting the SRAM is formed on the field effect transistor forming the storage node via an insulating film. In this manner, in the state where information is written, at least one threshold voltage of the field effect transistor constituting the inverter whose output terminal is the potential of the power supply voltage among the two sets of inverters constituting the SRAM is positive. Or the threshold voltage of the field effect transistor connecting the output terminal of the inverter and the bit line or the inverted bit line changes in the negative direction. Or, the threshold voltage of at least one of the field effect transistors constituting the inverter of which the output terminal is at the ground potential among the two sets of inverters constituting the SRAM changes in the negative direction, or the output terminal of the inverter The threshold voltage of the field effect transistor connecting the bit line or the inverted bit line changes in the positive direction. As a result, the upper limit of the amount of noise that is not lost in the stored information increases. That is, SNM can be increased under a constant power supply voltage.

FIG. 1 is a circuit configuration diagram showing the semiconductor memory device according to the first embodiment. FIG. 2 is a bird's-eye view showing a schematic structure of the semiconductor memory device according to the first embodiment. FIG. 3 is a cross-sectional view showing a schematic structure of the semiconductor memory device according to the first embodiment. FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor memory device according to the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor memory device according to the first embodiment. FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment. FIG. 7 is a characteristic diagram showing a butterfly curve when there is no variation in the threshold voltage, for explaining the performance of the semiconductor memory device according to the first embodiment. FIG. 8A is a characteristic diagram for explaining the performance of the semiconductor memory device according to the first embodiment and showing a butterfly curve when the threshold voltage varies. FIG. 8B is a characteristic diagram illustrating a butterfly curve when the threshold voltage varies in order to explain the performance of the semiconductor memory device according to the first embodiment. FIG. 9 is a bird's-eye view showing the structure of the first modification of the first embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the first modification of the first embodiment. FIG. 11 is a bird's-eye view showing the structure of the second modification of the first embodiment. FIG. 12 is a bird's-eye view showing the structure of the third modification of the first embodiment. FIG. 13 is a bird's-eye view showing a schematic structure of the semiconductor memory device according to the second embodiment. FIG. 14A is a characteristic diagram for explaining the performance of the semiconductor memory device according to the second embodiment. FIG. 14B is a characteristic diagram for explaining the performance of the semiconductor memory device according to the second embodiment. FIG. 15 is a bird's eye view showing a schematic structure of a semiconductor memory device according to a modification of the second embodiment. FIG. 16A is a characteristic diagram for explaining the performance of the semiconductor memory device according to the modification of the second embodiment. FIG. 16B is a characteristic diagram for explaining the performance of the semiconductor memory device according to the modification of the second embodiment. FIG. 17 is a bird's-eye view showing a schematic structure of the semiconductor memory device according to the third embodiment. FIG. 18A is a characteristic diagram for explaining the performance of the semiconductor memory device according to the third embodiment. FIG. 18B is a characteristic diagram for explaining the performance of the semiconductor memory device according to the third embodiment. FIG. 19 is a bird's-eye view showing a schematic structure of a semiconductor memory device according to a modification of the third embodiment. FIG. 20A is a characteristic diagram for explaining the performance of the semiconductor memory device according to the modification of the third embodiment. FIG. 20B is a characteristic diagram for explaining the performance of the semiconductor memory device according to the modification of the third embodiment. FIG. 21 is a bird's-eye view showing a schematic structure of the semiconductor memory device according to the fourth embodiment. FIG. 22 is a bird's-eye view showing a schematic structure of a semiconductor memory device according to a modification of the fourth embodiment. FIG. 23 is a bird's-eye view showing a schematic structure of the semiconductor memory device according to the fifth embodiment. FIG. 24 is a bird's-eye view showing a schematic structure of a semiconductor memory device according to a modification of the fifth embodiment.

Hereinafter, the semiconductor memory device of the embodiment will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit configuration diagram showing a semiconductor memory device according to the first embodiment of the present invention.

In the figure, Tpi (i = 1, 2) is the i-th p-type field effect transistor, Tnj (j = 1, 2, 3, 4) is the j-th n-type field effect transistor, and VDD is at the power supply voltage. The maintained wiring, GND represents a wiring whose potential is maintained at the ground potential, WL represents a word line, BL represents a bit line, and BL ′ represents an inverted bit line. The substrate electrode of the field effect transistor is omitted.

FIG. 2 schematically shows the structure of the first embodiment in a bird's-eye view. In the following bird's-eye view, only a part of the insulating film and the wiring formed on the semiconductor substrate are shown. Further, the thickness of the semiconductor layer on which the field effect transistor formed on the insulating film formed on the semiconductor substrate is omitted, and the interlayer insulating film thereon is also omitted. Further, the substrate electrode of the field effect transistor formed on the semiconductor substrate is omitted. In order to make the figure easy to see, the distance between the field effect transistor formed on the semiconductor substrate and the field effect transistor formed on the insulating film in the direction perpendicular to the surface of the semiconductor substrate is enlarged. . In general, the scale of the figure is not accurate.

In the semiconductor memory device of this embodiment, first and second p-type field effect transistors Tp1 and Tp2 and first and second n-type field effect transistors Tn1 and Tn2 are formed on a semiconductor substrate. Third and fourth n-type field effect transistors Tn3 and Tn4 are formed on the insulating film formed above. The channel region of the third n-type field effect transistor Tn3 is formed so as to overlap the gate electrode of the second p-type field effect transistor Tp2 when viewed from the normal direction of the semiconductor substrate. The channel region of the field effect transistor Tn4 is formed so as to overlap the gate electrode of the first p-type field effect transistor Tp1 when viewed from the normal direction of the semiconductor substrate. The normal direction is a direction perpendicular to the surface of the semiconductor substrate.

FIG. 3 schematically shows a cross-sectional structure of the present embodiment. In the following cross-sectional views,
A cross section of only the first p-type field effect transistor Tp1 and the first and fourth n-type field effect transistors Tn1 and Tn4 is schematically shown as if they were formed in the same direction. Also, the scale of the figure is not accurate. Further, the wiring or the interlayer insulating film of the second layer or higher is omitted.

For example, an element isolation region 2 made of, for example, silicon oxide is formed in a semiconductor substrate 1 made of, for example, silicon, and an n-well region 3 and a p-well region 4 are formed in regions separated by the element isolation region 2. A gate electrode 6 is formed on each of the n well region 3 and the p well region 4 with a gate insulating film 5 interposed therebetween. In the n-well region 3 and the p-well region 4, a source / drain region 7 is formed so as to sandwich the gate electrode 6, and a gate sidewall 8 is formed in contact with the gate electrode. As a result, the first p-type field effect transistor Tp1 is formed in the n-well region 3, and the first n-type field-effect transistor Tn1 is formed in the p-well region 4, respectively. An interlayer insulating film 9 made of, for example, silicon oxide is formed on the first p-type field effect transistor Tp1 and the first n-type field effect transistor Tn1, and made of, for example, silicon. A semiconductor layer 10 containing p-type impurities is formed.

A gate electrode 6 is formed on the semiconductor layer 10 with a gate insulating film 5 interposed therebetween. A source / drain region 7 is formed in the semiconductor layer 10 so as to sandwich the gate electrode 6, and a gate sidewall 8 is formed in contact with the gate electrode, so that the fourth n-type field effect transistor Tn 4 is formed. Is formed. The channel region 11 formed between the source / drain regions 7 of the fourth n-type field effect transistor Tn4 is a gate electrode of the first p-type field effect transistor Tp1 when viewed from the normal direction of the semiconductor substrate 1. 6 is formed so as to overlap.

Although not shown in FIG. 3, a second p-type field effect transistor Tp2 and second and third n-type field effect transistors Tn2 and Tn3 are also formed, and the third n-type field effect transistor Tn3 is also formed. The channel region is formed so as to overlap the gate electrode of the second p-type field effect transistor Tp2 when viewed from the normal direction of the semiconductor substrate 1.

In addition, this invention is not limited to this embodiment thru | or the following embodiment, A various change can be used.

The manufacturing process of the semiconductor memory device of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 4A, an element isolation region 2 is formed on a silicon substrate 1 by a method such as shallow trench isolation (STI).

Next, as shown in FIG. 4B, for example, As (arsenic) is implanted into the p-type field effect transistor formation region of the semiconductor substrate 1, and B (boron) is introduced into the n-type field effect transistor formation region of the semiconductor substrate 1, for example. And then a thermal process is performed to form n well region 3 and p well region 4. It is possible to introduce an impurity only into a specific region by using a method such as a photo-etching method or a lithography process.

Next, as shown in FIG. 4C, an HfO ₂ film 12 having a thickness of 5 nm is formed on the semiconductor substrate 1 by a method such as chemical vapor deposition.

Next, as shown in FIG. 4D, a tungsten film 13 having a thickness of 50 nm is formed by a method such as chemical vapor deposition.

Next, as shown in FIG. 4E, a part of the tungsten film 13 is selectively removed by performing a process such as an active ion etching method to form the gate electrode 6. Subsequently, a part of the HfO ₂ film 12 is selectively removed by performing a process such as an active ion etching method, and the gate insulating film 5 is formed.

Next, as shown in FIG. 5F, for example, B is implanted into the p-type field effect transistor formation region, and As is implanted into the n-type field effect transistor formation region, the extension region 14 is formed.

Next, as shown in FIG. 5G, a silicon oxide film (not shown) having a thickness of 20 nm is formed by a method such as chemical vapor deposition. Subsequently, a part of the silicon oxide film is selectively removed by etching back by, for example, an active ion etching method, and the gate sidewall 8 is formed.

Next, as shown in FIG. 5 (h), for example, B is implanted into the p-type field effect transistor formation region, As is implanted into the n-type field effect transistor formation region, and a thermal process is performed. At the same time, source / drain regions 7 are formed.

Next, as shown in FIG. 5I, a silicon oxide film (not shown) having a thickness of 100 nm is formed on the entire surface of the semiconductor substrate 1 by a method such as chemical vapor deposition, and planarization is performed. Thus, the interlayer insulating film 9 is formed. And although illustration is abbreviate | omitted, the wiring process etc. similar to a prior art are performed.

Next, as shown in FIG. 6J, a 20 nm thick silicon layer (not shown) containing B is formed on the interlayer insulating film 9 by a method such as chemical vapor deposition, for example. Element isolation is performed by a method such as a mesa element isolation method to form the semiconductor layer 10.

Next, as shown in FIG. 6 (k), an HfO ₂ film (not shown) having a thickness of 5 nm is formed on the semiconductor layer 10 by a method such as chemical vapor deposition. Subsequently, a 50 nm-thickness tungsten film (not shown) is formed on the HfO ₂ film (not shown) by a method such as chemical vapor deposition. Then, a part of the tungsten film (not shown) is selectively removed, for example, by performing a process such as an active ion etching method, and the gate electrode 6 is formed. Subsequently, the gate insulating film 5 is formed by selectively removing a part of the HfO ₂ film (not shown) by, for example, active ion etching.

Next, as shown in FIG. 6L, an extension region 14 is formed in the surface portion of the semiconductor layer 10 by implanting, for example, As. Next, a silicon oxide film (not shown) having a thickness of 20 nm is formed by a method such as chemical vapor deposition. Subsequently, a part of the silicon oxide film is selectively removed by etching back by, for example, an active ion etching method, and the gate sidewall 8 is formed.

Next, for example, As is implanted, and the source / drain region 7 is formed together with the extension region 14 by performing a thermal process. Thereafter, the structure shown in FIG. 3 is formed through an interlayer insulating film forming process, a wiring process, and the like in the same manner as the prior art.

In this embodiment, the case where a semiconductor memory device is formed using a bulk substrate has been described as an example, but the same applies to a semiconductor substrate in which a semiconductor layer is formed on a support substrate via an insulating film. In addition, a semiconductor memory device can be formed, and similar effects can be obtained. In addition, when an element is formed using a semiconductor substrate having the above structure, the same effect can be obtained by forming an element having a structure in which gate electrodes are provided above and below a channel region in an element formed on a semiconductor layer. It is done. Such a structure is preferable because controllability of the gate electrode with respect to the potential of the channel region can be improved.

Further, in the present embodiment, the case of a planar structure element is shown as an example. However, in an element formed on a semiconductor substrate, for example, a FinFET, a triple gate (Triple Gate)
Similar effects can be obtained in the case of a three-dimensional element such as a structure, a gate all around structure, and a vertical structure. It is preferable to form a semiconductor memory device using an element having such a structure because the controllability of the gate electrode with respect to the potential of the channel region can be improved.

In the present embodiment, the formation process of only a single semiconductor memory device is shown. In addition to a single semiconductor memory device, active elements such as a field effect transistor, a bipolar transistor, and a single electron transistor, The present invention can also be used when a semiconductor memory device is formed as a part of a semiconductor device including a passive element such as a resistor, a diode, an inductor, a capacitor, or an element using a magnetic material, for example. The same applies to the case where the semiconductor memory device is formed as a part of OEIC (Optical Electrical Integrated Circuit) or MEMS (Micro Electro Mechanical System).

In this embodiment, As (arsenic) is used as the impurity for forming the n-type semiconductor region, and B (boron) is used as the impurity for forming the p-type semiconductor region. Another group V impurity may be used as an impurity for forming the region, or another group III impurity may be used as an impurity for forming the p-type semiconductor region. The introduction of Group III or Group V impurities may be carried out in the form of a compound containing them.

In this embodiment, the introduction of impurities into the source / drain regions is performed using ion implantation, but may be performed using a method other than ion implantation such as solid phase diffusion or vapor phase diffusion. Furthermore, a method of depositing or growing a semiconductor containing impurities may be used. When the ion implantation method is used, there is an advantage that it is easy to form a complementary semiconductor device including an n-type semiconductor element and a p-type semiconductor element. When impurities are introduced using a method such as vapor phase diffusion, there is an advantage that it is easy to realize a high impurity concentration.

Although not mentioned in this embodiment, a stressor may be formed on the source / drain regions. It is preferable to apply strain to the channel region in this manner because the mobility of current carriers is improved.

In this embodiment, no impurity is introduced for adjusting the threshold voltage of the element, but an impurity for adjusting the threshold voltage separately from the introduction of the impurity into the silicon substrate for forming the well region. You may introduce. In this way, there is an advantage that the threshold voltage can be easily set to a desired value. In addition, the present embodiment has an advantage that the process can be simplified.

In this embodiment, silicon is used as a semiconductor layer for forming an element. However, the semiconductor layer is not limited to silicon, and germanium or a mixed crystal of silicon and germanium may be used. Germanium or a mixed crystal of silicon and germanium is preferable because it has an advantage of higher mobility of current carriers than silicon.

Alternatively, a semiconductor that is a compound of a group III element and a group V element may be used as a semiconductor layer forming the element. Such compounds are also preferred because they have the advantage of higher current carrier mobility than silicon. In particular, InAs (indium arsenide), In _x Ga _1-x As (0 ≦ x ≦ 1) (indium gallium arsenide), InSb (indium antimony), and the like are preferable because the mobility of current carriers is particularly high. It is also preferable to apply strain to the channel region because mobility can be improved. On the other hand, when silicon is used as the semiconductor layer, the conventional manufacturing process can be used as it is, which has another advantage that the manufacturing process can be easily constructed.

In this embodiment, the source / drain regions are formed after the processing of the gate electrode and the gate insulating film. However, the order is not essential, and the order may be reversed. Depending on the material of the gate electrode or the gate insulating film, it may not be preferable to perform the thermal process. In such a case, it is preferable to perform an impurity introduction and activation thermal process in the source / drain regions prior to processing of the gate electrode or the gate insulating film.

In this embodiment, the gate electrode is formed using tungsten, but may be formed using another metal. Alternatively, a semiconductor such as single crystal silicon or amorphous silicon, a compound containing a metal, or a stacked layer thereof may be used. When a gate electrode is formed using a semiconductor, there is an advantage that the threshold voltage can be easily controlled. When a complementary semiconductor device is formed, either an n-type semiconductor element or a p-type semiconductor element is used. However, there is another advantage that it is easy to set the threshold voltage to a desired value. In addition, it is preferable to form the gate electrode using a metal or a compound containing a metal because resistance of the gate electrode is suppressed, so that high-speed operation of the device can be obtained. Further, when the gate electrode is formed of metal, the oxidation reaction does not proceed easily, so that there is an advantage that the interface controllability such as suppression of the level at the interface between the gate electrode and the insulating film is good.

In this embodiment, the gate electrode is formed using a method in which anisotropic etching is performed after depositing the material. For example, a method such as embedding such as a damascene process is used. May be formed. In the case where the source / drain regions are formed prior to the formation of the gate electrode, it is preferable to use a damascene process because the source / drain regions and the gate electrode are formed in a self-aligned manner.

In the present embodiment, the length of the gate electrode measured in the main direction of the current flowing through the element is equal to the upper part and the lower part of the gate electrode, but this is not essential. For example, the length of the upper part of the gate electrode measured in the shape of an alphabet “T” may be longer than the length measured in the lower part. In this case, there is an advantage that the gate resistance can be reduced.

In the present embodiment, although the silicide or germanide process is not mentioned, a silicide or germanide layer or the like may be formed on the source / drain region. Alternatively, a method of depositing or growing a layer containing a metal on the source / drain regions may be used. This is preferable because the resistance of the source / drain regions is reduced. When the gate electrode is formed of polycrystalline silicon or the like, a process such as silicide or germanide may be performed on the gate electrode. In that case, it is preferable to perform a process such as silicide or germanide because the gate resistance is reduced. Further, an elevator structure may be used. The elevated structure is also preferable because the resistance of the source / drain regions is reduced.

In this embodiment, the upper part of the gate electrode has a structure in which the electrode is exposed, but an insulator such as silicon oxide, silicon nitride, or silicon oxynitride may be provided on the upper part. In particular, when the gate electrode is formed of a material containing metal and a silicide or germanide layer or the like is formed on the source / drain region, the gate electrode needs to be protected during the manufacturing process, etc. It is essential to provide a protective material such as silicon oxide, silicon nitride, or silicon oxynitride on the gate electrode.

In this embodiment, the HfO ₂ film is used as the gate insulating film. However, an insulating film such as a silicon oxide film or a silicon oxynitride film, or another insulating film such as a stacked layer thereof may be used. When nitrogen is present in the insulating film, when polycrystalline silicon containing impurities is used as the gate electrode, it is suppressed that the impurities are diffused into the substrate, so that variation in threshold voltage is suppressed. This is preferable because of its advantages. On the other hand, when silicon oxide is used, there is an advantage that variation in device characteristics is suppressed because there are few interface states at the interface with the gate electrode or fixed charges in the insulating film.

Further, when an oxide of a certain substance is used as the insulating film, a method of first forming a film of the substance and oxidizing it may be used. Moreover, you may expose to the oxygen gas of the excited state which does not necessarily accompany temperature rising. Forming by using a method of exposing to an excited oxygen gas that is not accompanied by an increase in temperature is preferable because impurities in the channel region can be prevented from changing the concentration distribution due to diffusion.

Further, when silicon oxynitride is used, first, a silicon oxide film may be formed, and then nitrogen may be introduced into the insulating film by exposure to a gas containing nitrogen in a heated or excited state. Forming by using a method of exposing to an excited nitrogen gas that is not accompanied by an increase in temperature is preferable because the concentration distribution of the impurities in the channel region can be suppressed by diffusion. Alternatively, first, a silicon nitride film may be formed, and then oxygen may be introduced into the insulating film by exposure to a gas containing oxygen in a heated or excited state. Forming by using a method of exposing to an excited oxygen gas that is not accompanied by an increase in temperature is preferable because impurities in the channel region can be prevented from changing the concentration distribution due to diffusion.

In addition, Hf (hafnium), Zr (zirconium), Ti (titanium), Sc (scandium), Y (yttrium), Ta (tantalum), Al (aluminum), La (lanthanum), Ce (cerium), Pr (praseodymium) Or other oxides of metals such as other lanthanoid series elements, silicate materials containing various elements such as these elements, or insulating films containing nitrogen in them. Other insulating films such as a body film or a laminate thereof may be used. The method for forming the insulating film is not limited to the chemical vapor deposition method, and other methods such as a thermal oxidation method, a vapor deposition method, a sputtering method, or an epitaxial growth method may be used.

In the present embodiment, post-oxidation after the formation of the gate electrode is not mentioned, but a post-oxidation step may be performed if possible in view of the material of the gate electrode. Further, the process is not necessarily limited to post-oxidation, and a process of rounding the corners of the gate electrode may be performed using a method such as chemical treatment or exposure to a reactive gas. If these steps are possible, the electric field at the lower end corner of the gate electrode is relaxed, which improves the reliability of the gate insulating film, which is preferable.

In this embodiment, the silicon oxide film is used as the interlayer insulating film. However, a substance other than silicon oxide such as a low dielectric constant material may be used for the interlayer insulating film. If the dielectric constant of the interlayer insulating film is set low, there is an advantage that high-speed operation of the device can be obtained because the parasitic capacitance of the device is reduced.

Also, although no mention is made of contact holes, it is possible to form self-aligned contacts. The use of the self-aligned contact is preferable because the area of the element can be reduced, and the degree of integration can be improved.

Although not specified in the present embodiment, the formation of the metal layer for wiring may be performed using, for example, a sputtering method or a method such as a deposition method. Furthermore, a method such as selective growth of metal may be used, or a method such as damascene method may be used. Further, as the material of the wiring metal, for example, Al (aluminum) containing silicon may be used, or a metal such as Cu (copper) may be used. In particular, Cu is preferable because of its low resistivity.

Although not specified in this embodiment, the semiconductor layer formed on the interlayer insulating film may be crystallized. Since crystallization increases the carrier mobility, there is an advantage that the operation speed can be improved.

Further, the schematic diagram of the structure of this embodiment is merely an example, and the arrangement of the field effect transistor in the direction perpendicular to the surface of the semiconductor substrate is essential, but the arrangement in the direction parallel to the surface of the semiconductor substrate is essential. is not. Even if other arrangements are used, the same effect can be obtained. Also, the arrangement or shape of the wiring is not essential, and the same effect can be obtained with other arrangements or shapes as long as the connection relationship is maintained.

Next, the results of numerical calculations regarding the semiconductor memory device having the structure of this embodiment will be described. The gate length of the element is 25 nm, the first and second p-type field effect transistors Tp1 and Tp2 have the same characteristics, and the first to fourth n-type field effect transistors Tn1 to Tn4 are all the same. It was set as the element of the characteristic. The gate insulating film was made of silicon oxide having a thickness of 1 nm.

Fig. 7 shows the butterfly curve (Butterfly Curve) when there is no fluctuation in the threshold voltage. In FIG. 7, the drain region of the first p-type field effect transistor Tp1, the drain region of the first n-type field effect transistor Tn1, the gate electrode of the second p-type field effect transistor Tp2, and the second n-type. The potential at the connection point between the gate electrode of the n-type field effect transistor Tn2 and the drain region of the third n-type field effect transistor Tn3 is V1, and the drain region of the second p-type field effect transistor Tp2 is The drain region of the second n-type field effect transistor Tn2, the gate electrode of the first p-type field effect transistor Tp1, the gate electrode of the first n-type field effect transistor Tn1, and the drain region of the fourth n-type field effect transistor Tn4 The potential at the connection point connected to each other is denoted as V2.

At the time of writing, the potential of the bit line BL is the power supply voltage, the potential of the inverted bit line BL ′ is the ground potential, and after the writing, the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL V1 and V2 are P1 in the figure. In addition, the potential of the bit line BL is set to the ground potential and the potential of the inverted bit line BL ′ is set to the power supply voltage at the time of writing, and the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL after the writing. V1 and V2 become P2 in the figure.

The shape of the butterfly curve changes due to noise, and when the closed curve of L1 in the figure disappears, the state of P1 becomes unstable and becomes the state of P2 regardless of whether the previous state was P1 or P2. Also, the shape of the butterfly curve changes due to noise, and when the closed curve of L2 in the figure disappears, the state of P2 becomes unstable and becomes the state of P1 regardless of whether the previous state was P1 or P2. That is, in any case, the stored information is lost. Therefore, the larger the closed curve of L1 or L2, the larger the upper limit of the magnitude of noise that does not lose information. An index indicating the upper limit is the above-described SNM, and a specific value is included in L1 or L2 and the side is the largest of the squares parallel to the vertical and horizontal axes in the figure, that is, SQ1 or SQ2 respectively. Is given by the length of the side. In the example shown here, the SNM indicating the stability of P1 (ie, the length of the side of SQ1) and the SNM indicating the stability of P2 (ie, the length of the side of SQ2) are equal to 0.144V.

Next, consider the semiconductor memory device of this embodiment. First, consider a case where the potential of the bit line BL is set to the power supply voltage and the potential of the inverted bit line BL ′ is set to the ground potential at the time of writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P1. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 0.18V, and the gate electrode of the second p-type field effect transistor Tp2 is 1.0V. Therefore, the second p-type is compared with the threshold voltage of the fourth n-type field effect transistor Tn4 in which the channel region is formed on the gate electrode of the first p-type field effect transistor Tp1. The threshold voltage of the third n-type field effect transistor Tn3 where the channel region is formed on the gate electrode of the field effect transistor Tp2 changes in the negative direction.

Therefore, here, the threshold voltage of the third n-type field effect transistor Tn3 changes by 50 mV in the negative direction as compared with the case shown in FIG. 7, and the threshold of the fourth n-type field effect transistor Tn4 is changed. A butterfly curve was calculated on the assumption that the value voltage was changed by 50 mV in the positive direction. In other words, the threshold voltage in the case where there is no change is adjusted so that the threshold voltage of the both becomes the value described here as a result of the change. The results are shown in FIG. 8A. Compared to the case where there is no change in the threshold voltage shown in FIG. 7, the closed curve L1 is larger, and accordingly, the square SQ1 representing the SNM indicating the stability of P1 is also larger. I understand. The specific value of SNM in this case is 0.170V.

Next, consider a case where the potential of the bit line BL is set to the ground potential and the potential of the inverted bit line BL ′ is set to the power supply voltage at the time of writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P2. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 1.0V, and the gate electrode of the second p-type field effect transistor Tp2 is 0.18V. Therefore, the first p-type is compared with the threshold voltage of the third n-type field effect transistor Tn3 in which the channel region is formed on the gate electrode of the second p-type field effect transistor Tp2. The threshold voltage of the fourth n-type field effect transistor Tn4 where the channel region is formed on the gate electrode of the field effect transistor Tp1 changes in the negative direction.

Therefore, here, the threshold voltage of the third n-type field effect transistor Tn3 changes by 50 mV in the positive direction as compared with the case shown in FIG. 7, and the threshold of the fourth n-type field effect transistor Tn4 is changed. The butterfly curve was calculated on the assumption that the value voltage was changed by 50 mV in the negative direction. In other words, the threshold voltage in the case where there is no change is adjusted so that the threshold voltage of the both becomes the value described here as a result of the change. The results are shown in FIG. 8B. In this case, it becomes a curve in which the vertical axis and the horizontal axis of the butterfly curve shown in FIG. 8A are interchanged. Compared to the case where there is no change in the threshold voltage shown in FIG. 7, the closed curve L2 is larger, and accordingly, the square SQ2 representing the SNM indicating the stability of P2 is also larger. I understand. The specific value of the SNM in this case is 0.170 V, which is the same as that shown in FIG. 8A.

Therefore, compared with the semiconductor memory device having the conventional structure in which the threshold voltage does not change, the semiconductor memory device of this embodiment has an increased SNM, that is, improved resistance to noise. I know that.

The reason why the SNM is increased in the semiconductor memory device of this embodiment is that the channel regions of the third and fourth n-type field effect transistors Tn3 and Tn4 are the second and first p-type electric fields, respectively. As a result of overlapping the gate electrodes of the effect transistors Tp2 and Tp1, the gate electrodes of the second and first p-type field effect transistors Tp2 and Tp1 are effectively third and fourth n-type, respectively. It is to act as the back gate electrode of the field effect transistors Tn3 and Tn4. Even if the channel regions of the third and fourth n-type field effect transistors Tn3 and Tn4 are formed so as to overlap the gate electrodes of the second and first p-type field effect transistors Tp2 and Tp1, respectively, If the fourth n-type field effect transistors Tn3 and Tn4 have a structure other than a planar structure such as a columnar structure, the threshold voltage does not change, so the effect of the present embodiment cannot be obtained. Therefore, it is essential that the third and fourth n-type field effect transistors Tn3 and Tn4 have a planar structure.

In the present embodiment, the channel regions of the third and fourth n-type field effect transistors Tn3 and Tn4 are formed so as to overlap the gate electrodes of the second and first p-type field effect transistors Tp2 and Tp1, respectively. Yes. As a result, the increase in the SNM is essential because the gate electrodes of the second and first p-type field effect transistors Tp2 and Tp1 are effectively third and fourth n respectively. This is because it functions as the back gate electrode of the type field effect transistors Tn3 and Tn4. Therefore, the channel regions of the third and fourth n-type field effect transistors Tn3 and Tn4 are not necessarily formed so as to overlap the gate electrodes of the second and first p-type field effect transistors Tp2 and Tp1, respectively. The same effect can be obtained even if they are formed so as to overlap with the wirings connected to the gate electrodes of the second and first p-type field effect transistors Tp2 and Tp1, respectively.

The essence of increasing the SNM in the semiconductor memory device of this embodiment is that the gate electrodes of the second and first p-type field effect transistors Tp2 and Tp1 are effectively third and fourth, respectively. The threshold voltage of the third and fourth n-type field effect transistors Tn3 and Tn4 has changed as a result of acting as the back gate electrodes of the n-type field effect transistors Tn3 and Tn4. There is fluctuation in the electric potential at normal temperature, which is the thermal potential, ie, kT / q (k is Boltzmann's constant, T is 300 K at absolute temperature, ie, normal temperature, q is elementary charge, ie, 1.6 × 10 ⁻¹⁹ C, kT / q. Of room temperature is about 26 mV). Therefore, in order to obtain an increase in the stable region of the semiconductor memory device due to an increase in SNM, it is necessary to change the threshold voltage of the field effect transistor constituting the semiconductor memory device to three times the potential fluctuation, that is, about 78 mV. is there.

Using the elements used in the above numerical calculation, the change in threshold voltage accompanying the application of the voltage to the back gate electrode was calculated. By applying 1 V of the assumed power supply voltage to the back gate electrode, In order to obtain a change amount of the threshold voltage of 78 mV, it has been found that the thickness of the insulating film between the channel region and the back gate electrode needs to be 70 nm or less. Therefore, it is formed on the insulating film among the lower end of the channel region of the field effect transistor formed on the insulating film and the gate electrode of the field effect transistor formed on the semiconductor substrate and the wiring connected to the gate electrode. The distance measured in the direction perpendicular to the surface of the semiconductor substrate between the upper end of the region overlapping the channel region of the field effect transistor is preferably 70 nm or less.

Also, in the two cases described above, a voltage of 1V−0.18V = 0.82V, which is a difference in gate voltage value of the field effect transistor formed on the semiconductor substrate, is applied to the back gate electrode. Accordingly, it has been found that the thickness of the insulating film between the channel region and the back gate electrode needs to be 40 nm or less in order to obtain a change in threshold voltage of 78 mV. Therefore, it is formed on the insulating film among the lower end of the channel region of the field effect transistor formed on the insulating film and the gate electrode of the field effect transistor formed on the semiconductor substrate and the wiring connected to the gate electrode. More preferably, the distance measured in the direction perpendicular to the surface of the semiconductor substrate with respect to the upper end of the region overlapping the channel region of the field effect transistor is 40 nm or less.

(First modification of the first embodiment)
Next, a first modification of the first embodiment will be described.

The semiconductor memory device of this modification has the same circuit as that of the first embodiment shown in FIG. 1, but has a different three-dimensional structure. That is, in this modification, as schematically shown in FIG. 9, the first and second p-type field effect transistors Tp1, Tp2 and the first and second n-type field effect transistors Tn1 are formed on the semiconductor substrate. , Tn2 are formed, and third and fourth n-type field effect transistors Tn3, Tn4 are formed on the insulating film formed thereon. The channel region of the third n-type field effect transistor Tn3 is formed so as to overlap the gate electrode of the second n-type field effect transistor Tn2 when viewed from the normal direction of the semiconductor substrate. The channel region of the field effect transistor Tn4 is formed so as to overlap the gate electrode of the first n-type field effect transistor Tn1 when viewed from the normal direction of the semiconductor substrate.

The manufacturing process of the semiconductor memory device of this modification will be described with reference to FIG.

Subsequent to the steps shown in FIGS. 4A to 5I, as shown in FIG. 10A, B is formed on the interlayer insulating film 9 by a method such as chemical vapor deposition. A silicon layer (not shown) having a thickness of 20 nm including is formed, and element isolation is performed by a method such as a mesa element isolation method to form the semiconductor layer 10.

Next, as shown in FIG. 10B, an HfO ₂ film (not shown) having a thickness of 5 nm is formed on the semiconductor layer 10 by a method such as chemical vapor deposition. Subsequently, a 50 nm thick tungsten film (not shown) is formed on the HfO ₂ film (not shown) by a method such as chemical vapor deposition. Then, a part of the tungsten film (not shown) is selectively removed by subjecting the tungsten film (not shown), for example, to a gate electrode 6. Subsequently, a part of the HfO ₂ film (not shown) is selectively removed, for example, by performing a process such as an active ion etching method to form the gate insulating film 5.

Next, as shown in FIG. 10C, the extension region 14 is formed in the surface portion of the semiconductor layer 10 by implanting, for example, As. Subsequently, a silicon oxide film (not shown) having a thickness of 20 nm is formed by a method such as chemical vapor deposition. Thereafter, a part of the silicon oxide film is selectively removed by etching back using a method such as an active ion etching method, and the gate sidewall 8 is formed.

Next, for example, As is implanted, and the source / drain region 7 is formed together with the extension region 14 by performing a thermal process. Thereafter, the semiconductor memory device having the structure shown in FIG. 9 is formed through an interlayer insulating film forming process or a wiring process in the same manner as in the prior art.

The gate electrode of the first n-type field effect transistor Tn1 and the gate electrode of the first p-type field effect transistor Tp1 are connected to each other, and the gate electrode of the second n-type field effect transistor Tn2 is connected to the second p-type field effect transistor Tn2. The gate electrode of the type field effect transistor Tp2 is mutually connected. Therefore, the gate electrode of the first n-type field effect transistor Tn1 and the gate electrode of the first p-type field effect transistor Tp1 are at the same potential, and the gate electrode of the second n-type field effect transistor Tn2 And the gate electrode of the second p-type field effect transistor Tp2 have the same potential. Therefore, also in the semiconductor memory device of this modification, the same changes as in the semiconductor memory device of the above embodiment occur in the threshold voltages of the third and fourth n-type field effect transistors Tn3 and Tn4. Therefore, the semiconductor memory device of the present modification can achieve the same effects as those of the semiconductor memory device of the above embodiment.

Also in this modification, various modifications as described in the above embodiment are possible, and the same effect can be obtained.

(Second modification of the first embodiment)
Next, a second modification of the first embodiment will be described.

The semiconductor memory device of this modification has the same circuit as that of the first embodiment shown in FIG. 1, but has a different three-dimensional structure. That is, in this modification, as schematically shown in FIG. 11, the first and second p-type field effect transistors Tp1, Tp2 and the first and second n-type field effect transistors Tn1 are formed on the semiconductor substrate. , Tn2 are formed, and third and fourth n-type field effect transistors Tn3, Tn4 are formed on the insulating film formed thereon. The channel region of the third n-type field effect transistor Tn3 is formed so as to overlap the gate electrode of the second p-type field effect transistor Tp2 when viewed from the normal direction of the semiconductor substrate. The channel region of the field effect transistor Tn4 is formed so as to overlap the gate electrode of the first n-type field effect transistor Tn1 when viewed from the normal direction of the semiconductor substrate.

The manufacturing process of the semiconductor memory device according to the present modification is essentially the same as the manufacturing process according to the first embodiment or the first modification, and a description thereof will be omitted.

(Third Modification of First Embodiment)
Next, a third modification of the first embodiment will be described.

The semiconductor memory device of this modification has the same circuit as that of the first embodiment shown in FIG. 1, but has a different three-dimensional structure. That is, in this modification, as schematically shown in FIG. 12, the first and second p-type field effect transistors Tp1, Tp2 and the first and second n-type field effect transistors Tn1 are formed on the semiconductor substrate. , Tn2 are formed, and third and fourth n-type field effect transistors Tn3, Tn4 are formed on the insulating film formed thereon. The channel region of the third n-type field effect transistor Tn3 is formed so as to overlap the gate electrode of the second n-type field effect transistor Tn2 when viewed from the normal direction of the semiconductor substrate. The channel region of the field effect transistor Tn4 is formed so as to overlap the gate electrode of the first p-type field effect transistor Tp1 when viewed from the normal direction of the semiconductor substrate.

The manufacturing process of the semiconductor memory device of the present modification is essentially the same as the manufacturing process of the first embodiment or the first or second modification thereof, and will not be described.

(Second Embodiment)
Next, a second embodiment of the semiconductor memory device of the present invention will be described.

FIG. 13 is a bird's eye view showing a schematic structure of a semiconductor memory device according to the second embodiment of the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

The semiconductor memory device of this embodiment has the same circuit as that of the first embodiment shown in FIG. 1, but the first and second p-type electric fields are schematically shown in FIG. The effect transistors Tp1, Tp2 and the third and fourth n-type field effect transistors Tn3, Tn4 are formed on the semiconductor substrate, and the first and second n-type electric fields are formed on the interlayer insulating film formed thereon. Effect transistors Tn1 and Tn2 are formed. The channel region of the first n-type field effect transistor Tn1 is formed so as to overlap the gate electrode of the first p-type field effect transistor Tp1 when viewed from the normal direction of the semiconductor substrate, and the second region The channel region of the n-type field effect transistor Tn2 is formed so as to overlap the gate electrode of the second p-type field effect transistor Tp2 when viewed from the normal direction of the semiconductor substrate.

The manufacturing process of the semiconductor memory device of the present embodiment is essentially the same as the manufacturing process of the first embodiment or its modification, and will not be described.

Next, the result of numerical calculation regarding the semiconductor memory device having the structure of this embodiment will be described. First,
Consider a case where the potential of the bit line BL is the power supply voltage and the potential of the inverted bit line BL ′ is the ground potential during writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P1. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 0.18V, and the gate electrode of the second p-type field effect transistor Tp2 is 1.0V. Therefore, the second p-type is compared with the threshold voltage of the first n-type field effect transistor Tn1 in which the channel region is formed on the gate electrode of the first p-type field effect transistor Tp1. The threshold voltage of the second n-type field effect transistor Tn2 where the channel region is formed on the gate electrode of the field effect transistor Tp2 changes in the negative direction.

Therefore, here, compared with the case shown in FIG. 7, the threshold voltage of the first n-type field effect transistor Tn1 changes by 50 mV in the positive direction, and the second n-type field effect transistor Tn2 has a threshold voltage. The butterfly curve was calculated on the assumption that the threshold voltage had changed by 50 mV in the negative direction. In other words, the threshold voltage in the case where there is no change is adjusted so that the threshold voltage of the both becomes the value described here as a result of the change. The results are shown in FIG. 14A. It can be seen that the closed curve L1 is larger than that in the case where there is no change in the threshold voltage shown in FIG. 7, and accordingly, the square SQ1 representing the SNM indicating the stability of P1 is also increased. . The specific value of SNM in this case is 0.188V.

Next, consider a case where the potential of the bit line BL is set to the ground potential and the potential of the inverted bit line BL ′ is set to the power supply voltage at the time of writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P2. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 1.0V, and the gate electrode of the second p-type field effect transistor Tp2 is 0.18V. Therefore, the butterfly curve is a curve in which the vertical axis and the horizontal axis in the case shown in FIG. 14A are interchanged. The results are shown in FIG. 14B. It can be seen that the closed curve L2 is larger than the case where there is no change in the threshold voltage shown in FIG. 7, and accordingly, the square SQ2 representing the SNM indicating the stability of P2 is also increased. . The specific value of SNM in this case is 0.188 V, which is the same as that shown in FIG. 14A.

Also in this embodiment, various modifications as described in the above embodiment are possible, and similar effects can be obtained.

(Modification of the second embodiment)
Next, a modification of the second embodiment will be described.

The semiconductor memory device of this modification has the same circuit as that of the first embodiment shown in FIG. 1, but has a different three-dimensional structure. That is, in the present modification, as schematically shown in FIG. 15, the first to fourth n-type field effect transistors Tn1 to Tn4 are formed on the semiconductor substrate, and the interlayer insulation formed thereon is formed. First and second p-type field effect transistors Tp1 and Tp2 are formed on the film. The channel region of the first p-type field effect transistor Tp1 is formed so as to overlap the gate electrode of the first n-type field effect transistor Tn1 when viewed from the normal direction of the semiconductor substrate, and the second region The channel region of the p-type field effect transistor Tp2 is formed so as to overlap the gate electrode of the second n-type field effect transistor Tn2 when viewed from the normal direction of the semiconductor substrate.

The manufacturing process of the semiconductor memory device of the present modification is essentially the same as the manufacturing process of the above-described embodiment or its modification, and will not be described.

Next, the results of numerical calculations related to the semiconductor memory device having the modified structure will be described. First, consider a case where the potential of the bit line BL is set to the power supply voltage and the potential of the inverted bit line BL ′ is set to the ground potential at the time of writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P1. Therefore, the gate electrode of the first n-type field effect transistor Tn1 is 0.18V, and the gate electrode of the second n-type field effect transistor Tn2 is 1.0V. Therefore, compared with the threshold voltage of the first p-type field effect transistor Tp1 in which the channel region is formed on the gate electrode of the first n-type field effect transistor Tn1, the second n-type The threshold voltage of the second p-type field effect transistor Tp2 in which the channel region is formed on the gate electrode of the field effect transistor Tn2 changes in the negative direction.

Therefore, here, the threshold voltage of the first p-type field effect transistor Tp1 changes by 50 mV in the positive direction as compared with the case shown in FIG. 7, and the second p-type field effect transistor Tp2 has a threshold voltage. The butterfly curve was calculated on the assumption that the threshold voltage had changed by 50 mV in the negative direction. In other words, the threshold voltage in the case where there is no change is adjusted so that the threshold voltage of the both becomes the value described here as a result of the change. The results are shown in FIG. 16A. It can be seen that the closed curve L1 is larger than that in the case where there is no change in the threshold voltage shown in FIG. 7, and accordingly, the square SQ1 representing the SNM indicating the stability of P1 is also increased. . The specific value of SNM in this case is 0.156V.

Next, consider a case where the potential of the bit line BL is set to the ground potential and the potential of the inverted bit line BL ′ is set to the power supply voltage at the time of writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P2. Therefore, the gate electrode of the first n-type field effect transistor Tn1 is 1.0V, and the gate electrode of the second n-type field effect transistor Tn2 is 0.18V. Therefore, the butterfly curve is a curve in which the vertical axis and the horizontal axis in the case shown in FIG. 16A are interchanged. The results are shown in FIG. 16B. It can be seen that the closed curve L2 is larger than the case where there is no change in the threshold voltage shown in FIG. 7, and accordingly, the square SQ2 representing the SNM indicating the stability of P2 is also increased. . The specific value of the SNM in this case is 0.156 V, which is the same as that shown in FIG. 16A.

(Third embodiment)
Next, a third embodiment of the semiconductor memory device of the present invention will be described.

FIG. 17 is a bird's eye view showing a schematic structure of a semiconductor memory device according to the third embodiment of the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

The semiconductor memory device of the present embodiment has a circuit similar to that of the first embodiment shown in FIG. 1, but the first and second p-type electric fields as schematically shown in FIG. The effect transistors Tp1 and Tp2 are formed on a semiconductor substrate, and first to fourth n-type field effect transistors Tn1 to Tn4 are formed on an interlayer insulating film formed thereon. The channel regions of the first and fourth n-type field effect transistors Tn1 and Tn4 are formed so as to overlap the gate electrode of the first p-type field effect transistor Tp1 when viewed from the normal direction of the semiconductor substrate. The channel regions of the second and third n-type field effect transistors Tn2 and Tn3 are formed so as to overlap the gate electrode of the second p-type field effect transistor Tp2 when viewed from the normal direction of the semiconductor substrate. .

The manufacturing process of the semiconductor memory device of the present embodiment is essentially the same as the manufacturing process of the above-described embodiment or its modification, and will not be described.

Next, the result of numerical calculation regarding the semiconductor memory device having the structure of this embodiment will be described. First,
Consider a case where the potential of the bit line BL is the power supply voltage and the potential of the inverted bit line BL ′ is the ground potential during writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P1. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 0.18V, and the gate electrode of the second p-type field effect transistor Tp2 is 1.0V. Therefore, compared with the threshold voltages of the first and fourth n-type field effect transistors Tn1 and Tn4 in which the channel region is formed on the gate electrode of the first p-type field effect transistor Tp1, The threshold voltages of the second and third n-type field effect transistors Tn2 and Tn3 where the channel region is formed on the gate electrode of the second p-type field effect transistor Tp2 change in the negative direction. is doing.

Therefore, here, compared with the case shown in FIG. 7, the threshold voltages of the first and fourth n-type field effect transistors Tn1 and Tn4 change by 50 mV in the positive direction, and the second and third The butterfly curve was calculated on the assumption that the threshold voltages of the n-type field effect transistors Tn2 and Tn3 were changed by 50 mV in the negative direction. That is, the threshold voltages in the case where there is no change are adjusted so that those threshold voltages become the values described here as a result of the change. The results are shown in FIG. 18A. It can be seen that the closed curve L1 is larger than that in the case where there is no change in the threshold voltage shown in FIG. 7, and accordingly, the square SQ1 representing the SNM indicating the stability of P1 is also increased. . The specific value of SNM in this case is 0.213V.

Next, consider a case where the potential of the bit line BL is set to the ground potential and the potential of the inverted bit line BL ′ is set to the power supply voltage at the time of writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P2. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 1.0V, and the gate electrode of the second p-type field effect transistor Tp2 is 0.18V. Therefore, the butterfly curve is a curve in which the vertical axis and the horizontal axis in the case illustrated in FIG. 18A are interchanged. The results are shown in FIG. 18B. It can be seen that the closed curve L2 is larger than the case where there is no change in the threshold voltage shown in FIG. 7, and accordingly, the square SQ2 representing the SNM indicating the stability of P2 is also increased. . The specific value of SNM in this case is 0.213 V, which is the same as that shown in FIG. 18A.

(Modification of the third embodiment)
Next, a modification of the third embodiment will be described.

The semiconductor memory device of this modification has the same circuit as that of the first embodiment shown in FIG. 1, but has a different three-dimensional structure. That is, in the present modification, as schematically shown in FIG. 19, the first and second n-type field effect transistors Tn1 and Tn2 are formed on the semiconductor substrate, and the interlayer insulation formed on them. First and second p-type field effect transistors Tp1 and Tp2 and third and fourth n-type field effect transistors Tn3 and Tn4 are formed on the film. The channel regions of the first p-type field effect transistor Tp1 and the fourth n-type field effect transistor Tn4 overlap with the gate electrode of the first n-type field effect transistor Tn1 when viewed from the normal direction of the semiconductor substrate. The channel regions of the second p-type field effect transistor Tp2 and the third n-type field effect transistor Tn3 are formed in the second n-type field effect transistor Tn2 as viewed from the normal direction of the semiconductor substrate. It is formed so as to overlap with the gate electrode.

Next, the result of numerical calculation regarding the semiconductor memory device having the structure of this embodiment will be described. First,
Consider a case where the potential of the bit line BL is the power supply voltage and the potential of the inverted bit line BL ′ is the ground potential during writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P1. Therefore, the gate electrode of the first n-type field effect transistor Tn1 is 0.18V, and the gate electrode of the second n-type field effect transistor Tn2 is 1.0V. Therefore, the threshold values of the first p-type field effect transistor Tp1 and the fourth n-type field effect transistor Tn4 in which the channel region is formed on the gate electrode of the first n-type field effect transistor Tn1. Compared to the voltage, the second p-type field effect transistor Tp2 and the third n-type field effect transistor Tn3 in which the channel region is formed on the gate electrode of the second n-type field effect transistor Tn2 are used. The threshold voltage is changing in the negative direction.

Therefore, here, compared with the case shown in FIG. 7, the threshold voltages of the first p-type field effect transistor Tp1 and the fourth n-type field effect transistor Tn4 change by 50 mV in the positive direction. The butterfly curve was calculated on the assumption that the threshold voltages of the p-type field effect transistor Tp2 and the third n-type field effect transistor Tn3 were changed by 50 mV in the negative direction. That is, the threshold voltages in the case where there is no change are adjusted so that those threshold voltages become the values described here as a result of the change. The results are shown in FIG. 20A. It can be seen that the closed curve L1 is larger than that in the case where there is no change in the threshold voltage shown in FIG. 7, and accordingly, the square SQ1 representing the SNM indicating the stability of P1 is also increased. . The specific value of SNM in this case is 0.182V.

Next, consider a case where the potential of the bit line BL is set to the ground potential and the potential of the inverted bit line BL ′ is set to the power supply voltage at the time of writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P2. Therefore, the gate electrode of the first n-type field effect transistor Tn1 is 1.0V, and the gate electrode of the second n-type field effect transistor Tn2 is 0.18V. Therefore, the butterfly curve is a curve in which the vertical axis and the horizontal axis in the case shown in FIG. 20A are interchanged. The results are shown in FIG. 20B. It can be seen that the closed curve L2 is larger than the case where there is no change in the threshold voltage shown in FIG. 7, and accordingly, the square SQ2 representing the SNM indicating the stability of P2 is also increased. . The specific value of the SNM in this case is 0.182 V, which is the same as that shown in FIG. 20A.

(Fourth embodiment)
Next, a fourth embodiment of the semiconductor memory device of the present invention will be described.

FIG. 21 is a bird's eye view showing a schematic structure of a semiconductor memory device according to the fourth embodiment of the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

The semiconductor memory device of this embodiment has the same circuit as that of the first embodiment shown in FIG. 1, but the first and second p-type electric fields are schematically shown in FIG. The effect transistors Tp1 and Tp2 are formed on a semiconductor substrate, and first to fourth n-type field effect transistors Tn1 to Tn4 are formed on an interlayer insulating film formed thereon. The channel region of the first n-type field effect transistor Tn1 is formed so as to overlap the gate electrode of the first p-type field effect transistor Tp1 when viewed from the normal direction of the semiconductor substrate, and the second region The channel region of the n-type field effect transistor Tn2 is formed so as to overlap the gate electrode of the second p-type field effect transistor Tp2 when viewed from the normal direction of the semiconductor substrate.

Therefore, here, compared with the case shown in FIG. 7, the threshold voltage of the first n-type field effect transistor Tn1 changes by 50 mV in the positive direction, and the second n-type field effect transistor Tn2 has a threshold voltage. The butterfly curve was calculated on the assumption that the threshold voltage had changed by 50 mV in the negative direction. That is, the threshold voltages in the case where there is no change are adjusted so that those threshold voltages become the values described here as a result of the change. The result is equal to the calculation result for the semiconductor memory device of the second embodiment shown in FIG. 14A. Therefore, the specific value of SNM in this case is 0.188V.

Next, consider a case where the potential of the bit line BL is set to the ground potential and the potential of the inverted bit line BL ′ is set to the power supply voltage at the time of writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P2. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 1.0V, and the gate electrode of the second p-type field effect transistor Tp2 is 0.18V. Therefore, the butterfly curve is equal to the calculation result for the semiconductor memory device of the second embodiment shown in FIG. 14B. Therefore, the specific value of SNM in this case is 0.188V.

(Modification of the fourth embodiment)
Next, a modification of the fourth embodiment will be described.

The semiconductor memory device of this modification has the same circuit as that of the first embodiment shown in FIG. 1, but the first and second n-type field effects are schematically shown in FIG. The transistors Tn1 and Tn2 are formed on a semiconductor substrate, and first and second p-type field effect transistors Tp1 and Tp2 and third and fourth n-type field effect transistors are formed on an interlayer insulating film formed thereon. Tn3 and Tn4 are formed. The channel region of the first p-type field effect transistor Tp1 is formed so as to overlap the gate electrode of the first n-type field effect transistor Tn1 when viewed from the normal direction of the semiconductor substrate, and the second region The channel region of the p-type field effect transistor Tp2 is formed so as to overlap the gate electrode of the second n-type field effect transistor Tn2 when viewed from the normal direction of the semiconductor substrate.

Next, the result of numerical calculation regarding the semiconductor memory device having the structure of this embodiment will be described. First,
Consider a case where the potential of the bit line BL is the power supply voltage and the potential of the inverted bit line BL ′ is the ground potential during writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P1. Therefore, the gate electrode of the first n-type field effect transistor Tn1 is 0.18V, and the gate electrode of the second n-type field effect transistor Tn2 is 1.0V. Therefore, compared with the threshold voltage of the first p-type field effect transistor Tp1 in which the channel region is formed on the gate electrode of the first n-type field effect transistor Tn1, the second n-type The threshold voltage of the second p-type field effect transistor Tp2 in which the channel region is formed on the gate electrode of the field effect transistor Tn2 changes in the negative direction.

Therefore, here, the threshold voltage of the first p-type field effect transistor Tp1 changes by 50 mV in the positive direction as compared with the case shown in FIG. 7, and the second p-type field effect transistor Tp2 has a threshold voltage. The butterfly curve was calculated on the assumption that the threshold voltage had changed by 50 mV in the negative direction. That is, the threshold voltages in the case where there is no change are adjusted so that those threshold voltages become the values described here as a result of the change. The result is equal to the calculation result for the modification of the second embodiment shown in FIG. 16A. Therefore, the specific value of SNM is 0.156V.

Next, consider a case where the potential of the bit line BL is set to the ground potential and the potential of the inverted bit line BL ′ is set to the power supply voltage at the time of writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P2. Therefore, the gate electrode of the first n-type field effect transistor Tn1 is 1.0V, and the gate electrode of the second n-type field effect transistor Tn2 is 0.18V. Therefore, the butterfly curve is equal to the calculation result in the case of the modification of the second embodiment shown in FIG. 16B. Therefore, the specific value of SNM is 0.156V.

(Fifth embodiment)
Next, a fifth embodiment of the semiconductor memory device of the present invention will be described.

FIG. 23 is a circuit diagram showing a semiconductor memory device according to the fifth embodiment of the present invention.

The same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

The semiconductor memory device of this embodiment has the same circuit as that of the first embodiment shown in FIG. 1, but the first and second p-type electric fields are schematically shown in FIG. The effect transistors Tp1 and Tp2 are formed on the semiconductor substrate, and the first to fourth n-type field effects are formed on the interlayer insulating film formed on the first and second p-type field effect transistors Tp1 and Tp2. Transistors Tn1 to Tn4 are formed. The channel region of the third n-type field effect transistor Tn3 is formed so as to overlap the gate electrode of the second p-type field effect transistor Tp2 when viewed from the normal direction of the semiconductor substrate, and the fourth The channel region of the n-type field effect transistor Tn4 is formed so as to overlap the gate electrode of the first p-type field effect transistor Tp1 when viewed from the normal direction of the semiconductor substrate.

Next, the result of numerical calculation regarding the semiconductor memory device having the structure of this embodiment will be described. First,
Consider a case where the potential of the bit line BL is the power supply voltage and the potential of the inverted bit line BL ′ is the ground potential during writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P1. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 0.18V, and the gate electrode of the second p-type field effect transistor Tp2 is 1.0V. Therefore, the second p-type is compared with the threshold voltage of the fourth n-type field effect transistor Tn4 in which the channel region is formed on the gate electrode of the first p-type field effect transistor Tp1. The threshold voltage of the third n-type field effect transistor Tn3 where the channel region is formed on the gate electrode of the field effect transistor Tp2 changes in the negative direction.

Therefore, here, compared with the case shown in FIG. 7, the threshold voltage of the third n-type field effect transistor Tn3 changes by 50 mV in the negative direction, and the fourth n-type field effect transistor Tn4 has a threshold voltage. The butterfly curve was calculated on the assumption that the threshold voltage was changed by 50 mV in the positive direction. That is, the threshold voltages in the case where there is no change are adjusted so that those threshold voltages become the values described here as a result of the change. The result is equal to the calculation result for the semiconductor memory device of the first embodiment shown in FIG. 8A. Therefore, the specific value of SNM in this case is 0.170V.

Next, consider a case where the potential of the bit line BL is set to the ground potential and the potential of the inverted bit line BL ′ is set to the power supply voltage at the time of writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P2. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 1.0V, and the gate electrode of the second p-type field effect transistor Tp2 is 0.18V. Therefore, the butterfly curve is equal to the calculation result for the semiconductor memory device of the first embodiment shown in FIG. 8B. Therefore, the specific value of SNM in this case is 0.170V.

(Modification of the fifth embodiment)
Next, a modification of the fifth embodiment will be described.

The semiconductor memory device of this modification has the same circuit as that of the first embodiment shown in FIG. 1, but has a different three-dimensional structure. That is, in this modification, as schematically shown in FIG. 24, the first and second n-type field effect transistors Tn1 and Tn2 are formed on the semiconductor substrate, and the interlayer insulation formed on them. First and second p-type field effect transistors Tp1 and Tp2 and third and fourth n-type field effect transistors Tn3 and Tn4 are formed on the film. The channel region of the third n-type field effect transistor Tn3 is formed so as to overlap the gate electrode of the second n-type field effect transistor Tn2 when viewed from the normal direction of the semiconductor substrate, and the fourth The channel region of the n-type field effect transistor Tn4 is formed to overlap the gate electrode of the first n-type field effect transistor Tn1 when viewed from the normal direction of the semiconductor substrate.

Next, the result of numerical calculation regarding the semiconductor memory device having the structure of this embodiment will be described. First,
Consider a case where the potential of the bit line BL is the power supply voltage and the potential of the inverted bit line BL ′ is the ground potential during writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P1. Therefore, the gate electrode of the first n-type field effect transistor Tn1 is 0.18V, and the gate electrode of the second n-type field effect transistor Tn2 is 1.0V. Therefore, as compared with the threshold voltage of the fourth n-type field effect transistor Tn4 in which the channel region is formed on the gate electrode of the first n-type field effect transistor Tn1, the second n-type The threshold voltage of the third n-type field effect transistor Tn3 where the channel region is formed on the gate electrode of the field effect transistor Tn2 changes in the negative direction.

Therefore, here, compared with the case shown in FIG. 7, the threshold voltage of the third n-type field effect transistor Tn3 changes by 50 mV in the negative direction, and the fourth n-type field effect transistor Tn4 has a threshold voltage. The butterfly curve was calculated on the assumption that the threshold voltage was changed by 50 mV in the positive direction. That is, the threshold voltages in the case where there is no change are adjusted so that those threshold voltages become the values described here as a result of the change. The result is equal to the calculation result for the first embodiment shown in FIG. 8A. Therefore, the specific value of SNM is 0.170V.

Next, consider a case where the potential of the bit line BL is set to the ground potential and the potential of the inverted bit line BL ′ is set to the power supply voltage at the time of writing. In this case, as described above, when the potential of the bit line BL, the potential of the inverted bit line BL ′, and the potential of the word line WL are at the power supply voltage after writing, V1 and V2 are P2. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 1.0V, and the gate electrode of the second p-type field effect transistor Tp2 is 0.18V. Therefore, the butterfly curve is equal to the calculation result for the first embodiment shown in FIG. 8B. Therefore, the specific value of SNM is 0.170V.

(Modification)
The present invention is not limited to the above-described embodiments.

With respect to overlapping the channel of the upper field effect transistor on the gate electrode of the lower field effect transistor, which is a feature of the present invention, the entire channel region of the upper transistor must necessarily overlap the gate electrode of the lower transistor. Instead, some of them may overlap. Further, the wiring may be overlapped with the wiring connected to the gate electrode, not the gate electrode itself. That is, at least a part of the channel region of the upper transistor may overlap with at least a part of the gate electrode of the lower transistor and a wiring connected to the gate electrode.

Further, the configuration of each transistor is not limited to the structure shown in FIG. 3, and can be appropriately changed according to the specification. Furthermore, the film thickness, material, and the like of each part can be appropriately changed according to the specifications.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

1 ... Silicon substrate (semiconductor substrate)
2 ... Element isolation region 3 ... n well region 4 ... p well region 5 ... gate insulating film 6 ... gate electrode 7 ... source / drain region 8 ... gate sidewall 9 ... interlayer insulating film 10 ... semiconductor layer 11 ... channel region 12 ... HfO ₂ films 13 ... tungsten film 14 ... extension area

Claims

A semiconductor substrate;
First and second p-type field effect transistors and first and second n-type field effect transistors formed on the semiconductor substrate;
An insulating film formed on the first and second p-type field effect transistors and on the first and second n-type field effect transistors;
Third and fourth n-type field effect transistors formed on the insulating film;
Including
Each source region and each substrate electrode of the first and second p-type field effect transistors are connected to a wiring whose potential is maintained at a power supply voltage, and each of the first and second n-type field effect transistors is The source region and each substrate electrode are connected to a wiring whose potential is kept at the ground potential,
Drain regions of the first p-type field effect transistor and the first n-type field effect transistor; gate electrodes of the second p-type field effect transistor and the second n-type field effect transistor; A drain region of the third n-type field effect transistor is connected to each other;
Drain regions of the second p-type field effect transistor and the second n-type field effect transistor; gate electrodes of the first p-type field effect transistor and the first n-type field effect transistor; A drain region of the fourth n-type field effect transistor is connected to each other;
Each gate electrode of the third and fourth n-type field effect transistors is connected to a word line,
A source region of the third n-type field effect transistor is connected to a bit line; a source region of the fourth n-type field effect transistor is connected to an inverted bit line;
The third and fourth n-type field effect transistors have a planar structure,
At least a part of the channel region of the third n-type field effect transistor includes a gate electrode of the second p-type field effect transistor, a wiring connected to the gate electrode, and the second n-type field effect transistor And at least part of the gate electrode and the wiring connected to the gate electrode so as to overlap when viewed from the normal direction of the semiconductor substrate,
At least a part of the channel region of the fourth n-type field effect transistor includes a gate electrode of the first p-type field effect transistor, a wiring connected to the gate electrode, and the first n-type field effect transistor A semiconductor memory device formed so as to overlap at least a part of the gate electrode and a wiring connected to the gate electrode when viewed from the normal direction of the semiconductor substrate.
A semiconductor substrate;
First and second p-type field effect transistors formed on the semiconductor substrate;
An insulating film formed on the first and second p-type field effect transistors;
First and second n-type field effect transistors formed on the insulating film;
Third and fourth n-type field effect transistors formed on the semiconductor substrate;
Including
Each source region and each substrate electrode of the first and second p-type field effect transistors are connected to a wiring whose potential is maintained at a power supply voltage, and each of the first and second n-type field effect transistors is The source region and each substrate electrode of the third and fourth n-type field effect transistors are connected to a wiring whose potential is kept at the ground potential,
Drain regions of the first p-type field effect transistor and the first n-type field effect transistor; gate electrodes of the second p-type field effect transistor and the second n-type field effect transistor; A drain region of the third n-type field effect transistor is connected to each other;
Drain regions of the second p-type field effect transistor and the second n-type field effect transistor; gate electrodes of the first p-type field effect transistor and the first n-type field effect transistor; A drain region of the fourth n-type field effect transistor is connected to each other;
Each gate electrode of the third and fourth n-type field effect transistors is connected to a word line,
A source region of the third n-type field effect transistor is connected to a bit line; a source region of the fourth n-type field effect transistor is connected to an inverted bit line;
The first and second n-type field effect transistors have a planar structure;
At least part of the channel region of the first n-type field effect transistor is formed on the gate electrode of the first p-type field effect transistor and at least part of the wiring connected to the gate electrode. It is formed to overlap when seen from the line direction,
At least part of the channel region of the second n-type field effect transistor is formed on the gate electrode of the second p-type field effect transistor and at least part of the wiring connected to the gate electrode. A semiconductor memory device formed so as to overlap when viewed from the line direction.
A semiconductor substrate;
First and second p-type field effect transistors formed on the semiconductor substrate;
An insulating film formed on the first and second p-type field effect transistors;
First to fourth n-type field effect transistors formed on the insulating film;
Including
Each source region and each substrate electrode of the first and second p-type field effect transistors are connected to a wiring whose potential is maintained at a power supply voltage, and each of the first and second n-type field effect transistors is The source region is connected to a wiring whose potential is kept at the ground potential,
Drain regions of the first p-type field effect transistor and the first n-type field effect transistor; gate electrodes of the second p-type field effect transistor and the second n-type field effect transistor; A drain region of the third n-type field effect transistor is connected to each other;
Drain regions of the second p-type field effect transistor and the second n-type field effect transistor; gate electrodes of the first p-type field effect transistor and the first n-type field effect transistor; A drain region of the fourth n-type field effect transistor is connected to each other;
Each gate electrode of the third and fourth n-type field effect transistors is connected to a word line,
A source region of the third n-type field effect transistor is connected to a bit line; a source region of the fourth n-type field effect transistor is connected to an inverted bit line;
The first to fourth n-type field effect transistors have a planar structure,
At least part of the channel region of the first n-type field effect transistor is formed on the gate electrode of the first p-type field effect transistor and at least part of the wiring connected to the gate electrode. It is formed to overlap when seen from the line direction,
At least part of the channel region of the second n-type field effect transistor is formed on the gate electrode of the second p-type field effect transistor and at least part of the wiring connected to the gate electrode. It is formed to overlap when seen from the line direction,
At least part of the channel region of the third n-type field effect transistor is formed on the gate electrode of the second p-type field effect transistor and at least part of the wiring connected to the gate electrode. It is formed to overlap when seen from the line direction,
At least part of the channel region of the fourth n-type field effect transistor is formed on the gate electrode of the first p-type field effect transistor and at least part of the wiring connected to the gate electrode. A semiconductor memory device formed so as to overlap when viewed from the line direction.
A semiconductor substrate;
First and second p-type field effect transistors formed on the semiconductor substrate;
An insulating film formed on the first and second p-type field effect transistors;
First to fourth n-type field effect transistors formed on the insulating film;
Including
Each source region and each substrate electrode of the first and second p-type field effect transistors are connected to a wiring whose potential is maintained at a power supply voltage, and each of the first and second n-type field effect transistors is The source region is connected to a wiring whose potential is kept at the ground potential,
The drain regions of the first p-type field effect transistor and the first n-type field effect transistor, the gate electrodes of the second p-type field effect transistor and the second n-type field effect transistor, and the first 3 are connected to the drain region of the n-type field effect transistor,
The drain regions of the second p-type field effect transistor and the second n-type field effect transistor, the gate electrodes of the first p-type field effect transistor and the first n-type field effect transistor, and the first 4 is connected to the drain region of the n-type field effect transistor,
Each gate electrode of the third and fourth n-type field effect transistors is connected to a word line,
A source region of the third n-type field effect transistor is connected to a bit line; a source region of the fourth n-type field effect transistor is connected to an inverted bit line;
The first and second n-type field effect transistors have a planar structure;
At least part of the channel region of the first n-type field effect transistor is formed on the gate electrode of the first p-type field effect transistor and at least part of the wiring connected to the gate electrode. It is formed to overlap when seen from the line direction,
At least part of the channel region of the second n-type field effect transistor is formed on the gate electrode of the second p-type field effect transistor and at least part of the wiring connected to the gate electrode. A semiconductor memory device, wherein the semiconductor memory devices are formed so as to overlap each other when viewed from the line direction.
A semiconductor substrate;
First and second p-type field effect transistors formed on the semiconductor substrate;
An insulating film formed on the first and second p-type field effect transistors;
First to fourth n-type field effect transistors formed on the insulating film;
Including
Each source region and each substrate electrode of the first and second p-type field effect transistors are connected to a wiring whose potential is maintained at a power supply voltage, and each of the first and second n-type field effect transistors is The source region is connected to a wiring whose potential is kept at the ground potential,
Drain regions of the first p-type field effect transistor and the first n-type field effect transistor; gate electrodes of the second p-type field effect transistor and the second n-type field effect transistor; A drain region of the third n-type field effect transistor is connected to each other;
Drain regions of the second p-type field effect transistor and the second n-type field effect transistor; gate electrodes of the first p-type field effect transistor and the first n-type field effect transistor; A drain region of the fourth n-type field effect transistor is connected to each other;
The gate electrodes of the third and fourth n-type field effect transistors are connected to a word line, the source region of the third n-type field effect transistor is connected to a bit line, and the fourth n-type field effect The source region of the transistor is connected to the inverted bit line,
The third and fourth n-type field effect transistors have a planar structure,
At least part of the channel region of the third n-type field effect transistor is formed on the gate electrode of the second p-type field effect transistor and at least part of the wiring connected to the gate electrode. It is formed to overlap when seen from the line direction,
At least part of the channel region of the fourth n-type field effect transistor is formed on the gate electrode of the first p-type field effect transistor and at least part of the wiring connected to the gate electrode. A semiconductor memory device, wherein the semiconductor memory devices are formed so as to overlap each other when viewed from the line direction.
A semiconductor substrate;
First to fourth n-type field effect transistors formed on the semiconductor substrate;
An insulating film formed on the first to fourth n-type field effect transistors;
First and second p-type field effect transistors formed on the insulating film;
Including
The source regions of the first and second p-type field effect transistors are connected to a wiring whose potential is maintained at a power supply voltage, and each of the source regions of the first and second n-type field effect transistors, The substrate electrodes of the first to fourth n-type field effect transistors are connected to a wiring whose potential is maintained at the ground potential,
Drain regions of the first p-type field effect transistor and the first n-type field effect transistor; gate electrodes of the second p-type field effect transistor and the second n-type field effect transistor; A drain region of the third n-type field effect transistor is connected to each other;
Drain regions of the second p-type field effect transistor and the second n-type field effect transistor; gate electrodes of the first p-type field effect transistor and the first n-type field effect transistor; A drain region of the fourth n-type field effect transistor is connected to each other;
The gate electrodes of the third and fourth n-type field effect transistors are connected to a word line, the source region of the third n-type field effect transistor is connected to a bit line, and the fourth n-type field effect The source region of the transistor is connected to the inverted bit line,
The first and second p-type field effect transistors have a planar structure;
At least a part of the channel region of the first p-type field effect transistor is formed on the gate electrode of the first n-type field effect transistor and at least a part of the wiring connected to the gate electrode. It is formed to overlap when seen from the line direction,
At least a part of the channel region of the second p-type field effect transistor is formed on the gate electrode of the second n-type field effect transistor and at least a part of the wiring connected to the gate electrode. A semiconductor memory device formed so as to overlap when viewed from the line direction.
A semiconductor substrate;
First and second n-type field effect transistors formed on the semiconductor substrate;
An insulating film formed on the first and second n-type field effect transistors;
First and second p-type field effect transistors and third and fourth n-type field effect transistors formed on the insulating film;
Including
Each source region of the first and second p-type field effect transistors is connected to a wiring whose potential is maintained at a power supply voltage, and each source region and each substrate of the first and second n-type field effect transistors The electrode is connected to the wiring whose potential is kept at the ground potential,
Drain regions of the first p-type field effect transistor and the first n-type field effect transistor; gate electrodes of the second p-type field effect transistor and the second n-type field effect transistor; A drain region of the third n-type field effect transistor is connected to each other;
Drain regions of the second p-type field effect transistor and the second n-type field effect transistor; gate electrodes of the first p-type field effect transistor and the first n-type field effect transistor; A drain region of the fourth n-type field effect transistor is connected to each other;
Each gate electrode of the third and fourth n-type field effect transistors is connected to a word line,
A source region of the third n-type field effect transistor is connected to a bit line; a source region of the fourth n-type field effect transistor is connected to an inverted bit line;
The first and second p-type field effect transistors and the third and fourth n-type field effect transistors have a planar structure,
At least a part of the channel region of the first p-type field effect transistor is formed on the gate electrode of the first n-type field effect transistor and at least a part of the wiring connected to the gate electrode. It is formed to overlap when seen from the line direction,
At least a part of the channel region of the second p-type field effect transistor is formed on the gate electrode of the second n-type field effect transistor and at least a part of the wiring connected to the gate electrode. It is formed to overlap when seen from the line direction,
At least part of the channel region of the third n-type field effect transistor is formed on the gate electrode of the second n-type field effect transistor and at least part of the wiring connected to the gate electrode. It is formed to overlap when seen from the line direction,
At least a part of the channel region of the fourth n-type field effect transistor is formed on the gate electrode of the first n-type field effect transistor and at least a part of the wiring connected to the gate electrode. A semiconductor memory device formed so as to overlap when viewed from the line direction.
A semiconductor substrate;
First and second n-type field effect transistors formed on the semiconductor substrate;
An insulating film formed on the first and second n-type field effect transistors;
First and second p-type field effect transistors and third and fourth n-type field effect transistors formed on the insulating film;
Including
Each source region of the first and second p-type field effect transistors is connected to a wiring whose potential is maintained at a power supply voltage, and each source region and each substrate of the first and second n-type field effect transistors The electrode is connected to the wiring whose potential is kept at the ground potential,
Drain regions of the first p-type field effect transistor and the first n-type field effect transistor; gate electrodes of the second p-type field effect transistor and the second n-type field effect transistor; A drain region of the third n-type field effect transistor is connected to each other;
Drain regions of the second p-type field effect transistor and the second n-type field effect transistor; gate electrodes of the first p-type field effect transistor and the first n-type field effect transistor; A drain region of the fourth n-type field effect transistor is connected to each other;
Each gate electrode of the third and fourth n-type field effect transistors is connected to a word line,
A source region of the third n-type field effect transistor is connected to a bit line; a source region of the fourth n-type field effect transistor is connected to an inverted bit line;
The first and second p-type field effect transistors have a planar structure;
At least a part of the channel region of the first p-type field effect transistor is formed on the gate electrode of the first n-type field effect transistor and at least a part of the wiring connected to the gate electrode. It is formed to overlap when seen from the line direction,
At least a part of the channel region of the second p-type field effect transistor is formed on the gate electrode of the second n-type field effect transistor and at least a part of the wiring connected to the gate electrode. A semiconductor memory device formed so as to overlap when viewed from the line direction.
A semiconductor substrate;
First and second n-type field effect transistors formed on the semiconductor substrate;
An insulating film formed on the first and second n-type field effect transistors;
First and second p-type field effect transistors and third and fourth n-type field effect transistors formed on the insulating film;
Including
Each source region of the first and second p-type field effect transistors is connected to a wiring whose potential is maintained at a power supply voltage, and each source region and each substrate of the first and second n-type field effect transistors The electrode is connected to the wiring whose potential is kept at the ground potential,
Drain regions of the first p-type field effect transistor and the first n-type field effect transistor; gate electrodes of the second p-type field effect transistor and the second n-type field effect transistor; A drain region of the third n-type field effect transistor is connected to each other;
Drain regions of the second p-type field effect transistor and the second n-type field effect transistor; gate electrodes of the first p-type field effect transistor and the first n-type field effect transistor; A drain region of the fourth n-type field effect transistor is connected to each other;
The gate electrodes of the third and fourth n-type field effect transistors are connected to a word line, the source region of the third n-type field effect transistor is connected to a bit line, and the fourth n-type field effect The source region of the transistor is connected to the inverted bit line,
The third and fourth n-type field effect transistors have a planar structure,
At least part of the channel region of the third n-type field effect transistor is formed on the gate electrode of the second n-type field effect transistor and at least part of the wiring connected to the gate electrode. It is formed to overlap when seen from the line direction,
At least a part of the channel region of the fourth n-type field effect transistor is formed on the gate electrode of the first n-type field effect transistor and at least a part of the wiring connected to the gate electrode. A semiconductor memory device formed so as to overlap when viewed from the line direction.
The field effect transistor formed on the insulating film among the gate electrode of the field effect transistor formed on the semiconductor substrate and a wiring connected to the gate electrode in a direction perpendicular to the surface of the semiconductor substrate. 10. The semiconductor memory device according to claim 1, wherein an interval between an upper end of a region overlapping with the channel region and a lower end of the channel region of the field effect transistor formed on the insulating film is 70 nm or less.
The field effect transistor formed on the insulating film among the gate electrode of the field effect transistor formed on the semiconductor substrate and a wiring connected to the gate electrode in a direction perpendicular to the surface of the semiconductor substrate. 10. The semiconductor memory device according to claim 1, wherein a distance between an upper end of a region overlapping with the channel region and a lower end of the channel region of the field effect transistor formed on the insulating film is 40 nm or less.