TW201444027A - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device comprises: a first and a second p-type field-effect transistors (Tp1, Tp2), and a first and a second n-type field-effect transistors (Tn1, Tn2) formed on a semiconductor substrate; an insulating film formed on each transistor; and a third and a fourth n-type field-effect transistors (Tn3, Tn4) formed on the insulating film. An SRAM is composed of these six transistors. Also, the transistors (Tn3, Tn4) have a planar structure; at least one portion of the channel region of the transistor (Tn3) is formed on at least one portion of gate electrodes of the transistors (Tp2, Tn2) in such a manner as to overlap when viewed from the normal direction of the semiconductor substrate; and at least one portion of the channel region of the transistor (Tn4) is formed on at least one portion of gate electrodes of the transistors (Tp1, Tn1) in such a manner as to overlap when viewed from the normal direction of the semiconductor substrate.

Description

Semiconductor memory device Field of invention

The embodiment of the present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which an SRAM (Static Random Access Memory) is fabricated in a three-dimensional structure.

Background of the invention

Although there is progress in the semiconductor integrated circuit to reduce the power supply voltage for low power consumption, one of the obstacles in its implementation is the static noise margin (SRAM) of the SRAM. . SNM is the upper limit of the size of the noise that does not lose the information that has been memorized. If the SNM is zero, the upper limit of the size of the noise that does not lose the memorized information is zero, that is, the information that has been memorized will be lost regardless of the noise. That is, since this means that noise is not allowed at all, such an SRAM cannot be used. In general, SNM is reduced with a lower voltage of the power supply voltage. Therefore, the voltage reduction of the power supply voltage is limited because of the reduction in SNM accompanying the low power supply voltage.

Advanced technical literature Non-patent literature

Non-Patent Document 1 Benton H. Calhoun, Anantha P. Chandrakasan, "Static Noise Margin Variation for Sub-threshold SRAM in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 41, no. 7, (2006) pp. 1673-1679

Summary of invention

As above, it is known that there is a contradiction between increasing the SNM and lowering the power supply voltage in the SRAM. Therefore, there is a limit to low power supply voltage regulation, in particular, an increase in SNM under a certain power supply voltage.

The problem to be solved by the invention is to provide a semiconductor memory device in which an increase in SNM can be achieved under a certain power supply voltage in an SRAM structure.

A semiconductor memory device according to an embodiment includes a semiconductor substrate; first and second p-type field effect transistors formed on the semiconductor substrate; and first and second n-type field effect transistors; formed on each of the transistors The insulating film; the third and fourth n-type field effect transistors formed on the insulating film. Each of the source regions and the substrate electrodes of the first and second p-type field effect transistors are connected to a wiring having a potential maintained at a power supply voltage, and each of the source regions of the first and second n-type field effect transistors And each of the substrate electrodes is connected to a wiring having a potential maintained at a ground potential, and each of the first p-type field effect transistor and the first n-type field effect transistor, and the second p-type field effect transistor Crystal and each of the gate electrodes of the second n-type field effect transistor, the third The field of the n-type field effect transistor is connected to each other, and the second p-type field effect transistor and the second n-type field effect transistor, the first p-type field effect transistor and The gate electrodes of the first n-type field effect transistor and the first n-type field effect transistor are connected to each other, and the gate electrodes of the third and fourth n-type field effect transistors are The word line is connected, and the source field of the third n-type field effect transistor is connected to the bit line, and the source field of the fourth n-type field effect transistor is connected to the inverted bit line. Further, the third and fourth n-type field effect transistors have a planar structure, and at least a part of the channel region of the third n-type field effect transistor is viewed from a normal direction of the semiconductor substrate. And overlapping the gate electrode of the second p-type field effect transistor and the wiring connected to the gate electrode, the gate electrode of the second n-type field effect transistor, and at least a portion of the wiring connected to the gate electrode Forming, at least a portion of the channel region of the fourth n-type field effect transistor is a gate electrode that appears to overlap the first p-type field effect transistor from the normal direction of the semiconductor substrate and the gate The electrode connection wiring, the gate electrode of the first n-type field effect transistor, and at least a part of the wiring connected to the gate electrode are formed.

In the present invention, at least one of the field effect transistors constituting the SRAM is formed over the field effect transistor forming the memory node via an insulating film. In this way, in the state in which the information has been written, the threshold voltage of at least one of the field effect transistors configured to constitute the potential of the power supply voltage of the two sets of inverters of the SRAM is positive. Direction change, or the output terminal of the inverter is connected to a bit line or a reverse bit line The threshold voltage of the field effect transistor changes in a negative direction. Alternatively, the threshold voltage of at least one of the field effect transistors formed by the inverters that constitute the ground potential of the two sets of inverters of the SRAM is changed in a negative direction, or the inverter is The threshold voltage of the field effect transistor in which the output terminal is associated with the bit line or the inverted bit line changes in a positive direction. As a result, the upper limit of the size of the noise that does not lose the memorized information increases. That is, it is possible to increase the SNM at a certain power supply voltage.

1‧‧‧矽 substrate (semiconductor substrate)

2‧‧‧Parts of component separation

3‧‧‧n well field

4‧‧‧p well field

5‧‧‧Brake insulation film

6‧‧‧ gate electrode

7‧‧‧Source ‧ lead or

8‧‧‧ gate sidewall

9‧‧‧Interlayer insulating film

10‧‧‧Semiconductor layer

11‧‧‧Channel area

12‧‧‧HfO ₂ film

13‧‧‧Tungsten film

14‧‧‧Extended fields

BL‧‧‧ bit line

BL’‧‧‧ reverse bit line

GND‧‧‧Wiring with potential at ground potential

Tn1~Tn4‧‧‧n type field effect transistor

Tp1~Tp2‧‧‧p type field effect transistor

VDD‧‧‧ potential is maintained at the wiring of the power supply voltage

WL‧‧‧ word line

Fig. 1 is a circuit configuration diagram showing a semiconductor memory device according to a first embodiment.

Fig. 2 is a bird's eye view showing a schematic structure of a semiconductor memory device according to the first embodiment.

3 is a cross-sectional view showing a schematic structure of a semiconductor memory device according to the first embodiment.

4(a) to 4(e) are cross-sectional views showing the manufacturing steps of the semiconductor memory device according to the first embodiment.

5(f) to 5(i) are cross-sectional views showing the manufacturing steps of the semiconductor memory device according to the first embodiment.

6(j) to (l) are cross-sectional views showing the manufacturing steps of the semiconductor memory device according to the first embodiment.

FIG. 7 is a view for explaining the performance of the semiconductor memory device according to the first embodiment, and is a characteristic diagram showing a butterfly curve when the threshold voltage is not changed.

Fig. 8A is a view for explaining a semiconductor related to the first embodiment The graph of the performance of the memory device is a characteristic diagram of the butterfly curve in the case where the threshold voltage is varied.

8B is a view for explaining the performance of the semiconductor memory device according to the first embodiment, and is a characteristic diagram showing a butterfly curve when the threshold voltage is varied.

Fig. 9 is a bird's eye view showing the structure of a first modification of the first embodiment.

(a) to (c) of FIG. 10 are cross-sectional views showing a manufacturing procedure of a first modification of the first embodiment.

Fig. 11 is a bird's eye view showing the structure of a second modification of the first embodiment.

Fig. 12 is a bird's eye view showing the structure of a third modification of the first embodiment.

Fig. 13 is a bird's eye view showing a schematic structure of a semiconductor memory device according to a second embodiment.

Fig. 14A is a characteristic diagram for explaining the performance of the semiconductor memory device according to the second embodiment.

Fig. 14B is a characteristic diagram for explaining the performance of the semiconductor memory device according to the second embodiment.

Fig. 15 is a bird's eye view showing a schematic structure of a semiconductor memory device according to a modification of the second embodiment.

Fig. 16A is a characteristic diagram for explaining the performance of a semiconductor memory device according to a modification of the second embodiment.

Fig. 16B is a half guide for explaining a modification of the second embodiment; A characteristic map of the performance of a bulk memory device.

Fig. 17 is a bird's eye view showing a schematic structure of a semiconductor memory device according to a third embodiment.

Fig. 18A is a characteristic diagram for explaining the performance of the semiconductor memory device according to the third embodiment.

Fig. 18B is a characteristic diagram for explaining the performance of the semiconductor memory device according to the third embodiment.

Fig. 19 is a bird's eye view showing a schematic structure of a semiconductor memory device according to a modification of the third embodiment.

Fig. 20A is a characteristic diagram for explaining the performance of a semiconductor memory device according to a modification of the third embodiment.

Fig. 20B is a characteristic diagram for explaining the performance of the semiconductor memory device according to a modification of the third embodiment.

Fig. 21 is a bird's eye view showing a schematic configuration of a semiconductor memory device according to a fourth embodiment.

Fig. 22 is a bird's eye view showing a schematic structure of a semiconductor memory device according to a modification of the fourth embodiment.

Fig. 23 is a bird's eye view showing a schematic structure of a semiconductor memory device according to a fifth embodiment.

Fig. 24 is a bird's eye view showing a schematic structure of a semiconductor memory device according to a modification of the fifth embodiment.

Form for implementing the invention

Hereinafter, the semiconductor memory of the embodiment will be described with reference to the drawings. Device.

(First embodiment)

1 is a circuit configuration diagram showing a semiconductor memory device according to a first embodiment of the present invention.

In the figure, Tpi (i = 1, 2) is the p-type field effect transistor of the ith, Tnj (j = 1, 2, 3, 4) is the n-type field effect transistor of the jth, and VDD is The potential is maintained at the wiring of the power supply voltage, GND is the wiring indicating that the potential is maintained at the ground potential, WL is the word line, BL is the bit line, and BL' is the inverted bit line. Incidentally, the substrate electrode of the field effect transistor is omitted.

In Fig. 2, the structure of the first embodiment is schematically shown in a bird's eye view. Incidentally, in the bird's-eye view below, only a part of the insulating film and the wiring formed on the semiconductor substrate are shown. Further, the thickness of the semiconductor layer formed by the field effect transistor formed on the insulating film formed on the semiconductor substrate is omitted, and the interlayer insulating film thereon is also omitted. Further, the substrate electrode of the field effect transistor formed on the semiconductor substrate is omitted. Further, in order to make the figure easy to see, the interval between the field effect transistor formed on the semiconductor substrate and the field effect transistor formed on the insulating film in the direction perpendicular to the surface of the semiconductor substrate is enlarged display. In general, the scale of the figure is not correct.

In the semiconductor memory device of the present embodiment, the first and second p-type field effect transistors Tp1 and Tp2 and the first and second n-type field effect transistors Tn1 and Tn2 are formed on the semiconductor substrate, and are formed in those On the upper insulating film, the third and fourth n-type field effect transistors Tn3 and Tn4 are formed. and, The channel region of the third n-type field effect transistor Tn3 is formed so as to overlap with the gate electrode of the second p-type field effect transistor Tp2 from the normal direction of the semiconductor substrate, and the fourth n-type field effect The channel region of the transistor Tn4 is formed so as to overlap the gate electrode of the first p-type field effect transistor Tp1 from the normal direction of the semiconductor substrate. Incidentally, the normal direction is a direction perpendicular to the plane of the semiconductor substrate.

Further, the cross-sectional structure of this embodiment is schematically shown in Fig. 3 . Incidentally, in the cross-sectional views below, only the cross sections of the first p-type field effect transistor Tp1, the first and fourth n-type field effect transistors Tn1, Tn4 are schematically and three are formed in the same direction. Displayed like this. In addition, the scale of the figure is not correct. In addition, the interlayer insulating film which is wired to the second layer or more is omitted.

In the semiconductor substrate 1 formed of, for example, germanium, an element isolation region 2 made of, for example, hafnium oxide is formed, and in the field separated by the n well region 3 and the p well region 4 are formed. Further, on the n well region 3 and the p well region 4, the gate electrode 6 is formed via the gate insulating film 5, respectively. In the n well region 3 and the p well region 4, an active ‧ 汲 region 7 is formed so as to sandwich the gate electrode 6, and the gate sidewall 8 is formed in contact with the gate electrode. Thereby, the first p-type field effect transistor Tp1 is formed in the n well field 3, and the first n-type field effect transistor Tn1 is formed in the p well field 4. Further, an interlayer insulating film 9 made of, for example, yttrium oxide is formed over the first p-type field effect transistor Tp1 and the first n-type field effect transistor Tn1, and is formed thereon, for example, by tantalum And a semiconductor layer 10 containing p-type impurities.

On the semiconductor layer 10, a gate electrode is formed via the gate insulating film 5 Extreme 6. Further, in the semiconductor layer 10, an active ‧ 汲 region 7 is formed so as to sandwich the gate electrode 6, and a gate sidewall 8 is formed in contact with the gate electrode, and a fourth n-type field effect transistor Tn4 is formed. The channel region 11 formed by the source ‧ 汲 field 7 of the 4th n-type field effect transistor Tn4 is a gate which appears from the normal direction of the semiconductor substrate 1 and the first p-type field effect transistor Tp1 The electrodes 6 are formed in such a manner as to overlap.

Although not shown in FIG. 3, the second p-type field effect transistor Tp2, the second and third n-type field effect transistors Tn2 and Tn3 are formed in the same manner, and the third n-type field effect transistor is also formed. The channel region of the crystal Tn3 is formed so as to overlap the gate electrode of the second p-type field effect transistor Tp2 from the normal direction of the semiconductor substrate 1.

Incidentally, the present invention is not limited to the embodiment to the following embodiments, and various modifications can be made.

The manufacturing steps of the semiconductor memory device of the present embodiment will be described with reference to Figs. 4 to 6 .

First, as shown in FIG. 4(a), the element isolation region 2 is formed on the germanium substrate 1 by a method such as shallow trench isolation (STI).

Next, as shown in FIG. 4(b), for example, As (arsenic) is implanted in the field of p-type field effect transistor formation of the semiconductor substrate 1, and B (boron) is implanted in the field of n-type field effect transistor formation of the semiconductor substrate 1. And then form n well field 3, p well field 4 by performing a thermal step. Incidentally, regarding the introduction of impurities only in a specific field, a method such as a photolithography method or a lithography step can be used.

Next, as shown in FIG. 4(c), a HfO ₂ film 12 having a thickness of 5 nm is formed on the semiconductor substrate 1 by a method such as chemical vapor deposition.

Next, as shown in FIG. 4(d), a tungsten film 13 having a thickness of 50 nm is formed by a method such as chemical vapor deposition.

Next, as shown in FIG. 4(e), the tungsten electrode 13 is selectively removed by a treatment such as a reactive ion etching method to form the gate electrode 6. Then, a part of the HfO ₂ film 12 is selectively removed by a treatment such as a reactive ion etching method to form the gate insulating film 5.

Next, as shown in FIG. 5(f), for example, B is implanted in the field of p-type field effect transistor formation, and for example, As is implanted in the field of n-type field effect transistor formation, thereby forming the extension region 14.

Next, as shown in FIG. 5(g), a ruthenium oxide film (not shown) having a thickness of 20 nm is formed by a method such as chemical vapor deposition. Then, one of the foregoing hafnium oxide films is selectively removed by etch back by a method such as a reactive ion etching method to form the gate sidewalls 8.

Next, as shown in FIG. 5(h), for example, B is implanted in the field of p-type field effect transistor formation, and for example, As is implanted in the field of n-type field effect transistor formation, and a thermal step is performed, thereby forming together with the extension field 14. Source ‧ 汲 field 7.

Next, as shown in FIG. 5(i), a ruthenium oxide film (not shown) having a thickness of 100 nm is formed on the entire surface of the semiconductor substrate 1 by a method such as chemical vapor deposition, and is formed by planarization. Interlayer insulating film 9. Then, although illustration is omitted, wiring steps and the like similar to those of the prior art are performed.

Next, as shown in FIG. 6(j), by, for example, chemical vapor deposition A layer of germanium (not shown) having a thickness of B of B is formed on the interlayer insulating film 9 by a method such as a method, and the element layer is separated by a method such as a mesa type element separation method to form the semiconductor layer 10.

Next, as shown in FIG. 6(k), an HfO ₂ film (not shown) having a thickness of 5 nm is formed on the semiconductor layer 10 by a method such as chemical vapor deposition. Then, a tungsten film (not shown) having a thickness of 50 nm is formed on a HfO ₂ film (not shown) by a method such as chemical vapor deposition. Then, a portion of the gate electrode 6 is selectively removed by performing a treatment such as a reactive ion etching method by a tungsten film (not shown). Then, a portion of the gate insulating film 5 is formed by selectively removing a part of the HfO ₂ film (not shown) by a process such as a reactive ion etching method.

Next, as shown in FIG. 6(1), the extended region 14 is formed by injecting, for example, As into the surface portion of the semiconductor layer 10. Next, a ruthenium oxide film (not shown) having a thickness of 20 nm is formed by a method such as chemical vapor deposition. Then, a portion of the yttrium oxide film is selectively removed by deep etching by, for example, a reactive ion etching method to form the gate sidewall 8.

Next, a thermal step is performed by injecting, for example, As, thereby forming a source field 7 together with the extension field 14. After that, the structure shown in FIG. 3 described above is formed through the interlayer insulating film forming step, the wiring step, and the like in the same manner as the prior art.

In the present embodiment, an example is described in which a semiconductor memory device is formed using a bulk substrate. However, a semiconductor memory in which a semiconductor layer is formed on a support substrate via an insulating film can also form a semiconductor memory. The device achieves the same effect. Also, in use In the case where the element is formed by the semiconductor substrate having the above structure, the same effect can be obtained with respect to the element formed on the semiconductor layer even if the element having the structure in which the gate electrode is provided above the channel region is formed. It is preferable to adopt such a structure to improve the controllability of the gate electrode with respect to the potential of the channel region.

Further, although the present embodiment is an example of a device for displaying a planar structure, an element formed on a semiconductor substrate is, for example, a FinFET, a Triple Gate structure, a Gate All Around structure, and a vertical structure. The same effect can be obtained by the components of the three-dimensional structure. It is preferable that the semiconductor memory device is formed by using the thus constructed element to improve the controllability of the gate electrode with respect to the potential of the channel region.

Further, although the present embodiment is a step of forming a single semiconductor memory device, it may be used as an active device including a field effect transistor, a bipolar transistor, or a single electron transistor in addition to a single semiconductor memory device. A semiconductor memory device is formed by a component, a resistor or a diode, or a passive component such as an inductor or a capacitor, or a portion of a semiconductor device using, for example, a component of a magnetic body. The same applies to the case where a semiconductor memory device is formed as part of an OEIC (photoelectric integrated circuit) or a MEMS (microelectromechanical system).

Further, in the present embodiment, As (arsenic) is used as an impurity for forming an n-type semiconductor, and B (boron) is used as an impurity for forming a p-type semiconductor, other V-type impurities may be used as It is used to form impurities in the field of n-type semiconductors or to use other group III impurities as impurities for forming a field of p-type semiconductors. In addition, The introduction of the III or V impurity may also be carried out in the form of a compound containing those.

Further, in the present embodiment, the introduction of impurities into the source ‧ 汲 field is performed by ion implantation, but it may be carried out by a method such as solid phase diffusion or gas phase diffusion other than ion implantation. Further, a method of depositing or growing a semiconductor containing impurities may be used. When the ion implantation method is used, there is an advantage that a semiconductor device including a complementary type of an n-type semiconductor element and a p-type semiconductor element can be easily formed, and a method of using a semiconductor containing impurity or solid phase diffusion or vapor phase diffusion can be used. When the introduction of impurities is carried out, there is an advantage that the concentration of impurities is high.

Further, although this embodiment is not mentioned, a stressor may be formed in the field of ‧ 汲It is preferable to apply strain in the channel region to enhance the mobility of carriers.

Further, in the present embodiment, the introduction of the impurity for adjusting the threshold voltage is not performed, but the introduction of the impurity for adjusting the threshold voltage may be performed in addition to the introduction of the impurity into the substrate in the well field. In this way, an advantage that it is easy to set the threshold voltage to a desired value can be obtained. Further, in the case of the present embodiment, there is an advantage that the steps can be simplified.

Further, in the present embodiment, germanium is used as the semiconductor layer forming the device, but the semiconductor layer is not limited to germanium, and germanium or a mixed crystal of germanium and germanium may be used. It is preferable because helium or a mixed crystal of lanthanum and cerium has the advantage that the mobility of carriers is higher than that of ruthenium.

Further, a semiconductor of a compound of a group III element and a group V element may be used as the semiconductor layer forming the element. Since such a compound also has the advantage that the mobility of carriers is higher than that of ruthenium, it is preferable. In particular, InAs (indium arsenide), In _x Ga _1-x As (0 ≦ x ≦ 1) (indium gallium arsenide), InSb (indium antimonide), etc., since the mobility of carriers is particularly high, good. In addition, it is better to apply the strain in the channel field to improve mobility. On the other hand, since germanium is used as the semiconductor layer, the conventional manufacturing steps can be used as it is, and there are other advantages in that the manufacturing steps can be easily constructed.

Further, in the present embodiment, the formation of the source ‧ 汲 field is performed after the processing of the gate electrode and the gate insulating film, but these orders are not essential and may be performed in the reverse order. It may be because the gate electrode or the material of the gate insulating film is not suitable for the thermal step. In this case, the thermal step of introducing and activating the impurities into the source ‧ 汲 field should be performed first than the processing of the gate electrode or the gate insulating film.

Further, in the present embodiment, the gate electrode is formed using tungsten, but other metals may be used. Further, it may be formed by a semiconductor such as a single crystal ruthenium or an amorphous ruthenium, a compound containing a metal, or the like, or a laminate or the like. If a semiconductor is used to form the gate electrode, there is an advantage that the threshold voltage can be easily controlled, and in the case of forming a complementary semiconductor device, it is easy to set the threshold even for any of the n-type semiconductor element and the p-type semiconductor element. Other advantages of setting the voltage to the desired value. Further, when the gate electrode is formed of a metal or a compound containing a metal, since the resistance of the gate electrode can be suppressed, high-speed operation of the element can be obtained. Further, since the oxidation reaction is not easily progressed by forming the gate electrode with a metal, the level of the interface between the gate electrode and the insulating film is suppressed. The advantage of the control of the interface is good.

Further, in the present embodiment, the gate electrode is formed by a method in which a non-isotropic etching is performed after depositing a material, but it may be formed by a method such as embedding of a damascene process or the like. . In the case where the source ‧ 汲 field is formed before the formation of the gate electrode, it is preferable that the source ‧ 汲 field and the gate electrode are formed in a self-aligned manner by using the damascene process

Further, in the present embodiment, the length of the gate electrode measured in the main direction of the current flowing through the element is equal to the upper portion and the lower portion of the gate electrode, but this is not essential. For example, the length measured on the upper portion of the gate electrode may be longer than the length measured in the lower portion, such as the letter "T". In this case, the advantage of reducing the gate resistance is obtained.

Further, in the present embodiment, although a step such as a telluride or a telluride is not mentioned, a telluride or a telluride layer or the like may be formed in the field of the source. In addition, it is also possible to use a method of stacking or growing a layer containing a metal in the field of ‧ 汲Since it is possible to reduce the resistance of the source ‧ 汲 field, it is preferable. Further, in the case where the gate electrode is formed by polycrystalline germanium or the like, a step such as deuteration or silicide formation with respect to the gate electrode may be performed. In this case, it is preferable to reduce the gate resistance by performing steps such as telluride or bismuth. In addition, an elevated configuration can also be used. Since the resistance of the source ‧ 汲 field can also be reduced by raising the structure, it is preferable.

Further, in the present embodiment, the upper portion of the gate electrode is a structure in which the electrode is exposed, but an insulator such as hafnium oxide, tantalum nitride or hafnium oxynitride may be provided on the upper portion. In particular, the gate is formed from a material containing metal In the case where the electrode forms a telluride or a telluride layer on the source ‧ 汲 field, etc., in the case where it is necessary to protect the gate electrode in the middle of the manufacturing step, it is necessary to provide yttrium oxide and tantalum nitride on the upper portion of the gate electrode. Protective materials such as bismuth oxynitride.

Further, in the present embodiment, an HfO ₂ film is used as the gate insulating film, but an insulating film such as a hafnium oxide film or a hafnium oxynitride film or another insulating film such as those laminated layers may be used. When nitrogen is present in the insulating film, when a polycrystalline germanium containing an impurity is used as the gate electrode, it is preferable to suppress the diffusion of impurities into the substrate, and it is advantageous in suppressing the variation of the threshold voltage. On the other hand, if yttrium oxide is used, since the interface level with the interface of the gate electrode or the fixed charge in the insulating film is small, the advantage of suppressing the characteristics of the element is obtained.

Further, when an oxide of a certain substance is used as an insulating film or the like, a method of forming a film of the substance first and then oxidizing it may be used. In addition, it may be an oxygen gas that is exposed to a state in which the temperature rise is not accompanied. Since it is formed by a method of exposing to an oxygen gas which is not exposed to the rising state, it is preferable to suppress the concentration distribution due to the diffusion of impurities in the channel field.

Further, in the case of using yttrium oxynitride, it is also possible to form a ruthenium oxide film first, and then expose it to a gas containing nitrogen in a temperature rising state or an excited state, thereby introducing nitrogen into the insulating film. It is preferable to use a method of exposing to a nitrogen gas which is not exposed to the rising temperature to suppress the concentration distribution due to the diffusion of impurities in the channel field. Alternatively, a tantalum nitride film may be formed first, and then exposed to a temperature-increasing state or excitation. A gas of oxygen in a state in which oxygen is introduced into the insulating film. Since it is formed by a method of exposing to an oxygen gas which is not exposed to the rising state, it is preferable to suppress the concentration distribution due to the diffusion of impurities in the channel field.

Further, Hf (铪), Zr (zirconium), Ti (titanium), Sc (钪), Y (钇), Ta (钽), Al (aluminum), La (镧), Ce (铈), Pr (鐠), an oxide such as a metal such as a lanthanoid element, or the like, or a tantalum material containing various elements such as those elements, or a high dielectric material such as an insulating film containing nitrogen. Membrane or other insulating film such as those laminated layers. Further, the method of forming the insulating film is not limited to the chemical vapor deposition method, and other methods such as a thermal oxidation method, a vapor deposition method, a sputtering method, or an epitaxial growth method may be used.

Further, in the present embodiment, although the oxidation after the formation of the gate electrode is not mentioned, the post-oxidation step may be performed in view of the possibility of the material of the gate electrode or the like. Further, the treatment is not limited to post-oxidation, and the process of smoothing the corners of the gate electrode may be performed by, for example, a chemical liquid treatment or a method of exposure to a reactive gas. Since the electric field of the lower end corner of the gate electrode can be alleviated by these steps, it is preferable that the reliability of the gate insulating film is improved.

In the present embodiment, a ruthenium oxide film is used as the interlayer insulating film. However, a material other than ruthenium oxide such as a low dielectric material may be used for the interlayer insulating film. When the dielectric of the interlayer insulating film is set to be low, the parasitic capacitance of the element is lowered, so that the high-speed operation of the element is obtained.

In addition, although contact holes are not mentioned, it is also possible to form self-aligned contacts. Since the self-aligned contact can be used to reduce the area of the element, it is preferable to improve the degree of the integrated body.

Although the present embodiment is not described in detail, the formation of the metal layer for wiring may be performed by a sputtering method or the like, or may be performed by a method such as a deposition method. Further, it may be a method of growing using a metal, or a method such as a mosaic method. Further, as the material of the wiring metal, for example, Al (aluminum) or the like containing ruthenium may be used, or a metal such as Cu (copper) may be used. In particular, Cu is preferred because it has a low electrical resistivity.

Further, although not described in the present embodiment, crystallization of the semiconductor layer formed on the interlayer insulating film can be performed. When the crystallization is performed, the mobility of the carrier is increased, so that the operation speed can be improved.

Further, the schematic diagram of the structure of the present embodiment is only an example, and the arrangement of the field effect transistor in the direction perpendicular to the surface of the semiconductor substrate is essential, but the arrangement in the direction parallel to the surface of the semiconductor substrate is not essential. The same effect can be obtained with other configurations. In addition, the arrangement or shape of the wiring is not essential, and other configurations or shapes can achieve the same effect as long as the connection relationship can be maintained.

Next, the results of numerical calculations relating to the semiconductor memory device having the structure of the present embodiment will be described. The gate length of the device is 25 nm, and the first and second p-type field effect transistors Tp1 and Tp2 are elements having the same characteristics, and the first to fourth n-type field effect transistors Tn1 to Tn4 are all identical to each other. Sexual components. Further, the gate insulating film is cerium oxide having a thickness of 1 nm.

Figure 7 shows the Butterfly Curve with no change in threshold voltage. Incidentally, in FIG. 7, the field of the first p-type field effect transistor Tp1, the first n-type field effect transistor Tn1, and the second p-type field effect transistor Tp2 are shown. The potential of the electrode, the gate electrode of the second n-type field effect transistor Tn2, and the connection point of the third n-type field effect transistor Tn3 are recorded as V1, and the second p-type field effect electric The field of crystal Tp2, the field of the second n-type field effect transistor Tn2, the gate electrode of the first p-type field effect transistor Tp1, the gate electrode of the first n-type field effect transistor Tn1, the fourth The potential of the connection point of the interconnected fields of the n-type field effect transistor Tn4 is denoted as V2.

The potential of the write bit line BL is the power supply voltage, the potential of the inverted bit line BL' is the ground potential, the potential of the bit line BL after writing, the potential of the inverted bit line BL', and the word When the potential of the line WL is at the potential of the power supply voltage, V1 and V2 are P1 in the figure. Further, the potential of the write bit line BL is the ground potential, the potential of the inverted bit line BL' is the power supply voltage, and the potential of the bit line BL after writing and the potential of the inverted bit line BL' When the potential of the word line WL is at the potential of the power supply voltage, V1 and V2 are P2 in the figure.

If the shape of the butterfly curve changes due to noise, and the closed curve of L1 in the figure is destroyed, the state of P1 becomes unstable, regardless of whether the state is P1 or P2. In addition, if the shape of the butterfly curve changes due to noise, and the closed curve of L2 in the figure is extinguished, the state of P2 becomes unstable, and the state of P1 or P2 becomes P1 regardless of the state. That is, no matter which one In all cases, the information that has been memorized is lost. Therefore, the larger the closed curve of L1 or L2, the larger the upper limit of the size of the noise that does not lose information. The index indicating the upper limit is the above-mentioned SNM, and the specific value is the side of the largest one (ie, SQ1 or SQ2) which is included in the square parallel to the vertical axis and the horizontal axis of the graph L1 or L2. The length is given. In the example shown here, the SNM showing the stability of P1 (that is, the length of the side of SQ1) is the same as the SNM showing the stability of P2 (that is, the length of the side of SQ2) is 0.144V.

Next, the semiconductor memory device of this embodiment will be considered. First, a case where the potential of the write timing bit line BL is the power supply voltage and the potential of the inverted bit line BL' is the ground potential is considered. In this case, when the potential of the post-bit bit line BL, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P1 in the figure. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 0.18V, and the gate electrode of the second p-type field effect transistor Tp2 is 1.0V. Therefore, compared with the threshold voltage of the fourth n-type field effect transistor Tn4 formed in the channel region on the gate electrode of the first p-type field effect transistor Tp1, the second p-type field effect transistor is used. The threshold voltage of the third n-type field effect transistor Tn3 formed in the channel region above the gate electrode of Tp2 is changed in a negative direction.

Therefore, here, compared with the case shown in FIG. 7, the threshold voltage of the third n-type field effect transistor Tn3 is changed by 50 mV in the negative direction, and the threshold voltage of the fourth n-type field effect transistor Tn4 is positive. The direction of the change is 50mV to calculate the butterfly curve. That is, the threshold voltage in the case where there is no change as a result of the change in the threshold voltage between the two is adjusted. The results are shown in Figure 8A. There is no change in the threshold voltage shown in Figure 7. In contrast, it can be seen that the closed curve L1 becomes large, and the square SQ1 indicating the SNM for displaying the stability of P1 is also increased. The specific value of SNM in this case is 0.170V.

Next, a case where the potential of the write timing bit line BL is the ground potential and the potential of the inverted bit line BL' is the power supply voltage is considered. In this case, when the potential of the bit line BL after writing, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P2 in the figure. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 1.0V, and the gate electrode of the second p-type field effect transistor Tp2 is 0.18V. Therefore, compared with the threshold voltage of the third n-type field effect transistor Tn3 formed in the channel region on the gate electrode of the second p-type field effect transistor Tp2, the first p-type field effect transistor is The threshold voltage of the fourth n-type field effect transistor Tn4 in which the channel region is formed on the gate electrode of Tp1 is changed in a negative direction.

Therefore, here, compared with the case shown in FIG. 7, the threshold voltage of the third n-type field effect transistor Tn3 changes 50 mV in the positive direction, and the threshold voltage of the fourth n-type field effect transistor Tn4 becomes negative. The direction of the change is 50mV to calculate the butterfly curve. That is, the threshold voltage in the case where there is no change as a result of the change in the threshold voltage between the two is adjusted. The results are shown in Fig. 8B. In this case, it is a curve in which the vertical axis and the horizontal axis of the butterfly curve shown in FIG. 8A are replaced. As compared with the case where the threshold voltage shown in FIG. 7 does not change, it can be seen that the closed curve L2 becomes large, and the square SQ2 indicating the SNM for displaying the stability of P2 also becomes large. The specific value of the SNM in this case is 0.170 V which is the same as the case shown in Fig. 8A.

Therefore, compared with the semiconductor memory device of the conventional structure in which the threshold voltage does not change, it can be seen that the semiconductor memory device of the present embodiment is intended to increase the SNM, that is, to improve the resistance to noise.

Incidentally, the reason why the SNM is increased in the semiconductor memory device of the present embodiment is that the channel fields of the third and fourth n-type field effect transistors Tn3 and Tn4 are respectively the second and the first p As a result of the overlap of the gate electrodes of the type field effect transistors Tp2 and Tp1, the gate electrodes of the second and first p-type field effect transistors Tp2 and Tp1 are effectively used as the third and fourth n-type field effect transistors, respectively. The gate electrodes of the crystals Tn3 and Tn4 act. Even if the channel fields of the third and fourth n-type field effect transistors Tn3 and Tn4 are overlapped with the gate electrodes of the second and first p-type field effect transistors Tp2 and Tp1, respectively, if the third and fourth sides are When the n-type field effect transistors Tn3 and Tn4 have a structure other than a planar structure such as a columnar structure, the effect of the present embodiment cannot be obtained because the threshold voltage does not change. Therefore, the third and fourth n-type field effect transistors Tn3 and Tn4 have a planar structure.

Further, in the present embodiment, the channel regions of the third and fourth n-type field effect transistors Tn3 and Tn4 are formed so as to overlap the gate electrodes of the second and first p-type field effect transistors Tp2 and Tp1, respectively. As a result, the essence of the increase of SNM is that the gate electrodes of the second and first p-type field effect transistors Tp2 and Tp1 are effectively used as the third and fourth n-type field effect transistors Tn3 and Tn4, respectively. The back gate electrode acts. Therefore, the channel fields of the third and fourth n-type field effect transistors Tn3 and Tn4 do not necessarily overlap with the gate electrodes of the second and first p-type field effect transistors Tp2 and Tp1, respectively, even if they are respectively Superimposed on the gate electrodes of the second and first p-type field effect transistors Tp2 and Tp1 The same effect can be obtained by wiring.

Incidentally, in the semiconductor memory device of the present embodiment, the essence of the increase in SNM is that the gate electrodes of the second and first p-type field effect transistors Tp2 and Tp1 are effectively used as the third and fourth, respectively. As a result of the action of the back gate electrodes of the n-type field effect transistors Tn3 and Tn4, the threshold voltages of the third and fourth n-type field effect transistors Tn3 and Tn4 are changed. There is an ups and downs at the potential of normal temperature, that is, the thermal potential is kT/q (k is the Boltzmann constant, T is the absolute temperature, that is, the normal temperature is 300K, q is the basic charge, that is, 1.6×10 ^-19 C, kT The value of /q at room temperature is 26mV). Therefore, in order to obtain an expansion of the field of stabilization of the semiconductor memory device due to an increase in the SNM, it is necessary to change the threshold voltage of the field effect transistor constituting the semiconductor memory device to three times the potential fluctuation, that is, 78 mV.

Using the element used in the numerical calculation described above, the change in the threshold voltage accompanying the application of the voltage to the back gate electrode is calculated. It is known that 78 mV is obtained by applying 1 V of the assumed power supply voltage to the back gate electrode. The amount of change in the threshold voltage, the thickness of the insulating film between the channel region and the back gate electrode needs to be below 70 nm. Therefore, the lower end of the field effect transistor formed on the insulating film, the gate electrode of the field effect transistor formed on the semiconductor substrate, and the wiring connected to the gate electrode and the field effect electricity formed on the insulating film The upper end of the field in which the channel region of the crystal overlaps is preferably spaced below 70 nm in the direction perpendicular to the surface of the semiconductor substrate.

In addition, it has been known that the value of the gate voltage of the field effect transistor formed on the semiconductor substrate will be accompanied by the two cases described above. A voltage of 1V-0.18V = 0.82V is applied to the back gate electrode to obtain a threshold voltage change of 78 mV, and the thickness of the insulating film between the channel region and the back gate electrode needs to be 40 nm or less. Therefore, the lower end of the field effect transistor formed on the insulating film, the gate electrode of the field effect transistor formed on the semiconductor substrate, and the wiring connected to the gate electrode and the field effect electricity formed on the insulating film The interval measured at the upper end of the field in which the channel region of the crystal overlaps is perpendicular to the surface of the semiconductor substrate, and is preferably 40 nm or less.

(First Modification of First Embodiment)

Next, a first modification of the first embodiment will be described.

The semiconductor memory device of the present modification has the same circuit as that of the first embodiment shown in FIG. 1, but the three-dimensional structure is different. That is, the present modification is a structure schematically shown in FIG. 9, in which the first and second p-type field effect transistors Tp1, Tp2, the first and second n-type field effect transistors are formed on the semiconductor substrate. Tn1 and Tn2 are formed on the insulating film formed on those of the third and fourth n-type field effect transistors Tn3 and Tn4. Further, the channel region of the third n-type field effect transistor Tn3 is formed so as to overlap the gate electrode of the second n-type field effect transistor Tn2 from the normal direction of the semiconductor substrate, and the fourth n-type The channel region of the field effect transistor Tn4 is formed so as to overlap the gate electrode of the first n-type field effect transistor Tn1 from the normal direction of the semiconductor substrate.

The manufacturing steps of the semiconductor memory device of the present modification will be described with reference to FIG.

Continuing the steps shown in the foregoing FIGS. 4(a) to 5(i), as shown in FIG. 10(a), the interlayer insulation is performed by a method such as chemical vapor deposition. A germanium layer (not shown) having a thickness of B of 20 nm is formed on the film 9, and the element layer is separated by a method such as a mesa-type element separation method to form the semiconductor layer 10.

Next, as shown in FIG. 10(b), an HfO ₂ film (not shown) having a thickness of 5 nm is formed on the semiconductor layer 10 by a method such as chemical vapor deposition. Then, a tungsten film (not shown) having a thickness of 50 nm is formed on a HfO ₂ film (not shown) by a method such as chemical vapor deposition. Then, a portion of the gate electrode 6 is selectively removed by performing a treatment such as a reactive ion etching method by a tungsten film (not shown). Then, a portion of the gate insulating film 5 is formed by selectively removing a part of the HfO ₂ film (not shown) by a process such as a reactive ion etching method.

Next, as shown in FIG. 10(c), the extended region 14 is formed by injecting, for example, As into the surface portion of the semiconductor layer 10. Then, a ruthenium oxide film (not shown) having a thickness of 20 nm is formed by a method such as chemical vapor deposition. Thereafter, deep etching is performed using a method such as a reactive ion etching method, whereby one portion of the hafnium oxide film is selectively removed to form the gate sidewalls 8.

Next, a thermal step is performed by injecting, for example, As, thereby forming a source field 7 together with the extension field 14. After that, the semiconductor memory device having the structure shown in FIG. 9 described above is formed through the interlayer insulating film forming step, the wiring step, and the like in the same manner as the conventional technique.

The gate electrode of the first n-type field effect transistor Tn1 and the gate electrode of the first p-type field effect transistor Tp1 are connected to each other, and the gate electrode of the second n-type field effect transistor Tn2, the second p The gate electrode of the type field effect transistor Tp2 is mutual connection. Therefore, the gate electrode of the first n-type field effect transistor Tn1 and the gate electrode of the first p-type field effect transistor Tp1 are mutually equipotential, and the gate electrode of the second n-type field effect transistor Tn2, The gate electrodes of the p-type field effect transistor Tp2 of 2 are mutually equipotential. Therefore, even in the semiconductor memory device of the present modification, the threshold voltages of the third and fourth n-type field effect transistors Tn3 and Tn4 are similarly changed as those of the semiconductor memory device of the above-described embodiment. Therefore, even in the semiconductor memory device of the present modification, the same effects as those of the semiconductor memory device of the above-described embodiment can be obtained.

Even in the present modification, various modifications as described in the above embodiments can be performed, and the same effects can be obtained.

(Second Modification of First Embodiment)

Next, a second modification of the first embodiment will be described.

The semiconductor memory device of the present modification has the same circuit as that of the first embodiment shown in FIG. 1, but the three-dimensional structure is different. That is, the present modification is a structure schematically shown in FIG. 11, in which the first and second p-type field effect transistors Tp1, Tp2, the first and second n-type field effect transistors are formed on the semiconductor substrate. Tn1 and Tn2 are formed on the insulating film formed on those of the third and fourth n-type field effect transistors Tn3 and Tn4. Further, the channel region of the third n-type field effect transistor Tn3 is formed so as to overlap the gate electrode of the second p-type field effect transistor Tp2 from the normal direction of the semiconductor substrate, and the fourth n-type The channel region of the field effect transistor Tn4 is formed so as to overlap the gate electrode of the first n-type field effect transistor Tn1 from the normal direction of the semiconductor substrate.

Since the manufacturing steps of the semiconductor memory device of the present modification are Essentially, it is the same as the manufacturing procedure of the first embodiment or the first modification, and therefore will not be described.

The gate electrode of the first n-type field effect transistor Tn1 and the gate electrode of the first p-type field effect transistor Tp1 are connected to each other, and the gate electrode of the second n-type field effect transistor Tn2, the second p The gate electrodes of the field effect transistor Tp2 are connected to each other. Therefore, the gate electrode of the first n-type field effect transistor Tn1 and the gate electrode of the first p-type field effect transistor Tp1 are mutually equipotential, and the gate electrode of the second n-type field effect transistor Tn2, The gate electrodes of the p-type field effect transistor Tp2 of 2 are mutually equipotential. Therefore, even in the semiconductor memory device of the present modification, the threshold voltages of the third and fourth n-type field effect transistors Tn3 and Tn4 are similarly changed as those of the semiconductor memory device of the above-described embodiment. Therefore, even in the semiconductor memory device of the present modification, the same effects as those of the semiconductor memory device of the above-described embodiment can be obtained.

Even in the present modification, various modifications as described in the above embodiments can be performed, and the same effects can be obtained.

(Third Modification of First Embodiment)

Next, a third modification of the first embodiment will be described.

The semiconductor memory device of the present modification has the same circuit as that of the first embodiment shown in FIG. 1, but the three-dimensional structure is different. That is, the present modification is a structure schematically shown in FIG. 12, in which the first and second p-type field effect transistors Tp1, Tp2, the first and second n-type field effect transistors are formed on the semiconductor substrate. Tn1 and Tn2 are formed on the insulating film formed on those of the third and fourth n-type field effect transistors Tn3 and Tn4. Moreover, the channel region of the third n-type field effect transistor Tn3 is from a semiconductor substrate. The normal direction appears to overlap with the gate electrode of the second n-type field effect transistor Tn2, and the channel field of the fourth n-type field effect transistor Tn4 is seen from the normal direction of the semiconductor substrate. The gate electrode of the p-type field effect transistor Tp1 of 1 is formed by overlapping.

The manufacturing steps of the semiconductor memory device according to the present modification are substantially the same as the manufacturing steps of the first embodiment or the first modification or the second modification, and therefore will not be described.

The gate electrode of the first n-type field effect transistor Tn1 and the gate electrode of the first p-type field effect transistor Tp1 are connected to each other, and the gate electrode of the second n-type field effect transistor Tn2, the second p The gate electrodes of the field effect transistor Tp2 are connected to each other. Therefore, the gate electrode of the first n-type field effect transistor Tn1 and the gate electrode of the first p-type field effect transistor Tp1 are mutually equipotential, and the gate electrode of the second n-type field effect transistor Tn2, The gate electrodes of the p-type field effect transistor Tp2 of 2 are mutually equipotential. Therefore, even in the semiconductor memory device of the present modification, the threshold voltages of the third and fourth n-type field effect transistors Tn3 and Tn4 are similarly changed as those of the semiconductor memory device of the above-described embodiment. Therefore, even in the semiconductor memory device of the present modification, the same effects as those of the semiconductor memory device of the above-described embodiment can be obtained.

Even in the present modification, various modifications as described in the above embodiments can be performed, and the same effects can be obtained.

(Second embodiment)

Next, a second embodiment of the semiconductor memory device of the present invention will be described.

Figure 13 is a view showing a semiconductor guide according to a second embodiment of the present invention. A bird's eye view of the schematic structure of a body memory device. Incidentally, the same portions as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The semiconductor memory device of the present embodiment has the same circuit as that of the first embodiment shown in FIG. 1. However, as shown schematically in FIG. 13, the first and second p-type field effects are formed on the semiconductor substrate. The transistors Tp1, Tp2, the third and fourth n-type field effect transistors Tn3, Tn4 are formed on the interlayer insulating film formed on the first and second n-type field effect transistors Tn1. Tn2. Further, the channel region of the first n-type field effect transistor Tn1 is formed so as to overlap the gate electrode of the first p-type field effect transistor Tp1 from the normal direction of the semiconductor substrate, and the second n-type is formed. The channel field of the field effect transistor Tn2 is formed so as to overlap the gate electrode of the second p-type field effect transistor Tp2 from the normal direction of the semiconductor substrate.

Since the manufacturing steps of the semiconductor memory device of the present embodiment are essentially the same as the manufacturing steps of the first embodiment or its modifications, they are omitted.

Next, the results of numerical calculations relating to the semiconductor memory device having the structure of the present embodiment will be described. First, a case where the potential of the write timing bit line BL is the power supply voltage and the potential of the inverted bit line BL' is the ground potential is considered. In this case, when the potential of the post-bit bit line BL, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P1 in the figure. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 0.18V, and the gate electrode of the second p-type field effect transistor Tp2 is 1.0V. Therefore, the first n-type field effect transistor having the channel field is formed on the gate electrode of the first p-type field effect transistor Tp1. The threshold voltage of the second n-type field effect transistor Tn2 formed in the channel region above the gate electrode of the second p-type field effect transistor Tp2 is changed in a negative direction as compared with the threshold voltage of Tn1.

Therefore, here, compared with the case shown in FIG. 7, the threshold voltage of the first n-type field effect transistor Tn1 changes 50 mV in the positive direction, and the threshold voltage of the second n-type field effect transistor Tn2 becomes negative. The direction of the change is 50mV to calculate the butterfly curve. That is, the threshold voltage in the case where there is no change as a result of the change in the threshold voltage between the two is adjusted. The results are shown in Fig. 14A. As compared with the case where the threshold voltage shown in FIG. 7 does not change, it can be seen that the closed curve L1 becomes large, and the square SQ1 indicating the SNM for displaying the stability of P1 also becomes large. The specific value of SNM in this case is 0.188V.

Next, a case where the potential of the write timing bit line BL is the ground potential and the potential of the inverted bit line BL' is the power supply voltage is considered. In this case, when the potential of the bit line BL after writing, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P2 in the figure. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 1.0V, and the gate electrode of the second p-type field effect transistor Tp2 is 0.18V. Therefore, the butterfly curve is a curve in which the vertical axis and the horizontal axis are replaced when displayed in Fig. 14A. The results are shown in Fig. 14B. As compared with the case where the threshold voltage shown in FIG. 7 does not change, it can be seen that the closed curve L2 becomes large, and the square SQ2 indicating the SNM for displaying the stability of P2 also becomes large. The specific value of the SNM in this case is 0.188 V which is the same as that shown in Fig. 14A.

Even in the present embodiment, various modifications as described in the above embodiments can be performed, and the same effects can be obtained.

(Modification of Second Embodiment)

Next, a modification of the second embodiment will be described.

The semiconductor memory device of the present modification has the same circuit as that of the first embodiment shown in FIG. 1, but the three-dimensional structure is different. That is, the present modification is a configuration schematically shown in FIG. 15, in which the first to fourth n-type field effect transistors Tn1 to Tn4 are formed on the semiconductor substrate, on the interlayer insulating film formed on those, The first and second p-type field effect transistors Tp1 and Tp2 are formed. Further, the channel region of the first p-type field effect transistor Tp1 is formed so as to overlap the gate electrode of the first n-type field effect transistor Tn1 from the normal direction of the semiconductor substrate, and the second p-type The channel field of the field effect transistor Tp2 is formed so as to overlap the gate electrode of the second n-type field effect transistor Tn2 from the normal direction of the semiconductor substrate.

Since the manufacturing steps of the semiconductor memory device of the present modification are essentially the same as the manufacturing steps of the above-described embodiment or its modifications, they are omitted.

Next, the results of numerical calculations relating to the semiconductor memory device having the configuration of the modification will be described. First, a case where the potential of the write timing bit line BL is the power supply voltage and the potential of the inverted bit line BL' is the ground potential is considered. In this case, when the potential of the post-bit bit line BL, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P1 in the figure. Therefore, the gate electrode of the first n-type field effect transistor Tn1 is 0.18V, and the second n-type field effect transistor Tn2 The gate electrode is 1.0V. Therefore, compared with the threshold voltage of the first p-type field effect transistor Tp1 in the channel region formed on the gate electrode of the first n-type field effect transistor Tn1, the second n-type field effect transistor The threshold voltage of the second p-type field effect transistor Tp2 formed in the channel region above the gate electrode of Tn2 is changed in a negative direction.

Therefore, here, compared with the case shown in FIG. 7, the threshold voltage of the first p-type field effect transistor Tp1 is changed by 50 mV in the positive direction, and the threshold voltage of the second p-type field effect transistor Tp2 is turned negative. The direction of the change is 50mV to calculate the butterfly curve. That is, the threshold voltage in the case where there is no change as a result of the change in the threshold voltage between the two is adjusted. The results are shown in Fig. 16A. As compared with the case where the threshold voltage shown in FIG. 7 does not change, it can be seen that the closed curve L1 becomes large, and the square SQ1 indicating the SNM for displaying the stability of P1 also becomes large. The specific value of the SNM in this case is 0.156V.

Next, a case where the potential of the write timing bit line BL is the ground potential and the potential of the inverted bit line BL' is the power supply voltage is considered. In this case, when the potential of the bit line BL after writing, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P2 in the figure. Therefore, the gate electrode of the first n-type field effect transistor Tn1 is 1.0V, and the gate electrode of the second n-type field effect transistor Tn2 is 0.18V. Therefore, the butterfly curve is a curve in which the vertical axis and the horizontal axis are replaced when displayed in Fig. 16A. The results are shown in Fig. 16B. As compared with the case where the threshold voltage shown in FIG. 7 does not change, it can be seen that the closed curve L2 becomes large, and the square SQ2 indicating the SNM for displaying the stability of P2 also becomes large. This situation The specific value of the SNM is 0.156 V as in the case shown in Fig. 16A.

Even in the present modification, various modifications as described in the above embodiments can be performed, and the same effects can be obtained.

(Third embodiment)

Next, a third embodiment of the semiconductor memory device of the present invention will be described.

Fig. 17 is a bird's eye view showing a schematic configuration of a semiconductor memory device according to a third embodiment of the present invention. Incidentally, the same portions as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The semiconductor memory device of the present embodiment has the same circuit as that of the first embodiment shown in FIG. 1. However, as shown schematically in FIG. 17, the first and second p-type field effects are formed on the semiconductor substrate. The transistors Tp1, Tp2 are formed with the first to fourth n-type field effect transistors Tn1 to Tn4 on the interlayer insulating film formed on those. Further, the channel regions of the first and fourth n-type field effect transistors Tn1 and Tn4 are formed so as to overlap the gate electrode of the first p-type field effect transistor Tp1 from the normal direction of the semiconductor substrate. The channel region of the second and third n-type field effect transistors Tn2 and Tn3 is formed so as to overlap the gate electrode of the second p-type field effect transistor Tp2 from the normal direction of the semiconductor substrate.

Since the manufacturing steps of the semiconductor memory device of the present embodiment are essentially the same as the manufacturing steps of the above-described embodiment or its modifications, they are omitted.

Next, a semiconductor having the structure of the embodiment is described The result of numerical calculations related to the memory device. First, a case where the potential of the write timing bit line BL is the power supply voltage and the potential of the inverted bit line BL' is the ground potential is considered. In this case, when the potential of the post-bit bit line BL, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P1 in the figure. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 0.18V, and the gate electrode of the second p-type field effect transistor Tp2 is 1.0V. Therefore, compared with the threshold voltage of the first and fourth n-type field effect transistors Tn1 and Tn4 formed in the channel region on the gate electrode of the first p-type field effect transistor Tp1, in the second p The threshold voltages of the second and third n-type field effect transistors Tn2 and Tn3 formed in the channel region on the gate electrode of the field effect transistor Tp2 are changed in a negative direction.

Therefore, here, compared with the case shown in FIG. 7, the threshold voltages of the first and fourth n-type field effect transistors Tn1 and Tn4 are changed by 50 mV in the positive direction, and the second and third n-type field effects are changed. The threshold voltage of the transistors Tn2 and Tn3 is changed by 50 mV in the negative direction to calculate a butterfly curve. That is, the threshold voltage in the case where there is no change as a result of the change in the threshold voltage results is adjusted. The results are shown in Fig. 18A. As compared with the case where the threshold voltage shown in FIG. 7 does not change, it can be seen that the closed curve L1 becomes large, and the square SQ1 indicating the SNM for displaying the stability of P1 also becomes large. The specific value of the SNM in this case is 0.213V.

Next, a case where the potential of the write timing bit line BL is the ground potential and the potential of the inverted bit line BL' is the power supply voltage is considered. In this case, if the potential of the bit line BL after writing, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 is the P2 in the figure. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 1.0V, and the gate electrode of the second p-type field effect transistor Tp2 is 0.18V. Therefore, the butterfly curve is a curve in which the vertical axis and the horizontal axis are replaced when displayed in Fig. 18A. The results are shown in Fig. 18B. As compared with the case where the threshold voltage shown in FIG. 7 does not change, it can be seen that the closed curve L2 becomes large, and the square SQ2 indicating the SNM for displaying the stability of P2 also becomes large. The specific value of the SNM in this case is 0.213 V which is the same as that shown in Fig. 18A.

Even in the present embodiment, various modifications as described in the above embodiments can be performed, and the same effects can be obtained.

(Modification of the third embodiment)

Next, a modification of the third embodiment will be described.

The semiconductor memory device of the present modification has the same circuit as that of the first embodiment shown in FIG. 1, but the three-dimensional structure is different. That is, the present modification is a structure schematically shown in FIG. 19, in which the first and second n-type field effect transistors Tn1, Tn2 are formed on the semiconductor substrate, on the interlayer insulating film formed on those, The first and second p-type field effect transistors Tp1, Tp2, the third and fourth n-type field effect transistors Tn3 and Tn4 are formed. Moreover, the channel field of the first p-type field effect transistor Tp1 and the fourth n-type field effect transistor Tn4 is a gate that looks like the first n-type field effect transistor Tn1 from the normal direction of the semiconductor substrate. The electrodes are formed by overlapping, and the channel field of the second p-type field effect transistor Tp2 and the third n-type field effect transistor Tn3 is the same as the second n-type field effect from the normal direction of the semiconductor substrate. The gate electrodes of the crystal Tn2 are formed in such a manner as to overlap.

Since the manufacturing steps of the semiconductor memory device of the present modification are essentially the same as the manufacturing steps of the above-described embodiment or its modifications, they are omitted.

Next, the results of numerical calculations relating to the semiconductor memory device having the structure of the present embodiment will be described. First, a case where the potential of the write timing bit line BL is the power supply voltage and the potential of the inverted bit line BL' is the ground potential is considered. In this case, when the potential of the post-bit bit line BL, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P1 in the figure. Therefore, the gate electrode of the first n-type field effect transistor Tn1 is 0.18V, and the gate electrode of the second n-type field effect transistor Tn2 is 1.0V. Therefore, compared with the threshold voltage of the first p-type field effect transistor Tp1 and the fourth n-type field effect transistor Tn4 formed in the channel region on the gate electrode of the first n-type field effect transistor Tn1. The threshold voltage of the second p-type field effect transistor Tp2 and the third n-type field effect transistor Tn3 formed in the channel region on the gate electrode of the second n-type field effect transistor Tn2 is negative. The direction changes.

Therefore, here, compared with the case shown in FIG. 7, the threshold voltage of the first p-type field effect transistor Tp1 and the fourth n-type field effect transistor Tn4 is changed by 50 mV in the positive direction, and the second p is used. The threshold voltage of the field effect transistor Tp2 and the third n-type field effect transistor Tn3 is changed by 50 mV in the negative direction to calculate a butterfly curve. That is, the threshold voltage in the case where there is no change as a result of the change in the threshold voltage results is adjusted. The results are shown in Fig. 20A. Compared with the case where the threshold voltage shown in FIG. 7 does not change, it can be seen that the closed curve L1 becomes larger, and the accompanying expression is for display. The square SQ1 of the SNM of the stability of P1 also becomes large. The specific value of SNM in this case is 0.182V.

Next, a case where the potential of the write timing bit line BL is the ground potential and the potential of the inverted bit line BL' is the power supply voltage is considered. In this case, when the potential of the bit line BL after writing, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P2 in the figure. Therefore, the gate electrode of the first n-type field effect transistor Tn1 is 1.0V, and the gate electrode of the second n-type field effect transistor Tn2 is 0.18V. Therefore, the butterfly curve is a curve in which the vertical axis and the horizontal axis are replaced when displayed in Fig. 20A. The results are shown in Fig. 20B. As compared with the case where the threshold voltage shown in FIG. 7 does not change, it can be seen that the closed curve L2 becomes large, and the square SQ2 indicating the SNM for displaying the stability of P2 also becomes large. The specific value of the SNM in this case is 0.182 V which is the same as that shown in Fig. 20A.

Even in the present modification, various modifications as described in the above embodiments can be performed, and the same effects can be obtained.

(Fourth embodiment)

Next, a fourth embodiment of the semiconductor memory device of the present invention will be described.

Fig. 21 is a bird's eye view showing a schematic configuration of a semiconductor memory device according to a fourth embodiment of the present invention. Incidentally, the same portions as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The semiconductor memory device of the present embodiment has the same circuit as that of the first embodiment shown in FIG. 1, but is schematically shown in FIG. The first and second p-type field effect transistors Tp1 and Tp2 are formed on the semiconductor substrate, and the first to fourth n-type field effect transistors are formed on the interlayer insulating film formed on those of the semiconductor substrate. Tn1~Tn4. Further, the channel region of the first n-type field effect transistor Tn1 is formed so as to overlap the gate electrode of the first p-type field effect transistor Tp1 from the normal direction of the semiconductor substrate, and the second n-type is formed. The channel field of the field effect transistor Tn2 is formed so as to overlap the gate electrode of the second p-type field effect transistor Tp2 from the normal direction of the semiconductor substrate.

Since the manufacturing steps of the semiconductor memory device of the present embodiment are essentially the same as the manufacturing steps of the above-described embodiment or its modifications, they are omitted.

Next, the results of numerical calculations relating to the semiconductor memory device having the structure of the present embodiment will be described. First, a case where the potential of the write timing bit line BL is the power supply voltage and the potential of the inverted bit line BL' is the ground potential is considered. In this case, when the potential of the post-bit bit line BL, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P1 in the figure. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 0.18V, and the gate electrode of the second p-type field effect transistor Tp2 is 1.0V. Therefore, compared with the threshold voltage of the first n-type field effect transistor Tn1 formed in the channel region on the gate electrode of the first p-type field effect transistor Tp1, the second p-type field effect transistor The threshold voltage of the second n-type field effect transistor Tn2 in which the channel region is formed on the gate electrode of Tp2 is changed in a negative direction.

Therefore, here is compared with the case shown in the foregoing FIG. The threshold voltage of the n-type field effect transistor Tn1 is changed by 50 mV in the positive direction, and the threshold voltage of the second n-type field effect transistor Tn2 is changed by 50 mV in the negative direction to calculate the butterfly curve. That is, the threshold voltage in the case where there is no change as a result of the change in the threshold voltage results is adjusted. The result is the same as the calculation result for the semiconductor memory device of the second embodiment shown in Fig. 14A. Therefore, the specific value of the SNM in this case is 0.188V.

Next, a case where the potential of the write timing bit line BL is the ground potential and the potential of the inverted bit line BL' is the power supply voltage is considered. In this case, when the potential of the bit line BL after writing, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P2 in the figure. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 1.0V, and the gate electrode of the second p-type field effect transistor Tp2 is 0.18V. Therefore, the butterfly curve is equal to the calculation result of the semiconductor memory device of the second embodiment shown in Fig. 14B. Therefore, the specific value of the SNM in this case is 0.188V.

Even in the present embodiment, various modifications as described in the above embodiments can be performed, and the same effects can be obtained.

(Modification of the fourth embodiment)

Next, a modification of the fourth embodiment will be described.

The semiconductor memory device of the present modification has the same circuit as that of the first embodiment shown in FIG. 1. However, as shown schematically in FIG. 22, the first and second n-type field effects are formed on the semiconductor substrate. The transistors Tn1 and Tn2 are formed on the interlayer insulating film formed on those layers. 1 and 2nd p-type field effect transistors Tp1, Tp2, 3rd and 4th n-type field effect transistors Tn3, Tn4. Further, the channel region of the first p-type field effect transistor Tp1 is formed so as to overlap the gate electrode of the first n-type field effect transistor Tn1 from the normal direction of the semiconductor substrate, and the second p-type The channel field of the field effect transistor Tp2 is formed so as to overlap the gate electrode of the second n-type field effect transistor Tn2 from the normal direction of the semiconductor substrate.

Since the manufacturing steps of the semiconductor memory device of the present modification are essentially the same as the manufacturing steps of the above-described embodiment or its modifications, they are omitted.

Next, the results of numerical calculations relating to the semiconductor memory device having the structure of the present embodiment will be described. First, a case where the potential of the write timing bit line BL is the power supply voltage and the potential of the inverted bit line BL' is the ground potential is considered. In this case, when the potential of the post-bit bit line BL, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P1 in the figure. Therefore, the gate electrode of the first n-type field effect transistor Tn1 is 0.18V, and the gate electrode of the second n-type field effect transistor Tn2 is 1.0V. Therefore, compared with the threshold voltage of the first p-type field effect transistor Tp1 in the channel region formed on the gate electrode of the first n-type field effect transistor Tn1, the second n-type field effect transistor The threshold voltage of the second p-type field effect transistor Tp2 formed in the channel region above the gate electrode of Tn2 is changed in a negative direction.

Therefore, here, compared with the case shown in FIG. 7, the threshold voltage of the first p-type field effect transistor Tp1 is changed by 50 mV in the positive direction, and the threshold voltage of the second p-type field effect transistor Tp2 is turned negative. Direction change 50mV To calculate the butterfly curve. That is, the threshold voltage in the case where there is no change as a result of the change in the threshold voltage results is adjusted. The result is the same as the calculation result for the modification of the second embodiment shown in Fig. 16A. Therefore, the specific value of SNM is 0.156V.

Next, a case where the potential of the write timing bit line BL is the ground potential and the potential of the inverted bit line BL' is the power supply voltage is considered. In this case, when the potential of the bit line BL after writing, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P2 in the figure. Therefore, the gate electrode of the first n-type field effect transistor Tn1 is 1.0V, and the gate electrode of the second n-type field effect transistor Tn2 is 0.18V. Therefore, the butterfly curve is equal to the calculation result shown in the above-described modification of the second embodiment shown in Fig. 16B. Therefore, the specific value of SNM is 0.156V.

Even in the present modification, various modifications as described in the above embodiments can be performed, and the same effects can be obtained.

(Fifth Embodiment)

Next, a fifth embodiment of the semiconductor memory device of the present invention will be described.

Fig. 23 is a circuit configuration diagram showing a semiconductor memory device according to a fifth embodiment of the present invention.

Incidentally, the same portions as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The semiconductor memory device of the present embodiment has the same circuit as that of the first embodiment shown in FIG. 1, but is schematically shown in FIG. a first and second p-type field effect transistors Tp1 and Tp2 are formed on the semiconductor substrate, and are formed on the interlayer insulating film formed on the first and second p-type field effect transistors Tp1 and Tp2. The first to fourth n-type field effect transistors Tn1 to Tn4 are formed. Further, the channel region of the third n-type field effect transistor Tn3 is formed so as to overlap the gate electrode of the second p-type field effect transistor Tp2 from the normal direction of the semiconductor substrate, and the fourth n-type The channel field of the field effect transistor Tn4 is formed so as to overlap the gate electrode of the first p-type field effect transistor Tp1 from the normal direction of the semiconductor substrate.

Since the manufacturing steps of the semiconductor memory device of the present embodiment are essentially the same as the manufacturing steps of the above-described embodiment or its modifications, they are omitted.

Next, the results of numerical calculations relating to the semiconductor memory device having the structure of the present embodiment will be described. First, a case where the potential of the write timing bit line BL is the power supply voltage and the potential of the inverted bit line BL' is the ground potential is considered. In this case, when the potential of the post-bit bit line BL, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P1 in the figure. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 0.18V, and the gate electrode of the second p-type field effect transistor Tp2 is 1.0V. Therefore, compared with the threshold voltage of the fourth n-type field effect transistor Tn4 formed in the channel region on the gate electrode of the first p-type field effect transistor Tp1, the second p-type field effect transistor is used. The threshold voltage of the third n-type field effect transistor Tn3 formed in the channel region above the gate electrode of Tp2 is changed in a negative direction.

Therefore, here is compared with the case shown in the foregoing FIG. The threshold voltage of the n-type field effect transistor Tn3 is changed by 50 mV in the negative direction, and the threshold voltage of the fourth n-type field effect transistor Tn4 is changed by 50 mV in the positive direction to calculate the butterfly curve. That is, the threshold voltage in the case where there is no change as a result of the change in the threshold voltage results is adjusted. As a result, it is equivalent to the calculation result of the semiconductor memory device of the first embodiment shown in Fig. 8A. Therefore, the specific value of the SNM in this case is 0.170V.

Next, a case where the potential of the write timing bit line BL is the ground potential and the potential of the inverted bit line BL' is the power supply voltage is considered. In this case, when the potential of the bit line BL after writing, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P2 in the figure. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 1.0V, and the gate electrode of the second p-type field effect transistor Tp2 is 0.18V. Therefore, the butterfly curve is equal to the calculation result of the semiconductor memory device of the first embodiment shown in Fig. 8B. Therefore, the specific value of the SNM in this case is 0.170V.

Even in the present embodiment, various modifications as described in the above embodiments can be performed, and the same effects can be obtained.

(Modification of the fifth embodiment)

Next, a modification of the fifth embodiment will be described.

The semiconductor memory device of the present modification has the same circuit as that of the first embodiment shown in FIG. 1, but the three-dimensional structure is different. That is, the present modification is a structure schematically shown in FIG. 24, in which the first and second n-type field effect transistors Tn1 and Tn2 are formed on the semiconductor substrate, and are formed on the semiconductor substrate. The first and second p-type field effect transistors Tp1, Tp2, the third and fourth n-type field effect transistors Tn3 and Tn4 are formed on the interlayer insulating film. Further, the channel region of the third n-type field effect transistor Tn3 is formed so as to overlap the gate electrode of the second n-type field effect transistor Tn2 from the normal direction of the semiconductor substrate, and the fourth n-type The channel region of the field effect transistor Tn4 is formed so as to overlap the gate electrode of the first n-type field effect transistor Tn1 from the normal direction of the semiconductor substrate.

Since the manufacturing steps of the semiconductor memory device of the present modification are essentially the same as the manufacturing steps of the above-described embodiment or its modifications, they are omitted.

Next, the results of numerical calculations relating to the semiconductor memory device having the structure of the present embodiment will be described. First, a case where the potential of the write timing bit line BL is the power supply voltage and the potential of the inverted bit line BL' is the ground potential is considered. In this case, when the potential of the post-bit bit line BL, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P1 in the figure. Therefore, the gate electrode of the first n-type field effect transistor Tn1 is 0.18V, and the gate electrode of the second n-type field effect transistor Tn2 is 1.0V. Therefore, compared with the threshold voltage of the fourth n-type field effect transistor Tn4 formed in the channel region on the gate electrode of the first n-type field effect transistor Tn1, the second n-type field effect transistor The threshold voltage of the third n-type field effect transistor Tn3 in which the channel region is formed on the gate electrode of Tn2 is changed in a negative direction.

Therefore, here, compared with the case shown in FIG. 7, the threshold voltage of the third n-type field effect transistor Tn3 is changed by 50 mV in the negative direction. The threshold voltage of the 4th n-type field effect transistor Tn4 is changed by 50 mV in the positive direction to calculate a butterfly curve. That is, the threshold voltage in the case where there is no change as a result of the change in the threshold voltage results is adjusted. The result is equal to the calculation result shown in Fig. 8A for the first embodiment. Therefore, the specific value of SNM is 0.170V.

Next, a case where the potential of the write timing bit line BL is the ground potential and the potential of the inverted bit line BL' is the power supply voltage is considered. In this case, when the potential of the bit line BL after writing, the potential of the inverted bit line BL', and the potential of the word line WL are at the potential of the power supply voltage, V1 and V2 are P2 in the figure. Therefore, the gate electrode of the first p-type field effect transistor Tp1 is 1.0V, and the gate electrode of the second p-type field effect transistor Tp2 is 0.18V. Therefore, the butterfly curve is equal to the calculation result shown in the above-mentioned Fig. 8B for the first embodiment. Therefore, the specific value of SNM is 0.170V.

Even in the present modification, various modifications as described in the above embodiments can be performed, and the same effects can be obtained.

(Modification)

Incidentally, the present invention is not limited to the above embodiments.

Regarding the feature of the present invention, the channel of the upper field effect transistor is superimposed on the gate electrode of the field effect transistor on the lower side, and it is not necessary that the channel region of the upper side of the transistor overlaps the transistor of the lower side as a whole. The gate electrodes may also overlap partially. Furthermore, it may not overlap the gate electrode itself but may overlap the wiring connected to the gate electrode. That is, at least a portion of the channel region of the upper transistor is a gate of the transistor that overlaps the lower side. At least a part of the electrode and the wiring connected to the gate electrode may be used.

In addition, the configuration of each transistor is not limited to the structure shown in FIG. 3, and can be appropriately changed depending on the specifications. Further, the film thickness or material of each portion may be appropriately changed depending on the specifications.

While a few embodiments of the invention have been described, the embodiments are not intended to limit the scope of the invention. The embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The invention and its modifications are included in the scope of the invention and the scope of the invention as set forth in the scope of the invention.

BL‧‧‧ bit line

BL’‧‧‧ reverse bit line

GND‧‧‧Wiring with potential at ground potential

Tn1~Tn4‧‧‧n type field effect transistor

Tp1~Tp2‧‧‧p type field effect transistor

VDD‧‧‧ potential is maintained at the wiring of the power supply voltage

WL‧‧‧ word line

Claims (11)

A semiconductor memory device comprising: a semiconductor substrate; first and second p-type field effect transistors formed on the semiconductor substrate; and first and second n-type field effect transistors; formed in the first and second An insulating film on the p-type field effect transistor and the first and second n-type field effect transistors; and third and fourth n-type field effect transistors formed on the insulating film; Each of the source regions of the first and second p-type field effect transistors and the substrate electrodes are connected to a wiring having a potential maintained at a power supply voltage, and each of the source regions of the first and second n-type field effect transistors The substrate electrode is connected to a wiring having a potential maintained at a ground potential, and each of the first p-type field effect transistor and the first n-type field effect transistor, and the second p-type field effect transistor and The gate electrodes of the second n-type field effect transistor and the third field of the n-type field effect transistor are connected to each other, and the second p-type field effect transistor and the second n-type field effect Each of the fields of the transistor, the first p-type field effect transistor, and the gate electrode of the first n-type field effect transistor, the fourth The field of the n-type field effect transistor is connected to each other, and the gate electrodes of the third and fourth n-type field effect transistors are connected to the word line, and the source field of the third n-type field effect transistor is Bit line The source region of the fourth n-type field effect transistor is connected to the inverted bit line, and the third and fourth n-type field effect transistors have a planar structure, and the third n-type field effect At least a part of the channel region of the transistor is a gate electrode which is superposed on the second p-type field effect transistor from the normal direction of the semiconductor substrate, and a wiring connected to the gate electrode, and the second n-type Forming at least a portion of a gate electrode of the field effect transistor and a wiring connected to the gate electrode, at least a portion of the channel region of the fourth n-type field effect transistor being viewed from a normal direction of the semiconductor substrate a method of superimposing a gate electrode of the first p-type field effect transistor, a wiring connected to the gate electrode, a gate electrode of the first n-type field effect transistor, and at least a portion of a wiring connected to the gate electrode form. A semiconductor memory device comprising: a semiconductor substrate; first and second p-type field effect transistors formed on the semiconductor substrate; and an insulating film formed on the first and second p-type field effect transistors; First and second n-type field effect transistors formed on the insulating film; third and fourth n-type field effect transistors formed on the semiconductor substrate; and the first and second p-type fields Source areas and bases of the effect transistor The plate electrode is connected to a wiring having a potential maintained at a power supply voltage, and each of the source regions of the first and second n-type field effect transistors, and the substrate electrodes of the third and fourth n-type field effect transistors are Connected to a wiring having a potential maintained at a ground potential, each of the first p-type field effect transistor and the first n-type field effect transistor, the second p-type field effect transistor, and the second The gate electrodes of the n-type field effect transistor and the 汲 field of the third n-type field effect transistor are connected to each other, and the second p-type field effect transistor and the second n-type field effect transistor are In each of the fields, the first p-type field effect transistor and the gate electrode of the first n-type field effect transistor and the fourth n-type field effect transistor are connected to each other, and the third and third The gate electrodes of the fourth n-type field effect transistor are connected to the word line, and the source field of the third n-type field effect transistor is connected to the bit line, and the fourth n-type field effect transistor is The source field is connected to the inverted bit line, and the first and second n-type field effect transistors have a planar structure, and the first n-type field effect transistor At least a part of the channel region is formed so as to overlap at least a part of the gate electrode of the first p-type field effect transistor and the wiring connected to the gate electrode from a normal direction of the semiconductor substrate, and the second portion At least a portion of the channel region of the n-type field effect transistor is formed by overlapping with a gate electrode of the second p-type field effect transistor from a normal direction of the semiconductor substrate and connected to the gate electrode Forming at least a portion of the wiring. A semiconductor memory device comprising: a semiconductor substrate; first and second p-type field effect transistors formed on the semiconductor substrate; and an insulating film formed on the first and second p-type field effect transistors; The first to fourth n-type field effect transistors formed on the insulating film; the source regions of the first and second p-type field effect transistors and the substrate electrodes are maintained at a power supply voltage with a potential The wiring is connected, and each of the source regions of the first and second n-type field effect transistors is connected to a wiring having a potential maintained at a ground potential, and the first p-type field effect transistor and the first n-type field are connected The respective fields of the effect transistor, the second p-type field effect transistor, the gate electrode of the second n-type field effect transistor, and the third field of the n-type field effect transistor are connected to each other. Each of the second p-type field effect transistor and the second n-type field effect transistor, the first p-type field effect transistor, and the first n-type field effect transistor The electrode and the 汲 field of the fourth n-type field effect transistor are connected to each other, and each of the third and fourth n-type field effect transistors Electrodes are connected to the word line, the source of the field effect transistor 3 of the n-type field is connected to the bit line, the source of the fourth field of the n-type field effect transistor with inverted bits a line connection, wherein the first to fourth n-type field effect transistors have a planar structure, and at least a part of the channel region of the first n-type field effect transistor is overlapped from a normal direction of the semiconductor substrate Forming at least a portion of the gate electrode of the first p-type field effect transistor and the wiring connected to the gate electrode, at least a part of the channel region of the second n-type field effect transistor is from the semiconductor The normal direction of the substrate is formed to overlap the gate electrode of the second p-type field effect transistor and at least a portion of the wiring connected to the gate electrode, and the channel region of the third n-type field effect transistor At least a part of the semiconductor substrate is formed so as to overlap at least a part of a gate electrode of the second p-type field effect transistor and a wiring connected to the gate electrode from a normal direction of the semiconductor substrate, and the fourth At least a part of the channel field of the field effect transistor is a gate electrode which appears to overlap the first p-type field effect transistor from the normal direction of the semiconductor substrate and is connected to the gate electrode The form of at least a portion of the line is formed. A semiconductor memory device comprising: a semiconductor substrate; first and second p-type field effect transistors formed on the semiconductor substrate; and an insulating film formed on the first and second p-type field effect transistors; The first to fourth n-type field effect transistors formed on the insulating film; the source regions of the first and second p-type field effect transistors and the substrate electrodes are maintained at a power supply voltage with a potential The wiring is connected, and each of the source regions of the first and second n-type field effect transistors is connected to a wiring having a potential maintained at a ground potential, and the first p-type field effect transistor and the first n-type field are connected The respective fields of the effect transistor, the second p-type field effect transistor, the gate electrode of the second n-type field effect transistor, and the third field of the n-type field effect transistor are connected to each other. Each of the second p-type field effect transistor and the second n-type field effect transistor, the first p-type field effect transistor, and the first n-type field effect transistor The electrode and the 汲 field of the fourth n-type field effect transistor are connected to each other, and the gate electrodes of the third and fourth n-type field effect transistors are connected to the word line, and the third n-type field effect power The source field of the crystal is connected to the bit line, and the source field of the fourth n-type field effect transistor is connected to the inverted bit line, and the first and second n-types are The effect transistor has a planar structure, and at least a part of the channel region of the first n-type field effect transistor is a gate that appears to overlap the first p-type field effect transistor from a normal direction of the semiconductor substrate Forming at least a portion of the electrode and the wiring connected to the gate electrode, and at least one of the channel regions of the second n-type field effect transistor The minute portion is formed so as to overlap at least a part of the gate electrode of the second p-type field effect transistor and the wiring connected to the gate electrode from the normal direction of the semiconductor substrate. A semiconductor memory device comprising: a semiconductor substrate; first and second p-type field effect transistors formed on the semiconductor substrate; and an insulating film formed on the first and second p-type field effect transistors; The first to fourth n-type field effect transistors formed on the insulating film; the source regions of the first and second p-type field effect transistors and the substrate electrodes are maintained at a power supply voltage with a potential The wiring is connected, and each of the source regions of the first and second n-type field effect transistors is connected to a wiring having a potential maintained at a ground potential, and the first p-type field effect transistor and the first n-type field are connected The respective fields of the effect transistor, the second p-type field effect transistor, the gate electrode of the second n-type field effect transistor, and the third field of the n-type field effect transistor are connected to each other. Each of the second p-type field effect transistor and the second n-type field effect transistor, the first p-type field effect transistor, and the first n-type field effect transistor The electrode and the 汲 field of the fourth n-type field effect transistor are connected to each other, and each of the third and fourth n-type field effect transistors Electrode is the word In the line connection, the source field of the third n-type field effect transistor is connected to the bit line, and the source field of the fourth n-type field effect transistor is connected to the inverted bit line, the third and the third The n-type field effect transistor of 4 has a planar structure, and at least a part of the channel field of the third n-type field effect transistor is overlapped with the second p-type field from the normal direction of the semiconductor substrate Forming at least a portion of a gate electrode of the effect transistor and a wiring connected to the gate electrode, wherein at least a portion of the channel region of the fourth n-type field effect transistor is overlapped from a normal direction of the semiconductor substrate The gate electrode of the first p-type field effect transistor and at least a portion of the wiring connected to the gate electrode are formed. A semiconductor memory device comprising: a semiconductor substrate; first to fourth n-type field effect transistors formed on the semiconductor substrate; and an insulating film formed on the first to fourth n-type field effect transistors; The first and second p-type field effect transistors formed on the insulating film; the source regions of the first and second p-type field effect transistors are connected to a wiring having a potential maintained at a power supply voltage, and the foregoing Each of the source regions of the first and second n-type field effect transistors and the substrate electrodes of the first to fourth n-type field effect transistors are connected to a wiring having a potential maintained at a ground potential. Each of the first p-type field effect transistor and the first n-type field effect transistor, the second p-type field effect transistor, and the second n-type field effect transistor The electrodes and the 汲 field of the third n-type field effect transistor are connected to each other, and the second p-type field effect transistor and the second n-type field effect transistor are in the respective fields, and the first p-type The field effect transistor and each of the gate electrodes of the first n-type field effect transistor and the first n-type field effect transistor are connected to each other, and the third and fourth n-type field effect transistors are connected to each other. Each of the gate electrodes is connected to the word line, and the source field of the third n-type field effect transistor is connected to the bit line, and the source field of the fourth n-type field effect transistor is connected to the inverted bit line. The first and second p-type field effect transistors have a planar structure, and at least a part of the channel region of the first p-type field effect transistor is overlapped from the normal direction of the semiconductor substrate Forming a gate electrode of the first n-type field effect transistor and at least a portion of the wiring connected to the gate electrode, and the second p-type field The transistor channel is at least a portion of the field from the normal direction of the semiconductor substrate superposed on the look of a gate electrode wiring effect transistor of the second field and the n-type electrode connected to the gate of forming at least part of the way. A semiconductor memory device comprising: a semiconductor substrate; and first and second n-type field effect transistors formed on the semiconductor substrate An insulating film formed on the first and second n-type field effect transistors; first and second p-type field effect transistors formed on the insulating film; and third and fourth An n-type field effect transistor; each of the source regions of the first and second p-type field effect transistors is connected to a wiring having a potential maintained at a power supply voltage, and the first and second n-type field effect transistors are Each of the source regions and the substrate electrodes is connected to a wiring having a potential maintained at a ground potential, and each of the first p-type field effect transistor and the first n-type field effect transistor, and the second p-type The field effect transistor and each of the gate electrodes of the second n-type field effect transistor and the third n-type field effect transistor are connected to each other, and the second p-type field effect transistor and the second Each of the fields of the n-type field effect transistor, the first p-type field effect transistor, and the gate electrode of the first n-type field effect transistor, and the fourth n-type field effect transistor The fields are connected to each other, and the gate electrodes of the third and fourth n-type field effect transistors are connected to the word line, and the source field of the third n-type field effect transistor is a bit field In the line connection, the source field of the fourth n-type field effect transistor is connected to the inverted bit line, and the first and second p-type field effect transistors and the third and fourth n-type field effects The transistor is a planar structure, and at least one of the channel regions of the first p-type field effect transistor The sub-field is formed so as to overlap at least a part of the gate electrode of the first n-type field effect transistor and the wiring connected to the gate electrode from a normal direction of the semiconductor substrate, and the second p-type field At least a portion of the channel region of the effect transistor is formed in such a manner as to overlap at least a portion of the gate electrode of the second n-type field effect transistor and the wiring connected to the gate electrode from a normal direction of the semiconductor substrate At least a portion of the channel region of the third n-type field effect transistor is formed by overlapping a gate electrode of the second n-type field effect transistor from a normal direction of the semiconductor substrate and is connected to the gate electrode Forming at least a portion of the wiring, wherein at least a portion of the channel region of the fourth n-type field effect transistor overlaps with the first n-type field effect transistor from a normal direction of the semiconductor substrate The gate electrode and at least a portion of the wiring connected to the gate electrode are formed. A semiconductor memory device comprising: a semiconductor substrate; first and second n-type field effect transistors formed on the semiconductor substrate; and an insulating film formed on the first and second n-type field effect transistors; First and second p-type field effect transistors formed on the insulating film, and third and fourth n-type field effect transistors; respective sources of the first and second p-type field effect transistors Field is with electricity The bit line is connected to the power supply voltage, and each of the source regions and the substrate electrodes of the first and second n-type field effect transistors are connected to a wiring having a potential maintained at a ground potential, and the first p-type field effect is applied. Each of the fields of the transistor and the first n-type field effect transistor, the second p-type field effect transistor, and the gate electrode of the second n-type field effect transistor, and the third n-type The field of the field effect transistor is connected to each other, and the second p-type field effect transistor and the second n-type field effect transistor, the first p-type field effect transistor and the first The gate electrodes of the n-type field effect transistor and the germanium field of the fourth n-type field effect transistor are connected to each other, and the gate electrodes of the third and fourth n-type field effect transistors are connected to the word line. The source field of the third n-type field effect transistor is connected to the bit line, and the source field of the fourth n-type field effect transistor is connected to the inverted bit line, the first and second The p-type field effect transistor has a planar structure, and at least a part of the channel field of the first p-type field effect transistor is from the aforementioned semiconductor base The normal direction is formed to overlap the gate electrode of the first n-type field effect transistor and at least a portion of the wiring connected to the gate electrode, and the channel region of the second p-type field effect transistor is At least a portion is formed so as to overlap at least a part of the gate electrode of the second n-type field effect transistor and the wiring connected to the gate electrode from a normal direction of the semiconductor substrate. A semiconductor memory device comprising: a semiconductor substrate; first and second n-type field effect transistors formed on the semiconductor substrate; and an insulating film formed on the first and second n-type field effect transistors; First and second p-type field effect transistors formed on the insulating film, and third and fourth n-type field effect transistors; respective sources of the first and second p-type field effect transistors The field is connected to a wiring having a potential maintained at a power supply voltage, and each of the source regions and the substrate electrodes of the first and second n-type field effect transistors are connected to a wiring having a potential maintained at a ground potential, and the first p Each field of the field effect transistor and the first n-type field effect transistor, the second p-type field effect transistor, and the gate electrode of the second n-type field effect transistor, the third The field of the n-type field effect transistor is connected to each other, and the second p-type field effect transistor and the second n-type field effect transistor, the first p-type field effect transistor and The gate electrodes of the first n-type field effect transistor and the 汲 field of the fourth n-type field effect transistor are connected to each other, and the third The gate electrodes of the fourth n-type field effect transistor are connected to the word line, and the source field of the third n-type field effect transistor is connected to the bit line, and the fourth n-type field effect transistor is The source field is connected to the inverted bit line. The third and fourth n-type field effect transistors have a planar structure, and at least a part of the channel region of the third n-type field effect transistor is overlapped with the foregoing from the normal direction of the semiconductor substrate. Forming a gate electrode of the n-type field effect transistor and at least a portion of the wiring connected to the gate electrode, and at least a part of the channel region of the fourth n-type field effect transistor is a method from the semiconductor substrate The line direction appears to be superimposed on at least a portion of the gate electrode of the first n-type field effect transistor and the wiring connected to the gate electrode. The semiconductor memory device according to any one of claims 1 to 9, wherein in a direction perpendicular to a surface of the semiconductor substrate, a gate electrode of the field effect transistor formed in the semiconductor substrate and a wiring connected to the gate electrode The upper end of the field overlapping with the channel field of the aforementioned field effect transistor formed on the insulating film, and the lower end of the channel field of the aforementioned field effect transistor formed on the insulating film are 70 nm or less. The semiconductor memory device according to any one of claims 1 to 9, wherein in a direction perpendicular to a surface of the semiconductor substrate, a gate electrode of the field effect transistor formed in the semiconductor substrate and a wiring connected to the gate electrode The upper end of the field overlapping with the channel field of the aforementioned field effect transistor formed on the insulating film, and the lower end of the channel field of the field effect transistor formed on the insulating film are 40 nm or less.