JPH0513766A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the resistance of a power supply wire in a semiconductor memory device such as a SRAM, etc., and hereby reduce an off-current. CONSTITUTION:In a semiconductor memory device wherein a memory cell is constructed using a flip-flop formed with a pair of driving transistors 13 of the first conductivity type channel and a pair of load transistors 14 of the second conductivity type channel, and wherein the load transistor 14 is formed with a semiconductor thin film the amount of infection of impurity into a source region 14s of the load transistor 14 is set to be high concentration compared with the amount of infection of impurity of a drain region 14d.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, a so-called TFT (Thin Film Transistor) load type SRAM (Static Random Access Memory) in which, for example, semiconductor thin films are stacked to form a load transistor. And its manufacturing method.

[0002]

2. Description of the Related Art A TFT load type SRAM has a pair of driving transistors 12 and 13 of a first conductivity type channel and a pair of second conductivity type channels as shown in FIG. Load transistors 14 and 15
It is composed of a flip-flop circuit formed by a pair of inverter circuits and a switching transistor 16 and 17.

Transistors 12, 13, 16 and 17
Is an insulated gate field effect transistor (MOS-FE
T), the ground line 21 is connected to the source side of the driving transistors 12 and 13, and the power line 22 is connected to the source regions of the load transistors 14 and 15. The word line 23 is connected to the gate electrodes of the switching transistors 16 and 17, respectively, and the true and reverse bit lines 24 and 25 are connected to the source / drain regions of one of the transistors 16 and 17, respectively.

FIG. 4 is a cross-sectional view of the main part of an example of such a load-type SRAM composed of TFTs made of polycrystalline Si.
This is a case where the load transistor 14 is configured by a P-channel thin film transistor. In FIG. 4, reference numeral 1 denotes a substrate on which an element isolation layer 2 and a gate insulating layer 3 are formed by thermal oxidation or the like, and a gate made of a first conductivity type, in this case, n-type polycrystalline Si or the like. The electrodes 4a and 4b are patterned by photolithography or the like. One gate electrode 4b is provided, for example, as a pattern extending in a direction orthogonal to the paper surface of FIG. 4, and n-type impurities are diffused on both sides thereof to form diffusion layers 5 forming source / drain regions. , The switching transistor 16 is configured.

The other gate electrode 4a is formed, for example, in a pattern extending in the direction of the paper surface of FIG. 4, and one end thereof is in contact with the above-mentioned diffusion layer 5 via the gate insulating layer 3. Then, for example, source / drain regions (not shown) are formed by impurity diffusion on both sides in a direction orthogonal to the plane of the paper of FIG. 4 to form the driving transistor 13. Then, on this gate electrode 4a, SiO ₂ ,
An insulating layer 6 made of Si ₃ N ₄ or the like is deposited, one end of the gate electrode 4a near the diffusion layer 5 is exposed, and an n-type polycrystalline Si layer is deposited, and then photolithography or the like is applied. Then, the gate electrode 7 and the connection layer 8 are formed by patterning into a desired pattern. Connection layer 8 in this case
Is deposited over the one diffusion layer 5 of the switching transistor 16 from the upper surface of one end of the lower gate electrode 4a.

A semiconductor layer 9 made of polycrystalline Si or the like is formed on the gate electrode 7 with an insulating layer 6 made of SiO ₂ or the like interposed therebetween.
Is deposited, p-type impurities are implanted on both sides of the gate electrode 7 to form the source region 14s and the drain region 14d, and the load transistor 14 is formed by the TFT. The drain region 14d is connected to the connection layer 8 through an opening formed in the insulating layer 6. On the other hand, source area 1
A part of the power supply line for power supply is formed in the extension of 4s.

With such a configuration, the drain region 14d of the load transistor 14 is connected to the gate electrode 4a of one driving transistor 13 and to the diffusion layer 5 serving as the source / drain region of the switching transistor 16. Thus, one of a pair of SRAM inverter circuits is configured.

At this time, the source / drain regions of the load transistor 14 are selected to have the same impurity dose amount, and the source region 14s is formed by overlapping so as to partially cover the gate electrode 7, and the drain region 14d is formed. Is configured to have a so-called offset that is separated from the gate electrode 7 to some extent. For example, the channel length Lc is 1.3 μm and the offset length Ld is 0.4 μm. The reason for such a configuration is that the source region 1
If the 4s side is not overlapped, the on-current of the TFT load transistor 14 is reduced. On the other hand, if the drain region 14d side is overlapped, the off current is reduced due to the tunnel current between the bands at the gate-drain overlap portion. This is due to the large size (eg IEDM: International Electron Device
Meeting, 1990, Proceedings p.469-p.472).

However, in the case of such a configuration, it is necessary to reduce the wiring resistance of the power supply line in order to increase the on-current of the load transistor 14 composed of a TFT. If the impurity dose amount of the impurity is increased, the diffusion length of the impurity in the lateral direction increases and the effective channel length L of the transistor 14 increases.
There is a problem that c becomes small and the off current becomes large.

[0010]

SUMMARY OF THE INVENTION According to the present invention, in the semiconductor memory device as described above, the resistance of the power supply line can be reduced without causing a variation in off current.

[0011]

FIG. 1 shows an enlarged schematic cross-sectional view of a main part of an example of a semiconductor memory device according to the present invention.
According to the present invention, as shown in FIG. 1, a memory cell is configured by using a flip-flop formed by a pair of driving transistors 12 of a first conductivity type channel and a pair of load transistors 14 of a second conductivity type channel. In the semiconductor memory device in which the load transistors 14 and 15 are formed of a semiconductor thin film, the impurity implantation amount of the source region of the load transistor 14 is set to be higher than that of the drain region 14d.

According to another aspect of the present invention, in the above-described method of manufacturing a semiconductor memory device, the impurity dose amount of the source region 14s and the drain region 14d of the load transistor 14 is set to be large in the source region 14s and small in the drain region 14d.

[0013]

As described above, in the semiconductor memory device according to the present invention, the impurity implantation amount of the source region 14s of the load transistor 14 is formed by increasing the dose amount, that is, by setting the impurity concentration to a high concentration. Since the resistance of the power supply line can be reduced and this high-concentration impurity diffuses to the channel region side, the source region 14s can be overlaid on the gate electrode 4a by an appropriate amount by appropriately selecting the concentration. It can be lapped and the on-current can be increased. In addition, an appropriate channel length Lc can be obtained, and an increase in off current of the load transistor 14 can be avoided.

On the other hand, the drain region 14d side is formed with a small impurity dose amount, that is, the impurity concentration is set to a relatively low concentration. Therefore, as in the conventional semiconductor memory device, the overlap portion between the gate and the drain is formed. This can be prevented from occurring, and the off current can be prevented from becoming large due to the tunnel current between the bands.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a semiconductor memory device according to the present invention will be described below with reference to FIG. 1, and its manufacturing method will be described with reference to FIGS.
This will be described in detail with reference to the manufacturing process chart of C. in this case,
The TFT load type S described in the circuit diagram of FIG.
In the RAM, for example, load transistors 14 and 1
5 comprises a first conductivity type channel, eg P-channel polycrystalline thin film transistor, and these PMOS transistors 14 and 15 on the second conductivity type channel, eg N-channel polycrystalline thin film transistor, ie NMOS driving transistors 12 and 13. A case of a stacked CMOS type SRAM in which the memory cell area is reduced to the same level as the resistance load type SRAM by stacking is shown.

In FIG. 1, a load transistor 14 is formed on one of the drive transistors 13, the drain region of the load transistor 14 is connected to the gate electrode 4a of the drive transistor 13, and switching is performed. A portion where the source / drain region of the transistor 16 is connected is shown, and the formation of the source / drain region of the load transistor 14 is performed by the same manufacturing process as that described in the related art, for example, in FIG.

In FIG. 1, 1 is a substrate made of Si or the like,
An element isolation layer 2 and a gate insulating layer 3 are formed thereon by thermal oxidation or the like, and gate electrodes 4a, 4b made of a first conductivity type, in this case, n-type polycrystalline Si or the like are formed thereon by photolithography or the like. It is patterned. One gate electrode 4b is provided, for example, as a pattern extending in a direction orthogonal to the paper surface of FIG. 1, and on both sides thereof, for example, n-type impurities are implanted to form a diffusion layer 5 forming a source / drain region. , The switching transistor 16 is configured.

The other gate electrode 4a is formed, for example, in a pattern extending in the direction along the paper surface of FIG. 1, and one end thereof is in contact with the above-mentioned diffusion layer 5 via the gate insulating layer 3. Then, for example, source / drain regions (not shown) are formed by impurity diffusion on both sides in a direction orthogonal to the plane of the paper of FIG. 1 to form the driving transistor 13. Then, on this gate electrode 4a, SiO ₂ ,
An insulating layer 6 made of Si ₃ N ₄ or the like is deposited, one end of the gate electrode 4a near the diffusion layer 5 is exposed, and an n-type polycrystalline Si layer is deposited, and then photolithography or the like is applied. Then, the gate electrode 7 and the connection layer 8 are formed by patterning into a desired pattern. Connection layer 8 in this case
Is deposited over the one diffusion layer 5 of the switching transistor 16 from the upper surface of one end of the lower gate electrode 4a on the driving transistor 13 side.

A semiconductor layer 9 made of polycrystalline Si or the like is formed on the gate electrode 7 via an insulating layer 6 made of SiO ₂ or the like.
Is put on. The semiconductor layer 9 is connected to the connection layer 8 through an opening formed in the insulating layer 6. Then, p-type impurities are locally ion-implanted into the semiconductor layer 9 to form source / drain regions. This forming process will be described with reference to FIGS.

As shown in FIG. 2A, a resist 31 for exposing the source region, that is, the power source line side is formed on the semiconductor layer 9 by, for example, photoresist coating, pattern exposure, and development. This resist 31 is patterned with an offset of a distance Ls from the end of the gate electrode 7 on the source side. In this case, Ls is set to 0.1 μm, for example. Then, using the resist 31 as a mask, p-type impurities such as BF ₂ ⁺ are ion-implanted with a dose amount of about 1 to 3 × 10 ¹⁵ cm ⁻² to form the source region 14s. At this time, a part of the power supply line for supplying power is formed in the extension portion of the source region 14s. After that, the resist 31 is removed.

Next, as shown in FIG. 2B, a resist 32 is similarly formed in a pattern exposing the drain side of the gate electrode 7 on the semiconductor layer 9. At this time, patterning is performed with an offset of a distance Ld from the end of the gate electrode 7 on the drain side, and using this resist 32 as a mask, p-type impurities, for example, BF ₂ ⁺ having a lower concentration than that of the prior art, for example, 5 to 10 ×. Ions are implanted with a dose amount of about 10 ¹³ cm ^-2 to form the drain region 14d.

Thereafter, the resist 32 is removed, and the drain region 1 of the load transistor 14 is removed as shown in FIG. 2C.
4d is connected to the gate electrode 4a of the driving transistor 13 and is connected to the diffusion layer serving as the source / drain region of the switching transistor (not shown) by the connection layer 8, so that one of the paired inverter circuits of the SRAM is connected. Composed.

In this case, since the impurity is implanted at a high concentration in the source region 14s, it is possible to reduce the wiring resistance, and the impurity is gated by the heat treatment or the like during the subsequent formation of the interlayer insulating layer or the wiring layer. Is diffused to the upper side of the electrode 7 with a diffusion length indicated by Lf in the figure,
The gate electrode 7 can be overlapped so as to partially cover it. Thereby, reduction of the on-current of the load transistor 14 can be avoided, and the source region 14 can be prevented.
This on-current can be increased in order to increase the impurity concentration of s. At this time, the effective channel length Lc can be appropriately selected by selecting the offset amount Ls and the dose amount of the source region 14s in consideration of the diffusion length Lf, and the increase of the off current can be avoided. be able to.

Further, as described above, since the impurity concentrations of the source region 14s and the drain region 14d are individually set, the dose amount in the drain region 14d can be made lower than that of the conventional one. The offset amount can be made small, and the tunnel current between the source / drain bands can be reduced because the impurity concentration is small. Even if the exposure mask is misaligned during the patterning of each layer and the drain region 14d overlaps the gate electrode 7 so as to partially cover the gate electrode 7, the band-to-band tunnel current is reduced. Can be suppressed.

The present invention is not limited to the above-described embodiment, and for example, a so-called impurity-injection region having a lower concentration than the outside thereof is provided inside the source / drain region of the load transistor 14, that is, on the channel side. LDD (Lig
The present invention can be applied to semiconductor memory devices having various other configurations such as a htly doped drain structure.

The manufacturing method is not limited to the above-mentioned embodiment, and for example, both source and drain regions 14s and 1s are formed.
Various manufacturing methods can be employed, such as implanting impurities into 4d at the same concentration and then implanting impurities only in the source region 14s so that the impurity concentration becomes higher.

[0027]

As described above, according to the semiconductor memory device of the present invention, the source region 14s of the load transistor 14 is formed.
The resistance of the power supply line can be reduced by setting a relatively high concentration of the impurities to be implanted, and the concentration of the impurities is diffused to the channel region side, so that the concentration is appropriately selected. As a result, the source region 14s can be overlapped on the gate electrode 4a by an appropriate amount, and the ON current can be increased. Further, an appropriate channel length Lc can be obtained, and an increase in off current of the load transistor 14 can be avoided.

On the other hand, since the impurity concentration of the drain region 14d is set to a relatively low concentration, it is possible to avoid the overlap portion between the gate and the drain as in the conventional semiconductor memory device and to prevent the band-to-band overlap. It is possible to prevent the off current from becoming large due to the tunnel current.

[Brief description of drawings]

FIG. 1 is an enlarged schematic cross-sectional view of a main part of an example of a semiconductor memory device of the present invention.

FIG. 2 is a manufacturing process diagram of an example of a method of manufacturing a semiconductor memory device of the present invention.

FIG. 3 is a circuit diagram of a semiconductor memory device.

FIG. 4 is an enlarged schematic cross-sectional view of a main part of a conventional semiconductor memory device.

[Explanation of symbols]

1 base 2 element isolation layer 3 Gate insulation layer 4a Gate electrode 4b gate electrode 5 diffusion layer 6 insulating layers 7 Gate electrode 8 connection layers 9 Semiconductor layer 12 Driving transistor 13 Driving transistor 14 Load transistor 14s Source area 14d drain region 15 Load transistor 16 word transistor 17 word transistor 21 Ground wire 22 power line 23 word lines 24-bit line 25 bit line

Claims (2)

[Claims] 1. A memory cell is configured using a flip-flop formed by a pair of driving transistors of a first conductivity type channel and a pair of loading transistors of a second conductivity type channel, and the load transistor is a semiconductor. A semiconductor memory device formed of a thin film, wherein the amount of impurities implanted into the source region of the load transistor is set to be higher than the amount of impurities implanted into the drain region. 2. A memory cell is configured using a flip-flop formed by a pair of driving transistors of a first conductivity type channel and a pair of loading transistors of a second conductivity type channel, and the load transistor is a semiconductor. A method of manufacturing a semiconductor memory device formed of a thin film, characterized in that an impurity dose amount of the source region and the drain region of the load transistor is large in the source region and small in the drain region. .