WO2014173133A1 - Procédé de décodage et appareil de décodage pour code polaire - Google Patents

Procédé de décodage et appareil de décodage pour code polaire Download PDF

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Publication number
WO2014173133A1
WO2014173133A1 PCT/CN2013/088492 CN2013088492W WO2014173133A1 WO 2014173133 A1 WO2014173133 A1 WO 2014173133A1 CN 2013088492 W CN2013088492 W CN 2013088492W WO 2014173133 A1 WO2014173133 A1 WO 2014173133A1
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path
merge
length
paths
polar
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PCT/CN2013/088492
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English (en)
Chinese (zh)
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李斌
沈晖
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华为技术有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes

Definitions

  • Embodiments of the present invention relate to the field of codec and, more particularly, to a decoding method and decoding apparatus for a Polar code (polar code). Background technique
  • Communication systems usually use channel coding to improve the reliability of data transmission and ensure the quality of communication.
  • the Polar code is an encoding method that can achieve Shannon capacity and has low coding and decoding complexity.
  • the Polar code is a linear block code.
  • the generator matrix is GN.
  • BN is a transposed matrix, such as a bit reversal matrix.
  • u A. is a frozen bit, the number of which is (N_K), which is a known bit. For simplicity, these freeze bits can be set to zero.
  • the decoding of the Polar code can be decoded by SC (successive-cancellation).
  • SC uccessive-cancellation
  • y is the received signal vector (yl, ⁇ 2, ..., yN) and is the bit vector (ul, u2, -, ui-l) 0 W is the transition probability and L is the log likelihood ratio. If icA, the following judgment:
  • SC decoding The complexity of SC decoding is 0 (Nlog2N). SC decoding can achieve good performance under the condition that the code length N is very long, and it is close to the Shannon limit.
  • the bit-by-bit order decoding is performed, and after each bit is decoded, the hard bit is performed and then used for subsequent bit decoding. This may result in error propagation, resulting in degraded decoding performance.
  • List (decoding) Decoding preserves multiple candidate paths to achieve decoding performance that approximates maximum likelihood. The combination of SC decoding and List decoding results in SC-List decoding.
  • SC-List decoding can only perform bit-by-bit sequential decoding, with large decoding delay and low decoding throughput.
  • the embodiment of the invention provides a decoding method and a decoder for a Polar code, which can improve the decoding throughput of the Polar code.
  • a method for decoding a Polar code including: dividing a first Polar code of length N into s second Polar codes, wherein each second Polar code has a length of N/s N and s is an integer power of 2 and N>s; the path of the list of the second Polar codes is split in parallel, and the split paths of the s second Polar codes are merged after the path splitting, thereby obtaining Multiple merge paths of length N; select the number of multiple merge paths of length N bits a merge path, where the first merge path is the path with the largest path metric value among the plurality of merge paths with the length of N bits or the path of the CRC through the cyclic redundancy check in the multiple merge paths of length N bits; The first merge path obtains a decoding result of the first Polar code.
  • performing subsequent path splitting and merging processing according to the P strip merge path of length kXs to obtain multiple merges of length N The path includes: when k ⁇ N/s, if P Lma X , decomposing the P-type merge path of length kXs into s merge path groups, and each of the merge path groups includes P with length k
  • the strip merge path is used as a survivor path, and the s merge path groups are respectively used in path splitting and merging processing for the k+1th bit of the s second Polar codes; if P>Lmax, the slave length is kX s
  • the Lmax strip merge path with the largest path metric is selected in the P merge path, and the selected Lmax strip merge path is decomposed into s merge path groups, and each merge path group includes a Lmax strip merge path of length k as a survivor path.
  • combining s second according to the nature of the bit corresponding to the kth bit of the s second Polar codes in the first Polar code A total of sX2L split paths corresponding to the Polar code, resulting in a P-segment of length kXs
  • the path includes: when the bits corresponding to the kth bit of the s second Polar codes in the first Polar code are frozen bits, the split path whose kth bit is equal to the specific value is selected and merged to obtain a length of k X s
  • the s second are combined according to the nature of the bit corresponding to the kth bit of the s second Polar codes in the first Polar code.
  • a total of s X 2L split paths corresponding to the Polar code, and a P merge path of length k X s is obtained, including: when there are w bits in the first Polar code corresponding to the kth bit of the s second Polar codes
  • the split path corresponding to the k-th bit of the freeze bit is not equal to the specific value, and the remaining split paths are merged to obtain the middle of the P-length of k X s
  • the first Polar code of length N is divided into s second Polar codes that are coupled to each other, including: the first Polar code
  • the received signal vectors are sequentially equally divided into s-segment received signal vectors, and each received signal vector is used as a received signal vector of a second Polar code to determine s second Polar codes.
  • a decoding apparatus for a Polar code including: a segmentation unit, configured to divide a first Polar code of length N into s second Polar codes, wherein a length of each second Polar code N/s, N and s are integer powers of 2 and N>s; split merging unit, for splitting the path of Lis decoding of s second Polar codes in parallel, and s after path splitting The split path of the second Polar code is merged to obtain a plurality of merge paths of length N; the selecting unit is configured to select the first merge path of the plurality of merge paths of length N bits, and the first merge path is length a path having the largest path metric value among the plurality of merge paths of the N bits or a path for verifying the CRC by cyclic redundancy in a plurality of merge paths having a length of N bits; and determining means for obtaining the first according to the first merge path The decoding result of a Polar code.
  • the split combining unit further includes a decomposer.
  • the decomposer When k ⁇ N/s, if P Lmax, the decomposer is used to set the length to The P merge path of k X s is decomposed into s merge path groups, each merge path group contains P merge paths of length k as surviving paths, and the resolver is also used to output s merge path groups to s respectively.
  • Decoders so that s decoders perform path splitting of the k+1th bit of the s second Polar codes in parallel; if P>Lm ax , the resolver is used to merge from P strips of length k X s
  • the Lmax strip merge path with the largest path metric is selected in the path, and the selected Lmax strip merge path is decomposed into s merge path groups, and each merge path group includes a Lmax strip merge path of length k as a survivor path, and decomposed
  • the device is further configured to output s merge path groups to s decoders respectively, so that s decoders perform path splitting of the k+1th bits of the s second Polar codes in parallel; wherein Lmax is a predetermined maximum The number of paths.
  • the combiner is further configured to use a P-type merge path of length k X s as the length N. Multiple merge paths.
  • the combiner is specifically configured to: when the bit corresponding to the kth bit of the s second Polar codes in the first Polar code is frozen When the bit is selected, the split path with the kth bit equal to the specific value is selected and merged to obtain the P intermediate merge path of length k X s, and the P intermediate merge path is taken as the P merge path, where? 4.
  • the specific value is the value of the frozen bit.
  • the combiner is specifically configured to: when the bit corresponding to the kth bit of the s second Polar codes in the first Polar code exists When information bits and sw freeze bits, where w is an integer and 0 ws, the split path corresponding to the kth bit of the freeze bit is not equal to the specific value, and the remaining split paths are merged.
  • the decoder is further configured to calculate a path metric value of each split path.
  • the segmentation unit is specifically configured to sequentially divide the received signal vector of the first Polar code into s segment received signal vectors, each segment The received signal vector is used as a received signal vector of a second Polar code to determine s second Polar codes.
  • a Polar code of length N is divided into a multi-segment Polar code, and the segmented Polar code is independently split, and then the obtained split paths are combined, and finally the merge path with the largest path metric value is obtained.
  • the decoding result of the original Polar code is obtained, so that it is not necessary to sequentially decode N bits, which can improve the decoding throughput of the Polar code and reduce the decoding delay.
  • FIG. 1 is a flow chart of a method of decoding a Polar code according to an embodiment of the present invention.
  • Fig. 4 is a block diagram showing a decoding apparatus of a Polar code according to an embodiment of the present invention.
  • FIG. 5 is a schematic block diagram of an apparatus in accordance with another embodiment of the present invention. detailed description
  • Embodiment 1 As shown in FIG. 1 , a flowchart of a method for constructing a service message according to an embodiment of the present invention includes the following steps:
  • the technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
  • GSM Global System of Mobi le communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • UMTS Universal Mobi-Telecommunication System
  • FIG. 1 is a flow chart of a method of decoding a Polar code according to an embodiment of the present invention.
  • the method of Figure 1 can be performed by a decoding device of the Polar code.
  • the decoding means may be located in a receiving device of the Polar code, for example by a processor in the receiving device, or by a dedicated Polar decoder in the receiving device.
  • the first Polar code of length N is divided into s second Polar codes, wherein each second Polar code has a length of N/s, N and s are integer powers of 2, and N>s.
  • the s second Polar codes are coupled to each other, that is, the information bits of the s second Polar codes are Association.
  • the length of the Polar code refers to the number of bits included in the Polar code.
  • the Polar code has an intrinsic recursive structure and can be divided into a plurality of Polar codes that are coupled to each other and have a shorter length.
  • the received signal vector of the first Polar code may be sequentially equally divided into s segments, and each received signal vector is used as a received signal of the second Polar code.
  • a Polar code of length N can be divided into two N/2 long Polar codes that are coupled to each other, ie The above second Polar code.
  • two second Polar codes of length N/2 can be obtained:
  • step 101 the received signal vector of the first Polar code is divided into N/2
  • the received signal vector for the two second Polar codes The received signal vector for the two second Polar codes.
  • a Polar code of length N can be expressed as:
  • step 101 the received signal vector of the first Polar code is
  • the received signal vectors of 4 second Polar codes are / 4+1 > / 2+1 and _3 ⁇ 4/ 4+1 .
  • a Polar code of length N can be expressed as:
  • step 101 the received signal vector of the first Polar code is divided into eight received signal vectors of the second Polar code ⁇ " /8 , d :
  • s second Polar codes can be similarly obtained, and details are not described herein again.
  • the embodiment of the present invention does not limit the segmentation manner of the Polar code, and may also perform segmentation in other ways than the sequential division, as long as the mutual coupling between the segmented Polar codes is ensured.
  • Path splitting refers to two split paths based on the previous decoding path based on the current decoding bits of 0 and 1.
  • the path metrics of each split path can be settled. The larger the path metric value, the higher the reliability of the corresponding path.
  • An example of the path metric is the logarithm of the path probability value, but the embodiment of the present invention does not limit the specific form of the path metric.
  • the first merge path selecting, by the first merge path, the first merge path of the multiple merge paths of the length N, where the first merge path is the path with the largest path metric value among the multiple merge paths of the length N or The path of the CRC (Cyclic Redundancy Check) in the multiple merge paths of N.
  • CRC Cyclic Redundancy Check
  • the first merge path thus obtained is the most reliable path and can therefore be used to obtain the final decoded result.
  • the decoding result of the first Polar code can be obtained from the decoding result of the second Polar code according to the correspondence between the second Polar code and the respective bits of the first Polar code.
  • An exemplary process of obtaining a decoding result of the first Polar code will be described in more detail below in conjunction with a specific embodiment.
  • a Polar code of length N is divided into a multi-segment Polar code, and the segmented Polar code is independently split, and then the obtained split paths are combined to obtain a merge path with the largest path metric value.
  • the decoding result of the original Polar code is obtained, so that it is not necessary to sequentially decode N bits, which can improve the decoding throughput of the Polar code and reduce the decoding delay.
  • the embodiment of the present invention only needs a decoder with a length of N/s, which can reduce the resources and computational complexity occupied by a single decoder, so that it can be flexibly applied to a resource-constrained scenario.
  • the decoder in the embodiment of the present invention may be implemented entirely by dedicated hardware, such as a dedicated chip, an integrated circuit, or other firmware; or may be implemented by a general-purpose processor and its instructions, and the instructions may be stored in the processor. Or stored in a separate memory.
  • s length decoders of length N/s can be used to split the second Polar code and calculate the path metric of each split path. This eliminates the need to serially split the path bit by bit, improving the decoding throughput and reducing the decoding delay.
  • the total s corresponding to the s second Polar codes are combined.
  • P is a positive integer and P s X 2L.
  • the corresponding bit refers to the position of the kth bit of the second Polar code originally in the first Polar code.
  • the input bit of the first Polar code is represented as ( ⁇ , o
  • the path is merged according to the P strips of length k X s
  • different processing may be performed according to the current value of k.
  • Each merged path group includes an Lmax strip merge path of length k as a survivor path, and s merge path sets are used for path splitting and merging processing of the k+1th bit of the s second Polar codes, respectively.
  • Lmax is the predetermined maximum number of paths. Using the threshold Lmax can avoid excessive algorithm complexity.
  • the P-strip merge path of length k X s can be used as multiple merge paths of length N.
  • the total s X 2L split paths corresponding to the s second Polar codes are combined according to the nature of the bits corresponding to the kth bit of the s second Polar codes in the first Polar code.
  • the split path with the kth bit equal to the specific value is selected.
  • Combine to obtain P intermediate merge paths of length k X s, thus obtaining P L.
  • the above specific value is the value of the frozen bit, such as '0'.
  • the total s X 2L split paths corresponding to the s second Polar codes are combined according to the nature of the bits corresponding to the kth bit of the s second Polar codes in the first Polar code.
  • the P strip merge path of length k X s is obtained
  • the first Polar code is associated with s
  • the split path corresponding to the kth bit of the frozen bit is not equal to the specific value, and the merge is performed.
  • the above specific value is the value of the frozen bit, for example, '0'.
  • the received signal vector of the first Polar code may be sequentially equally divided into s-segment received signal vectors, and each received signal vector is received as a second Polar code.
  • the signal vector determines s second Polar codes.
  • the Polar code of length N is divided into two Polar codes of length N/2, that is, the first half of the received signal vector ⁇ and the second half of the received signal vector / 2+1 .
  • the corresponding input bits are satisfied:
  • Two SC-list decoders A and B of length N/2 can be used to perform parallel path splitting on two N/2 long Polar codes, respectively.
  • the current L surviving paths are: H Md ⁇ , where (i ⁇ w ⁇ ).
  • path ⁇ 1 , 2 ' ⁇ "' ⁇ ⁇ is used for decoder A
  • path ⁇ , , ⁇ , " ⁇ is used for decoder B.
  • the 2L merge paths are: ⁇ ⁇ , , ⁇ ⁇ ⁇ and
  • the path metric is the logarithm of the path probability value.
  • Path metric; M ( ⁇ , V f 2 » is the path metric for path ⁇ .
  • the embodiment of Fig. 2 decodes the two second Polar codes in parallel, thus improving decoding throughput and reducing latency.
  • the Polar code of length N is divided into four Polar codes of length N/4, that is, four received signal vectors, /2+1 and ⁇ /4+1 .
  • the corresponding input bits are satisfied:
  • the path of the merge path is a combination of 4 paths:
  • MP m v k , v k+N 4 , v k+N , v ⁇ , MA m , a m , k , + MB m , i mk , + MC m , d m , k , + MD m , k , .
  • the Lmax path with the largest Lmax path metric value is selected from the JL paths, and then the Lmax paths are decomposed from the selected Lmax paths ⁇ ' ⁇ ' ⁇ ' ⁇ ⁇ ⁇ ⁇ for decoder A Lmax path decoder B Lmax paths ⁇ C - ⁇ ⁇ for decoder C Lmax path decoder D
  • FIG. 4 is a block diagram showing a decoding apparatus of a Polar code according to an embodiment of the present invention.
  • the 40 includes a segmentation unit 41, a split merge unit 42, a selection unit 43, and a determination unit 44.
  • the segmentation unit 41 is configured to divide the first Polar code of length N into s second Polar codes coupled to each other, wherein each second Polar code has a length of N/s, and N and s are integer powers of 2.
  • the split merging unit 42 is configured to perform path splitting on the s second Polar codes in parallel, and combine the split paths of the s second Polar codes after the path splitting, thereby obtaining a length of N Strip merge path;
  • the selecting unit 43 is configured to select a first merge path of the multiple merge paths of the length N, where the first merge path is the path with the largest path metric value among the multiple merge paths of the length N or a length of N
  • the path of the CRC is verified by cyclic redundancy in multiple merge paths;
  • the determining unit 44 is configured to obtain a decoding result of the first Polar code according to the first merge path.
  • a Polar code of length N is divided into a multi-segment Polar code, and the segmented Polar code is independently split, and then the obtained split paths are combined, and finally the merge path with the largest path metric value is obtained.
  • the decoding result of the original Polar code is obtained, so that it is not necessary to sequentially decode N bits, which can improve the decoding throughput of the Polar code and reduce the decoding delay.
  • the embodiment of the present invention only needs a decoder with a length of N/s, which can reduce the resources and computational complexity occupied by a single decoder, so that it can be flexibly applied to a resource-constrained scenario.
  • the decoder in the embodiment of the present invention may be implemented entirely by dedicated hardware, such as a dedicated chip, an integrated circuit, or other firmware; or may be implemented by a general purpose processor and its instructions.
  • the commands can be stored in the processor or stored in a separate memory.
  • the combiner 422 is configured to combine the total s X 2L split paths corresponding to the s second Polar codes according to the nature of the bits corresponding to the kth bit of the s second Polar codes in the first Polar code, to obtain a length k P strip merge paths of X s, P is a positive integer and P s X 2L, and P merge paths of length k X s are used for subsequent path splitting and merging processing.
  • the split combining unit 42 may further include a decomposer 423.
  • the decomposer When k ⁇ N/s, if P Lmax, the decomposer is used to decompose the P strip merge path of length k X s into s merge path groups, and each merge path group contains P strip merge paths of length k as The path is survived, and the decomposer is further configured to output the s merge path groups to the s decoders, respectively, so that the s decoders perform the path splitting of the k+1th bits of the s second Polar codes in parallel.
  • the resolver is used to select the Lmax strip merge path with the largest path metric value from the P strip merge paths of length k X s, and decompose the selected Lmax strip merge path into s merge path groups, each The merge path group includes a Lmax strip merge path of length k as a survivor path, and the resolver is further configured to output s merge path groups to s decoders, respectively, so that s decoders perform s The path of the k+1th bit of the second Polar code is split.
  • Lmax is the predetermined maximum number of paths.
  • the combiner 422 is further configured to use a length of k X s
  • the P strip merge path is used as multiple merge paths of length N.
  • the combiner 422 is specifically configured to: when the bits corresponding to the kth bit of the s second Polar codes in the first Polar code are frozen bits, select the kth bit to be equal to the specific value.
  • the decoder 421 is further configured to calculate a path metric value for each split path.
  • the segmentation unit 41 is specifically configured to sequentially divide the received signal vector of the first Polar code into s-segment received signal vectors, each segment of the received signal vector as one of the second The received signal vector of the Polar code determines s second Polar codes.
  • FIG. 5 is a schematic block diagram of an apparatus in accordance with another embodiment of the present invention.
  • the apparatus 50 of FIG. 5 can be used to implement various steps and methods in the above method embodiments.
  • the device 50 can be applied to a base station or terminal in various communication systems.
  • apparatus 50 includes a transmit circuit 502, a receive circuit 503, a decode processor 504, a processing unit 505, a memory 506, and an antenna 501.
  • Processing unit 505 controls the operation of device 50 and is operable to process signals.
  • Processing unit 505 may also be referred to as a CPU (Central Processing Unit).
  • Memory 506 can include read only memory and random The memory is accessed and instructions and data are provided to processing unit 505.
  • a portion of memory 506 may also include non-volatile line random access memory (NVRAM).
  • device 50 may be embedded or may itself be a wireless communication device such as a mobile telephone, and may also include a carrier that houses transmit circuitry 502 and receive circuitry 503 to allow for data transmission between device 50 and a remote location. receive. Transmit circuit 502 and receive circuit 503 can be coupled to antenna 501.
  • the various components of device 50 are coupled together by a bus system 509, which in addition to the data bus includes a power bus, a control bus, and a status signal bus. However, for clarity of description, various buses are labeled as bus system 509 in the figure.
  • Decoding processor 504 may be an integrated circuit chip with signal processing capabilities. In an implementation process, the steps of the above method may be completed by an integrated logic circuit of the hardware in the decoding processor 504 or an instruction in the form of software. These instructions can be implemented and controlled by processing unit 505.
  • the above decoding processor may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable Logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA off-the-shelf programmable gate array
  • the general purpose processor may be a microprocessor or the processor or any conventional processor, decoder or the like.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented as a hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software modules can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory 506, and the decoding processor 504 reads the information in the memory 506, combining Its hardware completes the steps of the above method.
  • memory 506 can store instructions that cause decoding processor 504 or processing unit 505 to perform the following processes:
  • the first Polar code of length N is divided into s second Polar codes, wherein each second Polar code has a length of N/s, N and s are integer powers of 2 and N>s;
  • the second Polar code performs path splitting of the list List decoding, and merges the split paths of the s second Polar codes after the path splitting, thereby obtaining multiple merge paths of length N; selecting multiple pieces of length N
  • the first merge path in the merge path where the first merge path is the path with the largest path metric value among the multiple merge paths of length N or the path of the CRC through the cyclic redundancy check in the multiple merge paths of length N; According to the first merge path, the decoding result of the first Polar code is obtained.
  • a Polar code of length N is divided into a multi-segment Polar code, and the segmented Polar code is independently split, and then the obtained split paths are combined, and finally the merge path with the largest path metric value is obtained.
  • the decoding result of the original Polar code is obtained, so that it is not necessary to sequentially decode N bits, which can improve the decoding throughput of the Polar code and reduce the decoding delay.
  • the memory 506 also stores instructions that cause the decoding processor 504 or the processing unit 505 to perform the following process: When k ⁇ N/s, if P Lma X , the length is k X s The P strip merge path is decomposed into s merge path groups, each merge path group contains P merge paths of length k as surviving paths, and s merge path groups are respectively used for the kth of s second Polar codes.
  • the memory 506 also stores instructions that cause the decoding processor 504 or the processing unit 505 to perform the following process: when the bits corresponding to the kth bit of the s second Polar codes in the first Polar code
  • the split path corresponding to the k-th bit of the frozen bit is not equal to a specific value, and the remaining split paths are merged to obtain a length of k X s
  • the memory 506 further stores instructions that cause the decoding processor 504 or the processing unit 505 to perform the following process: sequentially dividing the received signal vector of the first Polar code into s-segment received signal vectors, Each segment of the received signal vector serves as a received signal vector of a second Polar code to determine s second Polar codes.
  • the disclosed systems, devices, and methods may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not executed.
  • the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be electrical, mechanical or otherwise.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. You can choose some of them according to actual needs or All units are used to achieve the objectives of the solution of this embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium.
  • the technical solution of the present invention which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and the like, which can store program codes. .

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Abstract

La présente invention concerne des modes de réalisation comportant un procédé de décodage et un appareil de décodage pour un code polaire. Le procédé comprend les étapes consistant à : grouper un premier code polaire ayant une longueur de N en s seconds codes polaires, la longueur de chaque second code polaire étant N/s, N et s étant des puissances entières de 2, et N>s; effectuer une division de chemin de décodage de liste sur s seconds codes polaires simultanément, et combiner les chemins divisés de s seconds codes polaires après la division de chemin, de sorte à obtenir plusieurs chemins combinés ayant une longueur de N; choisir un premier chemin combiné parmi plusieurs chemins combinés ayant une longueur de N bits, le premier chemin combiné étant un chemin ayant la plus grande valeur métrique de chemin parmi les plusieurs chemins combinés ayant une longueur de N bits, ou un chemin réussissant le contrôle de redondance cyclique (CRC) parmi les plusieurs chemins combinés ayant une longueur de N bits; et obtenir un résultat de décodage du premier code polaire en fonction du premier chemin combiné. Dans ce cas, un rendement de décodage du code polaire peut être amélioré, et un retard de décodage peut être diminué.
PCT/CN2013/088492 2013-04-27 2013-12-04 Procédé de décodage et appareil de décodage pour code polaire WO2014173133A1 (fr)

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