WO2014153973A1 - Preparation process for anti-potential induced degradation solar cell - Google Patents
Preparation process for anti-potential induced degradation solar cell Download PDFInfo
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- WO2014153973A1 WO2014153973A1 PCT/CN2013/087918 CN2013087918W WO2014153973A1 WO 2014153973 A1 WO2014153973 A1 WO 2014153973A1 CN 2013087918 W CN2013087918 W CN 2013087918W WO 2014153973 A1 WO2014153973 A1 WO 2014153973A1
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- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 230000015556 catabolic process Effects 0.000 title abstract 4
- 238000006731 degradation reaction Methods 0.000 title abstract 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 238000009792 diffusion process Methods 0.000 claims abstract description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000002161 passivation Methods 0.000 claims abstract description 12
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 10
- 238000004140 cleaning Methods 0.000 claims abstract description 3
- 239000005360 phosphosilicate glass Substances 0.000 claims abstract 2
- 238000005245 sintering Methods 0.000 claims abstract 2
- 239000010410 layer Substances 0.000 claims description 43
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- 229910002804 graphite Inorganic materials 0.000 claims description 2
- 239000010439 graphite Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 229920001296 polysiloxane Polymers 0.000 claims 2
- 229910021529 ammonia Inorganic materials 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 7
- 238000000429 assembly Methods 0.000 abstract 2
- 230000000712 assembly Effects 0.000 abstract 2
- 238000010422 painting Methods 0.000 abstract 1
- 239000011521 glass Substances 0.000 description 7
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to the field of solar cells, and more particularly to a process for preparing a solar cell resistant to potential induced attenuation.
- BACKGROUND OF THE INVENTION Potential-induced attenuation was first discovered by Sunpower in 2005.
- the solar cell module has long been exposed to high voltage, causing leakage current between the glass and the encapsulation material.
- a large amount of electric charge is accumulated on the surface of the cell sheet, which deteriorates the passivation effect on the surface of the cell, resulting in an open circuit voltage, a short circuit current and a reduced fill factor, and the component is made. Performance is below design standards.
- SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to provide a solar cell manufacturing process capable of ensuring stable performance of a photovoltaic module in a high-voltage working environment.
- a process for preparing a solar cell resistant to potential induced attenuation comprising the steps of: (a) cleaning a silicon wafer, removing a damage layer, (b) placing the silicon wafer in a tube diffusion furnace for diffusion; (c) removing the diffused silicon wafer from the phosphorous silica glass and the back junction; (d) growing a layer of silicon dioxide on the surface of the emitter, A layer of silicon nitride is deposited, or a silicon nitride passivation antireflection layer is deposited directly on the surface of the emitter; (e) screen printed back electrode and front side electrode; (f) sintered and tested for sorting.
- the step (d) of growing silicon dioxide is thermal oxidation, plasma vapor deposition, chemical oxidation or UV oxidation.
- the step (d) grows silica to have a thickness of 5-40 nm.
- the specific process steps of the step (d) are as follows:
- silicon nitride film and ammonia gas filling silicon nitride film and ammonia gas to deposit silicon nitride film at a temperature of 375 ° C to 500 ° C, a flow ratio of silicon germanium to ammonia gas of 0.4 to 0.06, a thickness of 40 to 85 nm, and a refractive index of 2.0 ⁇ 2.2.
- the step (d) controls the total thickness of the silicon oxide film and the silicon nitride film in the silicon nitride layer grown on the surface of the silicon oxide to be 75-85 nm.
- the silicon nitride passivation antireflection layer deposited directly on the emitter surface in the step (d) may be a single layer film or a multilayer film or a gradient film; the single layer film has a refractive index greater than 2.1, the thickness is 40 ⁇ 75nm ; the refractive index of the first film of the double film is greater than 2.4, the thickness is 20 ⁇ 30nm, the refractive index of the second film is 2.1 ⁇ 2.4, the thickness is 50 ⁇ 60nm ; the third film is a refractive index of more than 2.5, a thickness of 10 to 20 nm, a refractive index of the second film of 2.2 to 2.5, a thickness of 20 to 30 nm, a refractive index of the third film of 2.0 to 2.2, a thickness of 30 to 40 nm ; a gradient The refractive index of the film is from 2.5 to 2.1 from the bottom to the top, and the thickness is from thin to thick.
- the present invention is advantageous in that: the preparation process of the solar cell with resistance to potential-induced attenuation can improve the resistance to potential-induced attenuation of the solar cell and its fabricated components, thereby ensuring that the component is high. Stable performance in voltage working environments. detailed description:
- the silicon wafer is cleaned, the damaged layer is removed, and the velvet is removed; the silicon wafer is placed in a tube diffusion furnace for diffusion, the diffusion resistance is 50 ⁇ / ⁇ , and the junction depth is 0.35 ⁇ ; the diffused silicon wafer is removed from the phosphorous silicon glass and Removing the back junction; depositing a silicon nitride passivation antireflection layer on the emitter surface; the antireflection layer is a single layer film, thickness 70nm, refraction The rate was 2.2; screen printed front and back electrodes; sintered and tested for sorting.
- the silicon wafer is cleaned, the layer is damaged, and the velvet is removed; the silicon wafer is placed in a tube diffusion furnace for diffusion, the diffusion resistance is 55 ⁇ / ⁇ , and the junction depth is 0.30 ⁇ ; the diffused silicon wafer is removed from the phosphorous silicon glass and Removing the back junction; depositing a silicon nitride passivation antireflection layer on the emitter surface; the antireflection layer is a two-layer film, the first film has a thickness of 20 nm, a refractive index of 2.5, and the thickness of the second film is 50 nm, and the refractive index 2.1; screen printed front and back electrodes; sintered and tested for sorting.
- the silicon wafer is cleaned, the damaged layer is removed, and the velvet is removed; the silicon wafer is placed in a tube diffusion furnace for diffusion, the diffusion resistance is 50 ⁇ / ⁇ , and the junction depth is 0.35 ⁇ ; the diffused silicon wafer is removed from the phosphorous silicon glass and Removing the back junction; depositing a silicon nitride passivation anti-reflection layer on the emitter surface; the anti-reflection layer is a three-layer film, the first film has a thickness of 10 nm, a refractive index of 2.5, and the thickness of the second film is 20 nm, and the refractive index 2.2; the third film has a thickness of 40 n and a refractive index of 2.1; screen printed front and back electrodes; sintered and tested for sorting.
- the silicon wafer is cleaned, the damaged layer is removed, and the velvet is removed; the silicon wafer is placed in a tube diffusion furnace for diffusion, the diffusion resistance is 60 ⁇ / ⁇ , and the junction depth is 0.35 ⁇ ; the diffused silicon wafer is removed from the phosphorous silicon glass and The back junction is removed; the silicon nitride passivation antireflection layer is deposited on the emitter surface; the antireflection layer is a three layer film, the first film has a thickness of 30 nm, the refractive index is 2.4, and the thickness of the second film is 30 nm. 2.2; the third film has a thickness of 10 n and a refractive index of 2.0; screen printed front and back electrodes; sintered and tested for sorting.
- the silicon wafer is cleaned, the damaged layer is removed, and the fleece is removed; the silicon wafer is placed in a tube diffusion furnace for diffusion, the diffusion resistance is 65 ⁇ / ⁇ , and the junction depth is 0.35 ⁇ ; the diffused silicon wafer is removed from the phosphorous silicon glass and Remove the back knot;
- the surface of the emitter is thermally grown with a layer of silicon dioxide having a thickness of 15 nm; a silicon nitride passivation antireflection layer is deposited on the silicon dioxide film; the antireflection layer is a gradient film, and the refractive index is decreased from bottom to top from 2.5. To 2.0, the total thickness is 60 nm; the front electrode and the back electrode are printed from the screen; sintered and tested for sorting.
- the silicon wafer is cleaned, the damaged layer is removed, and the velvet is removed; the silicon wafer is placed in a tube diffusion furnace for diffusion, the diffusion resistance is 85 ⁇ / port, and the junction depth is 0.35 ⁇ ⁇ ; the diffused silicon wafer is removed. Phosphorus glass and removing the back junction; depositing a layer of silicon dioxide on the surface of the emitter with a thickness of 15 nm; depositing a silicon nitride passivation antireflection layer on the silicon dioxide film; the antireflection layer is a single layer film, refractive index 2 10, total thickness of 60 nm ; screen printed front and back electrodes; sintered and tested for sorting.
- the preparation process of the solar cell with anti-potential induced attenuation can improve the resistance to potential-induced attenuation of the solar cell and its fabricated components, thereby ensuring the stability of the component in a high-voltage working environment.
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- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
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- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
A preparation process for an anti-potential induced degradation solar cell, comprising the following steps: (a) cleaning a silicon chip, removing a damaged layer and making texture; (b) placing the silicon chip into a pipe diffusion furnace to diffuse; (c) removing phosphosilicate glass and a back junction from the diffused silicon chip; (d) growing a layer of silicon dioxide on the surface of an emitter, and then depositing a layer of silicon nitride or directly depositing a silicon nitride passivation antireflection layer on the surface of the emitter; (e) screen painting a back electrode and a front electrode; and (f) sintering, testing and selecting. The preparation process for an anti-potential induced degradation solar cell can improve the anti-potential induced degradation capability of a solar cell and prepared assemblies thereof, thereby ensuring that the performance of the assemblies is stable in a high-voltage working environment.
Description
说 明 书 一种抗电势诱导衰减的太阳能电池的制备工艺 技术领域： 本发明涉及太阳能电池领域， 尤其涉及一种抗电势诱导衰减的太阳能电池 的制备工艺。 背景技术： 电势诱导衰减最早是 Sunpower在 2005年发现的。 太阳能电池组件长期在 高电压作用下使得玻璃， 封装材料之间存在漏电流， 大量电荷聚集在电池片表 面， 使得电池表面的钝化效果恶化， 导致开路电压， 短路电流和填充因子降低， 使组件性能低于设计标准。 发明内容： 本发明所要解决的技术问题是， 提供一种能够保证光伏组件在高压工作环 境中性能稳定的一种抗电势诱导衰减的太阳能电池的制备工艺。 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of solar cells, and more particularly to a process for preparing a solar cell resistant to potential induced attenuation. BACKGROUND OF THE INVENTION Potential-induced attenuation was first discovered by Sunpower in 2005. The solar cell module has long been exposed to high voltage, causing leakage current between the glass and the encapsulation material. A large amount of electric charge is accumulated on the surface of the cell sheet, which deteriorates the passivation effect on the surface of the cell, resulting in an open circuit voltage, a short circuit current and a reduced fill factor, and the component is made. Performance is below design standards. SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to provide a solar cell manufacturing process capable of ensuring stable performance of a photovoltaic module in a high-voltage working environment.
为了解决上述技术问题， 本发明是通过以下技术方案实现的： 一种抗电势 诱导衰减的太阳能电池的制备工艺， 其特征是， 包括如下步骤： （a) 将硅片清 洗， 去损伤层， 制绒； （b ) 将硅片放入管式扩散炉中， 进行扩散； （c ) 将扩散 后的硅片去除磷硅玻璃和背结； （d ) 在发射极表面生长一层二氧化硅， 再沉积 一层氮化硅， 或者直接在发射极表面沉积氮化硅钝化减反射层； （e ) 丝网印刷 背电极和正面电极； （f ) 烧结并测试分选。 In order to solve the above technical problem, the present invention is achieved by the following technical solutions: A process for preparing a solar cell resistant to potential induced attenuation, comprising the steps of: (a) cleaning a silicon wafer, removing a damage layer, (b) placing the silicon wafer in a tube diffusion furnace for diffusion; (c) removing the diffused silicon wafer from the phosphorous silica glass and the back junction; (d) growing a layer of silicon dioxide on the surface of the emitter, A layer of silicon nitride is deposited, or a silicon nitride passivation antireflection layer is deposited directly on the surface of the emitter; (e) screen printed back electrode and front side electrode; (f) sintered and tested for sorting.
优选的， 所述步骤 （b ) 中扩散后的方阻值为 50〜80 Ω /口， 结深为 0. 25〜 5〜之间。 The step (b), the square resistance of the diffusion is 50~80 Ω / port, the depth of the knot is 0. 25~
0. 35 μ πι。 0. 35 μ πι.
优选的， 所述步骤 （d) 生长二氧化硅的方法为热氧化、 等离子体气相沉积 法、 化学氧化法或 UV氧化法。 Preferably, the step (d) of growing silicon dioxide is thermal oxidation, plasma vapor deposition, chemical oxidation or UV oxidation.
优选的， 所述步骤 （d) 生长二氧化硅的厚度为 5_40nm。
优选的， 所述步骤 （d) 的具体工艺步骤如下： Preferably, the step (d) grows silica to have a thickness of 5-40 nm. Preferably, the specific process steps of the step (d) are as follows:
(1) 将扩散后的硅片放入石墨舟上； (1) placing the diffused silicon wafer on the graphite boat;
(2) 充入氨气进行表面轰击； (2) Filling with ammonia gas for surface bombardment;
(3)充入硅垸和氨气进行氮化硅薄膜的沉积， 温度为 375°C〜500°C， 硅垸 和氨气的流量比为 0.4〜0.06， 厚度为 40〜85nm， 折射率为 2.0〜2.2。 (3) filling silicon nitride film and ammonia gas to deposit silicon nitride film at a temperature of 375 ° C to 500 ° C, a flow ratio of silicon germanium to ammonia gas of 0.4 to 0.06, a thickness of 40 to 85 nm, and a refractive index of 2.0~2.2.
优选的， 所述步骤 （d) 在氧化硅表面生长的氮化硅层中氧化硅膜和氮化硅 膜总厚度控制在 75_85nm。 Preferably, the step (d) controls the total thickness of the silicon oxide film and the silicon nitride film in the silicon nitride layer grown on the surface of the silicon oxide to be 75-85 nm.
优选的， 所述步骤 （d) 中在发射极表面直接沉积的氮化硅钝化减反射层可 以是单层膜也可以是多层膜或者是梯度膜； 所述单层膜的折射率大于 2.1， 厚度 为 40〜75nm; 双层膜第一层膜的折射率大于 2.4， 厚度为 20〜30nm， 第二层膜 的折射率为 2.1〜2.4， 厚度为 50〜60nm; 三层膜的第一层折射率大于 2.5， 厚 度为 10〜20nm， 第二层膜的折射率为 2.2〜2.5， 厚度为 20〜30nm， 第三层膜的 折射率为 2.0〜2.2， 厚度为 30〜40nm; 梯度膜的折射率由下往上为 2.5〜2.1， 厚度由薄到厚。 Preferably, the silicon nitride passivation antireflection layer deposited directly on the emitter surface in the step (d) may be a single layer film or a multilayer film or a gradient film; the single layer film has a refractive index greater than 2.1, the thickness is 40~75nm ; the refractive index of the first film of the double film is greater than 2.4, the thickness is 20~30nm, the refractive index of the second film is 2.1~2.4, the thickness is 50~60nm ; the third film is a refractive index of more than 2.5, a thickness of 10 to 20 nm, a refractive index of the second film of 2.2 to 2.5, a thickness of 20 to 30 nm, a refractive index of the third film of 2.0 to 2.2, a thickness of 30 to 40 nm ; a gradient The refractive index of the film is from 2.5 to 2.1 from the bottom to the top, and the thickness is from thin to thick.
与现有技术相比， 本发明的有益之处在于： 这种抗电势诱导衰减的太阳能 电池的制备工艺可以提高太阳能电池及其制成的组件的抗电势诱导衰减的能 力， 从而保证组件在高电压工作环境中性能的稳定。 具体实施方式： Compared with the prior art, the present invention is advantageous in that: the preparation process of the solar cell with resistance to potential-induced attenuation can improve the resistance to potential-induced attenuation of the solar cell and its fabricated components, thereby ensuring that the component is high. Stable performance in voltage working environments. detailed description:
下面通过具体实施方式对本发明进行详细描述。 The invention is described in detail below by means of specific embodiments.
实例一： Example 1:
将硅片清洗， 去损伤层， 制绒； 将硅片放入管式扩散炉中进行扩散， 扩散后 方阻为 50Ω/口， 结深为 0.35μπι; 将扩散后的硅片去除磷硅玻璃并去除背结； 发射极表面沉积氮化硅钝化减反射层； 减反射层为单层膜， 厚度为 70nm， 折射
率为 2.2; 丝网印刷正面电极和背电极； 烧结并测试分选。 The silicon wafer is cleaned, the damaged layer is removed, and the velvet is removed; the silicon wafer is placed in a tube diffusion furnace for diffusion, the diffusion resistance is 50 Ω/□, and the junction depth is 0.35 μπι ; the diffused silicon wafer is removed from the phosphorous silicon glass and Removing the back junction; depositing a silicon nitride passivation antireflection layer on the emitter surface; the antireflection layer is a single layer film, thickness 70nm, refraction The rate was 2.2; screen printed front and back electrodes; sintered and tested for sorting.
实例二： Example 2:
将硅片清洗， 去损伤层， 制绒； 将硅片放入管式扩散炉中进行扩散， 扩散后 方阻为 55Ω/口， 结深为 0.30μπι; 将扩散后的硅片去除磷硅玻璃并去除背结； 发射极表面沉积氮化硅钝化减反射层； 减反射层为双层膜， 第一层膜的厚度为 20nm， 折射率为 2.5， 第二层膜的厚度为 50nm， 折射率为 2.1; 丝网印刷正面电 极和背电极； 烧结并测试分选。 The silicon wafer is cleaned, the layer is damaged, and the velvet is removed; the silicon wafer is placed in a tube diffusion furnace for diffusion, the diffusion resistance is 55 Ω/□, and the junction depth is 0.30 μπι ; the diffused silicon wafer is removed from the phosphorous silicon glass and Removing the back junction; depositing a silicon nitride passivation antireflection layer on the emitter surface; the antireflection layer is a two-layer film, the first film has a thickness of 20 nm, a refractive index of 2.5, and the thickness of the second film is 50 nm, and the refractive index 2.1; screen printed front and back electrodes; sintered and tested for sorting.
实例三： Example three:
将硅片清洗， 去损伤层， 制绒； 将硅片放入管式扩散炉中进行扩散， 扩散后 方阻为 50Ω/口， 结深为 0.35μπι; 将扩散后的硅片去除磷硅玻璃并去除背结； 发射极表面沉积氮化硅钝化减反射层； 减反射层为三层膜， 第一层膜的厚度为 10nm, 折射率为 2.5， 第二层膜的厚度为 20nm， 折射率为 2.2; 第三层膜的厚度 为 40n， 折射率为 2.1; 丝网印刷正面电极和背电极； 烧结并测试分选。 The silicon wafer is cleaned, the damaged layer is removed, and the velvet is removed; the silicon wafer is placed in a tube diffusion furnace for diffusion, the diffusion resistance is 50 Ω/□, and the junction depth is 0.35 μπι ; the diffused silicon wafer is removed from the phosphorous silicon glass and Removing the back junction; depositing a silicon nitride passivation anti-reflection layer on the emitter surface; the anti-reflection layer is a three-layer film, the first film has a thickness of 10 nm, a refractive index of 2.5, and the thickness of the second film is 20 nm, and the refractive index 2.2; the third film has a thickness of 40 n and a refractive index of 2.1; screen printed front and back electrodes; sintered and tested for sorting.
实例四： Example four:
将硅片清洗， 去损伤层， 制绒； 将硅片放入管式扩散炉中进行扩散， 扩散后 方阻为 60Ω/口， 结深为 0.35μπι; 将扩散后的硅片去除磷硅玻璃并去除背结； 发射极表面沉积氮化硅钝化减反射层； 减反射层为三层膜， 第一层膜的厚度为 30nm, 折射率为 2.4， 第二层膜的厚度为 30nm， 折射率为 2.2; 第三层膜的厚度 为 10n， 折射率为 2.0; 丝网印刷正面电极和背电极； 烧结并测试分选。 The silicon wafer is cleaned, the damaged layer is removed, and the velvet is removed; the silicon wafer is placed in a tube diffusion furnace for diffusion, the diffusion resistance is 60 Ω/□, and the junction depth is 0.35 μπι ; the diffused silicon wafer is removed from the phosphorous silicon glass and The back junction is removed; the silicon nitride passivation antireflection layer is deposited on the emitter surface; the antireflection layer is a three layer film, the first film has a thickness of 30 nm, the refractive index is 2.4, and the thickness of the second film is 30 nm. 2.2; the third film has a thickness of 10 n and a refractive index of 2.0; screen printed front and back electrodes; sintered and tested for sorting.
实例五： Example 5:
将硅片清洗， 去损伤层， 制绒； 将硅片放入管式扩散炉中进行扩散， 扩散 后方阻为 65Ω/口，结深为 0.35μπι;将扩散后的硅片去除磷硅玻璃并去除背结；
发射极表面热生长一层二氧化硅层， 厚度为 15nm; 在二氧化硅薄膜上沉积氮化 硅钝化减反射层； 减反射层为梯度膜， 折射率从下往上从 2. 5递减至 2. 0， 总厚 度为 60nm; 从丝网印刷正面电极和背电极； 烧结并测试分选。 The silicon wafer is cleaned, the damaged layer is removed, and the fleece is removed; the silicon wafer is placed in a tube diffusion furnace for diffusion, the diffusion resistance is 65 Ω/□, and the junction depth is 0.35 μπι ; the diffused silicon wafer is removed from the phosphorous silicon glass and Remove the back knot; The surface of the emitter is thermally grown with a layer of silicon dioxide having a thickness of 15 nm; a silicon nitride passivation antireflection layer is deposited on the silicon dioxide film; the antireflection layer is a gradient film, and the refractive index is decreased from bottom to top from 2.5. To 2.0, the total thickness is 60 nm; the front electrode and the back electrode are printed from the screen; sintered and tested for sorting.
实例六： Example six:
将硅片清洗， 去损伤层， 制绒； 将硅片放入管式扩散炉中进行扩散， 扩散 后方阻为 85 Ω /口，结深为 0. 35 μ πι;将扩散后的硅片去除磷硅玻璃并去除背结； 发射极表面沉积一层二氧化硅层， 厚度为 15nm; 在二氧化硅薄膜上沉积氮化硅 钝化减反射层； 减反射层为单层膜， 折射率 2. 10， 总厚度为 60nm; 从丝网印刷 正面电极和背电极； 烧结并测试分选。 The silicon wafer is cleaned, the damaged layer is removed, and the velvet is removed; the silicon wafer is placed in a tube diffusion furnace for diffusion, the diffusion resistance is 85 Ω / port, and the junction depth is 0.35 μ πι ; the diffused silicon wafer is removed. Phosphorus glass and removing the back junction; depositing a layer of silicon dioxide on the surface of the emitter with a thickness of 15 nm; depositing a silicon nitride passivation antireflection layer on the silicon dioxide film; the antireflection layer is a single layer film, refractive index 2 10, total thickness of 60 nm ; screen printed front and back electrodes; sintered and tested for sorting.
抗电势诱导衰减的太阳能电池的制备工艺可以提高太阳能电池及其制成的 组件的抗电势诱导衰减的能力， 从而保证组件在高电压工作环境中性能的稳定。 The preparation process of the solar cell with anti-potential induced attenuation can improve the resistance to potential-induced attenuation of the solar cell and its fabricated components, thereby ensuring the stability of the component in a high-voltage working environment.
需要强调的是： 以上仅是本发明的较佳实施例而已， 并非对本发明作任何 形式上的限制， 凡是依据本发明的技术实质对以上实施例所作的任何简单修改、 等同变化与修饰， 均仍属于本发明技术方案的范围内。
It is to be understood that the above is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Any simple modification, equivalent change and modification to the above embodiments in accordance with the technical spirit of the present invention are Still falling within the scope of the technical solution of the present invention.
Claims
(1) 将扩散后的硅片放入石墨舟上； (1) Place the diffused silicon wafer on the graphite boat;
(2) 充入氨气进行表面轰击； (2) Fill ammonia gas for surface bombardment;
(3)充入硅垸和氨气进行氮化硅薄膜的沉积， 温度为 375°C〜500°C， 硅垸 和氨气的流量比为 0.4〜0.06，厚度为 40〜85nm，折射率为 2.0〜2.2。 、 根据权利要求 1所述的抗电势诱导衰减的太阳能电池的制备工艺， 其特征
是， 所述步骤 （d ) 在氧化硅表面生长的氮化硅层中氧化硅膜和氮化硅膜 总厚度控制在 75_85nm。 (3) Fill silicone and ammonia gas to deposit silicon nitride film, the temperature is 375°C~500°C, the flow ratio of silicone and ammonia is 0.4~0.06, the thickness is 40~85nm, and the refractive index is 2.0~2.2. . The preparation process of solar cells resistant to potential induced decay according to claim 1, characterized by Yes, the total thickness of the silicon oxide film and the silicon nitride film in the silicon nitride layer grown on the silicon oxide surface in step (d) is controlled to 75-85nm.
根据权利要求 1所述的抗电势诱导衰减的太阳能电池的制备工艺， 其特征 是， 所述步骤 （d ) 中在发射极表面直接沉积的氮化硅钝化减反射层可以 是单层膜也可以是多层膜或者是梯度膜； 所述单层膜的折射率大于 2. 1， 厚度为 40〜75nm; 双层膜第一层膜的折射率大于 2. 4， 厚度为 20〜30nm， 第二层膜的折射率为 2. 1〜2. 4， 厚度为 50〜60nm; 三层膜的第一层折射 率大于 2. 5， 厚度为 10〜20nm， 第二层膜的折射率为 2. 2〜2. 5， 厚度为 20〜30nm， 第三层膜的折射率为 2. 0〜2. 2， 厚度为 30〜40nm; 梯度膜的 折射率由下往上为 2. 5〜2. 1， 厚度由薄到厚。
The preparation process of solar cells resistant to potential induced decay according to claim 1, wherein the silicon nitride passivation anti-reflection layer directly deposited on the emitter surface in step (d) can be a single layer film or It can be a multi-layer film or a gradient film; the refractive index of the single-layer film is greater than 2.1, and the thickness is 40~75nm ; the refractive index of the first layer of the double-layer film is greater than 2.4, and the thickness is 20~30nm. The refractive index of the second layer of film is 2.1~2.4, and the thickness is 50~60nm ; the refractive index of the first layer of the three-layer film is greater than 2.5, the thickness is 10~20nm, and the refractive index of the second layer of film is 2.2~2.5, the thickness is 20~30nm, the refractive index of the third layer of film is 2.0~2.2, the thickness is 30~40nm ; the refractive index of the gradient film from bottom to top is 2.5~ 2. 1. Thickness from thin to thick.
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| CN103606599A (en) * | 2013-11-30 | 2014-02-26 | 浙江光隆能源科技股份有限公司 | Method for manufacturing high-refractive-index silicon nitride antireflection film |
| CN103943722B (en) * | 2014-04-03 | 2016-09-14 | 苏州阿特斯阳光电力科技有限公司 | A kind of anti-PID method for manufacturing solar battery |
| CN104241403A (en) * | 2014-09-01 | 2014-12-24 | 奥特斯维能源（太仓）有限公司 | Multilayer passivation anti-reflective coating of crystalline silicon cell and manufacturing method thereof |
| CN104900761A (en) * | 2015-05-29 | 2015-09-09 | 安徽旭能光伏电力有限公司 | Crystalline silicon solar cell production process |
| CN105140306B (en) * | 2015-07-27 | 2017-03-29 | 尚德太阳能电力有限公司 | The solar battery structure and production method of anti-PID effects |
| CN105355723B (en) * | 2015-12-14 | 2019-12-27 | 内蒙古日月太阳能科技有限责任公司 | Preparation method of silicon dioxide passivation film of crystalline silicon solar cell |
| CN105483832B (en) * | 2015-12-29 | 2018-01-19 | 辛煜 | The crystal silicon surface oxygenation device and its method of a kind of resisting potential induced degradation effect |
| CN106253850B (en) * | 2016-08-29 | 2018-09-14 | 奥特斯维能源（太仓）有限公司 | A kind of test method of the anti-PID performances of antireflective coating |
| CN111697084A (en) * | 2020-07-02 | 2020-09-22 | 常州斯威克光伏新材料有限公司 | Battery resistant to potential induced polarization attenuation and preparation process |
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