WO2014153836A1

WO2014153836A1 - Gate drive circuit, display panel, and display device

Info

Publication number: WO2014153836A1
Application number: PCT/CN2013/076601
Authority: WO
Inventors: 许益祯; 孙志华; 吴行吉; 汪建明; 张亮
Original assignee: 京东方科技集团股份有限公司; 北京京东方显示技术有限公司
Priority date: 2013-03-27
Filing date: 2013-05-31
Publication date: 2014-10-02
Also published as: CN103177703B; CN103177703A

Abstract

A gate drive circuit is applied to a display panel, and comprises: a signal generation circuit, for generating grid line drive signals for driving grid lines in the display panel, at least one grid line drive signal being a signal having a chamfering waveform. Also disclosed are a display panel and a display device. The gate drive circuit can alleviate signal distortion caused by an RC delay.

Description

Gate drive circuit, display panel and display device

The present invention relates to driving of a display panel, and more particularly to a gate driving circuit, a display panel, and a display device. Background technique

The liquid crystal display device is a flat display which is widely used at present, and has advantages of low power consumption, light weight, no radiation, and the like compared with other display modes.

The liquid crystal display device generally includes an array substrate, a color filter substrate, and a liquid crystal layer filled between the array substrate and the color filter substrate. The display area on the array substrate includes a plurality of sub-pixel areas, and each of the sub-pixel areas is generally formed by two gate lines (scanning lines) and two data lines.

A thin film transistor and a pixel electrode functioning as a switching device are disposed inside the sub-pixel region. The electric field intensity applied between the color filter substrate and the array substrate is controlled by controlling the voltage applied to the common electrode and/or the pixel electrode on the color filter substrate, thereby controlling the deflection direction of the liquid crystal molecules.

As the size of the display panel increases and the resolution increases. The RC delay on the gate and data lines (where the resistance R refers to the resistance of the gate and data lines, and the capacitance C includes the capacitance between the gate and data lines and the pixel electrode) also increases. This RC delay affects signal transmission.

As shown in FIG. 1, it is assumed that the left side is near the end of the gate driving circuit, and Von is the voltage corresponding to the TFT conduction. As can be seen from FIG. 1, the gate driving signal is substantially not distorted near the end of the gate driving circuit. To the end away from the gate drive circuit, the distortion of the gate drive signal is very serious, and this distortion causes the on-time of the TFTs in the same row to be different, which in turn causes the pixel electrode charging time to be inconsistent, which adversely affects the display. .

In the prior art, the adverse effects of RC delay are generally attenuated by improving the material, shape, size, etc. of the gate line. For example, a material having a low resistivity is used, and the width and thickness of the gate line are increased to reduce the resistance and reduce the resistance. The overlapping area of the gate lines and other conductive layers, etc., but these methods will undoubtedly affect the manufacturing process of the display panel, increasing the complexity and cost of the process. Summary of the invention

Embodiments of the present invention provide a gate driving circuit and a display device, from the perspective of a signal source Attenuate the adverse effects of RC delay.

Specifically, an embodiment of the present invention provides a gate driving circuit for a display panel, including: a signal generating circuit, configured to generate a gate line driving signal for driving a gate line located in the display panel;

At least one of the drive signals is a signal having a chamfered waveform.

In the above gate driving circuit, the display panel is provided with a data line driven by the data driving circuit, and the signal generating circuit includes:

a first signal generating sub-circuit for generating a first driving signal for driving a gate line located in a first region of the display panel;

a second signal generating sub-circuit for generating a second driving signal for driving a gate line located in a second region of the display panel;

a distance from the first region to the data driving circuit is greater than a distance from the second region to the data driving circuit;

The number of chamfering waveforms of the first driving signal is m, and the number of chamfering waveforms of the second driving signal is n, where m and n are natural numbers, and m > n.

In the gate driving circuit described above, the display panel is provided with a data line driven by the data driving circuit, and the display panel is divided into M display sub-regions in the extending direction of the data line, and M is greater than or equal to 2 The integer generation, the signal generation circuit includes:

M signal generation sub-circuits corresponding to M display sub-regions;

The driving signals generated by each of the signal generating sub-circuits are signals having a chamfered waveform, wherein in any two of the signal generating sub-circuits, a signal generating sub-circuit corresponding to a display sub-area far from the data driving circuit is generated The number of chamfering waveforms of the driving signal is not less than the number of chamfering waveforms of the driving signal generated by the other signal generating sub-circuit.

In the gate driving circuit described above, the chamfering waveform is located at a falling edge of the driving signal. In the gate driving circuit described above, the chamfering waveform is recessed toward the rising edge direction.

In the above gate driving circuit, the driving signal is maintained at the first voltage for a time greater than or equal to a predetermined gate line opening time, and the first voltage is a voltage capable of maintaining conduction of the thin film field effect transistor in the display panel. .

The embodiment of the invention further provides a display panel, wherein the display panel is provided with a plurality of gate lines, and the display panel is provided with the above-mentioned gate driving circuit for driving the gate lines. The embodiment of the invention further provides a display device comprising the above display panel. In the embodiment of the present invention, an improvement is made at one end of the gate driving circuit, so that the gate line driving signal generated by the gate driving circuit is no longer a square wave signal, but a signal with a chamfered waveform, which can reduce The signal distortion caused by RC delay can therefore reduce the adverse effects of RC delay.

In the embodiment of the present invention, a signal that is relatively insensitive to the RC delay effect is provided by the signal source to reduce the adverse effect caused by the RC delay, and has no influence on the manufacturing process of the panel, and does not increase the complexity of the process. It will not increase the cost of process modification. DRAWINGS

Figure 1 is a schematic diagram showing signal delay on a gate line;

2a-2h are schematic diagrams of signals with chamfered waveforms in accordance with an embodiment of the present invention;

3 is a schematic view showing a partition of a display panel in an embodiment of the present invention;

Figure 4 is a schematic view showing another partition of the display panel in the embodiment of the present invention;

Figure 5 is a schematic diagram showing signals outputted by different regions of the display panel of the embodiment of the present invention with different chamfering waveforms;

Fig. 6 is a view showing the parameters of a signal having a chamfered waveform in the embodiment of the present invention. detailed description

In the embodiment of the present invention, an improvement is made at one end of the gate driving circuit, so that the gate line driving signal generated by the gate driving circuit is no longer a square wave signal, but a signal with a chamfered waveform, and the signal can be reduced due to RC. The signal distortion caused by the delay can therefore reduce the adverse effects of RC delay.

Before explaining the embodiments of the present invention, the aspects of the embodiments of the present invention are described in detail in order to better understand the embodiments of the present invention.

In general, in a conventional gate driving device, a square wave signal as shown on the left side of Fig. 1 is outputted to the gate line.

The so-called signal with a chamfered waveform refers to:

On the rising edge of the drive signal, the voltage does not jump directly from VGL to VGH, but starts from VGL and goes up to VGH after a certain period of time; and / or

On the falling edge of the drive signal, the voltage does not jump directly from VGH to VGL, but from VGH At the beginning, it took a certain amount of time to fall to VGL.

In a particular embodiment of the invention, the length of time that elapses from VGH to VGL and the length of time that elapses from VGL to VGH can be set as desired.

2a-2h are several examples of signals with chamfered waveforms in an embodiment of the invention, but it should be understood that Figures 2a-2h do not cover all signals with chamfered waveforms, just an example .

In the figure, VGH is a high-order voltage corresponding to the on state of the TFT device, and VGL is a low-order voltage corresponding to the on state of the TFT device.

It can be seen from the figure that in a specific embodiment of the invention, the signal with the chamfered waveform can have a chamfered waveform, as shown in Figures 2a-2d, and can also have multiple chamfering waveforms, as shown in Figure 2e. -2f, where the signal shown in Figure 2e has two chamfered waveforms, while the signal shown in Figure 2f has three chamfered waveforms.

The signals for generating the chamfered waveforms shown in Figures 2a-2h can be implemented in various ways, such as generating multiple signals, outputting different signals at different stages, and combining different signals output at different stages to obtain Figure 2a- The signal of the chamfered waveform shown in 2h will not be described in detail here.

The embodiment of the invention provides a gate driving circuit for a display panel, and the gate driving circuit includes:

a signal generating circuit, configured to generate a gate line driving signal for driving a gate line located in the display panel;

At least one of the drive signals is a signal having a chamfered waveform.

Because the TFT LCD is close to the gate driving circuit, the signal distortion of the gate driving signal is small, and in the region away from the gate driving circuit, the signal distortion of the gate driving signal is large, that is, the same gate The waveform of the gate drive signal on the line is in a decreasing state. In the embodiment of the present invention, the gate driving signal outputted by the gate driving circuit has a chamfering waveform, so that the waveform of the driving signal is reduced at different positions on the same gate line, that is, can make The degree of distortion of the waveform on the same gate line is reduced, so that the difference in the on-time of the TFT on the same gate line is reduced, and the display quality is improved.

Meanwhile, in the embodiment of the present invention, the signal is relatively insensitive to the RC delay effect by the signal source, thereby reducing the adverse effect caused by the RC delay, so that it is not necessary to change the material, shape, and size of the gate line, that is, , has no effect on the manufacturing process of the panel, will not increase the work The complexity of the art will not increase the cost of the process.

In a specific embodiment of the present invention, the signal generating circuit can be implemented in various ways, which are respectively described below.

A drive signal having a chamfered waveform is output only to a part of the gate lines.

As shown in FIG. 3, according to the distribution of the data driving chip and the gate driving chip, the display panel is divided into four regions, wherein the region C is delayed by the RC delay effect due to the long transmission path of the data signal and the scanning signal. The impact is greatest, while regions B and D are second, and region A is least affected by the RC delay effect.

Considering the tolerance of the system, only the out-of-range RC delay effect effect may make the display quality intolerable. In this way, the embodiment of the present invention can output the driving signal with the chamfered waveform only to part of the gate line. .

Taking the case shown in FIG. 3 as an example, the driving signal having the chamfered waveform can be output only to the gate line located in the region D, that is, only the gate driving chip A needs to output the driving signal having the chamfered waveform, and the gate The pole drive chip B can output a square wave signal in accordance with the conventional method.

A drive signal having a chamfered waveform is output to all of the gate lines.

In the first method, the drive signal having the chamfered waveform is output only to the gate line in the region which is affected by the delay effect beyond a certain range.

However, it should be understood that no matter which area is in, it will be affected by the delay effect, the difference is only the size of the affected.

Therefore, in the second mode, the drive signal having the chamfered waveform can be output to all the gate lines without distinguishing the regions.

However, in the second mode, the driving signals having the chamfered waveforms outputted to each of the gate lines may have the same waveform, but may have different waveforms.

A drive signal having a chamfered waveform is output to all of the gate lines, and the number of chamfering waveforms of the drive signals in different areas is different.

As shown in FIG. 4, in the transmission direction of the data line, the display panel is divided into four regions, which are regions E, F, 0, and 11, respectively. According to the theoretical knowledge of delayed transmission, it can be known that the region H is delayed. The impact should be the largest, the region G is second, and the region F is again, the region E is least affected by the delay effect.

Therefore, in a specific embodiment of the present invention, when the same driving signal having a chamfered waveform is uniformly output to all regions, the driving signal may significantly reduce signal distortion due to RC delay only in a partial region. Role, but may not be obvious in other areas.

Based on the above considerations, in a specific embodiment of the present invention, when the gate driving circuit includes a plurality of sub-circuits, each of the sub-circuits has a corresponding display area, the sub-circuit generates and outputs a region corresponding to the region according to the corresponding region. Different drive signals with chamfered waveforms.

The display panel is provided with a data line driven by the data driving circuit. The display panel is divided into M display sub-areas in the extending direction of the data line, and M is an integer greater than or equal to 2. The signal generating circuit includes:

M signal generation sub-circuits corresponding to M display sub-regions;

The driving signals generated by each of the signal generating sub-circuits are signals having at least one chamfering waveform, wherein in any two of the signal generating sub-circuits, signal generation corresponding to the display sub-area far from the data driving circuit The number of chamfering waveforms of the driving signals generated by the sub-circuits is not less than the number of chamfering waveforms of the driving signals generated by the other signal generating sub-circuits.

For example, when the display panel is divided into two regions, the signal generating circuit includes:

The number of chamfering waveforms of the first driving signal is m, and the number of chamfering waveforms of the second driving signal is n, where m and n are natural numbers, and m is greater than or equal to n.

The case shown in Fig. 4 is illustrated as follows.

As shown in FIG. 4, the same drive signal XI having a chamfered waveform can be output to the regions E and F, and the same drive signal X2 having a chamfered waveform can be output to the regions G and H, wherein the number of chamfered waveforms of X2 The number of chamfered waveforms greater than XI;

The resulting signal is shown in Figure 5, where the arrows indicate the correspondence between the region and the gate drive signal input to the region. Of course, it is also possible to output the drive signal Y1 having the chamfered waveform to the region E, the drive signal Y2 having the chamfered waveform to the region F, the drive signal Y3 having the chamfered waveform to the region G, and the chamfered waveform to the region H. Drive signal Y4. The number of chamfering waveforms of Υ4 is greater than the number of chamfering waveforms of Υ3, the number of chamfering waveforms of Υ3 is greater than the number of chamfering waveforms of Υ2, and the number of chamfering waveforms of Υ2 is greater than the number of chamfering waveforms of Y1.

Of course, it can be other ways, not here - enumeration.

In a specific embodiment of the present invention, a chamfering waveform can be set on the rising edge of the signal to reduce signal distortion caused by the RC delay effect, but a more preferable method is to reduce the chamfering waveform on the falling edge of the driving signal to reduce The signal distortion caused by the RC delay effect is the case shown in Figures 2a and 2d-2g.

Meanwhile, in a specific embodiment of the present invention, when the chamfering waveform is set at the falling edge of the signal, the chamfering waveform is preferably recessed toward the rising edge direction as shown in Figs. 2d - 2g.

In a specific embodiment of the present invention, in order to ensure that the TFT has sufficient time to conduct, the driving signal is maintained at the first voltage for a time greater than or equal to a predetermined gate line opening time, and the first voltage is capable of maintaining the display panel. The voltage at which the thin film field effect transistor is turned on, that is, the VGH shown in Figures 2a-2h.

As for how to set the best chamfering waveform, it can be determined by continuous experimentation. The cylinder is introduced as follows.

As shown in FIG. 6, as a driving signal having two chamfering waveforms on the falling edge, it can be found that two parameters VGH and VGL of the driving signal are preset by the system, and other parameters determine the The final form of the drive signal, including:

VI or V2, which determines the voltage variation range of the first chamfering waveform and the second chamfering waveform; T1, which determines the sustaining time of the VGH voltage;

T2, which determines the duration of the first chamfering waveform;

T3, which determines the duration of the second chamfering waveform;

The curvature of the chamfered waveform (when the waveform is a curve) or the slope (when the waveform is a line segment) determines how the voltage changes.

The existing square wave signal is input to the gate line in advance, and the signal distortion caused by the RC delay effect is recorded.

Then, by changing one or more of the above parameters, the signal distortion caused by the RC delay effect under different parameters is recorded. Finally, from the various driving signals with different parameters, the signal with the lowest signal distortion can be selected. Of course, the above is only a parameter selection method of the driving signal. Of course, other methods can be used to determine the parameters of the driving signal with the chamfered waveform, thereby generating a driving signal with a chamfered waveform, which is not described here. .

The embodiment of the invention further provides a display panel, wherein the display panel is provided with a plurality of gate lines, and the display panel is provided with the above-mentioned gate driving circuit for driving the gate lines.

The embodiment of the invention further provides a display device comprising the above display panel. The display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like, or any display product or component.

The above description is only an embodiment of the present invention, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present invention. These improvements and retouchings should also be considered. It is the scope of protection of the present invention.

Claims

Claim

A gate driving circuit for a display panel, comprising:

At least one of the drive signals is a signal having a chamfered waveform.

2. The gate driving circuit according to claim 1, wherein the display panel is provided with a data line driven by a data driving circuit, and the signal generating circuit comprises:

The gate driving circuit according to claim 1, wherein the display panel is provided with a data line driven by a data driving circuit, and the display panel is divided into M display elements in a direction in which the data lines extend. The region, M is an integer greater than or equal to 2, the signal generating circuit includes: M signal generating sub-circuits corresponding to the M display sub-regions;

The driving signals generated by each of the signal generating sub-circuits are signals having a chamfered waveform, wherein in any two of the signal generating sub-circuits, the signal generating sub-circuit corresponding to the display sub-area far from the data driving circuit The number of chamfering waveforms of the generated driving signal is not less than the number of chamfering waveforms of the driving signals generated by the other signal generating sub-circuit.

The gate driving circuit according to claim 1, wherein the chamfering waveform is located at a falling edge of the driving signal.

The gate driving circuit according to claim 4, wherein the chamfering waveform is recessed toward the rising edge direction.

The gate driving circuit according to claim 4, wherein the driving signal is maintained at the first voltage for a time greater than or equal to a predetermined gate line opening time, and the first voltage is capable of maintaining the The voltage at which the thin film field effect transistor in the display panel is turned on.

A display panel, wherein the display panel is provided with a plurality of gate lines, wherein the display panel is provided with a gate for driving the gate lines according to any one of claims 1-6 Drive circuit.

A display device comprising the display panel of claim 7.