CN103177703B - Grid driving circuit, display panel and display device - Google Patents
Grid driving circuit, display panel and display device Download PDFInfo
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- CN103177703B CN103177703B CN201310102231.9A CN201310102231A CN103177703B CN 103177703 B CN103177703 B CN 103177703B CN 201310102231 A CN201310102231 A CN 201310102231A CN 103177703 B CN103177703 B CN 103177703B
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- display panel
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- top rake
- drive singal
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Crystallography & Structural Chemistry (AREA)
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- Computer Hardware Design (AREA)
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract
The embodiment of the invention discloses a grid driving circuit, a display panel and a display device. The grid driving circuit is used on the display panel and characterized by comprising a signal generating circuit and at least one signal, wherein the signal generating circuit is used for generating a grid line driving signal for driving a grid line positioned in the display panel, and the at least one signal enables the driving signal to have cutting angle waveform. The grid driving circuit, the display panel and the display device provide a scheme for weakening the negative influence caused by RC delay from the perspective of a signal source.
Description
Technical field
The present invention relates to the driving of display panel, particularly a kind of gate driver circuit, display panel and display device.
Background technology
Display device is a kind of flat-panel screens be widely used at present, and compared with other display modes, it has low-power consumption, the advantage such as lightweight, radiationless.
The liquid crystal layer that display device generally comprises array base palte, color membrane substrates and is filled between array base palte and color membrane substrates.Viewing area on array base palte comprises multiple subpixel area, and each subpixel area is generally two grid lines (sweep trace) and intersects to surround with two data lines and formed.
Subpixel area inside is provided with the thin film transistor (TFT) and pixel electrode that serve as switching device.By controlling to be applied to the public electrode on color membrane substrates and/or the voltage on pixel electrode, control the electric field intensity put between color membrane substrates and array base palte, and then control the yawing moment of liquid crystal molecule.
Along with the increase of size of display panels and the raising of resolution.RC on grid line and data line postpones (wherein resistance R refers to the resistance of grid line and data line, and electric capacity C comprises grid line and the electric capacity between data line and pixel electrode) and also increases thereupon.And this RC delay can impact Signal transmissions.
As shown in Figure 1, assuming that the left side is the one end near gate driver circuit, Von is voltage corresponding to TFT conducting, can find, in the one end close to gate driver circuit from Fig. 1, gate drive signal is substantially undistorted, and to the one end away from gate driver circuit, the distortion of gate drive signal is very serious, and this distortion will cause the ON time of the TFT being positioned at same a line different, and then cause the pixel electrode duration of charging inconsistent, bring adverse effect to display.
It is all generally the adverse effect that the mode such as material, shape, size by improving grid line weakens RC and postpones to bring in prior art, as adopted the material of low-resistivity, the width and the thickness that strengthen grid line reduce resistance, reduce the overlapping area etc. of grid line and other conductive layers, but the manufacture craft that these modes all can arrive display panel undoubtedly has an impact, increase complexity and the cost of technique.
Summary of the invention
The object of the embodiment of the present invention is to provide a kind of gate driver circuit and display device, weakens from the angle of signal source the adverse effect that RC postpones to bring.
To achieve these goals, embodiments provide a kind of gate driver circuit, for a display panel, described gate driver circuit comprises:
Signal generating circuit, for generating the grid line drive signal driving and be positioned at the grid line of described display panel;
Drive singal described at least one is the signal with top rake waveform.
Above-mentioned gate driver circuit, wherein, described display panel is provided with the data line being data driven more easily drives, described signal generating circuit comprises:
First signal generates electronic circuit, for generating the first drive singal driving and be positioned at the grid line of the first area of described display panel;
Secondary signal generates electronic circuit, for generating the second drive singal driving and be positioned at the grid line of the second area of described display panel;
Described first area is greater than the distance of described second area to described data drive circuit to the distance of described data drive circuit;
The number of the top rake waveform of described first drive singal is m, and the number of the top rake waveform of described second drive singal is n, and wherein m and n is natural number, and m > n.
Above-mentioned gate driver circuit, wherein, described display panel is provided with the data line being data driven more easily drives, described display panel is split into M display subregion on the bearing of trend of data line, M be more than or equal to 2 integer, described signal generating circuit comprises:
Show M the signal that subregion one_to_one corresponding arranges generate electronic circuit with M;
The drive singal that each signal generates electronic circuit generation is the signal with top rake waveform, and the number that the signal that the display subregion that the distance to described data drive circuit is far away is corresponding generates the top rake waveform of the drive singal that electronic circuit generates is more.
Above-mentioned gate driver circuit, wherein, described top rake waveform is positioned at the negative edge of described drive singal.
Above-mentioned gate driver circuit, wherein, described top rake waveform caves in towards rising edge direction.
Above-mentioned gate driver circuit, wherein, the time that described drive singal maintains the first voltage is greater than or equal to predetermined grid line opening time, and described first voltage is the voltage of the Thin Film Transistor (TFT) conducting that can maintain in described display panel.
To achieve these goals, the embodiment of the present invention additionally provides a kind of display panel, described display panel is provided with many grid lines, described display panel is provided with the above-mentioned gate driver circuit for driving described grid line.
To achieve these goals, the embodiment of the present invention additionally provides a kind of display device, comprises above-mentioned display panel.
The embodiment of the present invention has at least one in following beneficial effect:
In the embodiment of the present invention, improve in gate driver circuit one end, the grid line drive signal that gate driver circuit is generated is no longer square-wave signal, but with the signal of top rake waveform, this signal can reduce because RC postpones the distorted signals brought, therefore, it is possible to weaken the adverse effect that RC postpones to bring.
In the embodiment of the present invention, there is provided the signal to RC late effect relative insensitivity by signal source, reduce the adverse effect that RC postpones to bring, the manufacture craft of counter plate without any impact, the complexity of technique can not be increased, also can not increase the cost that technological transformation is brought.
Accompanying drawing explanation
Fig. 1 represents the schematic diagram of signal delay on grid line;
Fig. 2 a-2h is the schematic diagram with the signal of top rake waveform in the embodiment of the present invention;
Fig. 3 represents the schematic diagram of a kind of subregion of display panel in the embodiment of the present invention;
Fig. 4 represents the schematic diagram of the another kind of subregion of display panel in the embodiment of the present invention;
Fig. 5 represents that the zones of different of the display panel of the embodiment of the present invention exports the different schematic diagram with the signal of top rake waveform;
Fig. 6 represents the parameter schematic diagram with the signal of top rake waveform in the embodiment of the present invention.
Embodiment
In the embodiment of the present invention, improve in gate driver circuit one end, the grid line drive signal that gate driver circuit is generated is no longer square-wave signal, but with the signal of top rake waveform, this signal can reduce because RC postpones the distorted signals brought, therefore, it is possible to weaken the adverse effect that RC postpones to bring.
Before the embodiment of the present invention is described in detail, first the part concept that the embodiment of the present invention relates to is described in detail, so that better understand the embodiment of the present invention.
Generally, in common gate drive apparatus, what it exported to grid line is square-wave signal as shown in Fig. 1 left side.
And what is called refers to the signal of top rake waveform:
At the rising edge of drive singal, voltage is not directly jump to VGH from VGL, but from VGL, experience certain hour just rises to VGH; And/or
At the negative edge of drive singal, voltage is not directly jump to VGL from VGH, but from VGH, experience certain hour just drops to VGL.
In a particular embodiment of the present invention, from VGH drop to VGL experience time span and from VGL rise to VGH experience time span can arrange as required.
As several demonstrations that Fig. 2 a-2h is with the signal of top rake waveform in the embodiment of the present invention, but should be understood that, Fig. 2 a-2h does not contain all signals with top rake waveform, only illustrates.
In figure, VGH is the high plateau voltage of corresponding TFT device ON state, and VGL is the low order voltage of corresponding TFT device ON state.
Can find from figure, in a particular embodiment of the present invention, signal with top rake waveform can with a top rake waveform, as shown in Figure 2 a-2d, also can with multiple top rake waveform, as shown in Fig. 2 e-2f, wherein the signal shown in Fig. 2 e is with two top rake waveforms, and the signal shown in Fig. 2 f is with three top rake waveforms.
The signal generating the top rake waveform shown in Fig. 2 a-2h can be realized by various mode, as generated multiple signal, unlike signal is exported in different phase, the unlike signal that different phase exports combines the signal that can obtain the top rake waveform shown in Fig. 2 a-2h in time, does not elaborate at this.
The gate driver circuit of the embodiment of the present invention, for a display panel, described gate driver circuit comprises:
Signal generating circuit, for generating the grid line drive signal driving and be positioned at the grid line of described display panel;
Drive singal described at least one is the signal with top rake waveform.
Because TFT LCD is close in the region of gate driver circuit, the distorted signals degree of gate drive signal is less, and away from the region of gate driver circuit, the distorted signals degree of gate drive signal is comparatively large, and the wave mode of the gate drive signal that is on same grid line should be the state of successively decreasing.And in the embodiment of the present invention, the gate drive signal that gate driver circuit exports has top rake waveform, the diverse location on same grid line can be made, the change of the wave mode of drive singal reduces, that is, the distortion level of the waveform on same grid line can be made to reduce, and the gap of the opening time of the TFT therefore on same grid line reduces, and improves display quality.
Simultaneously, in the embodiment of the present invention, the signal to RC late effect relative insensitivity is provided by signal source, reduce the adverse effect that RC postpones to bring, therefore do not need the material to grid line, shape, size to change, that is, the manufacture craft of counter plate without any impact, the complexity of technique can not be increased, also can not increase the cost that technological transformation is brought.
In a particular embodiment of the present invention, this signal generating circuit can realize in several ways, is respectively described below.
< mode one >
The drive singal with top rake waveform is only exported to part grid line.
As shown in Figure 3, the distribution of foundation data driving chip and grid drive chip, display panel is whole is divided into 4 regions, wherein, region C due to the transmission path of data-signal and sweep signal all long, therefore be subject to RC late effect to have the greatest impact, and region B takes second place, it is minimum that region A is subject to the impact of RC late effect.
Consider the tolerance of system, may only have the impact of off-limits RC late effect that display quality just can be made to become and can not put up with, in this manner, the embodiment of the present invention only can export the drive singal with top rake waveform to part grid line.
For the situation shown in Fig. 3, only can export the drive singal with top rake waveform to the grid line being positioned at region D, that is, only have grid drive chip A to need to export the drive singal with top rake waveform, and grid drive chip B export square-wave signal according to existing mode.
< mode two >
The drive singal with top rake waveform is exported to all grid lines.
In mode one, only export the drive singal with top rake waveform to affecting the grid line exceeded in the region of certain limit by late effect.
But which region no matter should be understood that, be in, all can be subject to late effect impact, its difference is only affected size.
Therefore, in mode two, can not distinguishable region, the drive singal with top rake waveform is all exported to all grid lines.
But in mode two, the drive singal with top rake waveform exported to every root grid line can waveform identical, but also can waveform different.
< mode three >
Export the drive singal with top rake waveform to all grid lines, the number of the top rake waveform of the drive singal of zones of different is different.
As shown in Figure 4, in the transmission direction of data line, display panel is divided into 4 regions, is respectively region E, F, G and H.Knowwhy according to postponing transmission can be known, region H has the greatest impact by late effect, and region G takes second place, and again, region E affects minimum region F by late effect.
Therefore, in a particular embodiment of the present invention, to all regions unified export same there is the drive singal of top rake waveform time, this drive singal only may can play in subregion and reduce because RC postpones the effect of the distorted signals brought, and may act in other regions and not obvious.
Based on above consideration, in a particular embodiment of the present invention, comprise multiple electronic circuit at gate driver circuit, when each electronic circuit has each self-corresponding viewing area, according to the difference of corresponding region, electronic circuit generates and exports the different drive singal that have top rake waveform corresponding from region.
When display panel is divided into 3 and above region, described display panel is provided with the data line being data driven more easily drives, described display panel be split on the bearing of trend of data line M display subregion, M be more than or equal to 3 integer, described signal generating circuit comprises:
Show M the signal that subregion one_to_one corresponding arranges generate electronic circuit with M;
The drive singal that each signal generates electronic circuit generation is the signal with at least one top rake waveform, and the number that the signal that the display subregion that the distance to described data drive circuit is far away is corresponding generates the top rake waveform of the drive singal that electronic circuit generates is more.
When display panel is divided into 2 regions, described signal generating circuit comprises:
First signal generates electronic circuit, for generating the first drive singal driving and be positioned at the grid line of the first area of described display panel;
Secondary signal generates electronic circuit, for generating the second drive singal driving and be positioned at the grid line of the second area of described display panel;
Described first area is greater than the distance of described second area to described data drive circuit to the distance of described data drive circuit;
The number of the top rake waveform of described first drive singal is m, and the number of the top rake waveform of described second drive singal is n, and wherein m and n is natural number, and m > n.
Illustrate as follows with the situation shown in Fig. 4.
As shown in Figure 4, can export the same drive singal X1 with top rake waveform to region E and F, and export the same drive singal X2 with top rake waveform to region G and H, wherein the number of the top rake waveform of X2 is greater than the number of the top rake waveform of X1;
As shown in Figure 5, the arrow wherein in figure represents the corresponding relation between region and the gate drive signal being input to this region to the signal finally sent.
The drive singal Y1 with top rake waveform can certainly be exported to region E, export the drive singal Y2 with top rake waveform to region F, export the drive singal Y3 with top rake waveform to region G, export the drive singal Y4 with top rake waveform to region H.Wherein the number of the top rake waveform of Y4 is greater than the number of the top rake waveform of Y3, and the number of the top rake waveform of Y3 is greater than the number of the top rake waveform of Y2, and the number of the top rake waveform of Y2 is greater than the number of the top rake waveform of Y1.
Certainly can also be other mode, not enumerate at this.
In a particular embodiment of the present invention, the distorted signals that top rake waveform brings to reduce RC late effect can be set at the rising edge of signal, but more excellent way arranges the distorted signals that top rake waveform brings to reduce RC late effect, i.e. situation shown in Fig. 2 a, 2d-2g at the negative edge of drive singal.
Meanwhile, in a particular embodiment of the present invention, when arranging top rake waveform at the negative edge of signal, described top rake waveform preferably caves in towards rising edge direction, as shown in Fig. 2 d-2g.
In a particular embodiment of the present invention, in order to ensure that TFT has enough time to open, the time that described drive singal maintains the first voltage is greater than or equal to predetermined grid line opening time, described first voltage is the voltage of the Thin Film Transistor (TFT) conducting that can maintain in described display panel, i.e. VGH shown in Fig. 2 a-2h.
As for how arranging best top rake waveform, then can determine by constantly testing, briefly introducing as follows.
As shown in Figure 6, be a kind of drive singal at negative edge with two top rake waveforms, can find, wherein two parameter VGH and VGL of this drive singal are that system is pre-set, and other parameters determine the final form of this drive singal, comprising:
V1 or V2, which determines the voltage change range of first top rake waveform and second top rake waveform;
T1, which determines holding time of VGL voltage;
T2, which determines the duration of first top rake waveform;
T3, which determines the duration of second top rake waveform;
And the curvature of top rake waveform (when waveform is curve) or slope (when waveform is line segment), which determine the variation pattern of voltage.
In advance existing square-wave signal is input to grid line, and records the distorted signals that RC late effect brings.
Then one or more by what change in above-mentioned parameter, the distorted signals that under record different parameters, RC late effect is brought.
The last various drive singal different from parameter, select the signal that distorted signals is minimum.
Certainly, above is only a kind of Selecting parameter mode of drive singal, can certainly utilize other modes to determine the parameter of the drive singal with top rake waveform, and then produces the drive singal with top rake waveform, does not describe one by one at this.
The embodiment of the present invention additionally provides a kind of display panel, described display panel is provided with many grid lines, described display panel is provided with the above-mentioned gate driver circuit for driving described grid line.
The embodiment of the present invention additionally provides a kind of display device, comprises above-mentioned display panel.Described display device can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
The above is only embodiments of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1. a gate driver circuit, for a display panel, is characterized in that, described gate driver circuit comprises:
Signal generating circuit, for generating the grid line drive signal driving and be positioned at the grid line of described display panel;
Drive singal described at least one is the signal with top rake waveform;
Described display panel is provided with the data line being data driven more easily drives, described signal generating circuit comprises:
First signal generates electronic circuit, for generating the first drive singal driving and be positioned at the grid line of the first area of described display panel;
Secondary signal generates electronic circuit, for generating the second drive singal driving and be positioned at the grid line of the second area of described display panel;
Described first area is greater than the distance of described second area to described data drive circuit to the distance of described data drive circuit;
The number of the top rake waveform of described first drive singal is m, and the number of the top rake waveform of described second drive singal is n, and wherein m and n is natural number, and m>n;
Or
Described display panel is provided with the data line being data driven more easily drives, described display panel be split on the bearing of trend of data line M display subregion, M be more than or equal to 2 integer, described signal generating circuit comprises:
Show M the signal that subregion one_to_one corresponding arranges generate electronic circuit with M;
The drive singal that each signal generates electronic circuit generation is the signal with top rake waveform, and the number that the signal that the display subregion that the distance to described data drive circuit is far away is corresponding generates the top rake waveform of the drive singal that electronic circuit generates is more.
2. gate driver circuit according to claim 1, is characterized in that, described top rake waveform is positioned at the negative edge of described drive singal.
3. gate driver circuit according to claim 2, is characterized in that, described top rake waveform caves in towards rising edge direction.
4. gate driver circuit according to claim 2, it is characterized in that, the time that described drive singal maintains the first voltage is greater than or equal to predetermined grid line opening time, and described first voltage is the voltage of the Thin Film Transistor (TFT) conducting that can maintain in described display panel.
5. a display panel, described display panel is provided with many grid lines, it is characterized in that, described display panel is provided with the gate driver circuit for driving described grid line in claim 1-4 described in any one.
6. a display device, comprises display panel according to claim 5.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310102231.9A CN103177703B (en) | 2013-03-27 | 2013-03-27 | Grid driving circuit, display panel and display device |
| PCT/CN2013/076601 WO2014153836A1 (en) | 2013-03-27 | 2013-05-31 | Gate drive circuit, display panel, and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310102231.9A CN103177703B (en) | 2013-03-27 | 2013-03-27 | Grid driving circuit, display panel and display device |
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| CN103177703A CN103177703A (en) | 2013-06-26 |
| CN103177703B true CN103177703B (en) | 2015-05-13 |
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| CN201310102231.9A Active CN103177703B (en) | 2013-03-27 | 2013-03-27 | Grid driving circuit, display panel and display device |
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| WO (1) | WO2014153836A1 (en) |
Families Citing this family (5)
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|---|---|---|---|---|
| CN105741793B (en) * | 2014-12-12 | 2019-05-31 | 群创光电股份有限公司 | Scanning pulse modulation top rake circuit |
| CN105070243B (en) | 2015-09-15 | 2017-10-31 | 重庆京东方光电科技有限公司 | Gate turn-on voltage compensation circuit, display panel, driving method and display device |
| CN106200057B (en) * | 2016-09-30 | 2020-01-03 | 京东方科技集团股份有限公司 | Driving method of display panel, driving chip and display device |
| CN109686328A (en) * | 2018-12-21 | 2019-04-26 | 惠科股份有限公司 | Driving device and display device thereof |
| CN110288959A (en) * | 2019-06-27 | 2019-09-27 | 北海惠科光电技术有限公司 | The driving circuit and its driving method of a kind of display panel, display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3628676B2 (en) * | 2002-10-28 | 2005-03-16 | シャープ株式会社 | Display device |
| KR100514182B1 (en) * | 2003-09-08 | 2005-09-13 | 삼성에스디아이 주식회사 | Electro Luminescence display panel |
| JP3715306B2 (en) * | 2005-02-07 | 2005-11-09 | シャープ株式会社 | Display device and display method |
| TWI336461B (en) * | 2007-03-15 | 2011-01-21 | Au Optronics Corp | Liquid crystal display and pulse adjustment circuit thereof |
| CN101320998B (en) * | 2007-06-06 | 2012-03-14 | 广达电脑股份有限公司 | Communication and control system and method |
| CN101226714B (en) * | 2008-02-02 | 2010-09-22 | 友达光电股份有限公司 | Flat display device as well as control circuit and control method thereof |
| CN101315749B (en) * | 2008-06-26 | 2010-06-16 | 上海广电光电子有限公司 | Driving method of liquid crystal display |
| CN101644867B (en) * | 2009-09-03 | 2011-05-18 | 上海广电光电子有限公司 | Driving device of gate line of liquid crystal display |
| TWI405177B (en) * | 2009-10-13 | 2013-08-11 | Au Optronics Corp | Gate output control method and corresponding gate pulse modulator |
| CN101937640B (en) * | 2010-08-30 | 2012-08-29 | 友达光电股份有限公司 | Grid pulse wave modulation circuit and modulation method thereof |
| TWI440011B (en) * | 2011-10-05 | 2014-06-01 | Au Optronics Corp | Liquid crystal display having adaptive pulse shaping control mechanism |
| TW201340069A (en) * | 2012-03-16 | 2013-10-01 | Au Optronics Corp | Display device and method for generating scanning signal thereof |
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- 2013-03-27 CN CN201310102231.9A patent/CN103177703B/en active Active
- 2013-05-31 WO PCT/CN2013/076601 patent/WO2014153836A1/en active Application Filing
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| WO2014153836A1 (en) | 2014-10-02 |
| CN103177703A (en) | 2013-06-26 |
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