Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
  • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
  • H02H3/20—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess voltage
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
  • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
  • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
  • H02H9/041—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage using a short-circuiting device
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
  • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
  • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
  • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
  • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits

Definitions

• overvoltage circuitry may be included to protect against such overvoltage conditions.
• Some overvoltage protection circuitry includes the use of various transistors that switch on upon detection of an overvoltage condition on an input node. The amount of current such transistors may be required to sink may necessitate the transistors to be relatively large. A large transistor results in large parasitic capacitances caused by the transistor. Large parasitic capacitances may limit the bandwidth of the circuitry, which is a particular problem for high speed data signals.
• Some implementations are directed to an amplitude limiter circuit that includes an inductor and first and second transistors.
• the inductor has a first terminal connected to an input node.
• the first transistor is connected to a second terminal of the inductor and also is connected to ground.
• the second transistor is connected to the input node and to a gate of the first transistor. If an overvoltage condition forms on the input node, the second transistor is caused to conduct thereby turning on the first transistor which, in turn, causes an overvoltage current path to form from the input node, through the inductor, through the first transistor and to ground.
• the inductor of the amplitude limiter isolates the input signal from any parasitic capacitance that may be caused by the first transistor.
• the amplitude limiter includes an inductor having a first terminal connected to an input node.
• the limiter also includes a first transistor connected to a second terminal of the inductor.
• the first transistor is also connected to ground.
• the second transistor is connected to the input node and to a gate of the first transistor. When an overvoltage condition on the input node is formed, the second transistor is caused to conduct thereby turning on the first transistor which, in turn, causes an overvoltage current path to form from the input node, through the inductor, through the first transistor and to ground.
• FIG. 1 shows a system in accordance with principles of the disclosure and including an amplitude limiter circuit
• FIG. 2 shows an example of the amplitude limiter of FIG. 1
• FIG. 3 shows a more detailed implementation of the amplitude limiter circuit of FIG. 2;
• FIG. 4 shows a more detailed implementation of the amplitude limiter circuit of FIG. 2.
• FIG. 1 illustrates a system in which a transmitter 100 transmits a signal 105 to a receiver 110.
• the transmitter 100 and receiver 110 may be part of the same device or may be implemented in different devices.
• the transmitter 100 and receiver 110 may be embodied on a common silicon substrate, while such is not the case in other implementations.
• the receiver 110 includes an amplitude limiter 120 coupled to a host 130.
• the host 130 provides the receiver with its intended functionality and no limitation is made herein as to the functionality implemented by the transmitter 100 and receiver 110, other than for the transmitter to provide a signal 105 to the receiver.
• the signal 105 may be a single- ended or a differential signal.
• the amplitude limiter 120 receives the input signal 105 from the transmitter 100 and limits the amplitude of the input signal to a specified threshold. In some implementations, the amplitude limiter 120 limits the input signal to be less than, for example, 2V, although other overvoltage thresholds are possible as well. Any attempted deviation of the voltage amplitude of the input signal 105 outside the prescribed overvoltage threshold will be limited by the amplitude limiter 120 by forcing the voltage amplitude of the input signal 105 to be below the prescribed overvoltage threshold. The amplitude limiter 120 provides the amplitude limited input signal 105 to the host 130 as shown by signal 107. [0012] FIG. 2 shows an example of the amplitude limiter 120.
• the amplitude limiter 120 limits the amplitude of a single-ended signal.
• the implementation of FIG. 2 pertains to a differential input signal 105 and FIG. 2 shows the amplitude limiter 120 that limits the amplitude of the positive differential input signal— a corresponding amplitude limiter 120 would also be provided to limit the amplitude of the negative differential input signal.
• amplitude limiter 120 includes an inductor LI, a resistor Rl, and a shunt circuit 145.
• the input signal 105 is provided at an input node 140, and the input node 140 also provides the output signal 107 to host 130. That is, the input node both receives the signal 105 from the transmitter to be amplitude limited and is the amplitude limited signal 107 itself.
• the inductor LI includes a first terminal 150 connected to the input node 140.
• a second terminal 152 of the inductor LI connects to impedance matching resistor Rl and to the shunt circuit 145.
• the shunt circuit 145 connects to a low impedance node 146 (e.g., ground).
• the shunt circuit 145 also connects to the input node 140 so as to monitor the voltage level of the input signal 105.
• the shunt circuit 145 detects that the voltage on the input node 140 is beginning to exceed an overvoltage threshold, the shunt circuit causes an overvoltage current path 160 to from input node 140 through inductor LI, through shunt circuit 145 and to the low impedance node 146. Otherwise, the absence of an overvoltage condition, the overvoltage current path 160 does not form and no current from the input node 140 is shunted through the shunt circuit 145. By shunting current from the input node 140 to the low impedance node 146 and as further described below, the voltage on the input node is precluded from exceeding the overvoltage threshold.
• any parasitic capacitance caused the shunt circuit 145 is essentially isolated by the inductor LI .
• An inductor's impedance increases with increasing impedance.
• the equivalent impedance of the series combination of the inductor LI and the parasitic capacitance of the shunt circuit 145 is essentially dominated by the inductor LI .
• the parasitic capacitance of the shunt circuit 145 has little effect on the bandwidth of the input signal 105.
• FIG. 3 shows an example circuit implementation of the amplitude limiter 120.
• the illustrative circuit in FIG. 3 includes the inductor LI, transistors Ml and M2, and resistors R1-R4.
• An example of the shunt circuit 145 of FIG. 2 is illustrated in FIG. 3 as comprising transistors Ml and M2 and resistors R2-R4.
• transistor Ml is an N-channel metal oxide semiconductor (NMOS) transistor and transistor M2 is a P-channel MOS (PMOS) transistor, although other types of transistors and doping schemes can be implemented as well.
• NMOS N-channel metal oxide semiconductor
• PMOS P-channel MOS
• the input signal 105 is provided at input node 140, and the input node 140 also provides the output signal 107 to host 130. That is, the input node both receives the signal 105 from the transmitter to be amplitude limited and is the amplitude limited signal 107 itself.
• the first terminal 150 of inductor LI is connected to the input node 140.
• the second terminal 152 of the inductor LI connects to the drain Dl of transistor Ml.
• the source SI of transistor Ml is connected to a low impedance node which in the example of FIG. 2 (and FIG. 3) is ground.
• the second terminal 152 of the inductor LI also connects to a resistor Rl as shown. Resistor Rl is selected to function as an input termination resistor to match impedance with the transmitter 100 so as to better attenuate reflections that might otherwise occur if no termination resistor or an improperly selected termination resistance was used.
• Resistors R3 and R4 form a voltage divider whose divided voltage on node 172 is provided to the gate G2 of transistor M2.
• the source S2 of transistor M2 connects to the input node 140.
• the drain D2 of transistor M2 connects to resistor R2 (which connects to ground) and also to the gate Gl of transistor Ml.
• the connection point between the drain D2 of transistor M2, the gate Gl of transistor Ml and resistor R2 is labeled as node 175.
• the source S2 of transistor M2 may connect to the second terminal 152 of the inductor, rather than the input node 140.
• the voltage on node 172 from the voltage divider formed by resistors R3 and R4 is a reference voltage (VREF) for determining the overvoltage point (i.e., the point at which the voltage amplitude of the input signal 105 exceeds a maximum rating for host 130) for the amplitude limiter 110.
• VREF reference voltage
• the transistor M2 turns on. Otherwise, if the voltage on input node 140 relative to the voltage at node 172 is below transistor M2's threshold voltage, the transistor M2 remains off.
• transistor M2 is off. With transistor M2 off, the voltage on node 175 will be low thereby causing transistor Ml to be off as well. Thus, during normal system operation (no overvoltage condition), both transistors Ml and M2 are off and no current is conducted through either transistor.
• the voltage drops across the inductor LI and transistor Ml combine as the voltage on input node 140.
• the input voltage on input node 140 thus is influenced by two factors.
• the first factor is the voltage on the input signal 105 generated by the transmitter 100.
• the second factor is the combined voltages of the inductor LI and transistor Ml .
• the combined voltages from the inductor LI and transistor Ml dominate any competition caused by the transmitter, and the voltage on the input node 140 is thereby limited to the combined voltages of the inductor LI and transistor Ml .
• the component selection for the inductor LI and transistor Ml are such that the resulting voltages combine to form the target overvoltage threshold.
• an inductor's impedance increases with frequency.
• the inductor LI serves two purposes. First, the inductor LI ensures superior bandwidth properties for the system than without the inductor. At higher frequencies, the impedance of the inductor, which is in series with resistor Rl, increases. Resistor Rl is an input termination resistor, and, due to the frequency-dependent impedance of inductor LI, the effective input termination resistance increases with increasing frequency on the input signal 105.
• VCM voltage labeled in FIG. 3 refers to a common mode voltage between positive and negative signals of a differential signal pair.
• the example circuit of FIG. 3 includes only two transistors. However, in other examples, more than two transistors are possible.
• FIG. 4 shows another implementation of amplitude limiter 110.
• the implementation of FIG. 4 is similar in many respects to the implementation of FIG. 3.
• the principle difference is the inclusion of transistors M3 and M4.
• Transistor M3 preferably is a PMOS device and transistor M4 preferably is an NMOS device, although transistors M3 and M4 can be different in other implementations.
• the source and drain of transistor M3 are connected in series with voltage divider resistors R3 and R4.
• Transistor M4 connects to node 175 and ground as shown.
• Transistors M3 and M4 function to disable the overvoltage protection otherwise afforded by the amplitude limiter 110. Both transistors are controlled by the same control signal DISABLE, although separate disable signals may be used as well.
• the DISABLE signal may be controlled by host 130.
• the DISABLE signal is forced to a logic low level. With DISABLE low, transistor M3 is on and transistor M4 is off. With M3 on, the voltage divider provides the divided down voltage on node 172 to the gate of transistor M2 as explained above. Transistor M4 being off due to a low state for the DISABLE signal precludes M4 from having any effect on the operation of the circuit.
• the DISABLE signal is forced to a logic high level (e.g., by host 130). With DISABLE high, transistor M3 is off and transistor M4 is on. With transistor M3 in an off state, no current flows from the positive supply voltage through resistor R3 and, as a result, the voltage on node 175 is forced high. By forcing the voltage on node 172 to a high level, transistor M2 will not turn on despite on overvoltage condition on input node 140. With transistor M4 in an on state (and with its source connected to ground), node 175 is forced low which also precludes transistor Ml from turning on.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
• Semiconductor Integrated Circuits (AREA)
• Electronic Switches (AREA)
• Emergency Protection Circuit Devices (AREA)
• Amplifiers (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (2)

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• 2013
  • 2013-03-19 US US13/847,261 patent/US10541527B2/en active Active
• 2014
  • 2014-03-19 WO PCT/US2014/031206 patent/WO2014153400A2/en not_active Ceased
  • 2014-03-19 CN CN201480017145.0A patent/CN105103445A/zh active Pending
  • 2014-03-19 EP EP14767569.8A patent/EP2995001A4/en not_active Withdrawn
  • 2014-03-19 JP JP2016505496A patent/JP6665083B2/ja active Active

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