WO2014139167A1 - 一种改良栅结构的晶体管 - Google Patents

一种改良栅结构的晶体管 Download PDF

Info

Publication number
WO2014139167A1
WO2014139167A1 PCT/CN2013/072746 CN2013072746W WO2014139167A1 WO 2014139167 A1 WO2014139167 A1 WO 2014139167A1 CN 2013072746 W CN2013072746 W CN 2013072746W WO 2014139167 A1 WO2014139167 A1 WO 2014139167A1
Authority
WO
WIPO (PCT)
Prior art keywords
top gate
gate
channel region
region
voltage
Prior art date
Application number
PCT/CN2013/072746
Other languages
English (en)
French (fr)
Inventor
戴明志
Original Assignee
中国科学院宁波材料技术与工程研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院宁波材料技术与工程研究所 filed Critical 中国科学院宁波材料技术与工程研究所
Priority to PCT/CN2013/072746 priority Critical patent/WO2014139167A1/zh
Publication of WO2014139167A1 publication Critical patent/WO2014139167A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate

Definitions

  • the invention belongs to the field of microelectronics, and in particular relates to a transistor with improved gate structure.
  • a transistor is a solid-state semiconductor device that can be used for detection, rectification, amplification, switching, regulation, signal modulation, and many other functions.
  • the transistor controls the current flowing out based on the input voltage. Therefore, the transistor can be used as a current switch.
  • the difference between the transistor and the general mechanical switch is that the transistor is controlled by the electric signal, and the switching speed can be very fast. Switching speeds in the lab More than 100GHz.
  • Transistors can be divided into two main categories: bipolar transistors (BJT) and field effect transistors (FETs).
  • BJT bipolar transistors
  • FETs field effect transistors
  • the transistor has three poles; the three poles of the bipolar transistor are respectively composed of an emitter, a base and a collector of an N-type and a P-type; and three poles of a field effect transistor are a source (source region) respectively ( Source ), gate (gate) and drain (drain).
  • the authorization notice number is CN 101567392B
  • the invention discloses a thin film transistor having a gate insulating layer which has good characteristics and high reliability while ensuring good productivity, and the thin film transistor includes: an active source including a source region, a channel region, and a drain region on a substrate a layer, a gate electrode layer, and a thin film transistor of a gate insulating layer formed between the active layer and the gate electrode layer, the gate insulating layer being formed by the side of the active layer A silicon oxide film, a second silicon oxide film formed on the gate electrode layer side, and a silicon nitride film formed between the first silicon oxide film and the second silicon oxide film.
  • a transistor is a core component in a logic circuit.
  • Logic is a discrete signal transfer and processing in binary
  • the circuit for realizing the logic operation and operation of digital signals is mainly divided into combination logic circuit and sequential logic circuit, which is composed of the most basic "AND gate” circuit, "OR gate circuit” and “Non gate” circuit.
  • the invention provides a transistor with improved gate structure, which can reduce the number of transistors in the logic circuit, make the preparation method of the logic circuit simple, reduce the device area, thereby improving the yield of the logic circuit, reducing the manufacturing cost, and can be easily improved. Adjust the electrical performance of the logic circuit device.
  • a transistor with improved gate structure includes a substrate and a dielectric layer on the substrate, wherein the dielectric layer is provided with a source region, a drain region, and a channel region connected between the source region and the drain region.
  • a first top gate is provided in the channel region as an output terminal of the transistor, and a logic value of the output is logic when the channel region is turned on. 1 , logic 0 when the channel region is truncated;
  • the transistor is further provided with at least two input poles as control channel regions; at least one of the inputs is a second top gate; and at least one of the inputs is a third top gate and / Or a bottom gate; the second top gate and the third top gate are both located on the dielectric layer and beside the channel region.
  • the top gate beside the channel region is located on the dielectric layer. It should be understood that these top gates are in contact with at least the dielectric layer.
  • the top gate as the output pole does not cover the entire channel region, and the top gate has a stable output voltage; in order to make the top gate have a stable output voltage, the top gate should have a suitable length in the channel region.
  • the size is such that the output voltage of the top gate is a definite value, that is, the output voltage of the top gate remains relatively stable after the input pole voltage is determined.
  • the top gate size is as small as possible under the premise of ensuring strength and electrical conductivity.
  • a bottom gate for controlling the channel region is provided, the bottom gate being between or between the substrate and the dielectric layer.
  • the source region, the drain region, the top gate and the bottom gate can all adopt the conductive characteristic materials used in the prior art, including metals, alloys, conductive polymers, conductive carbon nanotubes, indium tin oxide (ITO), indium.
  • Gallium zinc oxide (IGZO And the like wherein the metal is aluminum, copper, tungsten, molybdenum, gold or ruthenium; the alloy contains at least two of aluminum, copper, tungsten, molybdenum, gold, and niobium; and the channel region uses a semiconductor material.
  • the semiconductor materials include organic semiconductor materials and inorganic semiconductor materials and the like, such as oxide semiconductors (such as indium tin oxide), zinc oxide nanowires, and carbon nanotubes.
  • Indium tin oxide is used for the source region, the drain region, the top gate, the bottom gate, and the channel region.
  • the source region, the drain region, the top gate, the bottom gate and the channel region are self-assembled by a single mask method, and the process is simple.
  • the substrate can be made of various materials, and only needs to have a certain strength to support, including glass, quartz, ceramic, diamond, paper, silicon wafer, plastic or resin.
  • the channel region is generally strip-shaped, and the 'side' may be either one side in the length direction of the channel region or one side in the width direction.
  • the length of the channel region is 0.001 ⁇ 5000 ⁇ m, and the width of the channel region is 0.0001 ⁇ 1000 ⁇ . m , the electrical thickness of the channel region is 0.001 ⁇ 8000nm;
  • the length of the channel region is 0.01 to 100 ⁇ m, and the width of the channel region is 0.01 to 100 ⁇ m.
  • the electrical thickness of the channel region is 0.01 ⁇ 200nm;
  • the length of the channel region is 0.1 to 10 ⁇ m, and the width of the channel region is 0.01 to 10 ⁇ m.
  • the electrical thickness of the channel region is 1 to 50 nm.
  • the dielectric layer is made of an insulating material, and the physical thickness of the dielectric layer is 0.001 ⁇ 1000 ⁇ m. Preferably, the dielectric layer has a physical thickness of 1 to 200 ⁇ m.
  • the dielectric layer is at least one of silicon dioxide (eg, porous silica, thermally grown silica), benzocyclobutene, polyester, acrylic, alumina, silicon oxynitride, high ⁇ gate dielectric material.
  • silicon dioxide eg, porous silica, thermally grown silica
  • benzocyclobutene polyester
  • acrylic e.g., acrylic, alumina, silicon oxynitride, high ⁇ gate dielectric material.
  • a capacitance is generated at the interface between the dielectric layer and the channel region.
  • the minimum lateral distance (distance along the length of the channel region) of the source and drain regions and the top gate as the output pole are both 0.0001 ⁇ 100 ⁇ m; the source or drain region and the outer trench of the channel
  • the minimum lateral distance is 0.0001 ⁇ 100 ⁇ m.
  • the top gate as the output pole can output a determined voltage which is determined by whether the channel region is turned on, the source/drain voltages V DS and l.
  • the top gate is not located in the channel region, then preferably the top gate is as close as possible to the channel region.
  • the transistor described in the present invention may be a thin film transistor.
  • the top gate, the source region and the drain region in the channel region are arranged in a first straight line.
  • the top gate is two, respectively a first top gate and a second top gate, wherein the first top gate is in the channel region, and is arranged first with the source region and the drain region.
  • a straight line, the second top gate is located on one side of the first straight line and aligned with the first top gate.
  • the top gate is two, respectively a first top gate and a second top gate, wherein the first top gate is in the channel region, and is arranged first with the source region and the drain region.
  • a straight line, the second top gate is located on the first straight line.
  • the source region, the drain region, the first top gate and the second top gate of the transistor are arranged in a strip shape, which is convenient for manufacturing a linear logic circuit.
  • the top gate is three, respectively a first top gate, a second top gate and a third top gate, wherein the first top gate is in the channel region, and the source region and the drain region are three
  • the first top gate and the third top gate are respectively located on both sides of the first straight line or on the same side of the first straight line.
  • the second top gate and the third top grid are arranged in a second straight line, and the second straight line is perpendicular to the first straight line.
  • the source region, the drain region, the first top gate, the second top gate, and the third top gate of the transistor are arranged in a block shape to facilitate the fabrication of a block type logic circuit.
  • the second top gate and the third top gate are located on the same side of the first straight line and Arranged in a second line, the second line being perpendicular to the first line.
  • one of the second top gate and the third top gate is aligned with the first top gate.
  • the second top gate and the third top gate are located on the same side of the first straight line and Arranged in a second line, the second line being perpendicular to the first line.
  • the shortest distances from the first top gate to the second top gate and the third top gate are equal.
  • the second top gate and the third top gate are respectively located on opposite sides of the first straight line and Arranged in a second line, the second line being perpendicular to the first line.
  • one of the second top gate and the third top gate is aligned with the first top gate.
  • the second top gate and the third top gate are respectively located on opposite sides of the first straight line and Arranged in a second line, the second line being perpendicular to the first line.
  • the shortest distances from the first top gate to the second top gate and the third top gate are equal.
  • the second top gate and the third top gate are located on the same side of the first straight line and Arranged in a second line, the second line being parallel to the first line.
  • the source region, the drain region, the first top gate, the second top gate, and the third top gate of the transistor are arranged in a block shape to facilitate the fabrication of a block type logic circuit.
  • the second top gate and the third top gate are located on the same side of the first straight line and Arranged in a second line, the second line being parallel to the first line.
  • one of the second top gate and the third top gate is aligned with the first top gate.
  • the second top gate and the third top gate are located on the same side of the first straight line and Arranged in a second line, the second line being parallel to the first line.
  • the shortest distances from the first top gate to the second top gate and the third top gate are equal.
  • the top gate is three, which are a first top gate, a second top gate and a third top gate, respectively, wherein the first top gate is in the channel region, and is arranged with the source region and the drain region.
  • the first straight line, the second top gate and the third top grid are arranged in a second straight line, and the second straight line coincides with the first straight line.
  • the second top gate and the third top gate are on the same side of the source region and away from the drain region. Or the second top gate and the third top gate are on the same side of the drain region and away from the source region.
  • the top gate is three, which are a first top gate, a second top gate and a third top gate, respectively, wherein the first top gate is in the channel region, and is arranged with the source region and the drain region.
  • the first straight line, the second top gate and the third top grid are arranged in a second straight line, and the second straight line coincides with the first straight line.
  • One of the second top gate and the third top gate is on one side of the source region and away from the drain region.
  • One of the second top gate and the third top gate is on one side of the source region and away from the source region.
  • the source region, the drain region, the first top gate, the second top gate, and the third top gate of the transistor are arranged in a strip shape, which is convenient for manufacturing a linear logic circuit.
  • the bottom gate is located between the substrate and the dielectric layer, the bottom gate is distributed in a partial area on the substrate, and the substrate is provided with a receiving groove corresponding to the position of the bottom gate, and the area of the bottom gate is at least capable of being
  • the top gate next to the channel region forms a coupling, To control the channel region.
  • the bottom gate is coupled to the top gate as an input pole for better control of the channel region.
  • the side of the substrate that is bonded to the dielectric layer should be a conductive material, and the side facing away from the dielectric layer should be a non-conductive material.
  • a conductive layer is disposed between the substrate and the dielectric layer.
  • the conductive layer is made of a conductive material such as ITO or IGZO .
  • ITO indium tin oxide
  • IGZO conductive material
  • each transistor has at least two top gates, and each of the top gates outside the channel region can regulate the channel region.
  • the same transistor can realize multiple logic circuit functions, for example, With doors, or doors, NAND gates, etc.
  • the first top gate, the second top gate, the third top gate and the fourth top gate respectively, wherein the first top gate is in the channel region, and the source region and the drain region are arranged in a first straight line a second top gate, a third top gate, and a fourth top gate are arranged in a second line, and the second line coincides with the first line.
  • the second top gate and the third top gate are on the same side of the source region and away from the drain region.
  • the second top gate and the third top gate are on the same side of the drain region and away from the source region.
  • the fourth top gate can be located at any position. Preferably, on one side of the source region and away from the drain region, or on one side of the drain region and away from the source region
  • the first top gate, the second top gate, the third top gate and the fourth top gate respectively, wherein the first top gate is in the channel region, and the source region and the drain region are arranged in a first straight line a second top gate, a third top gate, and a fourth top gate are arranged in a second line, and the second line coincides with the first line.
  • the second top gate and the third top gate are respectively located on one side of the source region and away from the drain region, and on one side of the drain region and away from the source region.
  • the fourth top gate can be located at any position. Preferably, on one side of the source region and away from the drain region, or on one side of the drain region and away from the source region.
  • the input pole does not include a bottom gate, and the top gate is four.
  • the arrangement can be as follows:
  • the first top gate is in the channel region, and is arranged in a first straight line with the source region and the drain region, and the second top gate, the third top gate and the fourth top gate. They are respectively located on two sides of the first straight line, on the first straight line or on the same side of the first straight line.
  • the second top gate, the third top gate and the fourth top grid are arranged in a second straight line, and the second straight line is perpendicular to the first straight line.
  • the source region, the drain region, the first top gate, the second top gate, and the third top gate of the transistor are arranged in a block shape to facilitate the fabrication of a block type logic circuit.
  • said second top gate, third top gate and fourth top gate are located on the same side of said first straight line and Arranged in a second line, the second line being perpendicular to the first line.
  • one of the second top gate, the third top gate, and the fourth top gate is aligned with the first top gate.
  • the second top gate, the third top gate and the fourth top gate are respectively located on two sides of the first straight line and Arranged in a second line, the second line being perpendicular to the first line.
  • one of the second top gate, the third top gate, and the fourth top gate is aligned with the first top gate.
  • said second top gate, third top gate and fourth top gate are located on the same side of said first straight line and Arranged in a second line, the second line being perpendicular to the first line.
  • the shortest distances from the first top gate to the second top gate and the third top gate are equal.
  • said second top gate, third top gate and fourth top gate are located on the same side of said first straight line and Arranged in a second line, the second line being parallel to the first line.
  • the source region, the drain region, the first top gate, the second top gate, and the third top gate of the transistor are arranged in a block shape to facilitate the fabrication of a block type logic circuit.
  • said second top gate, third top gate and fourth top gate are located on the same side of said first straight line and Arranged in a second line, the second line being parallel to the first line.
  • one of the second top gate and the third top gate is aligned with the first top gate.
  • the second top gate, the third top gate and the fourth top gate are located on both sides of the first straight line and at least any two of the grids Arranged in a second line, the second line being parallel to the first line.
  • one of the second top gate and the third top gate is aligned with the first top gate.
  • the second top gate, the third top gate and the fourth top gate are located on two sides of the first straight line and any two of the grids Arranged in a second line, the second line being perpendicular to the first line.
  • one of the second top gate and the third top gate is aligned with the first top gate.
  • the first top gate, the second top gate, the third top gate and the fourth top gate respectively, wherein the first top gate is in the channel region, and the source region and the drain region are arranged in a first straight line a second top gate, a third top gate, and a fourth top gate are arranged in a second line, and the second line coincides with the first line.
  • the second top gate and the third top gate are on the same side of the source region and away from the drain region.
  • the second top gate and the third top gate are on the same side of the drain region and away from the source region.
  • the fourth top gate can be located at any position. Preferably, on the same side of the source region and away from the drain region, or on one side of the drain region and away from the source region.
  • the first top gate, the second top gate, the third top gate and the fourth top gate respectively, wherein the first top gate is in the channel region, and the source region and the drain region are arranged in a first straight line a second top gate, a third top gate, and a fourth top gate are arranged in a second line, and the second line coincides with the first line.
  • the second top gate and the third top gate are respectively located on one side of the source region and away from the drain region, and on one side of the drain region and away from the source region.
  • the fourth top gate can be located at any position. Preferably, on one side of the source region and away from the drain region, or on one side of the drain region and away from the source region.
  • the invention has a transistor with improved gate structure, and a top gate is introduced in a channel region of the transistor.
  • the function of the logic circuit can be realized, so that the logic circuit function that originally needs multiple transistors is only required.
  • One transistor can be completed, which greatly simplifies the circuit and improves the production efficiency of the logic circuit.
  • FIG. 1 is a schematic view showing a first embodiment of a transistor having a modified gate structure according to the present invention
  • FIG. 2 is a schematic view showing a second embodiment of a transistor having a modified gate structure according to the present invention
  • FIG. 3 is a schematic view showing a third embodiment of a transistor having a modified gate structure according to the present invention.
  • FIG. 4 is a schematic view showing a fourth embodiment of a transistor having a modified gate structure according to the present invention.
  • FIG. 5 is a schematic view showing a fifth embodiment of a transistor having a modified gate structure according to the present invention.
  • FIG. 6 is a schematic view showing a sixth embodiment of a transistor having a modified gate structure according to the present invention.
  • Figure 7 A graph of channel current as a function of a bottom gate voltage when a voltage of a second top gate is changed in each embodiment of the transistor of the improved gate structure of the present invention (if there is a bottom gate);
  • FIG. 8 is a schematic diagram showing relationship between an input voltage and an output voltage in each embodiment of a transistor having a modified gate structure according to the present invention.
  • FIG. 9 is a diagram showing the influence of a third top gate or a bottom gate on a Schottky barrier ⁇ of a channel region when a transistor having a modified gate structure includes a third top gate or a bottom gate according to the present invention.
  • FIG. 10 is a schematic view showing a seventh embodiment of a transistor with a modified gate structure according to the present invention.
  • a transistor with improved gate structure includes a substrate 1 and a dielectric layer 3 and a dielectric layer 3 on the substrate 1.
  • a source region 5, a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6 are disposed thereon, and two top gates are disposed, and a bottom gate coupled with the two top gates is disposed.
  • the first top gate is the first top gate 4a and the second top gate 4b
  • the substrate 1 also serves as a bottom gate
  • the first top gate 4a is located in the channel region 7, and is arranged in a first straight line with the source region 5 and the drain region 6, and the second top gate 4b Located on one side of the first straight line and aligned with the first top gate 4a. If there is no bottom gate, a top gate outside the channel region is added instead of the bottom gate regulation channel.
  • the substrate 1 is made of a glass whose single surface is a conductive layer, and the conductive layer is made of indium tin oxide (ITO) and the dielectric layer 3, and the dielectric layer is laminated.
  • ITO indium tin oxide
  • 3 silicon dioxide is used, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m;
  • the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 are all indium tin oxide ( ITO is produced in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 nm; the lateral distance of the source region 5 from the first top gate 4a (in the figure along the length of the channel region) is 10 ⁇ m .
  • the size of the gate in the channel region must be such that a stable potential can be obtained.
  • the conductive layer may not be disposed between the substrate 1 and the dielectric layer 3, and the second top gate 4b and the dielectric layer 3
  • the interface forms an equivalent capacitance, so that the second top gate 4b can effectively regulate the carrier concentration of the channel region 7.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS is 1.5V
  • the voltage V G2 of the second top gate 4b located outside the channel region 7 is changed to -0.5V, 0V, 0.5V, 1V
  • the relationship between the channel current I DS at both ends of the source and drain and the voltage V G1 of the bottom gate (which also serves as the substrate 1) is as shown in FIG. 7.
  • the thin film of the improved gate structure is used in this embodiment.
  • the threshold voltage V TH of the transistor is 1.1 V, 0.85 V, 0.45 V, -0.05 V, respectively, and the current switching ratio is also significantly changed.
  • V DS 1.5V
  • drain voltage Vss 0V
  • first top gate 4a Output voltage V G3 ⁇ 0.7V, which is recorded as output 1
  • a transistor with improved gate structure includes a substrate 1 and a dielectric layer 3 and a dielectric layer 3 on the substrate 1.
  • a source region 5, a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6 are provided, and two top gates are provided, and a bottom gate 2 coupled with the two top gates is provided.
  • the two top gates are a first top gate 4a and a second top gate 4b, respectively, the bottom gate 2 is between the substrate 1 and the dielectric layer 3, and the bottom gate 2 is distributed in a partial area on the substrate 1, the substrate 1
  • the upper opening is provided with a receiving groove corresponding to the position of the bottom gate 2, and the area of the bottom gate 2 is at least capable of controlling the channel region 7, the first top gate 4a is located in the channel region 7, and the source region 5 and the drain region 6
  • the three are arranged in a first straight line, and the second top gate 4b is located on one side of the first straight line and aligned with the first top gate 4a. If there is no bottom gate, then a trench outer top gate is added instead of the bottom gate control channel.
  • a conductive layer is provided between the substrate 1 and the dielectric layer 3, the substrate 1 is made of glass, and the conductive layer is made of indium tin oxide (ITO).
  • the dielectric layer 3 is made of silicon dioxide, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m; the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 They are all made of indium tin oxide (ITO), in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 nm; the lateral distance between the source region 5 and the first top gate 4a is 10 ⁇ m.
  • the conductive layer may not be disposed between the substrate 1 and the dielectric layer 3, and the second top gate 4b and the dielectric layer 3
  • the interface forms an equivalent capacitance, so that the second top gate 4b can effectively regulate the channel region 7
  • the carrier concentration is adjusted to adjust the threshold voltage, leakage current, current switching ratio and the like of the thin film transistor of the improved gate structure of the present invention.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS is 1.5V
  • the voltage V G2 of the second top gate 4b located outside the channel region 7 is changed to -0.5V, 0V, 0.5V, 1V
  • the relationship between the channel current I DS across the source and drain and the voltage V G1 of the bottom gate 2 is as shown in FIG. 7.
  • the threshold voltage of the thin film transistor of the gate structure is improved in this embodiment.
  • TH is 1.1 V, 0.85V, 0.45V, -0.05V, respectively, and the current switching ratio is also significantly changed.
  • the transistor is used as an inverter, the relationship between V G1 input and V G3 output is shown in Fig. 8.
  • this embodiment In addition to the first top gate 4a in the channel region 7, the remaining gates, including the bottom gate 2 and the second top gate 4b, have the function of regulating the channel region 7, by changing the bottom gate 2 and the second The voltage of the top gate 4b controls the output of the channel region 7 to obtain an ideal inverter input and output result.
  • the OR gate logic can be obtained.
  • a transistor having a modified gate structure includes a substrate 1 and a dielectric layer 3 and a dielectric layer 3 on the substrate 1.
  • a source region 5, a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6 are disposed thereon, and three top gates are provided, and a bottom gate coupled with the three top gates, First top gate 4a, a second top gate 4b and a third top gate 4c, wherein the first top gate 4a is in the channel region 7 and is arranged in a first straight line with the source region 5 and the drain region 6, the second top gate 4b Third top gate 4c is located on both sides of the first straight line, the first top gate 4a, the second top gate 4b and the third top gate 4c are arranged in a second straight line, and the second straight line is perpendicular to the first straight line, and the base 1 also serves as the bottom gate . If there is no bottom gate, then a trench outer top gate is added instead of the bottom gate control channel.
  • the substrate 1 is made of a glass whose single surface is a conductive layer, and the conductive layer is made of indium tin oxide (ITO) and the dielectric layer 3, and the dielectric layer is laminated.
  • ITO indium tin oxide
  • 3 silicon dioxide is used, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m;
  • the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 are all indium tin oxide ( ITO is produced in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 ⁇ m. Nm; the lateral distance between the source region 5 and the first top gate 4a is 10 ⁇ m.
  • the conductive layer may not be disposed between the substrate 1 and the dielectric layer 3, and the second top gate 4b and the dielectric layer 3
  • the interface forms an equivalent capacitance
  • the interface between the third top gate 4c and the dielectric layer 3 also forms an equivalent capacitance.
  • the two capacitors are coupled to each other, so that the second top gate 4b and the third top gate 4c can effectively regulate the channel region.
  • the carrier concentration is adjusted to adjust the threshold voltage, leakage current, current switching ratio and the like of the thin film transistor of the improved gate structure of the present invention.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS 1.5 V and the voltage of the third top gate 4 c is 0 V
  • the second top gate 4 b located outside the channel region 7 is changed.
  • the voltage V G2 is -0.5V, 0V, 0.5V, 1V
  • the relationship between the channel current I DS across the source and drain and the voltage V G1 of the bottom gate (which also serves as the base 1) is as shown in Fig. 7, in four cases.
  • the threshold voltage V TH of the thin film transistor with improved gate structure is 1.1 V , 0.85 V , 0.45 V , and -0.05 V , respectively , and the current switching ratio is also significantly changed.
  • the transistor when the transistor is used as an inverter
  • the relationship between the V G1 input and the V G3 output is shown in FIG. 8.
  • the remaining gates include a bottom gate, a second top gate 4b, and a third top gate 4c. Both have the function of regulating the channel region 7, and the output of the channel region 7 is controlled by changing the voltages of the bottom gate, the second top gate 4b and the third top gate 4c to obtain an ideal inverter input and output result.
  • the transistor in this embodiment has three top gates due to the third top gate 4c
  • the potential of the channel region, that is, the electron concentration, can be regulated, so that a single transistor can implement various logic functions.
  • V G4 0V
  • source and drain voltage V DS 1.5V
  • drain voltage V SS 0V
  • the output voltage of the first top gate 4a V G3 ⁇ 1V , that is, the output is 1
  • the output voltage of the first top gate 4a is V.
  • FIG. 9 Effect of the third top gate Schottky barrier [Phi] 4c the channel region shown in Figure 9, in FIG. 9 (A) a top-gate voltage of the third portion ⁇ 1 is relatively negatively biased, in FIG. 9
  • the voltage of the third top gate in the portion (B) is 0 with respect to ⁇ 0
  • the voltage of the third top gate in the portion (C) of Fig. 9 is positively biased with respect to ⁇ 2 .
  • a transistor with improved gate structure includes a substrate 1 and a dielectric layer 3 and a dielectric layer 3 on the substrate 1.
  • a source region 5, a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6 are provided, and three top gates and a bottom gate 2 coupled with the three top gates are further disposed.
  • the three top gates are a first top gate 4a, a second top gate 4b and a third top gate 4c, respectively, wherein the first top gate 4a is in the channel region 7 and is connected to the source region 5 and the drain region 6
  • the three are arranged in a first straight line, and the second top gate 4b and the third top gate 4c are located on both sides of the first straight line, the first top gate 4a, the second top gate 4b and the third top gate 4c Arranged into a second straight line, and the second straight line is perpendicular to the first straight line, the bottom gate 2 is located between the substrate 1 and the dielectric layer 3, and the bottom gate 2 is distributed in a partial area on the substrate 1, and the bottom gate is opened on the substrate 1 2
  • the corresponding accommodating groove is located, and the area of the bottom gate 2 can control at least the channel region 7. If there is no bottom gate, then a trench outer top gate is added instead of the bottom gate control channel.
  • a conductive layer is disposed between the substrate 1 and the dielectric layer 3, the substrate 1 is made of glass, and the conductive layer is made of indium tin oxide (ITO).
  • ITO indium tin oxide
  • 3 silicon dioxide is used, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m; the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 are all indium tin oxide ( ITO is produced in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 nm; the lateral distance between the source region 5 and the first top gate 4a is 10 ⁇ m.
  • the conductive layer may not be disposed between the substrate 1 and the dielectric layer 3, and the second top gate 4b and the dielectric layer 3
  • the equivalent capacitance formed by the interface, the interface between the third top gate 4c and the dielectric layer 3 also forms an equivalent capacitance, and the two capacitors are coupled to each other, so that the second top gate 4b and the third top gate 4c can effectively regulate the channel region.
  • the carrier concentration is adjusted to adjust the threshold voltage, leakage current, current switching ratio and the like of the thin film transistor of the improved gate structure of the present invention.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS 1.5 V and the voltage of the third top gate 4 c is 0 V
  • the second top gate 4 b located outside the channel region 7 is changed.
  • the voltage V G2 is -0.5V, 0V, 0.5V, 1V
  • the relationship between the channel current I DS across the source and drain and the voltage V G1 of the bottom gate 2 is as shown in FIG. 7.
  • the threshold voltage V TH of the thin film transistor with improved gate structure is 1.1 V, 0.85 V, 0.45 V, -0.05 V, respectively, and the current switching ratio is also significantly changed.
  • the V G1 input and the V G3 output are used.
  • the relationship is shown in FIG. 8. Therefore, in this embodiment, except for the first top gate 4a in the channel region 7, the remaining gates, including the bottom gate 2, the second top gate 4b, and the third top gate 4c, are controllable.
  • the function of the channel region 7 controls the output of the channel region 7 by changing the voltages of the bottom gate 2, the second top gate 4b, and the third top gate 4c to obtain an ideal inverter input and output result.
  • the transistor in this embodiment has three top gates due to the third top gate 4c
  • the potential of the channel region, that is, the electron concentration, can be regulated, so that a single transistor can implement various logic functions.
  • the output voltage V G3 ⁇ 1V of the first top gate 4a is recorded as an output of 0 (the same as the input and output states of V G1 , V G2 ).
  • a transistor having a modified gate structure includes a substrate 1 and a dielectric layer 3 and a dielectric layer 3 on the substrate 1.
  • a source region 5, a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6 are disposed thereon, and three top gates are provided, and a bottom gate coupled with the three top gates, First top gate 4a, a second top gate 4b and a third top gate 4c, wherein the first top gate 4a is in the channel region 7 and is aligned with the source region 5 and the drain region 6 in a first straight line, the first top gate 4a Second top gate 4b and the third top gate 4c are arranged in a second straight line, and the second straight line coincides with the first straight line, and the second top gate 4b and the third top gate 4c are on the same side of the source region 5 and away from the drain region 6, Substrate 1 Also serves as the bottom grid. If there is no bottom gate, then a trench outer top gate is added instead of the bottom gate control channel.
  • the substrate 1 is made of a glass whose single surface is a conductive layer, and the conductive layer is made of indium tin oxide (ITO) and the dielectric layer 3, and the dielectric layer is laminated.
  • ITO indium tin oxide
  • 3 silicon dioxide is used, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m;
  • the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 are all indium tin oxide ( ITO is produced in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 nm; the lateral distance between the source region 5 and the first top gate 4a is 10 ⁇ m.
  • the conductive layer may not be disposed between the substrate 1 and the dielectric layer 3, and the second top gate 4b and the dielectric layer 3
  • the interface forms an equivalent capacitance
  • the interface between the third top gate 4c and the dielectric layer 3 also forms an equivalent capacitance.
  • the two capacitors are coupled to each other, so that the second top gate 4b and the third top gate 4c can effectively regulate the channel region.
  • the carrier concentration is adjusted to adjust the threshold voltage, leakage current, current switching ratio and the like of the thin film transistor of the improved gate structure of the present invention.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS 1.5 V and the voltage of the third top gate 4 c is 0 V
  • the second top gate 4 b located outside the channel region 7 is changed.
  • the voltage V G2 is -0.5V , 0V , 0.5V , 1V
  • the relationship between the channel current I DS across the source and drain and the voltage V G1 of the bottom gate (which also serves as the base 1) is shown in Figure 7.
  • the threshold voltage V TH of the thin film transistor with improved gate structure is 1.1 V, 0.85 V, 0.45 V, and -0.05 V, respectively, and the current switching ratio is also significantly changed.
  • V G1 When the transistor is used as an inverter, V G1
  • the remaining gates include the bottom gate, the second top gate 4b, and the third top gate 4c. Both have the function of regulating the channel region 7, and the output of the channel region 7 is controlled by changing the voltages of the bottom gate, the second top gate 4b and the third top gate 4c to obtain an ideal inverter input and output result.
  • the transistor in this embodiment has three top gates due to the third top gate 4c
  • the potential of the channel region, that is, the electron concentration, can be regulated, so that a single transistor can implement various logic functions.
  • the output voltage V G3 ⁇ 1V of the first top gate 4a is recorded as an output of 0 (the same as the input and output states of V G1 , V G2 ).
  • V G3 ⁇ 1V can be obtained.
  • the AND gate logic can be implemented as shown in Table 4.
  • a transistor with a modified gate structure includes a substrate 1 and a dielectric layer 3 and a dielectric layer 3 on the substrate 1.
  • a source region 5, a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6 are provided, and three top gates and a bottom gate 2 coupled with the three top gates are further disposed.
  • the three top gates are a first top gate 4a, a second top gate 4b and a third top gate 4c, respectively, wherein the first top gate 4a is in the channel region 7 and is connected to the source region 5 and the drain region 6
  • the three are arranged in a first straight line
  • the first top gate 4a, the second top gate 4b and the third top gate 4c are arranged in a second straight line
  • the second straight line coincides with the first straight line
  • the top grid 4c is in the source area
  • the bottom gate 2 is located between the substrate 1 and the dielectric layer 3, the substrate 1 is provided with a receiving groove corresponding to the position of the bottom gate 2, and the bottom gate 2 is distributed on the substrate 1
  • the upper region is upper, and the area of the bottom gate 2 is at least capable of controlling the channel region 7.
  • a conductive layer is disposed between the substrate 1 and the dielectric layer 3, the substrate 1 is made of glass, and the conductive layer is made of indium tin oxide (ITO).
  • ITO indium tin oxide
  • 3 silicon dioxide is used, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m; the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 are all indium tin oxide ( ITO is produced in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 nm; the lateral distance between the source region 5 and the first top gate 4a is 10 ⁇ m.
  • the conductive layer may not be disposed between the substrate 1 and the dielectric layer 3, and the second top gate 4b and the dielectric layer 3
  • the interface forms an equivalent capacitance
  • the interface between the third top gate 4c and the dielectric layer 3 also forms an equivalent capacitance.
  • the two capacitors are coupled to each other, so that the second top gate 4b and the third top gate 4c can effectively regulate the channel region.
  • the carrier concentration is adjusted to adjust the threshold voltage, leakage current, current switching ratio and the like of the thin film transistor of the improved gate structure of the present invention. If there is no bottom gate, then a trench outer top gate is added instead of the bottom gate control channel.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS 1.5 V and the voltage of the third top gate 4 c is 0 V
  • the second top gate 4 b located outside the channel region 7 is changed.
  • the voltage V G2 is -0.5V, 0V, 0.5V, 1V
  • the relationship between the channel current I DS across the source and drain and the voltage V G1 of the bottom gate 2 is as shown in FIG. 7.
  • the threshold voltage V TH of the thin film transistor with improved gate structure is 1.1 V, 0.85 V, 0.45 V, -0.05 V, respectively, and the current switching ratio is also significantly changed.
  • the V G1 input and the V G3 output are used.
  • the relationship is shown in FIG. 8. Therefore, in this embodiment, except for the first top gate 4a in the channel region 7, the remaining gates, including the bottom gate 2, the second top gate 4b, and the third top gate 4c, are controllable.
  • the function of the channel region 7 controls the output of the channel region 7 by changing the voltages of the bottom gate 2, the second top gate 4b, and the third top gate 4c to obtain an ideal inverter input and output result.
  • the transistor in this embodiment has three top gates due to the third top gate 4c
  • the potential of the channel region, that is, the electron concentration, can be regulated, so that a single transistor can implement various logic functions.
  • the output voltage V G3 ⁇ 1V of the first top gate 4a is recorded as an output of 0 (the same as the input and output states of V G1 , V G2 ).
  • the AND gate logic can be implemented as shown in Table 4. Effect of the third top gate Schottky barrier [Phi] 4c the channel region shown in Figure 9, in FIG. 9 (A) a top-gate voltage of the third portion ⁇ 1 is relatively negatively biased, in FIG. 9 The voltage of the third top gate in the portion (B) is 0 with respect to ⁇ 0 , and the voltage of the third top gate in the portion (C) of Fig. 9 is positively biased with respect to ⁇ 2 .
  • a transistor having a modified gate structure includes a substrate 1 and a dielectric layer 3 and a dielectric layer 3 on the substrate 1.
  • a source region 5, a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6 are provided, and three top gates and a bottom gate 2 coupled with the three top gates are further disposed.
  • the three top gates are a first top gate 4a, a second top gate 4b and a third top gate 4c, respectively, wherein the first top gate 4a is in the channel region 7 and is connected to the source region 5 and the drain region 6
  • the three are arranged in a first straight line, and the second top gate 4b and the third top gate 4c are located on the same side of the first straight line.
  • the bottom gate 2 is located between the substrate 1 and the dielectric layer 3, and the bottom gate 2 is distributed in a partial region on the substrate 1, the substrate 1
  • the upper opening has a receiving groove corresponding to the position of the bottom gate 2, and the area of the bottom gate 2 can control at least the channel region 7.
  • a conductive layer is disposed between the substrate 1 and the dielectric layer 3, the substrate 1 is made of glass, and the conductive layer is made of indium tin oxide (ITO).
  • ITO indium tin oxide
  • 3 silicon dioxide is used, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m; the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 are all indium tin oxide ( ITO is produced in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 nm; the lateral distance between the source region 5 and the first top gate 4a is 10 ⁇ m.
  • the conductive layer may not be disposed between the substrate 1 and the dielectric layer 3, and the second top gate 4b and the dielectric layer 3
  • the equivalent capacitance formed by the interface, the interface between the third top gate 4c and the dielectric layer 3 also forms an equivalent capacitance, and the two capacitors are coupled to each other, so that the second top gate 4b and the third top gate 4c can effectively regulate the channel region.
  • the carrier concentration is adjusted to adjust the threshold voltage, leakage current, current switching ratio and the like of the thin film transistor of the improved gate structure of the present invention. If there is no bottom gate, then a trench outer top gate is added instead of the bottom gate control channel.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS 1.5 V and the voltage of the third top gate 4 c is 0 V
  • the second top gate 4 b located outside the channel region 7 is changed.
  • the voltage V G2 is -0.5V, 0V, 0.5V, 1V
  • the relationship between the channel current I DS across the source and drain and the voltage V G1 of the bottom gate 2 is as shown in FIG. 7.
  • the threshold voltage V TH of the thin film transistor with improved gate structure is 1.1 V, 0.85 V, 0.45 V, -0.05 V, respectively, and the current switching ratio is also significantly changed.
  • the V G1 input and the V G3 output are used.
  • the relationship is shown in FIG. 8. Therefore, in this embodiment, except for the first top gate 4a in the channel region 7, the remaining gates, including the bottom gate 2, the second top gate 4b, and the third top gate 4c, are controllable.
  • the function of the channel region 7 controls the output of the channel region 7 by changing the voltages of the bottom gate 2, the second top gate 4b, and the third top gate 4c to obtain an ideal inverter input and output result.
  • the transistor in this embodiment has three top gates due to the third top gate 4c
  • the potential of the channel region, that is, the electron concentration, can be regulated, so that a single transistor can implement various logic functions.
  • the output voltage V G3 ⁇ 1V of the first top gate 4a is recorded as an output of 0 (the same as the input and output states of V G1 , V G2 ).
  • a transistor having a modified gate structure comprising a substrate 1 and a dielectric layer 3 on the substrate 1, and a source region 5 on the dielectric layer 3 a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6, and a top gate of four control channels, respectively a first top gate 4a, a second top gate 4b, and a first Triple top gate 4c And a fourth top gate, wherein the first top gate 4a is in the channel region 7 and is arranged in a first straight line with the source region 5 and the drain region 6, the second top gate 4b and the third top gate 4c And the fourth top gate is located on the same side of the first straight line.
  • the bottom gate 2 can be disposed between the substrate 1 and the dielectric layer 3, and the bottom gate 2 is distributed on the substrate 1 In the upper portion, the substrate 1 is provided with a receiving groove corresponding to the position of the bottom gate 2, and the area of the bottom gate 2 can control at least the channel region 7. Substrate 1 and dielectric layer 3 in this embodiment There may be no conductive layer between them.
  • a conductive layer is disposed between the substrate 1 and the dielectric layer 3, the substrate 1 is made of glass, and the conductive layer is made of indium tin oxide (ITO).
  • ITO indium tin oxide
  • 3 silicon dioxide is used, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m; the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 are all indium tin oxide ( ITO is produced in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 nm; the lateral distance between the source region 5 and the first top gate 4a is 10 ⁇ m.
  • the conductive layer may not be disposed between the substrate 1 and the dielectric layer 3, and the second top gate 4b and the dielectric layer 3
  • the equivalent capacitance formed by the interface, the interface between the third top gate 4c and the dielectric layer 3 also forms an equivalent capacitance, and the two capacitors are coupled to each other, so that the second top gate 4b and the third top gate 4c can effectively regulate the channel region.
  • the carrier concentration is adjusted to adjust the threshold voltage, leakage current, current switching ratio and the like of the thin film transistor of the improved gate structure of the present invention.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS 1.5 V and the voltage of the third top gate 4 c is 0 V
  • the second top gate 4 b located outside the channel region 7 is changed.
  • the voltage V G2 is -0.5V, 0V, 0.5V, 1V
  • the relationship between the channel current I DS across the source and drain and the voltage V G1 of the fourth top gate is as shown in Fig. 7.
  • this implementation The threshold voltage V TH of the thin film transistor with improved gate structure is 1.1 V, 0.85 V, 0.45 V, -0.05 V, respectively, and the current switching ratio is also significantly changed.
  • V G1 input and V G3 The output relationship is shown in FIG. 8. Therefore, in this embodiment, except for the first top gate 4a in the channel region 7, the remaining gates, including the fourth top gate, the second top gate 4b, and the third top gate 4c, have The function of the channel region 7 can be regulated, and the output of the channel region 7 is controlled by the voltages of the fourth top gate, the second top gate 4b, and the third top gate 4c to obtain an ideal inverter input and output result.
  • the transistor in this embodiment has three top gates due to the third top gate 4c
  • the potential of the channel region, that is, the electron concentration, can be regulated, so that a single transistor can implement various logic functions.
  • the output voltage V G3 ⁇ 1V of the first top gate 4a is recorded as an output of 0 (the same as the input and output states of V G1 , V G2 ).
  • a transistor having a modified gate structure comprising a substrate 1 and a dielectric layer 3 on the substrate 1, and a source region 5 on the dielectric layer 3 a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6, and a top gate of four control channels, respectively a first top gate 4a, a second top gate 4b, and a first Triple top gate 4c And a fourth top gate, wherein the first top gate 4a is in the channel region 7 and is aligned with the source region 5 and the drain region 6 in a first straight line, the first top gate 4a, the second top gate 4b, and the first Triple top gate 4c
  • the fourth top grid is arranged in a second straight line, and the second straight line coincides with the first straight line.
  • a conductive layer is disposed between the substrate 1 and the dielectric layer 3, the substrate 1 is made of glass, and the conductive layer is made of indium tin oxide (ITO).
  • ITO indium tin oxide
  • 3 silicon dioxide is used, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m; the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 are all indium tin oxide ( ITO is produced in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the bottom gate 2 can be disposed between the substrate 1 and the dielectric layer 3, and the bottom gate 2 is distributed on the substrate 1 In the upper portion, the substrate 1 is provided with a receiving groove corresponding to the position of the bottom gate 2, and the area of the bottom gate 2 can control at least the channel region 7. Substrate 1 and dielectric layer 3 in this embodiment There may be no conductive layer between them.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 nm; the lateral distance between the source region 5 and the first top gate 4a is 10 ⁇ m.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS 1.5 V and the voltage of the third top gate 4 c is 0 V
  • the second top gate 4 b located outside the channel region 7 is changed.
  • the voltage V G2 is -0.5V, 0V, 0.5V, 1V
  • the relationship between the channel current I DS across the source and drain and the voltage V G1 of the fourth top gate is as shown in Fig. 7.
  • this implementation The threshold voltage V TH of the thin film transistor with improved gate structure is 1.1 V, 0.85 V, 0.45 V, -0.05 V, respectively, and the current switching ratio is also significantly changed.
  • V G1 input and V G3 The output relationship is shown in FIG. 8. Therefore, in this embodiment, except for the first top gate 4a in the channel region 7, the remaining gates, including the fourth top gate, the second top gate 4b, and the third top gate 4c, have The function of the channel region 7 can be regulated, and the output of the channel region 7 is controlled by the voltages of the fourth top gate, the second top gate 4b, and the third top gate 4c to obtain an ideal inverter input and output result.
  • the transistor in this embodiment has three top gates due to the third top gate 4c
  • the potential of the channel region, that is, the electron concentration, can be regulated, so that a single transistor can implement various logic functions.
  • the output voltage V G3 ⁇ 1V of the first top gate 4a is recorded as an output of 0 (the same as the input and output states of V G1 , V G2 ).
  • a transistor having a modified gate structure comprising a substrate 1 and a dielectric layer 3 on the substrate 1, and a source region 5 on the dielectric layer 3 a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6, and a top gate of four control channels, respectively a first top gate 4a, a second top gate 4b, and a first Triple top gate 4c And a fourth top gate, wherein the first top gate 4a is in the channel region 7 and is aligned with the source region 5 and the drain region 6 in a first straight line, the first top gate 4a, the second top gate 4b, and the first Triple top gate 4c
  • the fourth top grid is arranged in a second line, and the second line is perpendicular to the first line.
  • a conductive layer is disposed between the substrate 1 and the dielectric layer 3, the substrate 1 is made of glass, and the conductive layer is made of indium tin oxide (ITO).
  • ITO indium tin oxide
  • 3 silicon dioxide is used, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m; the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 are all indium tin oxide ( ITO is produced in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the bottom gate 2 can be disposed between the substrate 1 and the dielectric layer 3, and the bottom gate 2 is distributed on the substrate 1 In the upper portion, the substrate 1 is provided with a receiving groove corresponding to the position of the bottom gate 2, and the area of the bottom gate 2 can control at least the channel region 7. Substrate 1 and dielectric layer 3 in this embodiment There may be no conductive layer between them.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 nm; the lateral distance between the source region 5 and the first top gate 4a is 10 ⁇ m.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS 1.5 V and the voltage of the third top gate 4 c is 0 V
  • the second top gate 4 b located outside the channel region 7 is changed.
  • the voltage V G2 is -0.5V, 0V, 0.5V, 1V
  • the relationship between the channel current I DS across the source and drain and the voltage V G1 of the fourth top gate is as shown in Fig. 7.
  • this implementation The threshold voltage V TH of the thin film transistor with improved gate structure is 1.1 V, 0.85 V, 0.45 V, -0.05 V, respectively, and the current switching ratio is also significantly changed.
  • V G1 input and V G3 The output relationship is shown in FIG. 8. Therefore, in this embodiment, except for the first top gate 4a in the channel region 7, the remaining gates, including the fourth top gate, the second top gate 4b, and the third top gate 4c, have The function of the channel region 7 can be regulated, and the output of the channel region 7 is controlled by the voltages of the fourth top gate, the second top gate 4b, and the third top gate 4c to obtain an ideal inverter input and output result.
  • the transistor in this embodiment has three top gates due to the third top gate 4c
  • the potential of the channel region, that is, the electron concentration, can be regulated, so that a single transistor can implement various logic functions.
  • the output voltage V G3 ⁇ 1V of the first top gate 4a is recorded as an output of 0 (the same as the input and output states of V G1 , V G2 ).
  • a transistor having a modified gate structure comprising a substrate 1 and a dielectric layer 3 on the substrate 1, and a source region 5 on the dielectric layer 3 a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6 are further provided with two top gates and a bottom gate coupled with the two top gates, the two top gates being respectively First top gate 4a and second top gate 4b, the substrate 1 also serves as the bottom gate, and the first top gate 4a is located in the channel region 7, and is arranged in a first straight line with the source region 5 and the drain region 6, and the second top gate 4b and the first top gate 4a Arranged into a second straight line, and the second straight line coincides with the first straight line.
  • the substrate 1 is made of a glass whose single surface is a conductive layer, and the conductive layer is made of indium tin oxide (ITO) and the dielectric layer 3, and the dielectric layer is laminated.
  • ITO indium tin oxide
  • 3 silicon dioxide is used, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m;
  • the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 are all indium tin oxide ( ITO is produced in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 nm; the lateral distance of the source region 5 from the first top gate 4a (in the figure along the length of the channel region) is 10 ⁇ m .
  • the size of the gate in the channel region must be such that a stable potential can be obtained.
  • the conductive layer may not be disposed between the substrate 1 and the dielectric layer 3, and the second top gate 4b and the dielectric layer 3
  • the interface forms an equivalent capacitance, so that the second top gate 4b can effectively regulate the carrier concentration of the channel region 7.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS is 1.5V
  • the voltage V G2 of the second top gate 4b located outside the channel region 7 is changed to -0.5V, 0V, 0.5V, 1V
  • the relationship between the channel current I DS at both ends of the source and drain and the voltage V G1 of the bottom gate (which also serves as the substrate 1) is as shown in FIG. 7.
  • the thin film of the improved gate structure is used in this embodiment.
  • the threshold voltage V TH of the transistor is 1.1 V, 0.85 V, 0.45 V, -0.05 V, respectively, and the current switching ratio is also significantly changed.
  • the OR gate logic can be obtained.
  • a transistor having a modified gate structure comprising a substrate 1 and a dielectric layer 3 on the substrate 1, and a source region 5 on the dielectric layer 3 a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6, further provided with two top gates, and a bottom gate 2 coupled with the two top gates, the two top gates respectively Is the first top gate 4a And the second top gate 4b, the bottom gate 2 is located between the substrate 1 and the dielectric layer 3, the bottom gate 2 is distributed in a partial area on the substrate 1, and the substrate 1 is provided with a receiving groove corresponding to the position of the bottom gate 2,
  • the area of the bottom gate 2 can control at least the channel region 7, the first top gate 4a is located in the channel region 7, and is arranged in a first straight line with the source region 5 and the drain region 6, and the second top gate 4b and the second a top gate 4a Arranged into a second straight line, and the second straight line coincides with the first straight line.
  • a conductive layer is disposed between the substrate 1 and the dielectric layer 3, the substrate 1 is made of glass, and the conductive layer is made of indium tin oxide (ITO).
  • ITO indium tin oxide
  • 3 silicon dioxide is used, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m; the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 are all indium tin oxide ( ITO is produced in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 nm; the lateral distance between the source region 5 and the first top gate 4a is 10 ⁇ m.
  • the conductive layer may not be disposed between the substrate 1 and the dielectric layer 3, and the second top gate 4b and the dielectric layer 3
  • the interface forms an equivalent capacitance, so that the second top gate 4b can effectively regulate the channel region 7
  • the carrier concentration is adjusted to adjust the threshold voltage, leakage current, current switching ratio and the like of the thin film transistor of the improved gate structure of the present invention.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple. If there is no bottom gate, then a trench outer top gate is added instead of the bottom gate control channel.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS is 1.5V
  • the voltage V G2 of the second top gate 4b located outside the channel region 7 is changed to -0.5V, 0V, 0.5V, 1V
  • the relationship between the channel current I DS at both ends of the source and drain and the voltage V G1 of the bottom gate 2 is as shown in FIG. 7.
  • the threshold voltage V of the thin film transistor of the gate structure is improved in this embodiment.
  • TH is 1.1 V, 0.85V, 0.45V, -0.05V, respectively, and the current switching ratio is also significantly changed.
  • the transistor is used as an inverter, the relationship between V G1 input and V G3 output is shown in Fig. 8.
  • this embodiment In addition to the first top gate 4a in the channel region 7, the remaining gates, including the bottom gate 2 and the second top gate 4b, have the function of regulating the channel region 7, by changing the bottom gate 2 and the second The voltage of the top gate 4b controls the output of the channel region 7 to obtain an ideal inverter input and output result.
  • the OR gate logic can be obtained.
  • a transistor having a modified gate structure comprising a substrate 1 and a dielectric layer 3 on the substrate 1, and a source region 5 on the dielectric layer 3 a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6 are further provided with three top gates and a bottom gate coupled with the three top gates, and the three top gates are respectively a top gate 4a and a second top gate 4b and a third top gate 4c, wherein the first top gate 4a is in the channel region 7 and is arranged in a first straight line with the source region 5 and the drain region 6, the second top gate 4b and the third top gate 4c On the same side of the first straight line, the first top gate 4a, the second top gate 4b and the third top gate 4c are arranged in a second straight line, and the second straight line is perpendicular to the first straight line, and the substrate 1 also serves as a bottom gate. If there is no bottom gate, then a trench outer top gate is added instead of the bottom gate control channel.
  • the substrate 1 is made of a glass whose single surface is a conductive layer, and the conductive layer is made of indium tin oxide (ITO) and the dielectric layer 3, and the dielectric layer is laminated.
  • ITO indium tin oxide
  • 3 silicon dioxide is used, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m;
  • the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 are all indium tin oxide ( ITO is produced in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 nm; the lateral distance between the source region 5 and the first top gate 4a is 10 ⁇ m.
  • the conductive layer may not be disposed between the substrate 1 and the dielectric layer 3, and the second top gate 4b and the dielectric layer 3
  • the interface forms an equivalent capacitance
  • the interface between the third top gate 4c and the dielectric layer 3 also forms an equivalent capacitance.
  • the two capacitors are coupled to each other, so that the second top gate 4b and the third top gate 4c can effectively regulate the channel region.
  • the carrier concentration is adjusted to adjust the threshold voltage, leakage current, current switching ratio and the like of the thin film transistor of the improved gate structure of the present invention.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS 1.5 V and the voltage of the third top gate 4 c is 0 V
  • the second top gate 4 b located outside the channel region 7 is changed.
  • the voltage V G2 is -0.5V , 0V , 0.5V , 1V
  • the relationship between the channel current I DS across the source and drain and the voltage V G1 of the bottom gate (which also serves as the base 1) is shown in Figure 7.
  • the threshold voltage V TH of the thin film transistor with improved gate structure is 1.1 V , 0.85 V , 0.45 V , and -0.05 V , respectively , and the current switching ratio is also significantly changed.
  • the transistor when the transistor is used as an inverter
  • the relationship between the V G1 input and the V G3 output is shown in FIG. 8.
  • the remaining gates include a bottom gate, a second top gate 4b, and a third top gate 4c. Both have the function of regulating the channel region 7, and the output of the channel region 7 is controlled by changing the voltages of the bottom gate, the second top gate 4b and the third top gate 4c to obtain an ideal inverter input and output result.
  • the transistor in this embodiment has three top gates due to the third top gate 4c
  • the potential of the channel region, that is, the electron concentration, can be regulated, so that a single transistor can implement various logic functions.
  • the output voltage V G3 ⁇ 1V of the first top gate 4a is recorded as an output of 0 (the same as the input and output states of V G1 , V G2 ).
  • the AND gate logic can be implemented as shown in Table 4.
  • a transistor having a modified gate structure comprising a substrate 1 and a dielectric layer 3 on the substrate 1, and a source region 5 on the dielectric layer 3 a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6 are further provided with three top gates and a bottom gate 2 coupled with the three top gates, and the three top gates are respectively First top gate 4a a second top gate 4b and a third top gate 4c, wherein the first top gate 4a is in the channel region 7 and is aligned with the source region 5 and the drain region 6 in a first straight line, the second top gate 4b and Third top gate 4c Located on the same side of the first straight line, the first top gate 4a, the second top gate 4b, and the third top gate 4c are arranged in a second line, and the second line is perpendicular to the first line, and the bottom gate 2 is located on the substrate 1 and Dielectric layer 3 Between the bottom gate 2 is distributed in a partial area on the substrate 1, the substrate 1 is provided with a receiving groove
  • a conductive layer is disposed between the substrate 1 and the dielectric layer 3, the substrate 1 is made of glass, and the conductive layer is made of indium tin oxide (ITO).
  • ITO indium tin oxide
  • 3 silicon dioxide is used, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m; the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 are all indium tin oxide ( ITO is produced in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 nm; the lateral distance between the source region 5 and the first top gate 4a is 10 ⁇ m.
  • the conductive layer may not be disposed between the substrate 1 and the dielectric layer 3, and the second top gate 4b and the dielectric layer 3
  • the equivalent capacitance formed by the interface, the interface between the third top gate 4c and the dielectric layer 3 also forms an equivalent capacitance, and the two capacitors are coupled to each other, so that the second top gate 4b and the third top gate 4c can effectively regulate the channel region.
  • the carrier concentration is adjusted to adjust the threshold voltage, leakage current, current switching ratio and the like of the thin film transistor of the improved gate structure of the present invention.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS 1.5 V and the voltage of the third top gate 4 c is 0 V
  • the second top gate 4 b located outside the channel region 7 is changed.
  • the voltage V G2 is -0.5V, 0V, 0.5V, 1V
  • the relationship between the channel current I DS across the source and drain and the voltage V G1 of the bottom gate 2 is as shown in FIG. 7.
  • the threshold voltage V TH of the thin film transistor with improved gate structure is 1.1 V, 0.85 V, 0.45 V, -0.05 V, respectively, and the current switching ratio is also significantly changed.
  • the V G1 input and the V G3 output are used.
  • the relationship is shown in FIG. 8. Therefore, in this embodiment, except for the first top gate 4a in the channel region 7, the remaining gates, including the bottom gate 2, the second top gate 4b, and the third top gate 4c, are controllable.
  • the function of the channel region 7 controls the output of the channel region 7 by changing the voltages of the bottom gate 2, the second top gate 4b, and the third top gate 4c to obtain an ideal inverter input and output result.
  • the transistor in this embodiment has three top gates due to the third top gate 4c
  • the potential of the channel region, that is, the electron concentration, can be regulated, so that a single transistor can implement various logic functions.
  • V G4 0V
  • source and drain voltage V DS 1.5V
  • drain voltage V SS 0V
  • the output voltage of the first top gate 4a V G3 ⁇ 1V , that is, the output is 1
  • the output voltage of the first top gate 4a is V.
  • the OR gate logic can then be obtained, as shown in Table 3, when the voltage of the bottom gate 2 is V.
  • a transistor having a modified gate structure includes a substrate 1 and a dielectric layer 3 and a dielectric layer 3 on the substrate 1.
  • a source region 5, a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6 are disposed thereon, and three top gates are provided, and a bottom gate coupled with the three top gates, First top gate 4a, a second top gate 4b and a third top gate 4c, wherein the first top gate 4a is in the channel region 7 and is aligned with the source region 5 and the drain region 6 in a first straight line, the first top gate 4a Second top gate 4b and the third top gate 4c are arranged in a second straight line, and the second straight line coincides with the first straight line, and one of the second top gate 4b and the third top gate 4c is on one side of the source region 5 and away from the drain region 6 Another in the drain area One side of 6 and away from the source area 5, the base 1 also serves as the bottom grid. If there is no bottom gate, then
  • the substrate 1 is made of a glass whose single surface is a conductive layer, and the conductive layer is made of indium tin oxide (ITO) and the dielectric layer 3, and the dielectric layer is laminated.
  • ITO indium tin oxide
  • 3 silicon dioxide is used, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m;
  • the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 are all indium tin oxide ( ITO is produced in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 nm; the lateral distance between the source region 5 and the first top gate 4a is 10 ⁇ m.
  • the conductive layer may not be disposed between the substrate 1 and the dielectric layer 3, and the second top gate 4b and the dielectric layer 3
  • the interface forms an equivalent capacitance
  • the interface between the third top gate 4c and the dielectric layer 3 also forms an equivalent capacitance.
  • the two capacitors are coupled to each other, so that the second top gate 4b and the third top gate 4c can effectively regulate the channel region.
  • the carrier concentration is adjusted to adjust the threshold voltage, leakage current, current switching ratio and the like of the thin film transistor of the improved gate structure of the present invention.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS 1.5 V and the voltage of the third top gate 4 c is 0 V
  • the second top gate 4 b located outside the channel region 7 is changed.
  • the voltage V G2 is -0.5V , 0V , 0.5V , 1V
  • the relationship between the channel current I DS across the source and drain and the voltage V G1 of the bottom gate (which also serves as the base 1) is shown in Figure 7.
  • the threshold voltage V TH of the thin film transistor with improved gate structure is 1.1 V, 0.85 V, 0.45 V, and -0.05 V, respectively, and the current switching ratio is also significantly changed.
  • V G1 When the transistor is used as an inverter, V G1
  • the remaining gates include the bottom gate, the second top gate 4b, and the third top gate 4c. Both have the function of regulating the channel region 7, and the output of the channel region 7 is controlled by changing the voltages of the bottom gate, the second top gate 4b and the third top gate 4c to obtain an ideal inverter input and output result.
  • the transistor in this embodiment has three top gates due to the third top gate 4c
  • the potential of the channel region, that is, the electron concentration, can be regulated, so that a single transistor can implement various logic functions.
  • the output voltage V G3 ⁇ 1V of the first top gate 4a is recorded as an output of 0 (the same as the input and output states of V G1 , V G2 ).
  • V G3 ⁇ 1V can be obtained.
  • the AND gate logic can be implemented as shown in Table 4.
  • a transistor with a modified gate structure includes a substrate 1 and a dielectric layer 3 and a dielectric layer 3 on the substrate 1.
  • a source region 5, a drain region 6 and a channel region 7 connected between the source region 5 and the drain region 6 are provided, and three top gates and a bottom gate 2 coupled with the three top gates are further disposed.
  • the three top gates are a first top gate 4a, a second top gate 4b and a third top gate 4c, respectively, wherein the first top gate 4a is in the channel region 7 and is connected to the source region 5 and the drain region 6
  • the three are arranged in a first straight line
  • the first top gate 4a, the second top gate 4b and the third top gate 4c are arranged in a second straight line
  • the second straight line coincides with the first straight line
  • One of them is on one side of the source region 5, and is away from the drain region 6, and the other is on one side of the drain region 6, and away from the source region 5, and the substrate 1 also serves as a bottom gate.
  • the bottom gate 2 is located between the substrate 1 and the dielectric layer 3.
  • the substrate 1 is provided with a receiving groove corresponding to the position of the bottom gate 2, and the bottom gate 2 A partial area distributed on the substrate 1, and the area of the bottom gate 2 can control at least the channel region 7.
  • a conductive layer is disposed between the substrate 1 and the dielectric layer 3, the substrate 1 is made of glass, and the conductive layer is made of indium tin oxide (ITO).
  • ITO indium tin oxide
  • 3 silicon dioxide is used, and the physical thickness of the dielectric layer 3 is 0.5 ⁇ m; the source region 5, the drain region 6, the first top gate 4a, the second top gate 4b, and the channel region 7 are all indium tin oxide ( ITO is produced in which the channel region 7 is a semiconductor material and the rest is a conductor material.
  • the channel region 7 has a length of 15 ⁇ m, the channel region 7 has a width of 1 ⁇ m, and the channel region 7 has an electrical thickness of 30 nm; the lateral distance between the source region 5 and the first top gate 4a is 10 ⁇ m.
  • the conductive layer may not be disposed between the substrate 1 and the dielectric layer 3, and the second top gate 4b and the dielectric layer 3
  • the interface forms an equivalent capacitance
  • the interface between the third top gate 4c and the dielectric layer 3 also forms an equivalent capacitance.
  • the two capacitors are coupled to each other, so that the second top gate 4b and the third top gate 4c can effectively regulate the channel region.
  • the carrier concentration is adjusted to adjust the threshold voltage, leakage current, current switching ratio and the like of the thin film transistor of the improved gate structure of the present invention. If there is no bottom gate, then a trench outer top gate is added instead of the bottom gate control channel.
  • the dielectric layer in this embodiment 3 It is prepared by using inorganic materials, and its stability and reliability are relatively good compared with the preparation of organic materials, and it can be compatible with traditional semiconductor process lines, and the preparation is relatively simple.
  • the thin film transistor of the improved gate structure provided in this embodiment has a logic circuit function.
  • the source/drain voltage V DS 1.5 V and the voltage of the third top gate 4 c is 0 V
  • the second top gate 4 b located outside the channel region 7 is changed.
  • the voltage V G2 is -0.5V, 0V, 0.5V, 1V
  • the relationship between the channel current I DS across the source and drain and the voltage V G1 of the bottom gate 2 is as shown in FIG. 7.
  • the threshold voltage V TH of the thin film transistor with improved gate structure is 1.1 V, 0.85 V, 0.45 V, -0.05 V, respectively, and the current switching ratio is also significantly changed.
  • the V G1 input and the V G3 output are used.
  • the relationship is shown in FIG. 8. Therefore, in this embodiment, except for the first top gate 4a in the channel region 7, the remaining gates, including the bottom gate 2, the second top gate 4b, and the third top gate 4c, are controllable.
  • the function of the channel region 7 controls the output of the channel region 7 by changing the voltages of the bottom gate 2, the second top gate 4b, and the third top gate 4c to obtain an ideal inverter input and output result.
  • the transistor in this embodiment has three top gates due to the third top gate 4c
  • the potential of the channel region, that is, the electron concentration, can be regulated, so that a single transistor can implement various logic functions.
  • V G4 0V
  • source and drain voltage V DS 1.5V
  • drain voltage V SS 0V
  • the output voltage of the first top gate 4a V G3 ⁇ 1V , that is, the output is 1
  • the output voltage of the first top gate 4a is V.

Abstract

本发明公开了一种改良栅结构的晶体管，包括基底和处在基底上的介质层，所述介质层上设有一源区、一漏区以及连通在所述源区和漏区之间的沟道区，所述沟道区内设有第一顶栅作为晶体管的输出极，其输出的逻辑值在沟道区导通时为逻辑 1 ，在沟道区截断时为逻辑 0 ；所述晶体管还设有至少两个作为控制沟道区的输入极；其中至少有一个输入极为第二顶栅；还有至少有一个输入极为第三顶栅和 / 或底栅；所述第二顶栅和第三顶栅均位于所述介质层上，且处在所述沟道区的旁边。本发明晶体管，能够减少逻辑电路中晶体管的个数，使逻辑电路的制备方法简单，器件面积减少，从而提高逻辑电路的成品率，降低制作成本，并且可以方便改善调整逻辑电路器件的电学性能。

Description

一种改良栅结构的晶体管 技术领域
本发明属于微电子技术领域，具体涉及一种改良栅结构的晶体管。
背景技术
晶体管，是一种固体半导体器件，可以用于检波、整流、放大、开关、稳压、信号调制和许多其它功能。晶体管作为一种可变开关，基于输入的电压，控制流出的电流，因此晶体管可做为电流的开关，和一般机械开关不同处在于晶体管是利用电讯号来控制，而且开关速度可以非常之快，在实验室中的切换速度可达 100GHz 以上。
晶体管主要可以分为两大类 ： 双极性晶体管 （ BJT ）和 场效应晶体管 （ FET ） 。 晶体管具有三个极；双极性晶体管的三个极，分别由 N 型跟 P 型组成的发射极、基极和集电极；场效应晶体管的三个极，分别是源极（源区）（ Source ）、栅极（栅区）（ Gate ）和漏极（漏区）（ Drain ）。
授权公告号为 CN 101567392B 的发明公开了一种在确保良好的生产性同时又具有优良特性和高可靠性的栅绝缘层的薄膜晶体管，该薄膜晶体管包括：在基板上含有源区、沟道区、漏区的有源层，栅电极层，以及在有源层和栅电极层之间所形成的栅绝缘层的薄膜晶体管，栅绝缘层由在有源层一侧形成的第 1 氧化硅膜、在栅电极层一侧形成的第 2 氧化硅膜，和在第 1 氧化硅膜与第 2 氧化硅膜之间形成的氮化硅膜而形成。
晶体管是逻辑电路中的核心部件。逻辑电路是一种离散信号的传递和处理，以二进制 为原理、实现数字信号逻辑运算和操作的电路，主要分为组合逻辑电路和时序逻辑电路，由最基本的"与门"电路、" 或门电路" 和 "非门 "电路组成。
传统意义上的逻辑电路，为了实现不同的逻辑门运算，需要使用不同类型、不同种类、不同数目的晶体管，藉此对于大面积制作逻辑电路的工艺提出了较高的要求，包括用不同的掩膜版、不同的工艺、不同的材料以及不同的设计，因此制造过程比较复杂，逻辑电路的成品率难以保证。
 技术问题
本发明提供了一种改进栅结构的晶体管，能够减少逻辑电路中晶体管的个数，使逻辑电路的制备方法简单，器件面积减少，从而提高逻辑电路的成品率，降低制作成本，并且可以方便改善调整逻辑电路器件的电学性能。
技术解决方案
一种改良栅结构的晶体管，包括基底和处在基底上的介质层，所述介质层上设有一源区、一漏区以及连通在所述源区和漏区之间的沟道区，所述沟道区内设有第一顶栅作为晶体管的输出极，其输出的逻辑值在沟道区导通时为逻辑 1 ，在沟道区截断时为逻辑 0 ；
所述晶体管还设有至少两个作为控制沟道区的输入极；其中至少有一个输入极为第二顶栅；还有至少有一个输入极为第三顶栅和 / 或底栅；所述第二顶栅和第三顶栅均位于所述介质层上，且处在所述沟道区的旁边。本发明中沟道区旁边的顶栅位于所述介质层上应理解为这些顶栅至少与介质层接触。
作为输出极的顶栅并不覆盖整个沟道区，且该顶栅具有稳定的输出电压；为了使该顶栅具有稳定的输出电压，在沟道区的长度方向上，该顶栅应具有合适的尺寸，以保证该顶栅的输出电压是一个明确的值，即在输入极电压确定后该顶栅的输出电压保持相对稳定。一般情况下在保证强度和导电性能的前提下，该顶栅尺寸尽可能的小。
作为优选，还设有用于控制沟道区的底栅，所述底栅处在基底和介质层之间或由所述基底兼做。
所述的源区、漏区、顶栅和底栅均可采用现有技术中使用的导体特性材料，包括金属、合金、导电聚合物、导电碳纳米管、铟锡氧化物（ ITO ）、铟镓锌氧化物（ IGZO ）等，其中，金属为铝、铜、钨、钼、金或铯等；合金至少含有铝、铜、钨、钼、金、铯中的两种；所述的沟道区使用半导体材料，所述半导体材料包括有机半导体材料和无机半导体材料等，例如氧化物半导体（如铟锡氧化物）、氧化锌纳米线以及碳纳米管。
所述的源区、漏区、顶栅、底栅和沟道区均使用铟锡氧化物。采用一次掩膜法自组装形成源区、漏区、顶栅、底栅和沟道区，工艺简单。
所述的基底可以采用各种材料，只需具有一定的强度可以起到支撑作用即可，包括玻璃、石英、陶瓷、金刚石、纸张、硅片、塑料或树脂等。
所述沟道区一般是条状，所述的'旁边'既可以是沟道区长度方向的一侧，也可以是宽度方向的一侧。
所述的沟道区的长度为 0.001~5000 μ m ，沟道区的宽度为 0.0001~1000 μ m ，沟道区的电学厚度为 0.001~8000nm ；
较优选沟道区的长度为 0.01~100 μ m ，沟道区的宽度为 0.01~100 μ m ，沟道区的电学厚度为 0.01~200nm ；
更优选沟道区的长度为 0.1~10 μ m ，沟道区的宽度为 0.01~10 μ m ，沟道区的电学厚度为 1~50nm 。
所述的介质层采用绝缘材料，介质层的物理厚度为 0.001~1000 μ m ，优选地介质层的物理厚度为 1~200 μ m 。
所述的介质层为二氧化硅（例如多孔二氧化硅、热生长二氧化硅）、苯并环丁烯、聚酯、丙烯酸树脂、氧化铝、氮氧化硅、高κ栅介质材料中的至少一种。 介质层和沟道区之间界面产生电容。
所述的源区和漏区与作为输出极的顶栅的最小横向距离（沿沟道区长度方向的距离）均为 0.0001~100 μ m ；所述的源区或漏区与沟道外顶栅的最小横向距离为 0.0001~100 μ m 。设输出极到源区的最小横向距离为l 。
作为输出极的顶栅可以输出确定电压，这个确定电压是由沟道区是否开启、 源漏电压 VDS 和l决定。
如果顶栅没有位于沟道区内，则优选地，顶栅尽可能地靠近沟道区。
本发明中所述的晶体管可以是薄膜晶体管。
作为优选，所述沟道区内的顶栅、源区和漏区三者排列成第一直线。
作为优选，所述顶栅为两个，分别为第一顶栅和第二顶栅，其中第一顶栅处在所述沟道区内，且与源区和漏区三者排列形成第一直线，第二顶栅位于所述第一直线的一侧，且与第一顶栅对齐。
作为优选，所述顶栅为两个，分别为第一顶栅和第二顶栅，其中第一顶栅处在所述沟道区内，且与源区和漏区三者排列成第一直线，第二顶栅位于所述第一直线上。晶体管的源区、漏区、第一顶栅和第二顶栅呈条状排列，便于制造线型的逻辑电路。
作为优选，所述顶栅为三个，分别为第一顶栅、第二顶栅和第三顶栅，其中第一顶栅处在所述沟道区内，且与源区和漏区三者排列成第一直线，第二顶栅和第三顶栅分别位于所述第一直线的两侧，或位于所述第一直线的同侧。
作为优选， 所述第二顶栅和第三顶栅排列成第二直线，且第二直线与第一直线垂直。 晶体管的源区、漏区、第一顶栅、第二顶栅和第三顶栅呈块状排列，便于制造块型的逻辑电路。
作为优选， 所述第二顶栅和第三顶栅 位于所述第一直线的同侧且 排列成第二直线，所述第二直线与第一直线垂直。 作为进一步的优选， 所述第二顶栅和第三顶栅中的一者与 第一顶栅对齐。
作为优选， 所述第二顶栅和第三顶栅 位于所述第一直线的同侧且 排列成第二直线，所述第二直线与第一直线垂直。 作为进一步的优选， 所述 第一顶栅到 第二顶栅和第三顶栅的最短距离相等 。
作为优选， 所述第二顶栅和第三顶栅分别 位于所述第一直线的两侧且 排列成第二直线，所述第二直线与第一直线垂直。 作为进一步的优选，作为进一步的优选， 所述第二顶栅和第三顶栅中的一者与 第一顶栅对齐。
作为优选， 所述第二顶栅和第三顶栅分别 位于所述第一直线的两侧且 排列成第二直线，所述第二直线与第一直线垂直。 作为进一步的优选， 所述 第一顶栅到 第二顶栅和第三顶栅的最短距离相等 。
作为优选， 所述第二顶栅和第三顶栅 位于所述第一直线的同侧且 排列成第二直线，第二直线与第一直线平行。 晶体管的源区、漏区、第一顶栅、第二顶栅和第三顶栅呈块状排列，便于制造块型的逻辑电路。
作为优选， 所述第二顶栅和第三顶栅 位于所述第一直线的同侧且 排列成第二直线，所述第二直线与第一直线平行。 作为进一步的优选， 所述第二顶栅和第三顶栅中的一者与 第一顶栅对齐。
作为优选， 所述第二顶栅和第三顶栅 位于所述第一直线的同侧且 排列成第二直线，所述第二直线与第一直线平行。 作为进一步的优选， 所述 第一顶栅到 第二顶栅和第三顶栅的最短距离相等 。
作为优选， 所述顶栅为三个，分别为第一顶栅、第二顶栅和第三顶栅，其中第一顶栅处在所述沟道区内，且与源区和漏区三者排列成第一直线，所述第二顶栅和第三顶栅排列成第二直线，且第二直线与第一直线重合。所述第二顶栅和第三顶栅处在所述源区的同一侧且远离所述漏区。或所述第二顶栅和第三顶栅处在所述漏区的同一侧且远离所述源区。
作为优选， 所述顶栅为三个，分别为第一顶栅、第二顶栅和第三顶栅，其中第一顶栅处在所述沟道区内，且与源区和漏区三者排列成第一直线，所述第二顶栅和第三顶栅排列成第二直线，且第二直线与第一直线重合。所述第二顶栅和第三顶栅中的一个顶栅处在所述源区的一侧且远离所述漏区。所述第二顶栅和第三顶栅中的一个顶栅处在所述源区的一侧且远离所述源区。
晶体管的源区、漏区、第一顶栅、第二顶栅和第三顶栅呈条状排列，便于制造线型的逻辑电路。
作为优选， 所述底栅处在基底和介质层之间，所述底栅分布在基底上的局部区域，基底上开设有与底栅位置相应的容置槽，所述底栅的面积至少能够 与处在沟道区旁边的顶栅形成耦合， 以控制所述沟道区。底栅与作为输入极的 顶栅形成耦合，可以更好的控制沟道区。
若所述底栅由所述基底兼做，此时该基底与介质层贴合的一面应为导电材料，而背向介质层的一面应该为非导电材料。
优选地，所述基板与介质层之间设有导电层。所述的导电层采用导电材料，例如 ITO 或者 IGZO 。设置导电层能够增强电容耦合的效果，使得顶栅更易于调控沟道区。
本发明中每个晶体管具有至少两个顶栅，每个位于沟道区之外的顶栅均可以调控沟道区，通过改变顶栅电压，可以让同一个晶体管实现多个逻辑电路功能，例如与门、或门、与非门等。
作为优选，顶栅共有四个， 分别为第一顶栅、第二顶栅、第三顶栅和第四顶栅，其中第一顶栅处在所述沟道区内，且与源区和漏区三者排列成第一直线，所述第二顶栅、第三顶栅和第四顶栅排列成第二直线，且第二直线与第一直线重合。所述第二顶栅和第三顶栅处在所述源区的同一侧且远离所述漏区。或所述第二顶栅和第三顶栅处在所述漏区的同一侧且远离所述源区。第四顶栅可以位于任何位置。优选地，在所述源区的一侧且远离所述漏区，或者在所述漏区的一侧且远离所述源区
作为优选，顶栅共有四个， 分别为第一顶栅、第二顶栅、第三顶栅和第四顶栅，其中第一顶栅处在所述沟道区内，且与源区和漏区三者排列成第一直线，所述第二顶栅、第三顶栅和第四顶栅排列成第二直线，且第二直线与第一直线重合。所述第二顶栅和第三顶栅处分别在所述源区的一侧且远离所述漏区，以及在所述漏区的一侧且远离所述源区。第四顶栅可以位于任何位置。优选地，在所述源区的一侧且远离所述漏区，或者在所述漏区的一侧且远离所述源区。
作为优选，输 入 极不包含有底栅，所述顶栅为四个， 分别为第一顶栅、第二顶栅、第三顶栅和第四顶栅，其中第二顶栅、第三顶栅和第四顶栅均作为输入极。
由于没有底栅，为了实现复杂的逻辑功能，此时需要有至少三个输入极，例如采用三个输入极，分别为 第二顶栅、第三顶栅和第四顶栅。
在排列方式上可有如下方式：
其中第一顶栅处在所述沟道区内，且与源区和漏区三者排列成第一直线， 第二顶栅、第三顶栅和第四顶栅， 分别位于所述第一直线的两侧，第一直线上或位于所述第一直线的同侧。
作为优选， 所述第二顶栅、第三顶栅和第四顶栅排列成第二直线，且第二直线与第一直线垂直。 晶体管的源区、漏区、第一顶栅、第二顶栅和第三顶栅呈块状排列，便于制造块型的逻辑电路。
作为优选， 所述第二顶栅、第三顶栅和第四顶栅 位于所述第一直线的同侧且 排列成第二直线，所述第二直线与第一直线垂直。 作为进一步的优选， 所述第二顶栅、第三顶栅和第四顶栅的一者与 第一顶栅对齐。
作为优选， 所述第二顶栅、第三顶栅和第四顶栅分别 位于所述第一直线的两侧且 排列成第二直线，所述第二直线与第一直线垂直。 作为进一步的优选， 所述第二顶栅、第三顶栅和第四顶栅的一者与 第一顶栅对齐。
作为优选， 所述第二顶栅、第三顶栅和第四顶栅 位于所述第一直线的同侧且 排列成第二直线，所述第二直线与第一直线垂直。 作为进一步的优选， 所述 第一顶栅到 第二顶栅和第三顶栅的最短距离相等 。
作为优选， 所述第二顶栅、第三顶栅和第四顶栅 位于所述第一直线的同侧且 排列成第二直线，第二直线与第一直线平行。 晶体管的源区、漏区、第一顶栅、第二顶栅和第三顶栅呈块状排列，便于制造块型的逻辑电路。
作为优选， 所述第二顶栅、第三顶栅和第四顶栅 位于所述第一直线的同侧且 排列成第二直线，所述第二直线与第一直线平行。 作为进一步的优选， 所述第二顶栅和第三顶栅中的一者与 第一顶栅对齐。
作为优选， 所述第二顶栅、第三顶栅和第四顶栅 位于所述第一直线的两侧且至少其中任意两栅 排列成第二直线，所述第二直线与第一直线平行。 作为进一步的优选， 所述第二顶栅和第三顶栅中的一者与 第一顶栅对齐。
作为优选， 所述第二顶栅、第三顶栅和第四顶栅 位于所述第一直线的两侧且其中任意两栅 排列成第二直线，所述第二直线与第一直线垂直。 作为进一步的优选， 所述第二顶栅和第三顶栅中的一者与 第一顶栅对齐。
作为优选，顶栅共有四个， 分别为第一顶栅、第二顶栅、第三顶栅和第四顶栅，其中第一顶栅处在所述沟道区内，且与源区和漏区三者排列成第一直线，所述第二顶栅、第三顶栅和第四顶栅排列成第二直线，且第二直线与第一直线重合。所述第二顶栅和第三顶栅处在所述源区的同一侧且远离所述漏区。或所述第二顶栅和第三顶栅处在所述漏区的同一侧且远离所述源区。第四顶栅可以位于任何位置。优选地，在所述源区的同一侧且远离所述漏区，或者在所述漏区的一侧且远离所述源区。
作为优选，顶栅共有四个， 分别为第一顶栅、第二顶栅、第三顶栅和第四顶栅，其中第一顶栅处在所述沟道区内，且与源区和漏区三者排列成第一直线，所述第二顶栅、第三顶栅和第四顶栅排列成第二直线，且第二直线与第一直线重合。所述第二顶栅和第三顶栅处分别在所述源区的一侧且远离所述漏区，以及在所述漏区的一侧且远离所述源区。第四顶栅可以位于任何位置。优选地，在所述源区的一侧且远离所述漏区，或者在所述漏区的一侧且远离所述源区。
 有益效果
本发明一种改良栅结构的晶体管，在晶体管的沟道区引入顶栅，在具备传统晶体管的功能的前提下，能够实现逻辑电路的功能，使得原来需要多个晶体管完成的逻辑电路功能仅需要一个晶体管即可完成，大大简化了电路，提高了逻辑电路的生产加工效率。
附图说明
图 1 为本发明改良栅结构的晶体管第一种实施方式示意图；
图 2 为本发明改良栅结构的晶体管第二种实施方式示意图；
图 3 为本发明改良栅结构的晶体管第三种实施方式示意图；
图 4 为本发明改良栅结构的晶体管第四种实施方式示意图；
图 5 为本发明改良栅结构的晶体管第五种实施方式示意图；
图 6 为本发明改良栅结构的晶体管第六种实施方式示意图；
图 7 为本发明改良栅结构的晶体管各实施方式（若有底栅）中改变第二顶栅的电压时，沟道电流随底栅电压变化的曲线图；
图 8 为本发明改良栅结构的晶体管各实施方式中输入电压与输出电压的关系示意图；
图 9 为本发明改良栅结构的晶体管含有第三顶栅或底栅时，第三顶栅或底栅对沟道区的肖特基势垒φ的影响图；
图 10 为本发明改良栅结构的晶体管第七种实施方式示意图。
 本发明的实施方式
下面结合具体的实施例，对本发明一种改良栅结构的晶体管做详细描述。
实施例 1
如图 1 所示，一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有两个顶栅，以及和这两个顶栅形成耦合的底栅，两个顶栅分别为第一顶栅 4a 和第二顶栅 4b ，基底 1 兼做底栅，第一顶栅 4a 位于沟道区 7 内，且与源区 5 和漏区 6 三者排列成第一直线，第二顶栅 4b 位于第一直线的一侧，且与第一顶栅 4a 对齐。 如果没有底栅，则增加一沟道区外的顶栅代替底栅调控沟道。
基底 1 采用单表面为导电层的玻璃，其导电层采用铟锡氧化物（ ITO ）与 介质层 3 贴合 ，介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30 nm ；源区 5 与第一顶栅 4a 的横向距离（图中沿着沟道区的长度方向）为 10 μ m 。沟道区内的栅极的大小必须是能够得到一个稳定电位的大小。
需要说明的是，本实施例中的基板 1 与介质层 3 之间可以不设置导电层，第二顶栅 4b 与介质层 3 的界面形成等效电容，使第二顶栅 4b 能够有效调控沟道区 7 的载流子浓度。
本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与底栅（基底 1 兼做）的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，因此，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，其余的栅极，包括底栅和第二顶栅 4b 都具有可以调控沟道区 7 的功能，通过改变底栅和第二顶栅 4b 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果，逻辑输入输出结果见表 1 。
表 1
输入 输出
VG1 VG3 VG2
0(0 V) 1(1 V) 1(0.7 V)
1(0.7 V) 0(0 V) -1 （ -1V ）
设源漏电压 VDS=1.5V ，漏区电压 Vss=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 0.7V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 0.7V 即记为输出为 0 ，定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l/L=1/1.5 ，可以得到（ l 为第一顶栅 4a 到源区的距离） l=10μm ，所以当 l≥ 10μm ，可以得到 VG3 ≥ 1V 。于是可以得到 OR 门逻辑，如表 2 所示，当 VG1 和 VG2 都为 0 ， IDS=0 ， VG3=0 ，在底栅上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V 。
表 2
输入 输出
VG1 VG2 VG3
0 (0 V) 0 (0 V) 0 (0 V)
0 (0 V) 1 (0.7 V) 1 （ 1 V ）
1 (0.7 V) 0 (0 V) 1 （ 1 V ）
1 (0.7 V) 1 (0.7 V) 1 （ 1 V ）
实施例 2
如图 2 所示，一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有两个顶栅，以及和这两个顶栅形成耦合的底栅 2 ，两个顶栅分别为第一顶栅 4a 和第二顶栅 4b ，底栅 2 处在基底 1 和介质层 3 之间，底栅 2 分布在基底 1 上的局部区域， 基底 1 上开设有与底栅 2 位置相应的容置槽， 底栅 2 的面积至少能够控制沟道区 7 ，第一顶栅 4a 位于沟道区 7 内，且与源区 5 和漏区 6 三者排列成第一直线，第二顶栅 4b 位于第一直线的一侧，且与第一顶栅 4a 对齐。 如果没有底栅，则增加一沟道外顶栅代替底栅调控沟道。
基底 1 和介质层 3 之间设有导电层，基底 1 采用玻璃，导电层采用铟锡氧化物（ ITO ），介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30 nm ；源区 5 与第一顶栅 4a 的横向距离为 10 μ m 。
需要说明的是，本实施例中的基板 1 与介质层 3 之间可以不设置导电层，第二顶栅 4b 与介质层 3 的界面形成等效电容，使第二顶栅 4b 能够有效调控沟道区 7 的载流子浓度，从而调节本发明改良栅结构的薄膜晶体管的阈值电压、漏电流、电流开关比等电学性能。本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与底栅 2 的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，因此，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，，其余的栅极，包括底栅 2 和第二顶栅 4b 都具有可以调控沟道区 7 的功能，通过改变底栅 2 和第二顶栅 4b 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果。
设源漏电压 VDS=1.5V ，漏区电压 Vss=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 0.7V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 0.7V 即记为输出为 0 ，定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l/L=1/1.5 ，可以得到（ l为第一顶栅 4a 到源区的距离） l=10μm ，所以当 l≥ 10μm ，可以得到 VG3 ≥ 1V 。于是可以得到 OR 门逻辑，如表 2 所示，当 VG1 和 VG2 都为 0 ， IDS=0 ， VG3=0 ，在底栅上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V 。
实施例 3
如图 3 所示，一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有三个顶栅，以及和这三个顶栅形成耦合的底栅，三个顶栅分别为第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c ，其中第一顶栅 4a 处在沟道区 7 内且与源区 5 和漏区 6 三者排列成第一直线，第二顶栅 4b 和第三顶栅 4c 位于第一直线的两侧，第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c 排列成第二直线，且第二直线与第一直线垂直，基底 1 兼做底栅。 如果没有底栅，则增加一沟道外顶栅代替底栅调控沟道。
基底 1 采用单表面为导电层的玻璃，其导电层采用铟锡氧化物（ ITO ）与 介质层 3 贴合 ，介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30 nm ；源区 5 与第一顶栅 4a 的横向距离为 10 μ m 。
需要说明的是，本实施例中的基板 1 与介质层 3 之间可以不设置导电层，第二顶栅 4b 与介质层 3 的界面形成等效电容，第三顶栅 4c 与介质层 3 的界面也形成等效电容，这两个电容相互耦合，使第二顶栅 4b 和第三顶栅 4c 能够有效调控沟道区 7 的载流子浓度，从而调节本发明改良栅结构的薄膜晶体管的阈值电压、漏电流、电流开关比等电学性能。
本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，第三顶栅 4c 的电压为 0V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与底栅（基底 1 兼做）的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，因此，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，其余的栅极，包括底栅、第二顶栅 4b 和第三顶栅 4c 都具有可以调控沟道区 7 的功能，通过改变底栅、第二顶栅 4b 和第三顶栅 4c 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果。
该实施例中的晶体管具有三个顶栅，由于第三顶栅 4c 可以调控沟道区的电位、即电子浓度，因此单个晶体管可以实现多种逻辑功能。
如果第三顶栅 4c 的电压 VG4=0V ，假设源漏电压 VDS=1.5V ，漏区电压 VSS=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 1V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 1V 即记为输出为 0 ，（同理定义 VG1 ， VG2 的输入输出状态）定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l/L=1/1.5 ，可以得到（第一顶栅 4a 到源区的距离） l=10μm 。所以当 l ≥ 10μm ，可以得到 VG3 ≥ 1V 。于是可以得到 OR 门逻辑，如表 3 所示，当底栅的电压 VG1 和第二顶栅 4b 的电压 VG2 都为 0 ， IDS=0 ， VG3=0 ，在底栅上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V ，同样可以得到表 2 。如果第三顶栅 4c 的电压 VG4=1V ，那么 IDS 很难为零，沟道区常开，如果 VG4=-1V ，那 IDS 很难大于漏电流，沟道为关断状态，因此可实现与门逻辑，如表 4 所示。
表 3
输入 输出
VG1 VG2 VG3 VG4
0(0 V) 0(0 V) 0(0 V) 0 （ 0 V ）
0(0 V) 1 （ 0.7 V ） 1 （ 1 V ） 0 （ 0 V ）
1 （ 0.7 V ） 0(0 V) 1 （ 1 V ） 0 （ 0 V ）
1 （ 0.7 V ） 1 （ 0.7 V ） 1 （ 1 V ） 0 （ 0 V ）
表 4
输入 输出
VG1 VG2 VG3 VG4
0 (0 V) 0 (0 V) 0 (0 V) 0 （ -1 V ）
0 (0 V) 1 （ 0.7 V ） 0 (0 V) 0 （ -1 V ）
1 （ 0.7 V ） 0 (0 V) 0 (0 V) 0 （ -1 V ）
1 （ 0.7 V ） 1 （ 0.7 V ） 1 （ 1 V ） 1 （ 1 V ）
第三顶栅 4c 对沟道区的肖特基势垒φ的影响见图 9 ，在图 9 的 (A) 部分中的第三顶栅的电压相对φ 1 为负偏压，在图 9 的 (B) 部分中的第三顶栅的电压相对φ 0 为 0 ，在图 9 的 (C) 部分中的第三顶栅的电压相对φ 2 为正偏压。
实施例 4
如图 4 所示，一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有三个顶栅，以及和这三个顶栅形成耦合的底栅 2 ，三个顶栅分别为第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c ，其中第一顶栅 4a 处在沟道区 7 内且与源区 5 和漏区 6 三者排列成第一直线，第二顶栅 4b 和第三顶栅 4c 位于第一直线的两侧，第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c 排列成第二直线，且第二直线与第一直线垂直，底栅 2 位于基底 1 和介质层 3 之间，底栅 2 分布在基底 1 上的局部区域， 基底 1 上开设有与底栅 2 位置相应的容置槽， 且底栅 2 的面积至少能够控制沟道区 7 。 如果没有底栅，则增加一沟道外顶栅代替底栅调控沟道。
基底 1 和介质层 3 之间设有导电层，基底 1 采用玻璃，导电层采用铟锡氧化物（ ITO ），介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30nm ；源区 5 与第一顶栅 4a 的横向距离为 10 μ m 。
需要说明的是，本实施例中的基板 1 与介质层 3 之间可以不设置导电层，第二顶栅 4b 与介质层 3 的界面形成的等效电容，第三顶栅 4c 与介质层 3 的界面也形成等效电容，这两个电容相互耦合，使第二顶栅 4b 和第三顶栅 4c 能够有效调控沟道区 7 的载流子浓度，从而调节本发明改良栅结构的薄膜晶体管的阈值电压、漏电流、电流开关比等电学性能。
本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，第三顶栅 4c 的电压为 0V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与底栅 2 的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，因此，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，其余的栅极，包括底栅 2 、第二顶栅 4b 和第三顶栅 4c 都具有可以调控沟道区 7 的功能，通过改变底栅 2 、第二顶栅 4b 和第三顶栅 4c 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果。
该实施例中的晶体管具有三个顶栅，由于第三顶栅 4c 可以调控沟道区的电位、即电子浓度，因此单个晶体管可以实现多种逻辑功能。
如果第三顶栅 4c 的电压 VG4=0V ，假设源漏电压 VDS=1.5V ，漏区电压 VSS=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 1V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 1V 即记为输出为 0 ，（同理定义 VG1 ， VG2 的输入输出状态）定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l/L=1/1.5 ，可以得到（第一顶栅 4a 到源区的距离）l =10μm 。所以当 l≥ 10μm ，可以得到 VG3>1V 。于是可以得到 OR 门逻辑，如表 3 所示，当底栅 2 的电压 VG1 和第二顶栅 4b 的电压 VG2 都为 0 ， IDS=0 ， VG3=0 ，在底栅 2 上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V ，同样可以得到表 2 。如果第三顶栅 4c 的电压 VG4=1V ，那么沟道电流 IDS 很难为零，沟道区常开，如果 VG4=-1V ，那沟道电流 IDS 很难大于漏电流，沟道为关断状态，因此可实现与门逻辑，如表 4 所示。
实施例 5
如图 5 所示，一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有三个顶栅，以及和这三个顶栅形成耦合的底栅，三个顶栅分别为第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c ，其中第一顶栅 4a 处在沟道区 7 内且与源区 5 和漏区 6 三者排列成第一直线，第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c 排列成第二直线，且第二直线与第一直线重合，第二顶栅 4b 和第三顶栅 4c 处在源区 5 的同一侧，且远离漏区 6 ，基底 1 兼做底栅。 如果没有底栅，则增加一沟道外顶栅代替底栅调控沟道。
基底 1 采用单表面为导电层的玻璃，其导电层采用铟锡氧化物（ ITO ）与 介质层 3 贴合 ，介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30nm ；源区 5 与第一顶栅 4a 的横向距离为 10 μ m 。
需要说明的是，本实施例中的基板 1 与介质层 3 之间可以不设置导电层，第二顶栅 4b 与介质层 3 的界面形成等效电容，第三顶栅 4c 与介质层 3 的界面也形成等效电容这两个电容相互耦合，使第二顶栅 4b 和第三顶栅 4c 能够有效调控沟道区 7 的载流子浓度，从而调节本发明改良栅结构的薄膜晶体管的阈值电压、漏电流、电流开关比等电学性能。
本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，第三顶栅 4c 的电压为 0V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与底栅（基底 1 兼做）的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，因此，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，其余的栅极，包括底栅、第二顶栅 4b 和第三顶栅 4c 都具有可以调控沟道区 7 的功能，通过改变底栅、第二顶栅 4b 和第三顶栅 4c 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果。
该实施例中的晶体管具有三个顶栅，由于第三顶栅 4c 可以调控沟道区的电位、即电子浓度，因此单个晶体管可以实现多种逻辑功能。
如果第三顶栅 4c 的电压 VG4=0V ，假设源漏电压 VDS=1.5V ，漏区电压 VSS=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 1V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 1V 即记为输出为 0 ，（同理定义 VG1 ， VG2 的输入输出状态）定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l/L=1/1.5 ，可以得到（第一顶栅 4a 到源区的距离） l =10μm 。所以当 l≥ 10μm ，可以得到 VG3 ≥ 1V 。于是可以得到 OR 门逻辑，如表 3 所示，当底栅的电压 VG1 和第二顶栅 4b 的电压 VG2 都为 0 ， IDS=0 ， VG3=0 ，在底栅上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V ，同样可以得到表 2 。如果第三顶栅 4c 的电压 VG4=1V ，那么 IDS 很难为零，沟道区常开，如果 VG4=-1V ，那 IDS 很难大于漏电流，沟道为关断状态，因此可实现与门逻辑，如表 4 所示。
实施例 6
如图 6 所示，一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有三个顶栅，以及和这三个顶栅形成耦合的底栅 2 ，三个顶栅分别为第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c ，其中第一顶栅 4a 处在沟道区 7 内且与源区 5 和漏区 6 三者排列成第一直线，第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c 排列成第二直线，且第二直线与第一直线重合，第二顶栅 4b 和第三顶栅 4c 处在源区 5 的同一侧，且远离漏区 6 ，底栅 2 位于基底 1 和介质层 3 之间， 基底 1 上开设有与底栅 2 位置相应的容置槽， 底栅 2 分布在基底 1 上的局部区域，且底栅 2 的面积至少能够控制沟道区 7 。
基底 1 和介质层 3 之间设有导电层，基底 1 采用玻璃，导电层采用铟锡氧化物（ ITO ），介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30nm ；源区 5 与第一顶栅 4a 的横向距离为 10 μ m 。
需要说明的是，本实施例中的基板 1 与介质层 3 之间可以不设置导电层，第二顶栅 4b 与介质层 3 的界面形成等效电容，第三顶栅 4c 与介质层 3 的界面也形成等效电容，这两个电容相互耦合，使第二顶栅 4b 和第三顶栅 4c 能够有效调控沟道区 7 的载流子浓度，从而调节本发明改良栅结构的薄膜晶体管的阈值电压、漏电流、电流开关比等电学性能。如果没有底栅，则增加一沟道外顶栅代替底栅调控沟道。
本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，第三顶栅 4c 的电压为 0V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与底栅 2 的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，因此，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，其余的栅极，包括底栅 2 、第二顶栅 4b 和第三顶栅 4c 都具有可以调控沟道区 7 的功能，通过改变底栅 2 、第二顶栅 4b 和第三顶栅 4c 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果。
该实施例中的晶体管具有三个顶栅，由于第三顶栅 4c 可以调控沟道区的电位、即电子浓度，因此单个晶体管可以实现多种逻辑功能。
如果第三顶栅 4c 的电压 VG4=0V ，假设源漏电压 VDS=1.5V ，漏区电压 VSS=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 1V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 1V 即记为输出为 0 ，（同理定义 VG1 ， VG2 的输入输出状态）定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l/L=1/1.5 ，可以得到（第一顶栅 4a 到源区的距离） l=10μm 。所以当 l≥ 10μm ，可以得到 VG3l ≥ 1V 。于是可以得到 OR 门逻辑，如表 3 所示，当底栅 2 的电压 VG1 和第二顶栅 4b 的电压 VG2 都为 0 ， IDS=0 ， VG3=0 ，在底栅 2 上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V ，同样可以得到表 2 。如果第三顶栅 4c 的电压 VG4=1V ，那么 IDS 很难为零，沟道区常开，如果 VG4=-1V ，那 IDS 很难大于漏电流，沟道为关断状态，因此可实现与门逻辑，如表 4 所示。第三顶栅 4c 对沟道区的肖特基势垒φ的影响见图 9 ，在图 9 的 (A) 部分中的第三顶栅的电压相对φ 1 为负偏压，在图 9 的 (B) 部分中的第三顶栅的电压相对φ 0 为 0 ，在图 9 的 (C) 部分中的第三顶栅的电压相对φ 2 为正偏压。
实施例 7
如图 10 所示，一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有三个顶栅，以及和这三个顶栅形成耦合的底栅 2 ，三个顶栅分别为第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c ，其中第一顶栅 4a 处在沟道区 7 内且与源区 5 和漏区 6 三者排列成第一直线，第二顶栅 4b 和第三顶栅 4c 位于第一直线的同一侧。
底栅 2 位于基底 1 和介质层 3 之间，底栅 2 分布在基底 1 上的局部区域， 基底 1 上开设有与底栅 2 位置相应的容置槽， 且底栅 2 的面积至少能够控制沟道区 7 。
基底 1 和介质层 3 之间设有导电层，基底 1 采用玻璃，导电层采用铟锡氧化物（ ITO ），介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30nm ；源区 5 与第一顶栅 4a 的横向距离为 10 μ m 。
需要说明的是，本实施例中的基板 1 与介质层 3 之间可以不设置导电层，第二顶栅 4b 与介质层 3 的界面形成的等效电容，第三顶栅 4c 与介质层 3 的界面也形成等效电容，这两个电容相互耦合，使第二顶栅 4b 和第三顶栅 4c 能够有效调控沟道区 7 的载流子浓度，从而调节本发明改良栅结构的薄膜晶体管的阈值电压、漏电流、电流开关比等电学性能。如果没有底栅，则增加一沟道外顶栅代替底栅调控沟道。
本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，第三顶栅 4c 的电压为 0V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与底栅 2 的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，因此，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，其余的栅极，包括底栅 2 、第二顶栅 4b 和第三顶栅 4c 都具有可以调控沟道区 7 的功能，通过改变底栅 2 、第二顶栅 4b 和第三顶栅 4c 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果。
该实施例中的晶体管具有三个顶栅，由于第三顶栅 4c 可以调控沟道区的电位、即电子浓度，因此单个晶体管可以实现多种逻辑功能。
如果第三顶栅 4c 的电压 VG4=0V ，假设源漏电压 VDS=1.5V ，漏区电压 VSS=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 1V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 1V 即记为输出为 0 ，（同理定义 VG1 ， VG2 的输入输出状态）定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l /L=1/1.5 ，可以得到（第一顶栅 4a 到源区的距离） l=10μm 。所以当 l ≥ 10μm ，可以得到 VG3>1V 。于是可以得到 OR 门逻辑，如表 3 所示，当底栅 2 的电压 VG1 和第二顶栅 4b 的电压 VG2 都为 0 ， IDS=0 ， VG3=0 ，在底栅 2 上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V ，同样可以得到表 2 。如果第三顶栅 4c 的电压 VG4=1V ，那么沟道电流 IDS 很难为零，沟道区常开，如果 VG4=-1V ，那沟道电流 IDS 很难大于漏电流，沟道为关断状态，因此可实现与门逻辑，如表 4 所示。
实施例 8
一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有四个控制沟道的顶栅，分别为第一顶栅 4a 、第二顶栅 4b 、第三顶栅 4c 和第四顶栅，其中第一顶栅 4a 处在沟道区 7 内且与源区 5 和漏区 6 三者排列成第一直线，第二顶栅 4b 、第三顶栅 4c 和第四顶栅位于第一直线的同一侧。
需要说明的是，可以设置 底栅 2 位于基底 1 和介质层 3 之间，底栅 2 分布在基底 1 上的局部区域， 基底 1 上开设有与底栅 2 位置相应的容置槽， 且底栅 2 的面积至少能够控制沟道区 7 。 本实施例中的基板 1 与介质层 3 之间可以不设置导电层。
基底 1 和介质层 3 之间设有导电层，基底 1 采用玻璃，导电层采用铟锡氧化物（ ITO ），介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30nm ；源区 5 与第一顶栅 4a 的横向距离为 10 μ m 。
需要说明的是，本实施例中的基板 1 与介质层 3 之间可以不设置导电层，第二顶栅 4b 与介质层 3 的界面形成的等效电容，第三顶栅 4c 与介质层 3 的界面也形成等效电容，这两个电容相互耦合，使第二顶栅 4b 和第三顶栅 4c 能够有效调控沟道区 7 的载流子浓度，从而调节本发明改良栅结构的薄膜晶体管的阈值电压、漏电流、电流开关比等电学性能。本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，第三顶栅 4c 的电压为 0V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与第四顶栅的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，因此，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，其余的栅极，包括第四顶栅、第二顶栅 4b 和第三顶栅 4c 都具有可以调控沟道区 7 的功能，通过第四顶栅、第二顶栅 4b 和第三顶栅 4c 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果。
该实施例中的晶体管具有三个顶栅，由于第三顶栅 4c 可以调控沟道区的电位、即电子浓度，因此单个晶体管可以实现多种逻辑功能。
如果第三顶栅 4c 的电压 VG4=0V ，假设源漏电压 VDS=1.5V ，漏区电压 VSS=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 1V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 1V 即记为输出为 0 ，（同理定义 VG1 ， VG2 的输入输出状态）定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l /L=1/1.5 ，可以得到（第一顶栅 4a 到源区的距离） l=10μm 。所以当 l ≥ 10μm ，可以得到 VG3>1V 。于是可以得到 OR 门逻辑，如表 3 所示，当第四顶栅的电压 VG1 和第二顶栅 4b 的电压 VG2 都为 0 ， IDS=0 ， VG3=0 ，在第四顶栅上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V ，同样可以得到表 2 。如果第三顶栅 4c 的电压 VG4=1V ，那么沟道电流 IDS 很难为零，沟道区常开，如果 VG4=-1V ，那沟道电流 IDS 很难大于漏电流，沟道为关断状态，因此可实现与门逻辑，如表 4 所示。
实施例 9
一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有四个控制沟道的顶栅，分别为第一顶栅 4a 、第二顶栅 4b 、第三顶栅 4c 和第四顶栅，其中第一顶栅 4a 处在沟道区 7 内且与源区 5 和漏区 6 三者排列成第一直线，第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c 、第四顶栅排列成第二直线，且第二直线与第一直线重合。
基底 1 和介质层 3 之间设有导电层，基底 1 采用玻璃，导电层采用铟锡氧化物（ ITO ），介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
需要说明的是，可以设置 底栅 2 位于基底 1 和介质层 3 之间，底栅 2 分布在基底 1 上的局部区域， 基底 1 上开设有与底栅 2 位置相应的容置槽， 且底栅 2 的面积至少能够控制沟道区 7 。 本实施例中的基板 1 与介质层 3 之间可以不设置导电层。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30nm ；源区 5 与第一顶栅 4a 的横向距离为 10 μ m 。
本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，第三顶栅 4c 的电压为 0V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与第四顶栅的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，因此，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，其余的栅极，包括第四顶栅、第二顶栅 4b 和第三顶栅 4c 都具有可以调控沟道区 7 的功能，通过第四顶栅、第二顶栅 4b 和第三顶栅 4c 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果。
该实施例中的晶体管具有三个顶栅，由于第三顶栅 4c 可以调控沟道区的电位、即电子浓度，因此单个晶体管可以实现多种逻辑功能。
如果第三顶栅 4c 的电压 VG4=0V ，假设源漏电压 VDS=1.5V ，漏区电压 VSS=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 1V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 1V 即记为输出为 0 ，（同理定义 VG1 ， VG2 的输入输出状态）定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l/L=1/1.5 ，可以得到（第一顶栅 4a 到源区的距离） l =10μm 。所以当 l≥ 10μm ，可以得到 VG3>1V 。于是可以得到 OR 门逻辑，如表 3 所示，当第四顶栅的电压 VG1 和第二顶栅 4b 的电压 VG2 都为 0 ， IDS=0 ， VG3=0 ，在第四顶栅上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V ，同样可以得到表 2 。如果第三顶栅 4c 的电压 VG4=1V ，那么沟道电流 IDS 很难为零，沟道区常开，如果 VG4=-1V ，那沟道电流 IDS 很难大于漏电流，沟道为关断状态，因此可实现与门逻辑，如表 4 所示。
实施例 10
一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有四个控制沟道的顶栅，分别为第一顶栅 4a 、第二顶栅 4b 、第三顶栅 4c 和第四顶栅，其中第一顶栅 4a 处在沟道区 7 内且与源区 5 和漏区 6 三者排列成第一直线，第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c 、第四顶栅排列成第二直线，且第二直线与第一直线垂直。
基底 1 和介质层 3 之间设有导电层，基底 1 采用玻璃，导电层采用铟锡氧化物（ ITO ），介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
需要说明的是，可以设置 底栅 2 位于基底 1 和介质层 3 之间，底栅 2 分布在基底 1 上的局部区域， 基底 1 上开设有与底栅 2 位置相应的容置槽， 且底栅 2 的面积至少能够控制沟道区 7 。 本实施例中的基板 1 与介质层 3 之间可以不设置导电层。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30nm ；源区 5 与第一顶栅 4a 的横向距离为 10 μ m 。
本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，第三顶栅 4c 的电压为 0V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与第四顶栅的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，因此，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，其余的栅极，包括第四顶栅、第二顶栅 4b 和第三顶栅 4c 都具有可以调控沟道区 7 的功能，通过第四顶栅、第二顶栅 4b 和第三顶栅 4c 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果。
该实施例中的晶体管具有三个顶栅，由于第三顶栅 4c 可以调控沟道区的电位、即电子浓度，因此单个晶体管可以实现多种逻辑功能。
如果第三顶栅 4c 的电压 VG4=0V ，假设源漏电压 VDS=1.5V ，漏区电压 VSS=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 1V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 1V 即记为输出为 0 ，（同理定义 VG1 ， VG2 的输入输出状态）定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l/L=1/1.5 ，可以得到（第一顶栅 4a 到源区的距离） l=10μm 。所以当 l ≥ 10μm ，可以得到 VG3>1V 。于是可以得到 OR 门逻辑，如表 3 所示，当第四顶栅的电压 VG1 和第二顶栅 4b 的电压 VG2 都为 0 ， IDS=0 ， VG3=0 ，在第四顶栅上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V ，同样可以得到表 2 。如果第三顶栅 4c 的电压 VG4=1V ，那么沟道电流 IDS 很难为零，沟道区常开，如果 VG4=-1V ，那沟道电流 IDS 很难大于漏电流，沟道为关断状态，因此可实现与门逻辑，如表 4 所示。
实施例 11
一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有两个顶栅，以及和这两个顶栅形成耦合的底栅，两个顶栅分别为第一顶栅 4a 和第二顶栅 4b ，基底 1 兼做底栅，第一顶栅 4a 位于沟道区 7 内，且与源区 5 和漏区 6 三者排列成第一直线，第二顶栅 4b 与第一顶栅 4a 排列成第二直线，且第二直线与第一直线重合。
基底 1 采用单表面为导电层的玻璃，其导电层采用铟锡氧化物（ ITO ）与 介质层 3 贴合 ，介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30 nm ；源区 5 与第一顶栅 4a 的横向距离（图中沿着沟道区的长度方向）为 10 μ m 。沟道区内的栅极的大小必须是能够得到一个稳定电位的大小。
需要说明的是，本实施例中的基板 1 与介质层 3 之间可以不设置导电层，第二顶栅 4b 与介质层 3 的界面形成等效电容，使第二顶栅 4b 能够有效调控沟道区 7 的载流子浓度。
本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与底栅（基底 1 兼做）的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，因此，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，其余的栅极，包括底栅和第二顶栅 4b 都具有可以调控沟道区 7 的功能，通过改变底栅和第二顶栅 4b 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果，逻辑输入输出结果见表 1 。
设源漏电压 VDS=1.5V ，漏区电压 Vss=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 0.7V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 0.7V 即记为输出为 0 ，定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l/L=1/1.5 ，可以得到（ l 为第一顶栅 4a 到源区的距离） l =10μm ，所以当 l ≥ 10μm ，可以得到 VG3 ≥ 1V 。于是可以得到 OR 门逻辑，如表 2 所示，当 VG1 和 VG2 都为 0 ， IDS=0 ， VG3=0 ，在底栅上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V 。
实施例 12
一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有两个顶栅，以及和这两个顶栅形成耦合的底栅 2 ，两个顶栅分别为第一顶栅 4a 和第二顶栅 4b ，底栅 2 处在基底 1 和介质层 3 之间，底栅 2 分布在基底 1 上的局部区域， 基底 1 上开设有与底栅 2 位置相应的容置槽， 底栅 2 的面积至少能够控制沟道区 7 ，第一顶栅 4a 位于沟道区 7 内，且与源区 5 和漏区 6 三者排列成第一直线，第二顶栅 4b 与第一顶栅 4a 排列成第二直线，且第二直线与第一直线重合。
基底 1 和介质层 3 之间设有导电层，基底 1 采用玻璃，导电层采用铟锡氧化物（ ITO ），介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30 nm ；源区 5 与第一顶栅 4a 的横向距离为 10 μ m 。
需要说明的是，本实施例中的基板 1 与介质层 3 之间可以不设置导电层，第二顶栅 4b 与介质层 3 的界面形成等效电容，使第二顶栅 4b 能够有效调控沟道区 7 的载流子浓度，从而调节本发明改良栅结构的薄膜晶体管的阈值电压、漏电流、电流开关比等电学性能。本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。如果没有底栅，则增加一沟道外顶栅代替底栅调控沟道。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与底栅 2 的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，因此，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，，其余的栅极，包括底栅 2 和第二顶栅 4b 都具有可以调控沟道区 7 的功能，通过改变底栅 2 和第二顶栅 4b 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果。
设源漏电压 VDS=1.5V ，漏区电压 Vss=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 0.7V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 0.7V 即记为输出为 0 ，定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l/L=1/1.5 ，可以得到（ l为第一顶栅 4a 到源区的距离） l =10μm ，所以当 l≥ 10μm ，可以得到 VG3 ≥ 1V 。于是可以得到 OR 门逻辑，如表 2 所示，当 VG1 和 VG2 都为 0 ， IDS=0 ， VG3=0 ，在底栅上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V 。
实施例 13
一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有三个顶栅，以及和这三个顶栅形成耦合的底栅，三个顶栅分别为第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c ，其中第一顶栅 4a 处在沟道区 7 内且与源区 5 和漏区 6 三者排列成第一直线，第二顶栅 4b 和第三顶栅 4c 位于第一直线的同侧，第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c 排列成第二直线，且第二直线与第一直线垂直，基底 1 兼做底栅。 如果没有底栅，则增加一沟道外顶栅代替底栅调控沟道。
基底 1 采用单表面为导电层的玻璃，其导电层采用铟锡氧化物（ ITO ）与 介质层 3 贴合 ，介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30 nm ；源区 5 与第一顶栅 4a 的横向距离为 10 μ m 。
需要说明的是，本实施例中的基板 1 与介质层 3 之间可以不设置导电层，第二顶栅 4b 与介质层 3 的界面形成等效电容，第三顶栅 4c 与介质层 3 的界面也形成等效电容，这两个电容相互耦合，使第二顶栅 4b 和第三顶栅 4c 能够有效调控沟道区 7 的载流子浓度，从而调节本发明改良栅结构的薄膜晶体管的阈值电压、漏电流、电流开关比等电学性能。
本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，第三顶栅 4c 的电压为 0V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与底栅（基底 1 兼做）的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，因此，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，其余的栅极，包括底栅、第二顶栅 4b 和第三顶栅 4c 都具有可以调控沟道区 7 的功能，通过改变底栅、第二顶栅 4b 和第三顶栅 4c 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果。
该实施例中的晶体管具有三个顶栅，由于第三顶栅 4c 可以调控沟道区的电位、即电子浓度，因此单个晶体管可以实现多种逻辑功能。
如果第三顶栅 4c 的电压 VG4=0V ，假设源漏电压 VDS=1.5V ，漏区电压 VSS=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 1V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 1V 即记为输出为 0 ，（同理定义 VG1 ， VG2 的输入输出状态）定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l /L=1/1.5 ，可以得到（第一顶栅 4a 到源区的距离） l=10μm 。所以当 l ≥ 10μm ，可以得到 VG3 ≥ 1V 。于是可以得到 OR 门逻辑，如表 3 所示，当底栅的电压 VG1 和第二顶栅 4b 的电压 VG2 都为 0 ， IDS=0 ， VG3=0 ，在底栅上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V ，同样可以得到表 2 。如果第三顶栅 4c 的电压 VG4=1V ，那么 IDS 很难为零，沟道区常开，如果 VG4=-1V ，那 IDS 很难大于漏电流，沟道为关断状态，因此可实现与门逻辑，如表 4 所示。
实施例 14
一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有三个顶栅，以及和这三个顶栅形成耦合的底栅 2 ，三个顶栅分别为第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c ，其中第一顶栅 4a 处在沟道区 7 内且与源区 5 和漏区 6 三者排列成第一直线，第二顶栅 4b 和第三顶栅 4c 位于第一直线的同侧，第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c 排列成第二直线，且第二直线与第一直线垂直，底栅 2 位于基底 1 和介质层 3 之间，底栅 2 分布在基底 1 上的局部区域， 基底 1 上开设有与底栅 2 位置相应的容置槽， 且底栅 2 的面积至少能够控制沟道区 7 。 如果没有底栅，则增加一沟道外顶栅代替底栅调控沟道。
基底 1 和介质层 3 之间设有导电层，基底 1 采用玻璃，导电层采用铟锡氧化物（ ITO ），介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30nm ；源区 5 与第一顶栅 4a 的横向距离为 10 μ m 。
需要说明的是，本实施例中的基板 1 与介质层 3 之间可以不设置导电层，第二顶栅 4b 与介质层 3 的界面形成的等效电容，第三顶栅 4c 与介质层 3 的界面也形成等效电容，这两个电容相互耦合，使第二顶栅 4b 和第三顶栅 4c 能够有效调控沟道区 7 的载流子浓度，从而调节本发明改良栅结构的薄膜晶体管的阈值电压、漏电流、电流开关比等电学性能。
本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，第三顶栅 4c 的电压为 0V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与底栅 2 的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，因此，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，其余的栅极，包括底栅 2 、第二顶栅 4b 和第三顶栅 4c 都具有可以调控沟道区 7 的功能，通过改变底栅 2 、第二顶栅 4b 和第三顶栅 4c 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果。
该实施例中的晶体管具有三个顶栅，由于第三顶栅 4c 可以调控沟道区的电位、即电子浓度，因此单个晶体管可以实现多种逻辑功能。
如果第三顶栅 4c 的电压 VG4=0V ，假设源漏电压 VDS=1.5V ，漏区电压 VSS=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 1V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 1V 即记为输出为 0 ，（同理定义 VG1 ， VG2 的输入输出状态）定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l/L=1/1.5 ，可以得到（第一顶栅 4a 到源区的距离） l=10μm 。所以当 l≥ 10μm ，可以得到 VG3>1V 。于是可以得到 OR 门逻辑，如表 3 所示，当底栅 2 的电压 VG1 和第二顶栅 4b 的电压 VG2 都为 0 ， IDS=0 ， VG3=0 ，在底栅 2 上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V ，同样可以得到表 2 。如果第三顶栅 4c 的电压 VG4=1V ，那么沟道电流 IDS 很难为零，沟道区常开，如果 VG4=-1V ，那沟道电流 IDS 很难大于漏电流，沟道为关断状态，因此可实现与门逻辑，如表 4 所示。
实施例 15
如图 5 所示，一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有三个顶栅，以及和这三个顶栅形成耦合的底栅，三个顶栅分别为第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c ，其中第一顶栅 4a 处在沟道区 7 内且与源区 5 和漏区 6 三者排列成第一直线，第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c 排列成第二直线，且第二直线与第一直线重合，第二顶栅 4b 和第三顶栅 4c 其中一个在源区 5 的一侧，且远离漏区 6 ，另一个在漏区 6 的一侧，且远离源区 5 ，基底 1 兼做底栅。 如果没有底栅，则增加一沟道外顶栅代替底栅调控沟道。
基底 1 采用单表面为导电层的玻璃，其导电层采用铟锡氧化物（ ITO ）与 介质层 3 贴合 ，介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30nm ；源区 5 与第一顶栅 4a 的横向距离为 10 μ m 。
需要说明的是，本实施例中的基板 1 与介质层 3 之间可以不设置导电层，第二顶栅 4b 与介质层 3 的界面形成等效电容，第三顶栅 4c 与介质层 3 的界面也形成等效电容这两个电容相互耦合，使第二顶栅 4b 和第三顶栅 4c 能够有效调控沟道区 7 的载流子浓度，从而调节本发明改良栅结构的薄膜晶体管的阈值电压、漏电流、电流开关比等电学性能。
本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，第三顶栅 4c 的电压为 0V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与底栅（基底 1 兼做）的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，因此，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，其余的栅极，包括底栅、第二顶栅 4b 和第三顶栅 4c 都具有可以调控沟道区 7 的功能，通过改变底栅、第二顶栅 4b 和第三顶栅 4c 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果。
该实施例中的晶体管具有三个顶栅，由于第三顶栅 4c 可以调控沟道区的电位、即电子浓度，因此单个晶体管可以实现多种逻辑功能。
如果第三顶栅 4c 的电压 VG4=0V ，假设源漏电压 VDS=1.5V ，漏区电压 VSS=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 1V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 1V 即记为输出为 0 ，（同理定义 VG1 ， VG2 的输入输出状态）定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l /L=1/1.5 ，可以得到（第一顶栅 4a 到源区的距离） l =10μm 。所以当 l≥ 10μm ，可以得到 VG3 ≥ 1V 。于是可以得到 OR 门逻辑，如表 3 所示，当底栅的电压 VG1 和第二顶栅 4b 的电压 VG2 都为 0 ， IDS=0 ， VG3=0 ，在底栅上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V ，同样可以得到表 2 。如果第三顶栅 4c 的电压 VG4=1V ，那么 IDS 很难为零，沟道区常开，如果 VG4=-1V ，那 IDS 很难大于漏电流，沟道为关断状态，因此可实现与门逻辑，如表 4 所示。
实施例 16
如图 6 所示，一种改良栅结构的晶体管，包括基底 1 和处在基底 1 上的介质层 3 、介质层 3 上设有一源区 5 、一漏区 6 以及连通在源区 5 和漏区 6 之间的沟道区 7 ，还设有三个顶栅，以及和这三个顶栅形成耦合的底栅 2 ，三个顶栅分别为第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c ，其中第一顶栅 4a 处在沟道区 7 内且与源区 5 和漏区 6 三者排列成第一直线，第一顶栅 4a 、第二顶栅 4b 和第三顶栅 4c 排列成第二直线，且第二直线与第一直线重合，第二顶栅 4b 和第三顶栅 4c 其中一个在源区 5 的一侧，且远离漏区 6 ，另一个在漏区 6 的一侧，且远离源区 5 ，基底 1 兼做底栅。 如果没有底栅，则增加一沟道外顶栅代替底栅调控沟道。 底栅 2 位于基底 1 和介质层 3 之间， 基底 1 上开设有与底栅 2 位置相应的容置槽， 底栅 2 分布在基底 1 上的局部区域，且底栅 2 的面积至少能够控制沟道区 7 。
基底 1 和介质层 3 之间设有导电层，基底 1 采用玻璃，导电层采用铟锡氧化物（ ITO ），介质层 3 采用二氧化硅，且介质层 3 的物理厚度为 0.5 μ m ；源区 5 、漏区 6 、第一顶栅 4a 、第二顶栅 4b 和沟道区 7 均采用铟锡氧化物（ ITO ）制成，其中，沟道区 7 为半导体材料，其余为导体材料。
沟道区 7 的长度为 15 μ m ，沟道区 7 的宽度为 1 μ m ，沟道区 7 的电学厚度为 30nm ；源区 5 与第一顶栅 4a 的横向距离为 10 μ m 。
需要说明的是，本实施例中的基板 1 与介质层 3 之间可以不设置导电层，第二顶栅 4b 与介质层 3 的界面形成等效电容，第三顶栅 4c 与介质层 3 的界面也形成等效电容，这两个电容相互耦合，使第二顶栅 4b 和第三顶栅 4c 能够有效调控沟道区 7 的载流子浓度，从而调节本发明改良栅结构的薄膜晶体管的阈值电压、漏电流、电流开关比等电学性能。如果没有底栅，则增加一沟道外顶栅代替底栅调控沟道。
本实施例中的介质层 3 采用无机材料制备，相对于采用有机材料制备，其稳定性和可靠性相对较好，且能够与传统半导体工艺线相兼容，制备相对比较简单。
本实施例提供的改良栅结构的薄膜晶体管具有逻辑电路功能，当源漏电压 VDS=1.5V ，第三顶栅 4c 的电压为 0V ，改变位于沟道区 7 外部的第二顶栅 4b 的电压 VG2 为 -0.5V 、 0V 、 0.5V 、 1V ，则源漏两端的沟道电流 IDS 与底栅 2 的电压 VG1 的关系如图 7 所示，在四种情况下，本实施例改良栅结构的薄膜晶体管的阈值电压 VTH 分别为 1.1 V 、 0.85V 、 0.45V 、 -0.05V ，同时电流开关比也得到显著的调控改变，晶体管作为反相器用时 VG1 输入与 VG3 输出关系见图 8 ，因此，本实施例中除了沟道区 7 内的第一顶栅 4a 以外，其余的栅极，包括底栅 2 、第二顶栅 4b 和第三顶栅 4c 都具有可以调控沟道区 7 的功能，通过改变底栅 2 、第二顶栅 4b 和第三顶栅 4c 的电压控制沟道区 7 的输出，获得理想的反相器输入输出结果。
该实施例中的晶体管具有三个顶栅，由于第三顶栅 4c 可以调控沟道区的电位、即电子浓度，因此单个晶体管可以实现多种逻辑功能。
如果第三顶栅 4c 的电压 VG4=0V ，假设源漏电压 VDS=1.5V ，漏区电压 VSS=0V ，第一顶栅 4a 的输出电压 VG3 ≥ 1V ，即记为输出为 1 ，第一顶栅 4a 的输出电压 VG3 ＜ 1V 即记为输出为 0 ，（同理定义 VG1 ， VG2 的输入输出状态）定义沟道区的长度 L=15μm ， VDS=1.5V ，由 l /L=1/1.5 ，可以得到（第一顶栅 4a 到源区的距离） l =10μm 。所以当 l ≥ 10μm ，可以得到 VG3l ≥ 1V 。于是可以得到 OR 门逻辑，如表 3 所示，当底栅 2 的电压 VG1 和第二顶栅 4b 的电压 VG2 都为 0 ， IDS=0 ， VG3=0 ，在底栅 2 上施加电压或者在第二顶栅 4b 上施加电压时， VG3=1V ，同样可以得到表 2 。如果第三顶栅 4c 的电压 VG4=1V ，那么 IDS 很难为零，沟道区常开，如果 VG4=-1V ，那 IDS 很难大于漏电流，沟道为关断状态，因此可实现与门逻辑，如表 4 所示。

Claims (10)

  1. 1 、一种改良栅结构的晶体管，包括基底（ 1 ）和处在基底（ 1 ）上的介质层（ 3 ），所述介质层（ 3 ）上设有一源区（ 5 ）、一漏区（ 6 ）以及连通在所述源区（ 5 ）和漏区（ 6 ）之间的沟道区（ 7 ），其特征在于，所述沟道区（ 7 ）内设有第一顶栅（ 4a ）作为晶体管的输出极，其输出的逻辑值在沟道区导通时为逻辑 1 ，在沟道区截断时为逻辑 0 ；
    所述晶体管还设有至少两个控制沟道区（ 7 ）的输入极；
    其中至少有一个输入极为第二顶栅（ 4b ）；
    还有至少有一个输入极为第三顶栅（ 4c ）和 / 或底栅；
    所述第二顶栅和第三顶栅均位于所述介质层（ 3 ）上，且处在所述沟道区（ 7 ）的旁边。
  2. 2 、如权利要求 1 所述的改良栅结构的晶体管，其特征在于，所述底栅（ 2 ）处在基底（ 1 ）和介质层（ 3 ）之间或由所述基底（ 1 ）兼做。
  3. 3 、如权利要求 2 所述的改良栅结构的晶体管，其特征在于， 所述底栅（ 2 ）处在基底（ 1 ）和介质层（ 3 ）之间，所述底栅（ 2 ）分布在基底（ 1 ）上的局部区域，基底（ 1 ）上开设有与底栅（ 2 ）位置相应的容置槽，所述底栅（ 2 ）的面积至少能够 与处在沟道区（ 7 ）旁边的顶栅形成耦合， 以控制所述沟道区（ 7 ）。
  4. 4 、如权利要求 1 或 2 或 3 所述的改良栅结构的晶体管，其特征在于，所述顶栅为两个，分别为第一顶栅（ 4a ）和第二顶栅（ 4b ），其中第一顶栅（ 4a ）处在所述沟道区（ 7 ）内，且与源区（ 5 ）和漏区（ 6 ）三者排列形成第一直线，第二顶栅（ 4b ）位于所述第一直线的一侧。
  5. 5 、如权利要求 1 或 2 或 3 所述的改良栅结构的晶体管，其特征在于，所述顶栅为两个，分别为第一顶栅（ 4a ）和第二顶栅（ 4b ），其中第一顶栅（ 4a ）处在所述沟道区（ 7 ）内，且与源区（ 5 ）和漏区（ 6 ）三者排列成第一直线，第二顶栅（ 4b ）位于所述第一直线上。
  6. 6 、如权利要求 1 或 2 或 3 所述的改良栅结构的晶体管，其特征在于，所述顶栅为三个，分别为第一顶栅（ 4a ）、第二顶栅（ 4b ）和第三顶栅（ 4c ），其中第一顶栅（ 4a ）处在所述沟道区（ 7 ）内，且与源区（ 5 ）和漏区（ 6 ）三者排列成第一直线，第二顶栅（ 4b ）和第三顶栅（ 4c ）分别位于所述第一直线的两侧，或位于所述第一直线的同侧。
  7. 7 、 如权利要求 6 所述的改良栅结构的晶体管，其特征在于， 所述第二顶栅（ 4b ）和第三顶栅（ 4c ）排列成第二直线，且第二直线与第一直线垂直。
  8. 8 、 如权利要求 1 或 2 或 3 所述的改良栅结构的晶体管，其特征在于，所述顶栅为三个， 分别为第一顶栅（ 4a ）、第二顶栅（ 4b ）和第三顶栅（ 4c ），其中第一顶栅（ 4a ）处在所述沟道区（ 7 ）内，且与源区（ 5 ）和漏区（ 6 ）三者排列成第一直线，所述第二顶栅（ 4b ）和第三顶栅（ 4c ）排列成第二直线，且第二直线与第一直线重合或平行。
  9. 9 、 如权利要求 1 所述的改良栅结构的晶体管，其特征在于，输 入 极不包含有底栅，所述顶栅为四个， 分别为第一顶栅（ 4a ）、第二顶栅（ 4b ）、第三顶栅（ 4c ）和第四顶栅，其中第二顶栅（ 4b ）、第三顶栅（ 4c ）和第四顶栅均作为输入极。
  10. 10 、 如权利要求 1 所述的改良栅结构的晶体管，其特征在于， 所述基板与介质层之间设有导电层。
PCT/CN2013/072746 2013-03-15 2013-03-15 一种改良栅结构的晶体管 WO2014139167A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2013/072746 WO2014139167A1 (zh) 2013-03-15 2013-03-15 一种改良栅结构的晶体管

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2013/072746 WO2014139167A1 (zh) 2013-03-15 2013-03-15 一种改良栅结构的晶体管

Publications (1)

Publication Number Publication Date
WO2014139167A1 true WO2014139167A1 (zh) 2014-09-18

Family

ID=51535845

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/072746 WO2014139167A1 (zh) 2013-03-15 2013-03-15 一种改良栅结构的晶体管

Country Status (1)

Country Link
WO (1) WO2014139167A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7652330B1 (en) * 2003-07-03 2010-01-26 American Semiconductor, Inc. Independently-double-gated combinational logic
US20110187412A1 (en) * 2008-06-13 2011-08-04 Tso-Ping Ma Complementary metal oxide semiconductor devices
US20120146043A1 (en) * 2009-09-01 2012-06-14 Sharp Kabushiki Kaisha Semiconductor device, active matrix substrate, and display device
US20120175594A1 (en) * 2011-01-07 2012-07-12 International Business Machines Corporation Graphene Devices with Local Dual Gates
CN103178116A (zh) * 2013-03-15 2013-06-26 中国科学院宁波材料技术与工程研究所 一种改良栅结构的晶体管

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7652330B1 (en) * 2003-07-03 2010-01-26 American Semiconductor, Inc. Independently-double-gated combinational logic
US20110187412A1 (en) * 2008-06-13 2011-08-04 Tso-Ping Ma Complementary metal oxide semiconductor devices
US20120146043A1 (en) * 2009-09-01 2012-06-14 Sharp Kabushiki Kaisha Semiconductor device, active matrix substrate, and display device
US20120175594A1 (en) * 2011-01-07 2012-07-12 International Business Machines Corporation Graphene Devices with Local Dual Gates
CN103178116A (zh) * 2013-03-15 2013-06-26 中国科学院宁波材料技术与工程研究所 一种改良栅结构的晶体管

Similar Documents

Publication Publication Date Title
US11196414B2 (en) Circuit and method for controlling charge injection in radio frequency switches
US5596208A (en) Article comprising an organic thin film transistor
Hirama et al. Diamond field-effect transistors with 1.3 A/mm drain current density by Al2O3 passivation layer
WO2012097564A1 (zh) 一种自对准薄膜晶体管的制作方法
TWI297181B (en) Active element and switch circuit device
JP5386034B2 (ja) Ｍｏｓｆｅｔ及びデュアルゲートｊｆｅｔを含む電子回路
JPH0439770B2 (zh)
JPH07142722A (ja) 半導体装置
US8466566B2 (en) Semiconductor device, method for manufacturing of semiconductor device, and switching circuit
Kudara et al. High output power density of 2DHG diamond MOSFETs with thick ALD-Al 2 O 3
WO2015032296A1 (zh) 隧穿场效应晶体管
JPS59135760A (ja) 低い導通抵抗を有する通常オフの半導体装置及び回路類推
WO2009107993A2 (en) High current control circuit including metal-insulator transition device, and system including the high current control circuit
WO2014139167A1 (zh) 一种改良栅结构的晶体管
US5287072A (en) Semiconductor device for improving high-frequency characteristics and avoiding chip cracking
JPH08503576A (ja) 線形電圧制御抵抗素子
US5633513A (en) Diamond film field effect transistor
JPS60171771A (ja) 絶縁ゲ−ト半導体装置
WO2015182888A1 (ko) 산화물 반도체 박막 트랜지스터의 제조방법
US20030052373A1 (en) Field effect transistor formed on an insulating substrate and integrated circuit thereof
JP2018078146A (ja) 半導体装置
US6750698B1 (en) Cascade circuits utilizing normally-off junction field effect transistors for low on-resistance and low voltage applications
WO2017111275A1 (ko) 박막 트랜지스터 기판, 이를 포함하는 표시패널 및 표시장치
Liu et al. High current output hydrogenated diamond triple-gate MOSFETs
JP3273985B2 (ja) ダイヤモンド電界効果トランジスタ

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13878208

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13878208

Country of ref document: EP

Kind code of ref document: A1