WO2014131242A1 - Substrat à réseau de transistors en couches minces, procédé de préparation et dispositif d'affichage - Google Patents

Substrat à réseau de transistors en couches minces, procédé de préparation et dispositif d'affichage Download PDF

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Publication number
WO2014131242A1
WO2014131242A1 PCT/CN2013/074957 CN2013074957W WO2014131242A1 WO 2014131242 A1 WO2014131242 A1 WO 2014131242A1 CN 2013074957 W CN2013074957 W CN 2013074957W WO 2014131242 A1 WO2014131242 A1 WO 2014131242A1
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electrode layer
layer
pixel electrode
thin film
film transistor
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PCT/CN2013/074957
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English (en)
Chinese (zh)
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孔祥永
刘晓娣
成军
陈江博
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京东方科技集团股份有限公司
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Publication of WO2014131242A1 publication Critical patent/WO2014131242A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes

Definitions

  • Embodiments of the present invention relate to a method of fabricating a thin film transistor array substrate, a thin film transistor array substrate, and a display device. Background technique
  • TFT Thin Film Transistor
  • LCD liquid crystal display
  • OLED Organic Light-Emitting Diode
  • a thin film transistor As a driving element of a display device, a thin film transistor is directly related to the development direction of a high-performance flat panel display device.
  • the thin film transistor generally includes a gate electrode layer 2, a gate insulating layer 3, an active layer 4, a source/drain electrode layer 6, a passivation layer 7, and a pixel electrode layer 8, which are sequentially formed on the substrate 1, and the source/drain electrode layer 6
  • the pixel electrode layer 8 is connected to the via hole.
  • FIG. 1 is a cross-sectional view of the TFT formed by using the amorphous silicon material.
  • the upper layer of the active layer is an ohmic contact layer 51.
  • the cross section of the TFT formed by the metal oxide semiconductor material of the active layer 4 is as shown in FIG.
  • Above the source layer is an etch stop layer 52.
  • the pixel electrode layers are formed using indium tin oxide (ITO).
  • ITO indium tin oxide
  • a certain thickness of the indium tin oxide film layer is first formed by sputtering, and then the pattern is transferred to the indium tin oxide film layer by a photolithography process such as mask exposure.
  • a photolithography process such as mask exposure.
  • the thin film transistor array substrate preparation method encapsulates a production process of a thin film transistor array substrate, and improves utilization of a pixel electrode forming material.
  • An aspect of the invention provides a method for fabricating a thin film transistor array substrate, comprising the steps of: forming a gate electrode layer, a gate insulating layer, an active layer, a source/drain electrode layer, a passivation layer, and a pixel electrode layer on a substrate,
  • the passivation layer is formed into a structure pattern including via holes by a patterning process
  • the pixel electrode layer is formed in a structure pattern region by a dropping method, and the source/drain electrode layer and the pixel electrode layer are connected through via holes.
  • forming a structural pattern including via holes in the passivation layer is formed by a patterning process: exposing the photoresist over the passivation layer with a halftone mask or a gray tone mask, correspondingly forming The photoresist at the via region is completely removed, and the photoresist corresponding to the region where the pixel electrode layer is formed is partially removed.
  • the method further includes: performing curing and annealing treatment on the pixel electrode layer.
  • the material for forming the pixel electrode layer is a material containing an indium element, a tin element, and an oxygen element, and the material containing the indium element, the tin element, and the oxygen element is previously formed into a sol or ink and poured into a nozzle. Dropping through the nozzle is in the area of the structural pattern.
  • the material for forming the pixel electrode layer is indium tin oxide sol or ink
  • the indium tin oxide sol or ink is obtained by the following method: Pressing InCl 3 .4H 2 0 and SnCl 4 .5H 2 0 as 1 : ( 1-3 ) The ratio is dissolved in an aqueous solution; or, In 2 0 3 and SnCl 4 .5H 2 0 are dissolved in C 2 H 5 COOH in a ratio of 1: (2-6 ).
  • the temperature at which the pixel electrode layer is annealed is in the range of 300 to 600 °C.
  • the thickness of the pixel electrode layer ranges from 20 to 150 nm.
  • the passivation layer is formed of a single layer film layer or a multilayer composite film layer using at least two materials of silicon oxide, silicon nitride, germanium oxide, and aluminum oxide, and the thickness of the passivation layer is 300-500nm.
  • Another aspect of the present invention provides a thin film transistor array substrate formed by the above-described thin film transistor array substrate fabrication method.
  • Still another aspect of the present invention provides a display device including the above-described thin film transistor array Substrate.
  • FIG. 1 is a cross-sectional view of a conventional thin film transistor array substrate (an active layer is formed using an amorphous silicon material);
  • FIG. 2 is a cross-sectional view of a conventional thin film transistor array substrate (using a metal oxide semiconductor material to form an active layer);
  • FIG. 3 is a cross-sectional view showing a thin film transistor array substrate in Embodiment 1 of the present invention.
  • FIG. 4 is a view showing a process of preparing a thin film transistor array substrate of FIG. 3;
  • Figure 5 is a cross-sectional view showing a thin film transistor array substrate in Embodiment 2 of the present invention.
  • Fig. 6 is a view showing the process of preparing the thin film transistor array substrate of Fig. 5.
  • Embodiments of the present invention provide a method for fabricating a thin film transistor array substrate, including the steps of: forming a gate electrode layer, a gate insulating layer, an active layer, a source/drain electrode layer, and a passivation layer on a substrate, wherein The passivation layer forms a structure pattern including via holes by a patterning process, and the pixel electrode layer is formed in a structure pattern region by a dropping method, and the source/drain electrode layer and the pixel electrode layer are connected through via holes.
  • Embodiments of the present invention provide a thin film transistor array substrate formed by the above-described thin film transistor array substrate preparation method.
  • Embodiments of the present invention provide a display device including the above-described thin film transistor array substrate.
  • Example 1 Example 1:
  • the thin film transistor array substrate in this embodiment includes a gate electrode layer 2, a gate insulating layer 3, an active layer 4, a source/drain electrode layer 6, a passivation layer 7, and sequentially formed on the substrate 1.
  • the passivation layer 7 is formed into a structure pattern including via holes by a patterning process, and the pixel electrode layer 8 is formed in a structure pattern region by a dropping method, and the source/drain electrode layer 6 and the pixel electrode layer 8 pass through Hole connection.
  • the source/drain electrode layer 6 includes source and drain electrodes spaced apart from each other with a portion of the active layer 4 therebetween being a channel.
  • the active layer 4 is formed of an amorphous silicon material, and correspondingly, an ohmic contact layer 51 is formed above the active layer 4.
  • the ohmic contact layer 51 is formed, for example, of an amorphous silicon material doped with phosphorus, and a typical cross-sectional view of the thin film transistor array substrate is shown in FIG.
  • the method for preparing a thin film transistor array substrate in this embodiment specifically includes the following steps:
  • a gate electrode layer, a gate insulating layer, an active layer, and a source/drain electrode layer are sequentially formed on the substrate.
  • the gate electrode layer 2 is first formed over the substrate 1.
  • the gate electrode layer 2 may be formed of at least one of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu).
  • a layer or a multilayer composite laminate preferably a single layer film or a multilayer composite film layer composed of a phase (Mo ), aluminum (A1 ) or an alloy containing phase (Mo) or aluminum (A1), the gate electrode layer
  • the thickness of 2 ranges from 100 nm to 500 nm.
  • a gate insulating layer 3 is deposited over the gate electrode layer 2.
  • the gate insulating layer 3 one or two of silicon oxide (SiO x ), silicon nitride (SiN x ), hafnium oxide (HfO x ), silicon oxynitride (SiON), aluminum oxide (A10 x ), etc. may be used.
  • a multilayer composite film layer is formed.
  • the structure of the gate insulating layer 3 may be a stacked structure formed using SiN x /SiO x or a stacked structure formed using SiN x /SiON/SiO x , and the thickness of the gate insulating layer is 100- 400nm.
  • the gate insulating layer 3 may be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD).
  • an active layer 4 is formed over the gate insulating layer 3.
  • the active layer 4 is formed of an amorphous silicon material, and the amorphous silicon material can be formed by using plasma enhanced chemical vapor deposition (PECVD), and the thickness of the active layer 4 is 30- 200nm.
  • PECVD plasma enhanced chemical vapor deposition
  • an ohmic contact layer 51 is formed over the active layer 4.
  • the ohmic contact layer may be formed of a material of amorphous silicon doped with phosphorus, which is formed by a PECVD method, and the ohmic contact layer has a thickness ranging from 30 to 100 nm.
  • a source/drain electrode layer 6 is formed over the ohmic contact layer 51.
  • the source/drain electrode layer 6 may be formed of at least one of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu).
  • Mo molybdenum
  • MoNb molybdenum-niobium alloy
  • Al aluminum-niobium alloy
  • Ti titanium
  • Cu copper
  • a single-layer or multi-layer composite laminate preferably a single layer film or a multilayer composite film layer composed of a phase (Mo), aluminum (A1) or an alloy containing phase (Mo) or aluminum (A1), the source leakage
  • the thickness of the pole layer ranges from 100 to 500 nm.
  • a passivation layer 7 is formed over the source/drain electrode layer 6.
  • the passivation layer 7 may be formed of at least two materials of silicon oxide (SiO x ), silicon nitride (SiN x ), hafnium oxide (HfO x ), aluminum oxide (A10 x ), and the like.
  • the film layer or the multilayer composite film layer may be formed by plasma enhanced chemical vapor deposition (PECVD), and the passivation layer has a thickness ranging from 300 to 500 nm.
  • the passivation layer 7 is formed into a structure pattern including via holes by a patterning process: exposing the photoresist over the passivation layer with a halftone mask or a gray tone mask in the passivation layer Corresponding to forming the photoresist at the via region as a full exposure process, the photoresist corresponding to the region where the pixel electrode layer is formed is a half exposure process.
  • a patterning process may be performed on the passivation layer 7 to form a pattern of the pixel electrode layer and the via hole at the same time.
  • the patterning process generally includes steps of photoresist coating, exposure, development, etching, photoresist stripping, and the like. For a film layer having a photosensitive property itself, the use of a photoresist can be omitted, and the patterning process can eliminate the steps of photoresist coating, etching, and photoresist stripping.
  • a layer of photoresist is applied over the passivation layer 7, and in the case of a positive photoresist, a halftone mask or a gray tone mask is used to form a via 9
  • the photoresist of the region is subjected to a full exposure process, and the photoresist of the deposition region of the pixel electrode layer 8 to be formed is subjected to a half exposure (partial exposure) process, and the exposed photoresist is developed, and the photolithography is fully exposed.
  • the glue is removed and the half exposed photoresist is partially removed to become thin.
  • the photoresist corresponding to the region in which the via 9 is formed is subjected to a non-exposure process, and the photoresist of the deposition region of the pixel electrode layer 8 to be formed is subjected to a half exposure (partial exposure) process.
  • the exposed photoresist is subjected to development processing, the unexposed photoresist is removed, and the half-exposed photoresist is partially removed to be thinned.
  • etching is performed on the passivation layer 7 corresponding to the region where the via 9 is formed, and the etching time is controlled according to the specific production process and the layer thickness of the passivation layer to achieve the design.
  • the desired depth is preferably (the passivation layer 7 is not completely etched at this time); then, the photoresist remaining in the half-exposure region corresponding to the region where the pixel electrode layer 8 is formed is passed through an ashing process and a dry etching method.
  • the processed photoresist as an etch mask, the region corresponding to the via hole and the region forming the pixel electrode layer are integrally etched, and the pixel electrode is formed while the via 9 is etched.
  • the structural pattern of the layer is controlled according to the specific production process and the layer thickness of the passivation layer to achieve the design.
  • the desired depth is preferably (the passivation layer 7 is not completely etched at this time); then, the photoresist remaining in the half-exposure region corresponding to the region where the
  • the material for forming the pixel electrode layer is dropped through the nozzle 10 in the structural pattern region to form a transparent pixel electrode layer 8.
  • the material for forming the pixel electrode layer is a material containing an indium element, a tin element, and an oxygen element, and the material containing the indium element, the tin element, and the oxygen element is previously formed into a sol or ink and poured into the nozzle. Dropping through the nozzle is in the area of the structural pattern.
  • the material for forming the pixel electrode layer is an indium tin oxide (ITO) sol or ink.
  • the indium tin oxide sol or ink is obtained, for example, by the following method: InCl 4H 2 0 (indium trichloride tetrahydrate) and SnCl 4 '5H 2 0 (tin tetrachloride pentahydrate) are as follows: (1-3) Proportionally dissolved in an aqueous solution, preferably in a ratio of 1:1 ratio of InCl 3 .4H 2 0 (indium trichloride tetrachloride) and SnCl 4 .5H 2 0 (tin tetrachloride pentahydrate); or In 2 0 3 (indium trioxide) and SnCl 4 '5H 2 0 (tin tetrachloride pentahydrate) are dissolved in C 2 H 5 COOH (propionic acid) in a ratio of 1: (2-6 ), preferably In 2 0 3 (indium trioxide) and SnCl 4 '5H 2 0 (t
  • the formed pixel electrode layer 8 is cured and annealed.
  • the temperature range of the annealing process of the pixel electrode layer 8 is, for example, 300-600 ° C, which is higher than the annealing temperature (230-300 ° C) of the pixel electrode layer in the prior art, so that the pixel electrode layer can be better. Crystallization, while achieving better electrical conductivity.
  • the thickness of the pixel electrode layer may range from 20 to 150 nm.
  • This embodiment also provides a display device including a thin film transistor array substrate formed by the method for fabricating a thin film transistor array substrate of the present embodiment.
  • the active layer 4 in the thin film transistor array substrate of the present embodiment is formed of a metal oxide semiconductor, and a typical cross-sectional view of the thin film transistor array substrate is as shown in FIG.
  • an active layer 4 is formed over the gate insulating layer 3.
  • the active layer 4 is formed of a metal oxide semiconductor, and the metal oxide semiconductor may be composed of an oxygen element (0), an indium (In), a gallium (Ga), and a (Zn). At least two elements in tin (Sn) are formed (ie, they must contain oxygen).
  • the active layer may be formed using indium gallium oxide (IGZO), indium oxide (IZO), indium tin oxide (InSnO), or indium gallium tin oxide (InGaSnO), preferably IGZO and IZO.
  • the active layer is formed by a sputtering method or an inkjet printing method or a sol-plating method and an annealing treatment, and the annealing temperature may range from 200 to 500 ° C, and the thickness of the active layer may range from 10 to 100 nm.
  • an etch stop layer 52 is further formed on the active layer, and the etch stop layer may be silicon oxide (SiO x ), silicon nitride (SiN x ), or hafnium oxide (HfO x ). At least two (two or three) materials of aluminum oxide (A10 x ) form a single layer film or a multilayer composite film layer, and the etch barrier layer may have a thickness ranging from 50 to 200 nm.
  • the specific preparation process of the gate electrode layer 2, the gate insulating layer 3, the source/drain electrode layer 6, and the passivation layer 7 in this embodiment includes the materials selected for each, the corresponding layer thickness and the formation manner, respectively.
  • the embodiment 1 is the same and will not be described here.
  • the gate insulating layer 3, the passivation layer 7 and the etch stop layer 52 have a hydrogen content of 10% or less.
  • the hydrogen content in the above three layer structures is less than or equal to 10%.
  • the present embodiment provides a display device including a thin film transistor array substrate formed by the thin film transistor array substrate manufacturing method of the present embodiment.
  • the pixel electrode layer and the structure pattern of the via hole in the thin film transistor array substrate described in Embodiments 1 and 2 can also be used as a structural pattern region for forming an evaporated OLED device, or to form a printing or spraying.
  • Embodiments 1 and 2 form a pattern structure required for a pixel electrode layer and a via hole by patterning in a passivation layer of a thin film transistor array substrate, and then indium tin oxide sol or ink for forming a pixel electrode layer A pixel electrode layer is formed by dropping a nozzle into a structure pattern region formed in the passivation layer.
  • the thin film transistor array substrate preparation method in Embodiments 1 and 2 reduces the step of forming a pixel electrode layer by a patterning process, reduces the usage of the mask, and improves the pixel electrode. The layer formation material utilization rate while reducing production costs.

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  • Liquid Crystal (AREA)

Abstract

L'invention concerne un procédé de préparation de substrat à réseau de transistors en couches minces, un substrat à réseau de transistors en couches minces et un dispositif d'affichage. Le procédé de préparation de substrat à réseau de transistors en couches minces comprend les étapes suivantes : formation d'une couche (2) d'électrode de grille, d'une couche (3) isolante de grille, d'une couche (4) active, d'une couche (6) d'électrode de source/drain, d'une couche (7) de passivation et d'une couche (8) d'électrode de pixels sur un substrat (1), un modèle de structure comprenant un trou traversant (9) étant formé sur la couche de passivation par le biais d'un processus de modélisation, la couche (8) d'électrode de pixels étant formée dans la région du motif de structure par un processus d'égouttement et la couche (6) d'électrode de source/drain étant connectée à la couche (8) d'électrode de pixels par le biais du trou traversant (9). En utilisant le procédé de préparation de substrat à réseau de transistors en couches minces, les étapes de formation de la couche d'électrode de pixels par le processus de modélisation sont réduites, l'utilisation d'un masque est réduite, le taux d'utilisation du matériau de formation d'électrode de pixels est amélioré et, en même temps, le coût de production est réduit.
PCT/CN2013/074957 2013-02-28 2013-04-28 Substrat à réseau de transistors en couches minces, procédé de préparation et dispositif d'affichage WO2014131242A1 (fr)

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CN201310064170.1A CN103151305B (zh) 2013-02-28 2013-02-28 一种薄膜晶体管阵列基板、制备方法以及显示装置

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CN103489882A (zh) * 2013-10-17 2014-01-01 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN103700673B (zh) * 2013-12-24 2017-07-04 京东方科技集团股份有限公司 一种显示装置、阵列基板及其制作方法
CN104538357B (zh) 2015-01-13 2018-05-01 合肥京东方光电科技有限公司 制作阵列基板的方法和阵列基板
CN105374852B (zh) * 2015-11-16 2019-10-11 Tcl集团股份有限公司 一种无像素bank的印刷型发光显示器及其制作方法
CN105470282B (zh) * 2015-11-20 2020-03-31 Tcl集团股份有限公司 一种无像素bank的TFT-OLED及制备方法
CN105336763B (zh) * 2015-11-26 2019-08-02 Tcl集团股份有限公司 一种发光显示器及其制备方法
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