WO2014131242A1 - Thin film transistor array substrate, preparation method and display device - Google Patents

Thin film transistor array substrate, preparation method and display device Download PDF

Info

Publication number
WO2014131242A1
WO2014131242A1 PCT/CN2013/074957 CN2013074957W WO2014131242A1 WO 2014131242 A1 WO2014131242 A1 WO 2014131242A1 CN 2013074957 W CN2013074957 W CN 2013074957W WO 2014131242 A1 WO2014131242 A1 WO 2014131242A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode layer
layer
pixel electrode
thin film
film transistor
Prior art date
Application number
PCT/CN2013/074957
Other languages
French (fr)
Chinese (zh)
Inventor
孔祥永
刘晓娣
成军
陈江博
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2014131242A1 publication Critical patent/WO2014131242A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes

Definitions

  • Embodiments of the present invention relate to a method of fabricating a thin film transistor array substrate, a thin film transistor array substrate, and a display device. Background technique
  • TFT Thin Film Transistor
  • LCD liquid crystal display
  • OLED Organic Light-Emitting Diode
  • a thin film transistor As a driving element of a display device, a thin film transistor is directly related to the development direction of a high-performance flat panel display device.
  • the thin film transistor generally includes a gate electrode layer 2, a gate insulating layer 3, an active layer 4, a source/drain electrode layer 6, a passivation layer 7, and a pixel electrode layer 8, which are sequentially formed on the substrate 1, and the source/drain electrode layer 6
  • the pixel electrode layer 8 is connected to the via hole.
  • FIG. 1 is a cross-sectional view of the TFT formed by using the amorphous silicon material.
  • the upper layer of the active layer is an ohmic contact layer 51.
  • the cross section of the TFT formed by the metal oxide semiconductor material of the active layer 4 is as shown in FIG.
  • Above the source layer is an etch stop layer 52.
  • the pixel electrode layers are formed using indium tin oxide (ITO).
  • ITO indium tin oxide
  • a certain thickness of the indium tin oxide film layer is first formed by sputtering, and then the pattern is transferred to the indium tin oxide film layer by a photolithography process such as mask exposure.
  • a photolithography process such as mask exposure.
  • the thin film transistor array substrate preparation method encapsulates a production process of a thin film transistor array substrate, and improves utilization of a pixel electrode forming material.
  • An aspect of the invention provides a method for fabricating a thin film transistor array substrate, comprising the steps of: forming a gate electrode layer, a gate insulating layer, an active layer, a source/drain electrode layer, a passivation layer, and a pixel electrode layer on a substrate,
  • the passivation layer is formed into a structure pattern including via holes by a patterning process
  • the pixel electrode layer is formed in a structure pattern region by a dropping method, and the source/drain electrode layer and the pixel electrode layer are connected through via holes.
  • forming a structural pattern including via holes in the passivation layer is formed by a patterning process: exposing the photoresist over the passivation layer with a halftone mask or a gray tone mask, correspondingly forming The photoresist at the via region is completely removed, and the photoresist corresponding to the region where the pixel electrode layer is formed is partially removed.
  • the method further includes: performing curing and annealing treatment on the pixel electrode layer.
  • the material for forming the pixel electrode layer is a material containing an indium element, a tin element, and an oxygen element, and the material containing the indium element, the tin element, and the oxygen element is previously formed into a sol or ink and poured into a nozzle. Dropping through the nozzle is in the area of the structural pattern.
  • the material for forming the pixel electrode layer is indium tin oxide sol or ink
  • the indium tin oxide sol or ink is obtained by the following method: Pressing InCl 3 .4H 2 0 and SnCl 4 .5H 2 0 as 1 : ( 1-3 ) The ratio is dissolved in an aqueous solution; or, In 2 0 3 and SnCl 4 .5H 2 0 are dissolved in C 2 H 5 COOH in a ratio of 1: (2-6 ).
  • the temperature at which the pixel electrode layer is annealed is in the range of 300 to 600 °C.
  • the thickness of the pixel electrode layer ranges from 20 to 150 nm.
  • the passivation layer is formed of a single layer film layer or a multilayer composite film layer using at least two materials of silicon oxide, silicon nitride, germanium oxide, and aluminum oxide, and the thickness of the passivation layer is 300-500nm.
  • Another aspect of the present invention provides a thin film transistor array substrate formed by the above-described thin film transistor array substrate fabrication method.
  • Still another aspect of the present invention provides a display device including the above-described thin film transistor array Substrate.
  • FIG. 1 is a cross-sectional view of a conventional thin film transistor array substrate (an active layer is formed using an amorphous silicon material);
  • FIG. 2 is a cross-sectional view of a conventional thin film transistor array substrate (using a metal oxide semiconductor material to form an active layer);
  • FIG. 3 is a cross-sectional view showing a thin film transistor array substrate in Embodiment 1 of the present invention.
  • FIG. 4 is a view showing a process of preparing a thin film transistor array substrate of FIG. 3;
  • Figure 5 is a cross-sectional view showing a thin film transistor array substrate in Embodiment 2 of the present invention.
  • Fig. 6 is a view showing the process of preparing the thin film transistor array substrate of Fig. 5.
  • Embodiments of the present invention provide a method for fabricating a thin film transistor array substrate, including the steps of: forming a gate electrode layer, a gate insulating layer, an active layer, a source/drain electrode layer, and a passivation layer on a substrate, wherein The passivation layer forms a structure pattern including via holes by a patterning process, and the pixel electrode layer is formed in a structure pattern region by a dropping method, and the source/drain electrode layer and the pixel electrode layer are connected through via holes.
  • Embodiments of the present invention provide a thin film transistor array substrate formed by the above-described thin film transistor array substrate preparation method.
  • Embodiments of the present invention provide a display device including the above-described thin film transistor array substrate.
  • Example 1 Example 1:
  • the thin film transistor array substrate in this embodiment includes a gate electrode layer 2, a gate insulating layer 3, an active layer 4, a source/drain electrode layer 6, a passivation layer 7, and sequentially formed on the substrate 1.
  • the passivation layer 7 is formed into a structure pattern including via holes by a patterning process, and the pixel electrode layer 8 is formed in a structure pattern region by a dropping method, and the source/drain electrode layer 6 and the pixel electrode layer 8 pass through Hole connection.
  • the source/drain electrode layer 6 includes source and drain electrodes spaced apart from each other with a portion of the active layer 4 therebetween being a channel.
  • the active layer 4 is formed of an amorphous silicon material, and correspondingly, an ohmic contact layer 51 is formed above the active layer 4.
  • the ohmic contact layer 51 is formed, for example, of an amorphous silicon material doped with phosphorus, and a typical cross-sectional view of the thin film transistor array substrate is shown in FIG.
  • the method for preparing a thin film transistor array substrate in this embodiment specifically includes the following steps:
  • a gate electrode layer, a gate insulating layer, an active layer, and a source/drain electrode layer are sequentially formed on the substrate.
  • the gate electrode layer 2 is first formed over the substrate 1.
  • the gate electrode layer 2 may be formed of at least one of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu).
  • a layer or a multilayer composite laminate preferably a single layer film or a multilayer composite film layer composed of a phase (Mo ), aluminum (A1 ) or an alloy containing phase (Mo) or aluminum (A1), the gate electrode layer
  • the thickness of 2 ranges from 100 nm to 500 nm.
  • a gate insulating layer 3 is deposited over the gate electrode layer 2.
  • the gate insulating layer 3 one or two of silicon oxide (SiO x ), silicon nitride (SiN x ), hafnium oxide (HfO x ), silicon oxynitride (SiON), aluminum oxide (A10 x ), etc. may be used.
  • a multilayer composite film layer is formed.
  • the structure of the gate insulating layer 3 may be a stacked structure formed using SiN x /SiO x or a stacked structure formed using SiN x /SiON/SiO x , and the thickness of the gate insulating layer is 100- 400nm.
  • the gate insulating layer 3 may be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD).
  • an active layer 4 is formed over the gate insulating layer 3.
  • the active layer 4 is formed of an amorphous silicon material, and the amorphous silicon material can be formed by using plasma enhanced chemical vapor deposition (PECVD), and the thickness of the active layer 4 is 30- 200nm.
  • PECVD plasma enhanced chemical vapor deposition
  • an ohmic contact layer 51 is formed over the active layer 4.
  • the ohmic contact layer may be formed of a material of amorphous silicon doped with phosphorus, which is formed by a PECVD method, and the ohmic contact layer has a thickness ranging from 30 to 100 nm.
  • a source/drain electrode layer 6 is formed over the ohmic contact layer 51.
  • the source/drain electrode layer 6 may be formed of at least one of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu).
  • Mo molybdenum
  • MoNb molybdenum-niobium alloy
  • Al aluminum-niobium alloy
  • Ti titanium
  • Cu copper
  • a single-layer or multi-layer composite laminate preferably a single layer film or a multilayer composite film layer composed of a phase (Mo), aluminum (A1) or an alloy containing phase (Mo) or aluminum (A1), the source leakage
  • the thickness of the pole layer ranges from 100 to 500 nm.
  • a passivation layer 7 is formed over the source/drain electrode layer 6.
  • the passivation layer 7 may be formed of at least two materials of silicon oxide (SiO x ), silicon nitride (SiN x ), hafnium oxide (HfO x ), aluminum oxide (A10 x ), and the like.
  • the film layer or the multilayer composite film layer may be formed by plasma enhanced chemical vapor deposition (PECVD), and the passivation layer has a thickness ranging from 300 to 500 nm.
  • the passivation layer 7 is formed into a structure pattern including via holes by a patterning process: exposing the photoresist over the passivation layer with a halftone mask or a gray tone mask in the passivation layer Corresponding to forming the photoresist at the via region as a full exposure process, the photoresist corresponding to the region where the pixel electrode layer is formed is a half exposure process.
  • a patterning process may be performed on the passivation layer 7 to form a pattern of the pixel electrode layer and the via hole at the same time.
  • the patterning process generally includes steps of photoresist coating, exposure, development, etching, photoresist stripping, and the like. For a film layer having a photosensitive property itself, the use of a photoresist can be omitted, and the patterning process can eliminate the steps of photoresist coating, etching, and photoresist stripping.
  • a layer of photoresist is applied over the passivation layer 7, and in the case of a positive photoresist, a halftone mask or a gray tone mask is used to form a via 9
  • the photoresist of the region is subjected to a full exposure process, and the photoresist of the deposition region of the pixel electrode layer 8 to be formed is subjected to a half exposure (partial exposure) process, and the exposed photoresist is developed, and the photolithography is fully exposed.
  • the glue is removed and the half exposed photoresist is partially removed to become thin.
  • the photoresist corresponding to the region in which the via 9 is formed is subjected to a non-exposure process, and the photoresist of the deposition region of the pixel electrode layer 8 to be formed is subjected to a half exposure (partial exposure) process.
  • the exposed photoresist is subjected to development processing, the unexposed photoresist is removed, and the half-exposed photoresist is partially removed to be thinned.
  • etching is performed on the passivation layer 7 corresponding to the region where the via 9 is formed, and the etching time is controlled according to the specific production process and the layer thickness of the passivation layer to achieve the design.
  • the desired depth is preferably (the passivation layer 7 is not completely etched at this time); then, the photoresist remaining in the half-exposure region corresponding to the region where the pixel electrode layer 8 is formed is passed through an ashing process and a dry etching method.
  • the processed photoresist as an etch mask, the region corresponding to the via hole and the region forming the pixel electrode layer are integrally etched, and the pixel electrode is formed while the via 9 is etched.
  • the structural pattern of the layer is controlled according to the specific production process and the layer thickness of the passivation layer to achieve the design.
  • the desired depth is preferably (the passivation layer 7 is not completely etched at this time); then, the photoresist remaining in the half-exposure region corresponding to the region where the
  • the material for forming the pixel electrode layer is dropped through the nozzle 10 in the structural pattern region to form a transparent pixel electrode layer 8.
  • the material for forming the pixel electrode layer is a material containing an indium element, a tin element, and an oxygen element, and the material containing the indium element, the tin element, and the oxygen element is previously formed into a sol or ink and poured into the nozzle. Dropping through the nozzle is in the area of the structural pattern.
  • the material for forming the pixel electrode layer is an indium tin oxide (ITO) sol or ink.
  • the indium tin oxide sol or ink is obtained, for example, by the following method: InCl 4H 2 0 (indium trichloride tetrahydrate) and SnCl 4 '5H 2 0 (tin tetrachloride pentahydrate) are as follows: (1-3) Proportionally dissolved in an aqueous solution, preferably in a ratio of 1:1 ratio of InCl 3 .4H 2 0 (indium trichloride tetrachloride) and SnCl 4 .5H 2 0 (tin tetrachloride pentahydrate); or In 2 0 3 (indium trioxide) and SnCl 4 '5H 2 0 (tin tetrachloride pentahydrate) are dissolved in C 2 H 5 COOH (propionic acid) in a ratio of 1: (2-6 ), preferably In 2 0 3 (indium trioxide) and SnCl 4 '5H 2 0 (t
  • the formed pixel electrode layer 8 is cured and annealed.
  • the temperature range of the annealing process of the pixel electrode layer 8 is, for example, 300-600 ° C, which is higher than the annealing temperature (230-300 ° C) of the pixel electrode layer in the prior art, so that the pixel electrode layer can be better. Crystallization, while achieving better electrical conductivity.
  • the thickness of the pixel electrode layer may range from 20 to 150 nm.
  • This embodiment also provides a display device including a thin film transistor array substrate formed by the method for fabricating a thin film transistor array substrate of the present embodiment.
  • the active layer 4 in the thin film transistor array substrate of the present embodiment is formed of a metal oxide semiconductor, and a typical cross-sectional view of the thin film transistor array substrate is as shown in FIG.
  • an active layer 4 is formed over the gate insulating layer 3.
  • the active layer 4 is formed of a metal oxide semiconductor, and the metal oxide semiconductor may be composed of an oxygen element (0), an indium (In), a gallium (Ga), and a (Zn). At least two elements in tin (Sn) are formed (ie, they must contain oxygen).
  • the active layer may be formed using indium gallium oxide (IGZO), indium oxide (IZO), indium tin oxide (InSnO), or indium gallium tin oxide (InGaSnO), preferably IGZO and IZO.
  • the active layer is formed by a sputtering method or an inkjet printing method or a sol-plating method and an annealing treatment, and the annealing temperature may range from 200 to 500 ° C, and the thickness of the active layer may range from 10 to 100 nm.
  • an etch stop layer 52 is further formed on the active layer, and the etch stop layer may be silicon oxide (SiO x ), silicon nitride (SiN x ), or hafnium oxide (HfO x ). At least two (two or three) materials of aluminum oxide (A10 x ) form a single layer film or a multilayer composite film layer, and the etch barrier layer may have a thickness ranging from 50 to 200 nm.
  • the specific preparation process of the gate electrode layer 2, the gate insulating layer 3, the source/drain electrode layer 6, and the passivation layer 7 in this embodiment includes the materials selected for each, the corresponding layer thickness and the formation manner, respectively.
  • the embodiment 1 is the same and will not be described here.
  • the gate insulating layer 3, the passivation layer 7 and the etch stop layer 52 have a hydrogen content of 10% or less.
  • the hydrogen content in the above three layer structures is less than or equal to 10%.
  • the present embodiment provides a display device including a thin film transistor array substrate formed by the thin film transistor array substrate manufacturing method of the present embodiment.
  • the pixel electrode layer and the structure pattern of the via hole in the thin film transistor array substrate described in Embodiments 1 and 2 can also be used as a structural pattern region for forming an evaporated OLED device, or to form a printing or spraying.
  • Embodiments 1 and 2 form a pattern structure required for a pixel electrode layer and a via hole by patterning in a passivation layer of a thin film transistor array substrate, and then indium tin oxide sol or ink for forming a pixel electrode layer A pixel electrode layer is formed by dropping a nozzle into a structure pattern region formed in the passivation layer.
  • the thin film transistor array substrate preparation method in Embodiments 1 and 2 reduces the step of forming a pixel electrode layer by a patterning process, reduces the usage of the mask, and improves the pixel electrode. The layer formation material utilization rate while reducing production costs.

Abstract

A thin film transistor array substrate preparation method, a thin film transistor array substrate and a display device. The thin film transistor array substrate preparation method comprises the following steps: forming a gate electrode layer (2), a gate insulating layer (3), an active layer (4), a source/drain electrode layer (6), a passivation layer (7) and a pixel electrode layer (8) on a substrate (1), wherein a structure pattern comprising a through hole (9) is formed on the passivation layer through a patterning process, the pixel electrode layer (8) is formed within the region of the structure pattern in a dripping manner, and the source/drain electrode layer (6) is connected with the pixel electrode layer (8) via the through hole (9). With the help of the thin film transistor array substrate preparation method, the steps of forming the pixel electrode layer by the patterning process are reduced, the use of a mask is reduced, the utilization rate of the pixel electrode forming material is improved, and simultaneously, the production cost is lowered.

Description

薄膜晶体管阵列基板、 制备方法以及显示装置 技术领域  Thin film transistor array substrate, preparation method and display device
本发明的实施例涉及一种薄膜晶体管阵列基板制备方法、 薄膜晶体管阵 列基板以及显示装置。 背景技术  Embodiments of the present invention relate to a method of fabricating a thin film transistor array substrate, a thin film transistor array substrate, and a display device. Background technique
近年来， 显示技术得到快速的发展。 例如， 薄膜晶体管 （Thin Film Transistor: 筒称 TFT )技术由最初的非晶硅薄膜晶体管发展到现在的低温多 晶硅薄膜晶体管、 金属氧化物半导体薄膜晶体管等。 而发光技术也由最初的 液晶显示（ Liquid Crystal Display: LCD )技术发展为现在的有机电致发光显 示 ( Organic Light-Emitting Diode: OLED )技术。  In recent years, display technology has developed rapidly. For example, Thin Film Transistor (TFT) technology has evolved from the original amorphous silicon thin film transistor to the current low temperature polysilicon thin film transistor, metal oxide semiconductor thin film transistor, and the like. The luminescence technology has also evolved from the original liquid crystal display (LCD) technology to the current Organic Light-Emitting Diode (OLED) technology.
薄膜晶体管作为显示装置的驱动元件， 直接关系到高性能平板显示装置 的发展方向。 薄膜晶体管一般包括在基板 1上依次形成的栅电极层 2、 栅极 绝缘层 3、 有源层 4、 源漏电极层 6、 钝化层 7以及像素电极层 8, 所述源漏 电极层 6与所述像素电极层 8通过过孔连接。 有源层 4采用非晶硅材料形成 的 TFT剖视图如图 1所示， 有源层上方为欧姆接触层 51; 有源层 4采用金 属氧化物半导体材料形成的 TFT剖视图如图 2所示，有源层上方为刻蚀阻挡 层 52。  As a driving element of a display device, a thin film transistor is directly related to the development direction of a high-performance flat panel display device. The thin film transistor generally includes a gate electrode layer 2, a gate insulating layer 3, an active layer 4, a source/drain electrode layer 6, a passivation layer 7, and a pixel electrode layer 8, which are sequentially formed on the substrate 1, and the source/drain electrode layer 6 The pixel electrode layer 8 is connected to the via hole. FIG. 1 is a cross-sectional view of the TFT formed by using the amorphous silicon material. The upper layer of the active layer is an ohmic contact layer 51. The cross section of the TFT formed by the metal oxide semiconductor material of the active layer 4 is as shown in FIG. Above the source layer is an etch stop layer 52.
在上述两种薄膜晶体管中， 像素电极层均采用氧化铟锡（ITO )形成。 在薄膜晶体管的制备过程中， 为了形成像素电极层的图案， 需要先通过溅射 方式形成一定厚度的氧化铟锡膜层， 然后借助掩模板曝光等光刻工艺将图形 转移到氧化铟锡膜层上， 造成了像素电极形成材料的浪费。 同时， 在薄膜晶 体管阵列基板的制备过程中，所用到的掩模板的次数越多，则生产效率越低， 生产成本越高。  In both of the above thin film transistors, the pixel electrode layers are formed using indium tin oxide (ITO). In the preparation process of the thin film transistor, in order to form the pattern of the pixel electrode layer, a certain thickness of the indium tin oxide film layer is first formed by sputtering, and then the pattern is transferred to the indium tin oxide film layer by a photolithography process such as mask exposure. Upper, causing waste of the pixel electrode forming material. Meanwhile, in the preparation process of the thin film transistor array substrate, the more the number of masks used, the lower the production efficiency and the higher the production cost.
因此， 如何进一步减少薄膜晶体管阵列基板的制备过程中构图工艺的次 数， 提高生产效率， 提高像素电极形成材料的利用率， 降低生产成本是行业 内亟待解决的问题。 发明内容 阵列基板制备方法、 薄膜晶体管阵列基板以及显示装置， 该薄膜晶体管阵列 基板制备方法筒化了薄膜晶体管阵列基板的生产工艺， 提高了像素电极形成 材料的利用率。 Therefore, how to further reduce the number of patterning processes in the preparation process of the thin film transistor array substrate, improve the production efficiency, improve the utilization ratio of the pixel electrode forming material, and reduce the production cost are urgent problems to be solved in the industry. SUMMARY OF THE INVENTION An array substrate preparation method, a thin film transistor array substrate, and a display device, the thin film transistor array substrate preparation method encapsulates a production process of a thin film transistor array substrate, and improves utilization of a pixel electrode forming material.
本发明的一个方面提供了一种薄膜晶体管阵列基板制备方法， 包括以下 步骤： 在基板上形成栅电极层、 栅极绝缘层、 有源层、 源漏电极层、 钝化层 以及像素电极层， 所述钝化层通过构图工艺形成包括过孔的结构图案， 所述 像素电极层通过滴注方式形成在结构图案区域内， 所述源漏电极层与所述像 素电极层通过过孔连接。  An aspect of the invention provides a method for fabricating a thin film transistor array substrate, comprising the steps of: forming a gate electrode layer, a gate insulating layer, an active layer, a source/drain electrode layer, a passivation layer, and a pixel electrode layer on a substrate, The passivation layer is formed into a structure pattern including via holes by a patterning process, and the pixel electrode layer is formed in a structure pattern region by a dropping method, and the source/drain electrode layer and the pixel electrode layer are connected through via holes.
例如，在所述钝化层中形成包括过孔的结构图案采用以下构图工艺形成： 用半色调掩模板或灰色调掩模板对所述钝化层上方的光刻胶进行曝光处理， 对应着形成所述过孔区域处的光刻胶被完全去除， 对应着形成所述像素电极 层区域处的光刻胶被部分去除。  For example, forming a structural pattern including via holes in the passivation layer is formed by a patterning process: exposing the photoresist over the passivation layer with a halftone mask or a gray tone mask, correspondingly forming The photoresist at the via region is completely removed, and the photoresist corresponding to the region where the pixel electrode layer is formed is partially removed.
例如， 所述方法还进一步包括： 对所述像素电极层做固化及退火处理。 例如， 用于形成所述像素电极层的材料为含有铟元素、 锡元素以及氧元 素的材料， 所述含有铟元素、 锡元素以及氧元素的材料预先制成溶胶或墨水 并灌注于喷嘴中， 通过喷嘴滴注在所述结构图案区域内。  For example, the method further includes: performing curing and annealing treatment on the pixel electrode layer. For example, the material for forming the pixel electrode layer is a material containing an indium element, a tin element, and an oxygen element, and the material containing the indium element, the tin element, and the oxygen element is previously formed into a sol or ink and poured into a nozzle. Dropping through the nozzle is in the area of the structural pattern.
例如， 用于形成所述像素电极层的材料为氧化铟锡溶胶或墨水， 所述氧 化铟锡溶胶或墨水由以下方法制得： 将 InCl3.4H20和 SnCl4.5H20按 1: ( 1-3 ) 比例溶于水溶液中； 或者， 将 In203和 SnCl4.5H20按 1: ( 2-6 ) 比例溶于 C2H5COOH中。 For example, the material for forming the pixel electrode layer is indium tin oxide sol or ink, and the indium tin oxide sol or ink is obtained by the following method: Pressing InCl 3 .4H 2 0 and SnCl 4 .5H 2 0 as 1 : ( 1-3 ) The ratio is dissolved in an aqueous solution; or, In 2 0 3 and SnCl 4 .5H 2 0 are dissolved in C 2 H 5 COOH in a ratio of 1: (2-6 ).
例如， 所述像素电极层退火处理的温度范围为 300-600°C。  For example, the temperature at which the pixel electrode layer is annealed is in the range of 300 to 600 °C.
例如， 所述像素电极层的厚度范围为 20-150nm。  For example, the thickness of the pixel electrode layer ranges from 20 to 150 nm.
例如， 所述钝化层采用硅氧化物、 硅氮化物、 铪氧化物、 铝氧化物中的 至少两种材料形成单层膜层或多层复合膜层， 所述钝化层的厚度范围为 300-500nm。  For example, the passivation layer is formed of a single layer film layer or a multilayer composite film layer using at least two materials of silicon oxide, silicon nitride, germanium oxide, and aluminum oxide, and the thickness of the passivation layer is 300-500nm.
本发明的另一个方面提供了一种薄膜晶体管阵列基板， 采用上述的薄膜 晶体管阵列基板制备方法形成。  Another aspect of the present invention provides a thin film transistor array substrate formed by the above-described thin film transistor array substrate fabrication method.
本发明的再一个方面提供了一种显示装置， 包括上述的薄膜晶体管阵列 基板。 附图说明 Still another aspect of the present invention provides a display device including the above-described thin film transistor array Substrate. DRAWINGS
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。  In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, rather than to the present invention. limit.
图 1为现有的薄膜晶体管阵列基板的剖视图 （采用非晶硅材料形成有源 层） ；  1 is a cross-sectional view of a conventional thin film transistor array substrate (an active layer is formed using an amorphous silicon material);
图 2为现有的薄膜晶体管阵列基板的剖视图 （采用金属氧化物半导体材 料形成有源层） ；  2 is a cross-sectional view of a conventional thin film transistor array substrate (using a metal oxide semiconductor material to form an active layer);
图 3为本发明实施例 1中薄膜晶体管阵列基板的剖视图；  3 is a cross-sectional view showing a thin film transistor array substrate in Embodiment 1 of the present invention;
图 4为图 3中薄膜晶体管阵列基板的制备过程图；  4 is a view showing a process of preparing a thin film transistor array substrate of FIG. 3;
图 5为本发明实施例 2中薄膜晶体管阵列基板的剖视图；  Figure 5 is a cross-sectional view showing a thin film transistor array substrate in Embodiment 2 of the present invention;
图 6为图 5中薄膜晶体管阵列基板的制备过程图。  Fig. 6 is a view showing the process of preparing the thin film transistor array substrate of Fig. 5.
图中： 1 -基板； 2 -栅电极层； 3 -栅极绝缘层； 4 -有源层； 51 -欧姆 接触层； 52 -刻蚀阻挡层； 6 -源漏极层； 7 -钝化层； 8 -像素电极层； 9 - 过孔； 10 -喷嘴。 具体实施方式  In the figure: 1 - substrate; 2 - gate electrode layer; 3 - gate insulating layer; 4 - active layer; 51 - ohmic contact layer; 52 - etch barrier layer; 6 - source drain layer; Layer; 8 - pixel electrode layer; 9 - via; 10 - nozzle. detailed description
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。  The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 "一个" 、 "一" 或者 "该" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵 盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排 除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理 的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。Unless otherwise defined, technical terms or scientific terms used herein shall be of ordinary meaning as understood by those of ordinary skill in the art to which the invention pertains. The words "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. The words "including" or "comprising", etc., are intended to mean that the elements or objects preceding "including" or "comprising" are intended to encompass the elements or Component or object. "Connected" or "connected" and the like are not limited to physics. Or mechanical connections, but can include electrical connections, whether direct or indirect.
"上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对 象的绝对位置改变后， 则该相对位置关系也可能相应地改变。 "Up", "Down", "Left", "Right", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationship may also change accordingly.
本发明的实施例提供了一种薄膜晶体管阵列基板制备方法， 包括以下步 骤： 在基板上形成栅电极层、 栅极绝缘层、 有源层、 源漏电极层、 钝化层， 其中， 所述钝化层通过构图工艺形成包括过孔的结构图案， 所述像素电极层 通过滴注方式形成在结构图案区域内， 所述源漏电极层与所述像素电极层通 过过孔连接。  Embodiments of the present invention provide a method for fabricating a thin film transistor array substrate, including the steps of: forming a gate electrode layer, a gate insulating layer, an active layer, a source/drain electrode layer, and a passivation layer on a substrate, wherein The passivation layer forms a structure pattern including via holes by a patterning process, and the pixel electrode layer is formed in a structure pattern region by a dropping method, and the source/drain electrode layer and the pixel electrode layer are connected through via holes.
本发明的实施例提供了一种薄膜晶体管阵列基板， 采用上述的薄膜晶体 管阵列基板制备方法形成。  Embodiments of the present invention provide a thin film transistor array substrate formed by the above-described thin film transistor array substrate preparation method.
本发明的实施例提供了一种显示装置，包括上述的薄膜晶体管阵列基板。 实施例 1:  Embodiments of the present invention provide a display device including the above-described thin film transistor array substrate. Example 1:
如图 3所示， 本实施例中的薄膜晶体管阵列基板包括在基板 1上依次形 成的栅电极层 2、 栅极绝缘层 3、 有源层 4、 源漏电极层 6、 钝化层 7以及像 素电极层 8。 所述钝化层 7通过构图工艺形成包括过孔的结构图案， 所述像 素电极层 8通过滴注方式形成在结构图案区域内， 所述源漏电极层 6与所述 像素电极层 8通过过孔连接。 该源漏电极层 6包括彼此间隔开的源电极和漏 电极， 在二者之间的部分有源层 4为沟道。  As shown in FIG. 3, the thin film transistor array substrate in this embodiment includes a gate electrode layer 2, a gate insulating layer 3, an active layer 4, a source/drain electrode layer 6, a passivation layer 7, and sequentially formed on the substrate 1. Pixel electrode layer 8. The passivation layer 7 is formed into a structure pattern including via holes by a patterning process, and the pixel electrode layer 8 is formed in a structure pattern region by a dropping method, and the source/drain electrode layer 6 and the pixel electrode layer 8 pass through Hole connection. The source/drain electrode layer 6 includes source and drain electrodes spaced apart from each other with a portion of the active layer 4 therebetween being a channel.
在本实施例中， 所述有源层 4采用非晶硅材料形成， 相应的， 在所述有 源层 4的上方还形成有欧姆接触层 51。 所述欧姆接触层 51例如采用掺杂磷 元素的非晶硅材料形成， 该薄膜晶体管阵列基板的典型剖视图如图 3所示。  In the present embodiment, the active layer 4 is formed of an amorphous silicon material, and correspondingly, an ohmic contact layer 51 is formed above the active layer 4. The ohmic contact layer 51 is formed, for example, of an amorphous silicon material doped with phosphorus, and a typical cross-sectional view of the thin film transistor array substrate is shown in FIG.
如图 4a-4g所示， 本实施例中薄膜晶体管阵列基板的制备方法具体包括 如下步骤：  As shown in FIG. 4a-4g, the method for preparing a thin film transistor array substrate in this embodiment specifically includes the following steps:
S1 )在基板上依次形成栅电极层、 栅极绝缘层、 有源层、 源漏电极层。 在该步骤中， 如图 4a所示， 首先在基板 1的上方形成栅电极层 2。 所述 栅电极层 2可采用钼（ Mo )、钼铌合金（ MoNb )、铝（ A1 )、铝钕合金（ AlNd )、 钛（Ti )和铜 ( Cu ) 中的至少一种材料形成的单层或多层复合叠层， 优选为 相 （Mo ) 、 铝（A1 )或含相 （Mo ) 、 铝（A1 ) 的合金组成的单层膜层或多 层复合膜层， 所述栅电极层 2的厚度范围为 100nm-500nm。  S1) A gate electrode layer, a gate insulating layer, an active layer, and a source/drain electrode layer are sequentially formed on the substrate. In this step, as shown in Fig. 4a, the gate electrode layer 2 is first formed over the substrate 1. The gate electrode layer 2 may be formed of at least one of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu). a layer or a multilayer composite laminate, preferably a single layer film or a multilayer composite film layer composed of a phase (Mo ), aluminum (A1 ) or an alloy containing phase (Mo) or aluminum (A1), the gate electrode layer The thickness of 2 ranges from 100 nm to 500 nm.
如图 4b所示， 在栅电极层 2的上方沉积栅极绝缘层 3。 所述栅极绝缘层 3 可采用硅氧化物（SiOx ) 、 硅氮化物 （SiNx ) 、 铪氧化物 （HfOx ) 、 硅氮 氧化物（SiON ) 、 铝氧化物（A10x )等中的一种或两种形成多层复合膜层。 例如，栅极绝缘层 3的结构可以为采用 SiNx/SiOx形成的叠层结构，也可以为 采用 SiNx/SiON/SiOx形成的叠层结构，栅极绝缘层的厚度范围为 100-400nm。 至于 SiNx、 SiOx或 SiON各膜层厚度可根据设计需要做灵活调整， 这里不再 赘述。 所述栅极绝缘层 3 可以采用等离子体增强化学气相沉积法（Plasma Enhanced Chemical Vapor Deposition, PECVD )形成。 As shown in FIG. 4b, a gate insulating layer 3 is deposited over the gate electrode layer 2. The gate insulating layer 3 one or two of silicon oxide (SiO x ), silicon nitride (SiN x ), hafnium oxide (HfO x ), silicon oxynitride (SiON), aluminum oxide (A10 x ), etc. may be used. A multilayer composite film layer is formed. For example, the structure of the gate insulating layer 3 may be a stacked structure formed using SiN x /SiO x or a stacked structure formed using SiN x /SiON/SiO x , and the thickness of the gate insulating layer is 100- 400nm. As for the thickness of each layer of SiN x , SiO x or SiON, it can be flexibly adjusted according to the design requirements, and will not be described here. The gate insulating layer 3 may be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD).
如图 4c所示， 在栅极绝缘层 3的上方形成有源层 4。 在本实施例中， 所 述有源层 4采用非晶硅材料形成， 所述非晶硅材料可以通过采用等离子体增 强化学气相沉积法（PECVD )形成， 有源层 4的厚度范围为 30-200nm。  As shown in Fig. 4c, an active layer 4 is formed over the gate insulating layer 3. In this embodiment, the active layer 4 is formed of an amorphous silicon material, and the amorphous silicon material can be formed by using plasma enhanced chemical vapor deposition (PECVD), and the thickness of the active layer 4 is 30- 200nm.
如图 4d所示， 相应的， 在有源层 4的上方形成欧姆接触层 51。 所述欧 姆接触层可以采用掺杂磷元素的非晶硅的材料， 通过 PECVD法形成， 所述 欧姆接触层的厚度范围为 30-100nm。  As shown in Fig. 4d, correspondingly, an ohmic contact layer 51 is formed over the active layer 4. The ohmic contact layer may be formed of a material of amorphous silicon doped with phosphorus, which is formed by a PECVD method, and the ohmic contact layer has a thickness ranging from 30 to 100 nm.
如图 4e所示， 在所述欧姆接触层 51的上方形成源漏电极层 6。 所述源 漏电极层 6可采用钼（ Mo )、钼铌合金（ MoNb )、铝（ A1 )、铝钕合金（ AlNd )、 钛（Ti )和铜 ( Cu ) 中的至少一种材料形成的单层或多层复合叠层， 优选为 相 （Mo ) 、 铝（A1 )或含相 （Mo ) 、 铝（A1 ) 的合金组成的单层膜层或多 层复合膜层， 所述源漏电极层的厚度范围为 100-500nm。  As shown in Fig. 4e, a source/drain electrode layer 6 is formed over the ohmic contact layer 51. The source/drain electrode layer 6 may be formed of at least one of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu). a single-layer or multi-layer composite laminate, preferably a single layer film or a multilayer composite film layer composed of a phase (Mo), aluminum (A1) or an alloy containing phase (Mo) or aluminum (A1), the source leakage The thickness of the pole layer ranges from 100 to 500 nm.
S2 )形成钝化层， 所述钝化层中通过构图工艺同时形成所述像素电极层 以及所述过孔的结构图案。  S2) forming a passivation layer in which the pixel electrode layer and the structural pattern of the via are simultaneously formed by a patterning process.
如图 4f所示， 在源漏电极层 6的上方形成钝化层 7。 其中， 所述钝化层 7 可采用硅氧化物（SiOx ) 、 硅氮化物 （SiNx ) 、 铪氧化物 （HfOx ) 、 铝氧 化物（A10x )等中的至少两种材料形成单层膜层或多层复合膜层， 所述钝化 层可以采用等离子体增强化学气相沉积法（PECVD )形成， 所述钝化层的厚 度范围为 300-500nm。 As shown in FIG. 4f, a passivation layer 7 is formed over the source/drain electrode layer 6. The passivation layer 7 may be formed of at least two materials of silicon oxide (SiO x ), silicon nitride (SiN x ), hafnium oxide (HfO x ), aluminum oxide (A10 x ), and the like. The film layer or the multilayer composite film layer may be formed by plasma enhanced chemical vapor deposition (PECVD), and the passivation layer has a thickness ranging from 300 to 500 nm.
所述钝化层 7形成包括过孔的结构图案采用以下构图工艺形成： 在所述 钝化层中用半色调掩模板或灰色调掩模板对所述钝化层上方的光刻胶进行曝 光处理， 对应着形成所述过孔区域处的光刻胶为完全曝光处理， 对应着形成 所述像素电极层区域处的光刻胶为半曝光处理。 通过对钝化层 7可以采用构 图工艺做图案化处理，以同时形成所述像素电极层以及所述过孔的结构图案。 构图工艺通常包括光刻胶涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离等步骤。 对于本身具有感光性质的膜层， 可以省略使用光刻胶， 此时构图工艺可以省 掉光刻胶涂敷、 刻蚀、 光刻胶剥离的步骤。 The passivation layer 7 is formed into a structure pattern including via holes by a patterning process: exposing the photoresist over the passivation layer with a halftone mask or a gray tone mask in the passivation layer Corresponding to forming the photoresist at the via region as a full exposure process, the photoresist corresponding to the region where the pixel electrode layer is formed is a half exposure process. A patterning process may be performed on the passivation layer 7 to form a pattern of the pixel electrode layer and the via hole at the same time. The patterning process generally includes steps of photoresist coating, exposure, development, etching, photoresist stripping, and the like. For a film layer having a photosensitive property itself, the use of a photoresist can be omitted, and the patterning process can eliminate the steps of photoresist coating, etching, and photoresist stripping.
在一个示例中， 首先， 先在钝化层 7的上方涂覆一层光刻胶， 在使用正 性光刻胶情况下， 采用半色调掩模板或灰色调掩模板将对应着形成过孔 9区 域的光刻胶做完全曝光处理， 对将形成的像素电极层 8的沉积区域的光刻胶 做半曝光（部分曝光）处理， 将曝光后的光刻胶进行显影处理， 完全曝光的 光刻胶被去除， 而半曝光的光刻胶被部分去除从而变薄。 如果是使用负性光 刻胶， 则将对应着形成过孔 9区域的光刻胶做不曝光处理， 对将形成的像素 电极层 8的沉积区域的光刻胶做半曝光（部分曝光）处理， 从而将曝光后的 光刻胶进行显影处理， 未曝光的光刻胶被去除， 而半曝光的光刻胶被部分去 除从而变薄。  In one example, first, a layer of photoresist is applied over the passivation layer 7, and in the case of a positive photoresist, a halftone mask or a gray tone mask is used to form a via 9 The photoresist of the region is subjected to a full exposure process, and the photoresist of the deposition region of the pixel electrode layer 8 to be formed is subjected to a half exposure (partial exposure) process, and the exposed photoresist is developed, and the photolithography is fully exposed. The glue is removed and the half exposed photoresist is partially removed to become thin. If a negative photoresist is used, the photoresist corresponding to the region in which the via 9 is formed is subjected to a non-exposure process, and the photoresist of the deposition region of the pixel electrode layer 8 to be formed is subjected to a half exposure (partial exposure) process. Thereby, the exposed photoresist is subjected to development processing, the unexposed photoresist is removed, and the half-exposed photoresist is partially removed to be thinned.
接着， 使用光刻胶作为蚀刻掩膜， 在对应着形成过孔 9区域的钝化层 7 进行刻蚀， 刻蚀时间的控制根据具体生产工艺以及钝化层的层厚来决定， 以 达到设计所需的深度为宜 （此时钝化层 7未被完全刻透） ； 然后， 将对应着 将形成像素电极层 8的区域的半曝光区域残留的光刻胶通过灰化工艺及干刻 方法除去； 最后， 使用处理过的光刻胶作为蚀刻掩膜， 将对应着形成过孔的 区域以及形成像素电极层的区域做整体刻蚀， 在所述过孔 9刻蚀完成的同时 形成像素电极层的结构图案。  Next, using a photoresist as an etch mask, etching is performed on the passivation layer 7 corresponding to the region where the via 9 is formed, and the etching time is controlled according to the specific production process and the layer thickness of the passivation layer to achieve the design. The desired depth is preferably (the passivation layer 7 is not completely etched at this time); then, the photoresist remaining in the half-exposure region corresponding to the region where the pixel electrode layer 8 is formed is passed through an ashing process and a dry etching method. Finally, using the processed photoresist as an etch mask, the region corresponding to the via hole and the region forming the pixel electrode layer are integrally etched, and the pixel electrode is formed while the via 9 is etched. The structural pattern of the layer.
S3 )将用于形成所述像素电极层的材料滴注在所述结构图案区域内， 以 形成所述像素电极层。  S3) A material for forming the pixel electrode layer is dropped in the structure pattern region to form the pixel electrode layer.
如图 4g所示， 将用于形成所述像素电极层的材料通过喷嘴 10滴注在结 构图案区域内， 以形成透明的像素电极层 8。  As shown in Fig. 4g, the material for forming the pixel electrode layer is dropped through the nozzle 10 in the structural pattern region to form a transparent pixel electrode layer 8.
lieu,用于形成所述像素电极层的材料为含有铟元素、锡元素以及氧元素 的材料， 所述含有铟元素、 锡元素以及氧元素的材料预先制成溶胶或墨水并 灌注于喷嘴中， 通过喷嘴滴注在所述结构图案区域内。 用于形成所述像素电 极层的材料为氧化铟锡（ITO )溶胶或墨水。 该氧化铟锡溶胶或墨水例如由 以下方法制得： 将 InCl 4H20 (四水合三氯化铟）和 SnCl4'5H20 (五水合四 氯化锡）按 1: ( 1-3 )比例溶于水溶液中， 优选为将 InCl3.4H20 (四水合三氯 化铟）和 SnCl4.5H20 (五水合四氯化锡）按 1:1比例溶于水溶液中； 或者， 将 In203 (三氧化二铟 )和 SnCl4'5H20 (五水合四氯化锡）按 1: ( 2-6 ) 比例 溶于 C2H5COOH (丙酸)中， 优选为将 In203 (三氧化二铟 )和 SnCl4'5H20 (五 水合四氯化锡）按 1:2比例溶于 C2H5COOH (丙酸)中。 Lieu, the material for forming the pixel electrode layer is a material containing an indium element, a tin element, and an oxygen element, and the material containing the indium element, the tin element, and the oxygen element is previously formed into a sol or ink and poured into the nozzle. Dropping through the nozzle is in the area of the structural pattern. The material for forming the pixel electrode layer is an indium tin oxide (ITO) sol or ink. The indium tin oxide sol or ink is obtained, for example, by the following method: InCl 4H 2 0 (indium trichloride tetrahydrate) and SnCl 4 '5H 2 0 (tin tetrachloride pentahydrate) are as follows: (1-3) Proportionally dissolved in an aqueous solution, preferably in a ratio of 1:1 ratio of InCl 3 .4H 2 0 (indium trichloride tetrachloride) and SnCl 4 .5H 2 0 (tin tetrachloride pentahydrate); or In 2 0 3 (indium trioxide) and SnCl 4 '5H 2 0 (tin tetrachloride pentahydrate) are dissolved in C 2 H 5 COOH (propionic acid) in a ratio of 1: (2-6 ), preferably In 2 0 3 (indium trioxide) and SnCl 4 '5H 2 0 (tin tetrachloride pentahydrate) were dissolved in C 2 H 5 COOH (propionic acid) in a ratio of 1:2.
S4 )对所述像素电极层做固化及退火处理。  S4) curing and annealing the pixel electrode layer.
在该步骤中， 将成型后的像素电极层 8做固化及退火处理。 所述像素电 极层 8退火处理的温度范围例如为 300-600°C , 该温度高于现有技术中像素 电极层的退火温度（230-300°C ) , 以便于像素电极层能更好地结晶化， 同时 获得更好的导电性能。  In this step, the formed pixel electrode layer 8 is cured and annealed. The temperature range of the annealing process of the pixel electrode layer 8 is, for example, 300-600 ° C, which is higher than the annealing temperature (230-300 ° C) of the pixel electrode layer in the prior art, so that the pixel electrode layer can be better. Crystallization, while achieving better electrical conductivity.
所述像素电极层的厚度范围可以为 20-150nm。  The thickness of the pixel electrode layer may range from 20 to 150 nm.
该实施例还提供一种显示装置， 包括采用本实施例薄膜晶体管阵列基板 制备方法形成的薄膜晶体管阵列基板。  This embodiment also provides a display device including a thin film transistor array substrate formed by the method for fabricating a thin film transistor array substrate of the present embodiment.
实施例 2:  Example 2:
本实施例与实施例 1的区别在于， 本实施例薄膜晶体管阵列基板中的有 源层 4采用金属氧化物半导体形成， 该薄膜晶体管阵列基板的典型剖视图如 图 5所示。  The difference between this embodiment and the embodiment 1 is that the active layer 4 in the thin film transistor array substrate of the present embodiment is formed of a metal oxide semiconductor, and a typical cross-sectional view of the thin film transistor array substrate is as shown in FIG.
本实施例中薄膜晶体管阵列基板的制备过程如图 6a-6g所示。  The fabrication process of the thin film transistor array substrate in this embodiment is shown in Figures 6a-6g.
如图 6c所示，在所述栅极绝缘层 3的上方形成有源层 4。在本实施例中， 所述有源层 4采用金属氧化物半导体形成， 所述金属氧化物半导体可以采用 由包含氧元素（0 ) 以及铟 ( In ) 、 镓（Ga ) 、 辞（Zn ) 、 锡（ Sn ) 中的至 少两种元素形成（即其必须包含氧元素） 。 例如， 所述有源层可以采用氧化 铟镓辞（ IGZO )、氧化铟辞（ IZO )、氧化铟锡（ InSnO )、氧化铟镓锡（ InGaSnO ) 形成， 优选 IGZO和 IZO。 所述有源层通过溅射方式或喷墨打印方式或溶胶 旋涂方式并做退火处理形成， 退火温度范围可以为 200-500°C , 所述有源层 的厚度范围可以为 10-100nm。  As shown in Fig. 6c, an active layer 4 is formed over the gate insulating layer 3. In this embodiment, the active layer 4 is formed of a metal oxide semiconductor, and the metal oxide semiconductor may be composed of an oxygen element (0), an indium (In), a gallium (Ga), and a (Zn). At least two elements in tin (Sn) are formed (ie, they must contain oxygen). For example, the active layer may be formed using indium gallium oxide (IGZO), indium oxide (IZO), indium tin oxide (InSnO), or indium gallium tin oxide (InGaSnO), preferably IGZO and IZO. The active layer is formed by a sputtering method or an inkjet printing method or a sol-plating method and an annealing treatment, and the annealing temperature may range from 200 to 500 ° C, and the thickness of the active layer may range from 10 to 100 nm.
相应的， 在所述有源层的上方还形成有刻蚀阻挡层 52, 所述刻蚀阻挡层 可以采用硅氧化物（SiOx ) 、 硅氮化物 （SiNx ) 、 铪氧化物 （HfOx ) 、 铝氧 化物（A10x ) 中的至少两种（两种或三种）材料形成单层膜层或多层复合膜 层， 所述刻蚀阻挡层厚度范围可以为 50-200nm。 Correspondingly, an etch stop layer 52 is further formed on the active layer, and the etch stop layer may be silicon oxide (SiO x ), silicon nitride (SiN x ), or hafnium oxide (HfO x ). At least two (two or three) materials of aluminum oxide (A10 x ) form a single layer film or a multilayer composite film layer, and the etch barrier layer may have a thickness ranging from 50 to 200 nm.
本实施例中栅电极层 2、栅极绝缘层 3、源漏电极层 6以及钝化层 7的具 体制备过程， 包括其各自所选用的材料、 相应的层厚和形成方式均分别与实 施例 1相同， 这里不再赘述。 The specific preparation process of the gate electrode layer 2, the gate insulating layer 3, the source/drain electrode layer 6, and the passivation layer 7 in this embodiment includes the materials selected for each, the corresponding layer thickness and the formation manner, respectively. The embodiment 1 is the same and will not be described here.
在本实施例中， 所述栅极绝缘层 3、 所述钝化层 7和所述刻蚀阻挡层 52 中氢含量小于等于 10%。 在制备上述三种层结构时， 需控制相应层中氢含量 的水平， 以保证其具有良好的表面特性， 优选上述三种层结构中氢含量小于 等于 10%。  In this embodiment, the gate insulating layer 3, the passivation layer 7 and the etch stop layer 52 have a hydrogen content of 10% or less. In the preparation of the above three layer structures, it is necessary to control the level of hydrogen content in the corresponding layer to ensure that it has good surface characteristics, and it is preferable that the hydrogen content in the above three layer structures is less than or equal to 10%.
本实施例提供一种显示装置， 包括采用本实施例薄膜晶体管阵列基板制 备方法形成的薄膜晶体管阵列基板。  The present embodiment provides a display device including a thin film transistor array substrate formed by the thin film transistor array substrate manufacturing method of the present embodiment.
这里应该理解的是， 实施例 1、 2所述的薄膜晶体管阵列基板中像素电极 层以及所述过孔的结构图案， 也可用于作为形成蒸镀 OLED器件的结构图案 区域， 或者形成打印或喷墨滴注 PLED ( Polymer Light-Emitting Diode, 高分 子发光二极管） 的结构图案区域。  It should be understood here that the pixel electrode layer and the structure pattern of the via hole in the thin film transistor array substrate described in Embodiments 1 and 2 can also be used as a structural pattern region for forming an evaporated OLED device, or to form a printing or spraying. A structural pattern area of a PLED (Polymer Light-Emitting Diode).
实施例 1、 2通过在薄膜晶体管阵列基板的钝化层中进行图案化处理， 同 时形成像素电极层以及过孔所需的结构图案， 然后将用于形成像素电极层的 氧化铟锡溶胶或墨水通过喷嘴滴注于钝化层中形成的结构图案区域内以形成 像素电极层。 相比现有技术中薄膜晶体管阵列基板的制备方法， 实施例 1、 2 中的薄膜晶体管阵列基板制备方法减少了采用构图工艺形成像素电极层的步 骤， 减少了掩模板的使用量， 提高像素电极层形成材料的利用率， 同时降低 了生产成本。  Embodiments 1 and 2 form a pattern structure required for a pixel electrode layer and a via hole by patterning in a passivation layer of a thin film transistor array substrate, and then indium tin oxide sol or ink for forming a pixel electrode layer A pixel electrode layer is formed by dropping a nozzle into a structure pattern region formed in the passivation layer. Compared with the preparation method of the thin film transistor array substrate in the prior art, the thin film transistor array substrate preparation method in Embodiments 1 and 2 reduces the step of forming a pixel electrode layer by a patterning process, reduces the usage of the mask, and improves the pixel electrode. The layer formation material utilization rate while reducing production costs.
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。  The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

权利要求书 Claim
1. 一种薄膜晶体管阵列基板制备方法， 包括以下步骤： A method for fabricating a thin film transistor array substrate, comprising the steps of:
在基板上形成栅电极层、 栅极绝缘层、 有源层、 源漏电极层、 钝化层以 及像素电极层，  Forming a gate electrode layer, a gate insulating layer, an active layer, a source/drain electrode layer, a passivation layer, and a pixel electrode layer on the substrate,
其中， 所述钝化层通过构图工艺形成包括过孔的结构图案， 所述像素电 极层通过滴注方式形成在结构图案区域内， 所述源漏电极层与所述像素电极 层通过过孔连接。  The passivation layer is formed into a structure pattern including a via hole by a patterning process, and the pixel electrode layer is formed in a structure pattern region by a dropping method, and the source/drain electrode layer and the pixel electrode layer are connected through a via hole. .
2.根据权利要求 1所述的方法， 其中， 在所述钝化层中形成包括过孔的 结构图案采用以下构图工艺形成：  The method according to claim 1, wherein the forming of the structural pattern including the via holes in the passivation layer is formed by the following patterning process:
用半色调掩模板或灰色调掩模板对所述钝化层上方的光刻胶进行曝光处 理， 对应着形成所述过孔区域处的光刻胶被完全去除， 对应着形成所述像素 电极层区域处的光刻胶被部分去除。  Exposing the photoresist over the passivation layer with a halftone mask or a gray tone mask, corresponding to the photoresist formed at the via region being completely removed, corresponding to forming the pixel electrode layer The photoresist at the area is partially removed.
3.根据权利要求 1或 2所述的方法， 其中， 所述方法进一步包括： 对所 述像素电极层做固化及退火处理。  The method according to claim 1 or 2, wherein the method further comprises: curing and annealing the pixel electrode layer.
4.根据权利要求 3所述的方法， 其中， 用于形成所述像素电极层的材料 为含有铟元素、 锡元素以及氧元素的材料， 所述含有铟元素、 锡元素以及氧 元素的材料预先制成溶胶或墨水并灌注于喷嘴中， 通过喷嘴滴注在所述结构 图案区域内。  The method according to claim 3, wherein the material for forming the pixel electrode layer is a material containing an indium element, a tin element, and an oxygen element, and the material containing the indium element, the tin element, and the oxygen element is previously A sol or ink is formed and poured into the nozzle, and dripped through the nozzle in the area of the structural pattern.
5.根据权利要求 4所述的方法， 其中， 用于形成所述像素电极层的材料 为氧化铟锡溶胶或墨水， 所述氧化铟锡溶胶或墨水由以下方法制得：  The method according to claim 4, wherein the material for forming the pixel electrode layer is indium tin oxide sol or ink, and the indium tin oxide sol or ink is obtained by the following method:
将 InCl3.4H20和 SnCl4.5H20按 1: ( 1-3 ) 比例溶于水溶液中； 或者 将 In203和 SnCl4.5H20按 1: ( 2-6 ) 比例溶于 C2H5COOH中。 Dissolve InCl 3 .4H 2 0 and SnCl 4 .5H 2 0 in an aqueous solution at a ratio of 1: (1-3); or ratio of In 2 0 3 and SnCl 4 .5H 2 0 to 1: ( 2-6 ) Soluble in C 2 H 5 COOH.
6.根据权利要求 3所述的方法， 其中， 所述像素电极层退火处理的温度 范围为 300-600 °C。  The method according to claim 3, wherein the pixel electrode layer is annealed at a temperature ranging from 300 to 600 °C.
7.根据权利要求 3 所述的方法， 其中， 所述像素电极层的厚度范围为 20-150匪。  The method according to claim 3, wherein the pixel electrode layer has a thickness ranging from 20 to 150 Å.
8.根据权利要求 1-7任一所述的方法，其中，所述钝化层采用硅氧化物、 硅氮化物、 铪氧化物、 铝氧化物中的至少两种材料形成单层膜层或多层复合 膜层， 所述钝化层的厚度范围为 300-500nm。 The method according to any one of claims 1 to 7, wherein the passivation layer is formed of a single layer film using at least two materials of silicon oxide, silicon nitride, hafnium oxide, and aluminum oxide. The multilayer composite film layer has a thickness ranging from 300 to 500 nm.
9.一种薄膜晶体管阵列基板， 采用权利要求 1-8任一项所述的薄膜晶体 管阵列基板制备方法形成。 A thin film transistor array substrate formed by the method for producing a thin film transistor array substrate according to any one of claims 1-8.
10.一种显示装置， 包括权利要求 9所述的薄膜晶体管阵列基板。  A display device comprising the thin film transistor array substrate of claim 9.
PCT/CN2013/074957 2013-02-28 2013-04-28 Thin film transistor array substrate, preparation method and display device WO2014131242A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310064170.1A CN103151305B (en) 2013-02-28 2013-02-28 Thin film transistor array substrate, preparing method and display device
CN201310064170.1 2013-02-28

Publications (1)

Publication Number Publication Date
WO2014131242A1 true WO2014131242A1 (en) 2014-09-04

Family

ID=48549289

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/074957 WO2014131242A1 (en) 2013-02-28 2013-04-28 Thin film transistor array substrate, preparation method and display device

Country Status (2)

Country Link
CN (1) CN103151305B (en)
WO (1) WO2014131242A1 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103456740B (en) * 2013-08-22 2016-02-24 京东方科技集团股份有限公司 Pixel cell and manufacture method, array base palte and display unit
CN103489882A (en) * 2013-10-17 2014-01-01 京东方科技集团股份有限公司 Array substrate, preparation method for same and display device
CN103700673B (en) * 2013-12-24 2017-07-04 京东方科技集团股份有限公司 A kind of display device, array base palte and preparation method thereof
CN104538357B (en) * 2015-01-13 2018-05-01 合肥京东方光电科技有限公司 Make the method and array base palte of array base palte
CN105374852B (en) * 2015-11-16 2019-10-11 Tcl集团股份有限公司 A kind of printed form active display and preparation method thereof of no pixel bank
CN105470282B (en) * 2015-11-20 2020-03-31 Tcl集团股份有限公司 TFT-OLED (thin film transistor-organic light emitting diode) without pixel bank and preparation method
CN105489611A (en) * 2015-11-26 2016-04-13 Tcl集团股份有限公司 Printed type light emitting display and manufacturing method therefor
CN105336763B (en) * 2015-11-26 2019-08-02 Tcl集团股份有限公司 A kind of active display and preparation method thereof
CN105552103A (en) * 2015-12-25 2016-05-04 Tcl集团股份有限公司 Printed light emitting display and manufacturing method thereof
WO2018119652A1 (en) * 2016-12-27 2018-07-05 深圳市柔宇科技有限公司 Method for manufacturing array substrate
CN106775108A (en) * 2016-12-30 2017-05-31 武汉华星光电技术有限公司 A kind of In Cell touch-control array base paltes and preparation method thereof
CN111129106A (en) * 2020-01-20 2020-05-08 合肥京东方卓印科技有限公司 OLED substrate, preparation method thereof, display panel and display device
CN111312810A (en) * 2020-02-26 2020-06-19 合肥鑫晟光电科技有限公司 Array substrate and manufacturing method thereof, display panel and display device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020047963A1 (en) * 2000-10-25 2002-04-25 Lg. Philips Lcd Co., Ltd. Liquid crystal display panel and method for manufacturing the same
CN1871690A (en) * 2003-10-28 2006-11-29 株式会社半导体能源研究所 Method of manufacturing semiconductor device
CN1870225A (en) * 2005-05-27 2006-11-29 精工爱普生株式会社 Pixel electrode, method for forming the same, electrooptical device, and electronic apparatus
CN101034262A (en) * 2006-03-09 2007-09-12 京东方科技集团股份有限公司 Manufacturing method for array substrate of thin film transistor LCD
CN101487953A (en) * 2008-01-18 2009-07-22 北京京东方光电科技有限公司 Thin-film transistor LCD and its making method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI256732B (en) * 2002-08-30 2006-06-11 Sharp Kk Thin film transistor, liquid crystal display apparatus, manufacturing method of thin film transistor, and manufacturing method of liquid crystal display apparatus
KR101171056B1 (en) * 2005-08-16 2012-08-03 삼성전자주식회사 Liquid crystal display
US7847904B2 (en) * 2006-06-02 2010-12-07 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and electronic appliance
JP2009058717A (en) * 2007-08-31 2009-03-19 Seiko Epson Corp Electro-optical device, its manufacturing method, and electronic equipment
JPWO2010110179A1 (en) * 2009-03-23 2012-09-27 シャープ株式会社 Active element substrate, manufacturing method thereof, and display device using active element substrate manufactured by this manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020047963A1 (en) * 2000-10-25 2002-04-25 Lg. Philips Lcd Co., Ltd. Liquid crystal display panel and method for manufacturing the same
CN1871690A (en) * 2003-10-28 2006-11-29 株式会社半导体能源研究所 Method of manufacturing semiconductor device
CN1870225A (en) * 2005-05-27 2006-11-29 精工爱普生株式会社 Pixel electrode, method for forming the same, electrooptical device, and electronic apparatus
CN101034262A (en) * 2006-03-09 2007-09-12 京东方科技集团股份有限公司 Manufacturing method for array substrate of thin film transistor LCD
CN101487953A (en) * 2008-01-18 2009-07-22 北京京东方光电科技有限公司 Thin-film transistor LCD and its making method

Also Published As

Publication number Publication date
CN103151305B (en) 2015-06-03
CN103151305A (en) 2013-06-12

Similar Documents

Publication Publication Date Title
WO2014131242A1 (en) Thin film transistor array substrate, preparation method and display device
WO2016041304A1 (en) Thin film transistor and manufacturing method therefor, array substrate and manufacturing method therefor, and display device
TWI330890B (en) Liquid crystal display device and fabricating method thereof
WO2016000336A1 (en) Low-temperature poly-silicon tft array substrate, manufacturing method therefor, and display apparatus
WO2014166176A1 (en) Thin-film transistor and manufacturing method thereof, array base plate and display apparatus
WO2013131380A1 (en) Array substrate, manufacturing method thereof and display device thereof
WO2013013599A1 (en) Array substrate and manufacturing method thereof, liquid crystal panel, and display device
WO2013104228A1 (en) Method for manufacturing tft array substrate
WO2014127645A1 (en) Thin-film transistor and manufacturing method therefor, and display component
WO2013097554A1 (en) Method for manufacturing tft array substrate
WO2016165187A1 (en) Manufacturing method for dual-gate oxide semiconductor tft substrate, and structure of dual-gate oxide semiconductor tft substrate
CN107170759B (en) Array substrate, manufacturing method thereof and display device
WO2015096350A1 (en) Array substrate and preparation method therefor
WO2015096292A1 (en) Array substrate and manufacturing method thereof, and display device
WO2018113214A1 (en) Thin film transistor and manufacturing method therefor, display substrate and display device
WO2013135075A1 (en) Array substrate manufacturing method, array substrate and display device
WO2013127202A1 (en) Manufacturing method for array substrate, array substrate and display
WO2014146355A1 (en) Array substrate, manufacturing method therefor and display apparatus thereof
US10615282B2 (en) Thin-film transistor and manufacturing method thereof, array substrate, and display apparatus
TW201622158A (en) Thin film transistor and manufacturing method thereof
WO2015196633A1 (en) Array substrate manufacturing method, array substrate and display device
WO2015067054A1 (en) Cmos thin film transistor and manufacturing method thereof, array substrate and display device
WO2014117512A1 (en) Method for preparing thin film transistor, method for preparing thin film transistor driving back panel, and thin film transistor driving back panel
WO2013170574A1 (en) Oxide thin film transistor and manufacturing method thereof, array substrate and display device
WO2017024612A1 (en) Oxide semiconductor tft substrate manufacturing method and structure thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13876129

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 11/12/2015)

122 Ep: pct application non-entry in european phase

Ref document number: 13876129

Country of ref document: EP

Kind code of ref document: A1