CN106775108A - A kind of In Cell touch-control array base paltes and preparation method thereof - Google Patents
A kind of In Cell touch-control array base paltes and preparation method thereof Download PDFInfo
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- CN106775108A CN106775108A CN201611262899.XA CN201611262899A CN106775108A CN 106775108 A CN106775108 A CN 106775108A CN 201611262899 A CN201611262899 A CN 201611262899A CN 106775108 A CN106775108 A CN 106775108A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
- G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
- G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
- G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
- G06F2203/04111—Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
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Abstract
The present invention provides a kind of In Cell touch-control array base paltes and preparation method thereof, and the In Cell touch-controls array base palte includes underlay substrate, TFT structure layer, flatness layer, common electrode layer, the second interlayer insulating film, touch control electrode layer, pixel electrode insulating barrier and pixel electrode layer successively from the bottom up；Wherein, TFT drain top is provided with pixel electrode layer via, pixel electrode layer covers the pixel electrode layer via, pixel electrode insulating barrier is provided with pixel electrode layer groove, pixel electrode layer is on pixel electrode layer groove with pixel electrode layer via, and the surface of the pixel electrode layer beyond pixel electrode layer via, the surface with the pixel electrode insulating barrier outside pixel electrode layer groove is in same aspect.The present invention is solved in the prior art, due to the increase of the distance between public electrode and pixel electrode layer, causes the storage capacitors value formed between public electrode and pixel electrode layer to reduce, so that there is the problems such as signal cross-talk and electric leakage.
Description
【Technical field】
The present invention relates to field of liquid crystal display, more particularly to a kind of In-Cell touch-controls array base palte and preparation method thereof.
【Background technology】
The flat display apparatus such as liquid crystal display (Liquid Crystal Display, LCD) are because with high image quality, saving
Electricity, fuselage are thin and the advantages of have a wide range of application, and be widely used in mobile phone, TV, personal digital assistant, digital camera,
The various consumption electronic products such as notebook computer, desktop computer, as the main flow in display device.Liquid on existing market
It is backlight liquid crystal display that crystal device is most of, and it includes liquid crystal display panel (TFT-LCD) and backlight module.Liquid crystal
The operation principle of display panel is that liquid crystal molecule is placed in the middle of the parallel underlay substrate of two panels, is had perhaps in the middle of two panels underlay substrate
Many tiny electric wires vertically and horizontally, control liquid crystal molecule to change direction by whether being powered, and the light of backlight module is rolled over
Shoot out generation picture.
As shown in figure 14, in In-cell touch technologies, the size of coupled capacitor can influence touch-control sensitivity, that is, touch
The distance between control electrode layer 8 and common electrode layer 6 (Com ITO) (d1's in figure) is thicker, and its coupled capacitor is smaller, and touch-control is clever
Sensitivity is better.In existing In-cell touch technologies, in order to reach good touch-control sensitivity, often all d1 is increased,
But at the same time, the distance between pixel electrode layer 10 (Pixel ITO) and common electrode layer 6 d2 also can be with increases, its
Storage capacitors will reduce, and the size of storage capacitors can influence device signal to transmit, and storage capacitors are smaller, and Cross Talk show
As (i.e. signal cross-talk, signal and leakance to the region that should not be shown) is more serious, and storage capacitors are small, and leakage current is with electricity
The change of pressure will increase, brightness change increase, and Flicker phenomenons also can be more serious.
【The content of the invention】
It is an object of the invention to provide a kind of In-Cell touch-controls array base palte and preparation method thereof, to solve existing skill
In art, because by after the second interlayer insulating film increase between touch control electrode layer and public electrode so that public electrode and pixel
The distance between electrode layer increases, and then causes the capacitance of the storage capacitors formed between public electrode and pixel electrode layer to subtract
It is small, so that there is the problems such as signal cross-talk and electric leakage.
Technical scheme is as follows：
A kind of In-Cell touch-controls array base palte, the array base palte is including underlay substrate, on the underlay substrate
TFT structure layer, the flatness layer on TFT structure layer, the common electrode layer on a part of flatness layer, it is located at
The second interlayer insulating film on the common electrode layer and the flatness layer, the electricity of the touch-control on second interlayer insulating film
Pole layer, the pixel electrode insulating barrier on the touch control electrode layer with second interlayer insulating film, and located at a part
Pixel electrode layer on the pixel electrode insulating barrier；
Wherein, the corresponding flatness layer in TFT drain top of TFT structure layer, second interlayer insulating film with
The pixel electrode insulating barrier is provided with pixel electrode layer via, and the pixel electrode layer covers the pixel electrode layer via simultaneously
Contacted with the TFT drain by it, the preset position area of the pixel electrode insulating barrier is provided with pixel electrode layer groove,
The pixel electrode layer on the pixel electrode layer groove and the pixel electrode layer via, and in the pixel electrode layer
The surface of the pixel electrode layer beyond via, insulate with the pixel electrode outside the pixel electrode layer groove
The surface of layer is in same aspect.
Preferably, light shield layer is additionally provided with the underlay substrate, the underlay substrate is provided with shading with the light shield layer
Insulating barrier, the TFT structure layer is on the shading insulating barrier.
Preferably, the TFT structure layer includes：
TFT source contact portions, TFT drain contact site on the shading insulating barrier and connect positioned at the TFT source electrodes
Semiconductor active layer between contact portion and the TFT drain contact site；
Gate insulator on the TFT source contact portions, the TFT drain contact site and the semiconductor active layer
Layer；
Grid on the gate insulator, the grid is located at the corresponding grid in semiconductor active layer top
On insulating barrier；
The first interlayer insulating film on the grid with the gate insulator, the TFT source contact portions and institute
Corresponding first interlayer insulating film in TFT drain contact site top and the gate insulator position are stated, TFT sources are respectively equipped with
Pole via and TFT drain via, the TFT source electrodes via are provided with the TFT source electrodes contacted with the TFT source contact portions, institute
State TFT drain via and be provided with the TFT drain contacted with the TFT drain contact site；
Wherein, the flatness layer covers the TFT source electrodes and the TFT drain.
Preferably, between the TFT source contact portions and the TFT drain contact site and the semiconductor active layer respectively
It is provided with the doped layer of enhancing electric action.
Preferably, the making material of the light shield layer is metal material.
A kind of preparation method of In-Cell touch-control array base paltes as described in above-mentioned any one, comprises the following steps：
Light shield layer is formed on underlay substrate and cover the shading insulating barrier of the light shield layer and the underlay substrate：
TFT structure layer is formed on the light shield layer with the shading insulating barrier；
Flatness layer, common electrode layer, second layer insulating, touch control electrode layer are sequentially formed on TFT structure layer
With pixel electrode insulating barrier；
The corresponding pixel electrode insulating barrier forms pixel electrode insulating barrier via, and institute above the TFT drain
The pixel electrode insulating barrier for stating pixel electrode insulating barrier via bottom covers the TFT drain, the pixel electrode insulation
The side of layer via is followed successively by the pixel electrode insulating barrier, second layer insulating and the flatness layer from outside to inside；
Pixel electrode layer groove is formed in the preset position area of the pixel electrode insulating barrier, while making the TFT
Drain electrode is exposed to the pixel electrode insulating barrier via, and the pixel electrode layer groove is located at touch control electrode layer top correspondence
Outside the pixel electrode insulating barrier on；
Pixel electrode layer is formed on the pixel electrode layer groove with the pixel electrode insulating barrier via, while being formed
Pixel electrode layer via, and make the surface of the pixel electrode layer beyond the pixel electrode layer via, and positioned at described
The surface of the pixel electrode insulating barrier outside pixel electrode layer groove is in same aspect.
Preferably, flatness layer, common electrode layer, second layer insulating, touch-control are sequentially formed on TFT structure layer
Electrode layer and pixel electrode insulating barrier, specifically include：
Flatness layer is formed on TFT structure layer, the flatness layer covers the TFT structure layer；
Common electrode layer is formed on the flatness layer, the common electrode layer covers TFT drain top correspondence
Outer a part of described flatness layer；
Flatness layer via, the flatness layer via and institute are formed on the corresponding flatness layer above the TFT drain
TFT drain is stated to communicate；
Layer insulating between forming second in the flatness layer, the flatness layer via and the common electrode layer, and
Touch control electrode layer is formed on second layer insulating outside the correspondence of the TFT drain top；
Second layer insulating via, institute are formed on corresponding second layer insulating above the TFT drain
Second layer insulating via is stated to be communicated with the TFT drain；
Between the touch control electrode layer, second layer insulating and described second pixel is formed on layer insulating via
Electrode dielectric layer, the pixel electrode insulating barrier fills up second layer insulating via.
Preferably, during the pixel electrode insulating barrier forms the pixel electrode insulating barrier via, using covering
Lamina membranacea is exposed development to positivity photoresistance.
Preferably, the mistake of the pixel electrode layer groove is formed in the preset position area of the pixel electrode insulating barrier
Cheng Zhong, development is exposed using mask plate to negativity photoresistance.
Preferably, pixel electrode layer groove is formed in the preset position area of the pixel electrode insulating barrier, while making
The step of TFT drain is exposed to the pixel electrode layer via be：Development is exposed to positivity photoresistance using mask plate,
And its mask plate is identical with the mask plate used during the formation pixel electrode insulating barrier via.
Beneficial effects of the present invention：
A kind of In-Cell touch-controls array base palte of the invention and preparation method thereof, solves in the prior art, because will touch
Control electrode layer and public electrode between the second interlayer insulating film increase after so that between public electrode and pixel electrode layer away from
From increase, and then the capacitance of the storage capacitors formed between public electrode and pixel electrode layer is caused to reduce, so that there is letter
The problems such as number crosstalk and electric leakage.
【Brief description of the drawings】
Fig. 1 is In-Cell touch-controls array base palte the cuing open when light shield layer is formed with shading insulating barrier of the embodiment of the present invention
Face structural representation；
Fig. 2 is that cross-section structure of the In-Cell touch-controls array base palte of the embodiment of the present invention when TFT structure layer is formed is illustrated
Figure；
Fig. 3 is cross-sectional view of the In-Cell touch-controls array base palte of the embodiment of the present invention when flatness layer is formed；
Fig. 4 is that cross-section structure of the In-Cell touch-controls array base palte of the embodiment of the present invention when public electrode is formed is illustrated
Figure；
Fig. 5 is that cross-section structure of the In-Cell touch-controls array base palte of the embodiment of the present invention when flatness layer via is formed shows
It is intended to；
Fig. 6 is section knot of the In-Cell touch-controls array base palte of the embodiment of the present invention when second layer insulating is formed
Structure schematic diagram；
Fig. 7 is that cross-section structure of the In-Cell touch-controls array base palte of the embodiment of the present invention when touch control electrode layer is formed shows
It is intended to；
Fig. 8 is In-Cell touch-controls array base palte the cuing open when second layer insulating via is formed of the embodiment of the present invention
Face structural representation；
Fig. 9 is section knot of the In-Cell touch-controls array base palte of the embodiment of the present invention when pixel electrode insulating barrier is formed
Structure schematic diagram；
Figure 10 is In-Cell touch-controls array base palte the cuing open when pixel electrode insulating barrier via is formed of the embodiment of the present invention
Face structural representation；
Figure 11 is section knot of the In-Cell touch-controls array base palte of the embodiment of the present invention when pixel electrode layer groove is formed
Structure schematic diagram；
Figure 12 is covered forming pixel electrode layer and pixel electrode layer for the In-Cell touch-controls array base palte of the embodiment of the present invention
Cover cross-sectional view when whole pixel electrode insulating barrier and pixel electrode insulating barrier via；
Figure 13 is In-Cell touch-control array base palte overall structure diagrams or In-Cell the touch-controls battle array of the embodiment of the present invention
Cross-section structure when pixel electrode layer is formed on pixel electrode layer groove and pixel electrode insulating barrier via of row substrate is illustrated
Figure；
Figure 14 is the touch control electrode layer of In-Cell touch-control array base paltes of the embodiment of the present invention, pixel electrode layer and public
The distance between electrode layer relation schematic diagram；
Figure 15 is the preparation method flow chart of the In-Cell touch-control array base paltes of the embodiment of the present invention；
Figure 16 forms flatness layer, common electrical for the In-Cell touch-controls array base palte of the embodiment of the present invention on TFT structure layer
Pole layer, the flow chart of second layer insulating, touch control electrode layer and pixel electrode insulating barrier.
【Specific embodiment】
The explanation of following embodiment is, with reference to additional schema, to be used to illustrate the particular implementation that the present invention may be used to implement
Example.The direction term that the present invention is previously mentioned, for example " on ", D score, "front", "rear", "left", "right", " interior ", " outward ", " side "
Deng being only the direction with reference to annexed drawings.Therefore, the direction term for using is to illustrate and understand the present invention, and is not used to
The limitation present invention.In figure, the similar unit of structure is represented with identical label.
Embodiment one
Figure 13 is refer to, Figure 13 is the overall structure diagram of In-Cell touch-controls array base palte 100 of the present embodiment.
As seen from Figure 13, a kind of In-Cell touch-controls array base palte 100 of the invention, it includes underlay substrate 1, sets
In the TFT structure layer 4 on the underlay substrate 1, the flatness layer 5 on TFT structure layer 4, located at a part of described flat
Common electrode layer 6 on smooth layer 5, the second interlayer insulating film 7 in the common electrode layer 6 with the flatness layer 5, it is located at
Touch control electrode layer 8 on second interlayer insulating film 7, on the touch control electrode layer 8 with second interlayer insulating film 7
Pixel electrode insulating barrier 9, and the pixel electrode layer 10 on a part of pixel electrode insulating barrier 9；
Wherein, the corresponding flatness layer 5 in the top of TFT drain 49, second layer insulation of the TFT structure layer 4
Layer 7 is provided with pixel electrode layer via 93 with the pixel electrode insulating barrier 9, and the pixel electrode layer 10 covers the pixel electricity
Pole layer via 93 is simultaneously contacted by it with the TFT drain 49, and the preset position area of the pixel electrode insulating barrier 9 is provided with
Pixel electrode layer groove 92, the pixel electrode layer groove 92 is located at outside pixel electrode layer via 93, the pixel electrode layer
10 on the pixel electrode layer groove 92 and the pixel electrode layer via 93, and the pixel electrode layer via 93 with
The surface of the outer pixel electrode layer 10, with the pixel electrode insulating barrier outside the pixel electrode layer groove 92
9 surface is in same aspect.
In the present embodiment, light shield layer 2, the underlay substrate 1 and the shading are additionally provided with preferably described underlay substrate 1
Layer 2 is provided with shading insulating barrier 3, and the TFT structure layer 4 is on the shading insulating barrier 3.
In the present embodiment, the TFT structure layer 4 includes：
TFT source contact portions 41, TFT drain contact site 42 on the shading insulating barrier 3 and positioned at the TFT sources
Semiconductor active layer 43 between pole contact site 41 and the TFT drain contact site 42；
Grid on the TFT source contact portions 41, the TFT drain contact site 42 and the semiconductor active layer 43
Pole insulating barrier 45；
Grid 46 on the gate insulator 45, it is right that the grid 46 is located at the top of the semiconductor active layer 43
On the gate insulator 45 answered；
The first interlayer insulating film 47 on the grid 46 with the gate insulator 45, the TFT source contacts
Corresponding first interlayer insulating film 47 in the top of portion 41 and the TFT drain contact site 42 and the gate insulator 45
Put, be respectively equipped with the via of TFT source electrodes 48 and the via of TFT drain 49, the via of TFT source electrodes 48 is provided with and the TFT source electrodes
The TFT source electrodes 48 of the contact of contact site 41, the via of the TFT drain 49 is provided with the TFT contacted with the TFT drain contact site 42
Drain electrode 49；
Wherein, the flatness layer 5 covers the TFT source electrodes 48 and the TFT drain 49.
In the present embodiment, preferably described TFT source contact portions 41 and the TFT drain contact site 42 and the semiconductor
The doped layer 44 of enhancing electric action is respectively equipped between active layer 43.
In the present embodiment, the making material of preferably described light shield layer 2 is metal material.
A kind of In-Cell touch-controls array base palte 100 of the invention, by the predeterminated position of pixel electrode insulating barrier 9
Pixel electrode layer groove 92 is set, by pixel electrode layer 10 in pixel electrode layer groove 92, pixel electrode layer 10 is reduced
The distance between with common electrode layer 6, solve in the prior art, because by between touch control electrode layer 8 and common electrode layer 6
After second interlayer insulating film 7 increases so that the increase of the distance between common electrode layer 6 and pixel electrode layer 10, and then cause public affairs
The capacitance of the storage capacitors formed between common electrode layer 6 and pixel electrode layer 10 reduces, so that there is signal cross-talk and electric leakage
The problems such as.
Embodiment two
Figure 15 is refer to, Figure 15 is the preparation method flow of the In-Cell touch-controls array base palte 100 of the embodiment of the present invention
Figure.As seen from Figure 15, a kind of preparation method of In-Cell touch-controls array base palte 100 of the invention, comprises the following steps：
Step S101：Light shield layer 2 is formed on underlay substrate 1 and cover the screening of the light shield layer 2 and the underlay substrate 1
Light insulating barrier 3.As shown in figure 1, Fig. 1 is forming light shield layer 2 and shading for the In-Cell touch-controls array base palte 100 of the present embodiment
Cross-sectional view during insulating barrier 3.
Step S102：TFT structure layer 4 is formed on the light shield layer 2 with the shading insulating barrier 3.As shown in Fig. 2 Fig. 2
For the present embodiment In-Cell touch-controls array base palte 100 formed TFT structure layer 4 when cross-sectional view.
Step S103：Flatness layer 5,6, second layer insulating of common electrode layer are sequentially formed on TFT structure layer 4
7th, touch control electrode layer 8 and pixel electrode insulating barrier 9.As shown in figure 9, Fig. 9 is the In-Cell touch-control array base paltes of example of the present invention
100 cross-sectional view when pixel electrode insulating barrier 9 is formed.
Step S104：In the top of the TFT drain 49, the corresponding pixel electrode insulating barrier 9 forms pixel electrode insulation
Layer via 91, and the pixel electrode insulating barrier 9 of the bottom of pixel electrode insulating barrier via 91 covers the TFT drain
49, the side of the pixel electrode insulating barrier via 91 is followed successively by between the pixel electrode insulating barrier 9, described second from outside to inside
Layer insulating 7 and the flatness layer 5.As shown in Figure 10, Figure 10 is the In-Cell touch-controls array base palte 100 of the present embodiment in shape
Cross-sectional view during pixel electrode dielectric layer via 91.
Step S105：Pixel electrode layer groove 92 is formed in the preset position area of the pixel electrode insulating barrier 9, together
When the TFT drain 49 is exposed to the pixel electrode insulating barrier via 91, the pixel electrode layer groove 92 is located at described
On the pixel electrode insulating barrier 9 outside the correspondence of the top of touch control electrode layer 8.As shown in figure 11, Figure 11 is the In- of the present embodiment
Cross-sectional view of the Cell touch-controls array base palte 100 when pixel electrode layer groove 92 is formed.
Step S106：Pixel electricity is formed on the pixel electrode layer groove 92 with the pixel electrode insulating barrier via 91
Pole layer 10, while forming pixel electrode layer via 93, makes the pixel electrode layer beyond the pixel electrode layer via 93
10 surface, the surface with the pixel electrode insulating barrier 9 outside the pixel electrode layer groove 92 is in same layer
Face.As shown in Figures 12 and 13, Figure 12 for the present embodiment In-Cell touch-controls array base palte 100 formed pixel electrode layer 10 and
Pixel electrode layer 10 covers cross-sectional view when whole pixel electrode insulating barrier 9 and pixel electrode insulating barrier via 91,
Figure 13 is the In-Cell touch-controls array base palte 100 of the present embodiment in pixel electrode layer groove 92 and pixel electrode insulating barrier mistake
Cross-sectional view during pixel electrode layer 10 is formed on hole 91.
As shown in figure 16, Figure 16 for the embodiment of the present invention In-Cell touch-controls array base palte 100 TFT structure layer 4 on shape
Into the flow chart of flatness layer 5,6, second layer insulating 7 of common electrode layer, touch control electrode layer 8 and pixel electrode insulating barrier 9.
In the present embodiment, to sequentially form flatness layer 5, common electrode layer 6, the second interbed exhausted on TFT structure layer 4
Edge layer 7, touch control electrode layer 8 and pixel electrode insulating barrier 9, specifically include following steps：
Step S201：Flatness layer 5 is formed on TFT structure layer 4, the flatness layer 5 covers the TFT structure layer 4；
Step S202：Common electrode layer 6 is formed on the flatness layer 5, the common electrode layer 6 covers the TFT leakages
A part of described flatness layer 5 outside the correspondence of the top of pole 49；
Step S203：Flatness layer via 51 is formed on the corresponding flatness layer 5 in the top of the TFT drain 49, it is described
Flatness layer via 51 is communicated with the TFT drain 49；
Step S204：Formed between second in the flatness layer 5, the flatness layer via 51 and the common electrode layer 6
Touch control electrode layer is formed on layer insulating 7, and second layer insulating 7 outside the correspondence of the top of the TFT drain 49
8；
Step S205：It is exhausted the second interbed to be formed on corresponding second layer insulating 7 in the top of the TFT drain 49
Edge layer via 71, second layer insulating via 71 is communicated with the TFT drain 49；
Step S206：The layer insulating mistake between the touch control electrode layer 8, second layer insulating 7 and described second
Pixel electrode insulating barrier 9 is formed on hole 71, the pixel electrode insulating barrier 9 fills up second layer insulating via 71.
In the present embodiment, during pixel electrode insulating barrier 9 forms pixel electrode insulating barrier via 91, using covering
Lamina membranacea is exposed development to positivity photoresistance.
In the present embodiment, the pixel electrode layer is formed in the preset position area of the pixel electrode insulating barrier 9
During groove 92, development is exposed to negativity photoresistance using mask plate.
In the present embodiment, pixel electrode layer groove is formed in the preset position area of the pixel electrode insulating barrier 9
92, at the same the step of making the TFT drain 49 be exposed to pixel electrode layer via 93 be：Using mask plate to positivity photoresistance
Be exposed development, and its mask plate with form the pixel electrode insulating barrier via 91 during the mask plate phase that uses
Together.
The preparation method of a kind of In-Cell touch-controls array base palte 100 of the invention, by pixel electrode insulating barrier 9
Pixel electrode layer groove 92 is set on predeterminated position, by pixel electrode layer 10 in pixel electrode layer groove 92, picture is reduced
The distance between plain electrode layer 10 and common electrode layer 6, solve in the prior art, because by touch control electrode layer 8 and common electrical
After the second interlayer insulating film 7 between pole layer 6 increases so that the increase of the distance between common electrode layer 6 and pixel electrode layer 10,
And then cause the capacitance of the storage capacitors formed between common electrode layer 6 and pixel electrode layer 10 to reduce, so that there is signal
The problems such as crosstalk and electric leakage.Further, since forming pixel electrode layer in the preset position area of the pixel electrode insulating barrier 9
Groove 92, development is exposed using mask plate to positivity photoresistance, its mask plate with form the pixel electrode insulating barrier via
The mask plate used during 91 is identical, it is to avoid rearranges the operation of mask plate, saves production process and manpower thing
Power is consumed.
In sum, although the present invention it is disclosed above with preferred embodiment, but above preferred embodiment and be not used to limit
The system present invention, one of ordinary skill in the art without departing from the spirit and scope of the present invention, can make various changes and profit
Adorn, therefore protection scope of the present invention is defined by the scope that claim is defined.
Claims (10)
1. a kind of In-Cell touch-controls array base palte, it is characterised in that the array base palte includes underlay substrate, located at the lining
TFT structure layer on substrate, the flatness layer, public on a part of flatness layer on TFT structure layer
Electrode layer, the second interlayer insulating film in the common electrode layer with the flatness layer, located at second layer insulation
Touch control electrode layer on layer, the pixel electrode insulating barrier on the touch control electrode layer with second interlayer insulating film, with
And the pixel electrode layer on a part of pixel electrode insulating barrier；
Wherein, the corresponding flatness layer in TFT drain top of TFT structure layer, second interlayer insulating film with it is described
Pixel electrode insulating barrier is provided with pixel electrode layer via, and the pixel electrode layer covers the pixel electrode layer via and passes through
It is contacted with the TFT drain, and the preset position area of the pixel electrode insulating barrier is provided with pixel electrode layer groove, described
Pixel electrode layer on the pixel electrode layer groove and the pixel electrode layer via, and in the pixel electrode layer via
The surface of the pixel electrode layer in addition, with the pixel electrode insulating barrier outside the pixel electrode layer groove
Surface is in same aspect.
2. In-Cell touch-controls array base palte according to claim 1, it is characterised in that be additionally provided with the underlay substrate
Light shield layer, the underlay substrate is provided with shading insulating barrier with the light shield layer, and the TFT structure layer is located at shading insulation
On layer.
3. In-Cell touch-controls array base palte according to claim 2, it is characterised in that the TFT structure layer includes：
TFT source contact portions, TFT drain contact site on the shading insulating barrier and positioned at the TFT source contact portions
With the semiconductor active layer between the TFT drain contact site；
Gate insulator on the TFT source contact portions, the TFT drain contact site and the semiconductor active layer；
Grid on the gate insulator, the grid is located at the corresponding gate insulator in semiconductor active layer top
On layer；
The first interlayer insulating film on the grid with the gate insulator, the TFT source contact portions and the TFT
Corresponding first interlayer insulating film in drain contact top and the gate insulator position, are respectively equipped with TFT source electrode mistakes
Hole and TFT drain via, the TFT source electrodes via are provided with the TFT source electrodes contacted with the TFT source contact portions, the TFT
Drain via is provided with the TFT drain contacted with the TFT drain contact site；
Wherein, the flatness layer covers the TFT source electrodes and the TFT drain.
4. In-Cell touch-controls array base palte according to claim 3, it is characterised in that the TFT source contact portions and institute
State the doped layer that enhancing electric action is respectively equipped between TFT drain contact site and the semiconductor active layer.
5. In-Cell touch-controls array base palte according to claim 2, it is characterised in that the making material of the light shield layer
It is metal material.
6. the preparation method of a kind of In-Cell touch-control array base paltes as described in any one of Claims 1 to 5, it is characterised in that
Comprise the following steps：
Light shield layer is formed on underlay substrate and cover the shading insulating barrier of the light shield layer and the underlay substrate：
TFT structure layer is formed on the light shield layer with the shading insulating barrier；
Flatness layer, common electrode layer, second layer insulating, touch control electrode layer and picture are sequentially formed on TFT structure layer
Plain electrode dielectric layer；
The corresponding pixel electrode insulating barrier forms pixel electrode insulating barrier via, and the picture above the TFT drain
The pixel electrode insulating barrier of plain electrode dielectric layer via bottom covers the TFT drain, the pixel electrode insulating barrier mistake
The side in hole is followed successively by the pixel electrode insulating barrier, second layer insulating and the flatness layer from outside to inside；
Pixel electrode layer groove is formed in the preset position area of the pixel electrode insulating barrier, while making the TFT drain
The pixel electrode insulating barrier via is exposed to, the pixel electrode layer groove is outside the correspondence of touch control electrode layer top
The pixel electrode insulating barrier on；
Pixel electrode layer is formed on the pixel electrode layer groove with the pixel electrode insulating barrier via, while forming pixel
Electrode layer via, and make the surface of the pixel electrode layer beyond the pixel electrode layer via, and positioned at the pixel
The surface of the pixel electrode insulating barrier outside electrode layer groove is in same aspect.
7. preparation method according to claim 6, it is characterised in that sequentially formed on the TFT structure layer flatness layer,
Common electrode layer, second layer insulating, touch control electrode layer and pixel electrode insulating barrier, specifically include：
Flatness layer is formed on TFT structure layer, the flatness layer covers the TFT structure layer；
Common electrode layer is formed on the flatness layer, the common electrode layer is covered outside the correspondence of the TFT drain top
A part of flatness layer；
Flatness layer via, the flatness layer via and the TFT are formed on the corresponding flatness layer above the TFT drain
Drain electrode is communicated；
Layer insulating between forming second in the flatness layer, the flatness layer via and the common electrode layer, and described
Touch control electrode layer is formed on second layer insulating outside the correspondence of TFT drain top；
Second layer insulating via, described the are formed on corresponding second layer insulating above the TFT drain
Two layer insulating vias are communicated with the TFT drain；
Between the touch control electrode layer, second layer insulating and described second pixel electrode is formed on layer insulating via
Insulating barrier, the pixel electrode insulating barrier fills up second layer insulating via.
8. preparation method according to claim 6, it is characterised in that form the pixel in the pixel electrode insulating barrier
During electrode dielectric layer via, development is exposed to positivity photoresistance using mask plate.
9. preparation method according to claim 6, it is characterised in that in the predeterminated position area of the pixel electrode insulating barrier
During the pixel electrode layer groove is formed on domain, development is exposed to negativity photoresistance using mask plate.
10. preparation method according to claim 6, it is characterised in that in the predeterminated position of the pixel electrode insulating barrier
Pixel electrode layer groove is formed on region, while the step of making the TFT drain be exposed to the pixel electrode layer via is：Adopt
During development, and its mask plate and the formation pixel electrode insulating barrier via are exposed to positivity photoresistance with mask plate
The mask plate of use is identical.
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