CN103151305B - Thin film transistor array substrate, preparing method and display device - Google Patents
Thin film transistor array substrate, preparing method and display device Download PDFInfo
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- CN103151305B CN103151305B CN201310064170.1A CN201310064170A CN103151305B CN 103151305 B CN103151305 B CN 103151305B CN 201310064170 A CN201310064170 A CN 201310064170A CN 103151305 B CN103151305 B CN 103151305B
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- 239000010409 thin film Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000000758 substrate Substances 0.000 title claims abstract description 13
- 238000002161 passivation Methods 0.000 claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 30
- 238000002360 preparation method Methods 0.000 claims description 25
- 230000008569 process Effects 0.000 claims description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 239000012212 insulator Substances 0.000 claims description 16
- 238000000059 patterning Methods 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical group O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 10
- 239000002131 composite material Substances 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 5
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910021617 Indium monochloride Inorganic materials 0.000 claims description 4
- APHGZSBLRQFRCA-UHFFFAOYSA-M indium(1+);chloride Chemical compound [In]Cl APHGZSBLRQFRCA-UHFFFAOYSA-M 0.000 claims description 4
- 125000000896 monocarboxylic acid group Chemical group 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 239000000203 mixture Substances 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 239000004411 aluminium Substances 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 6
- 150000004706 metal oxides Chemical class 0.000 description 6
- 229910052750 molybdenum Inorganic materials 0.000 description 6
- 239000011733 molybdenum Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 239000002210 silicon-based material Substances 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- XBDQKXXYIPTUBI-UHFFFAOYSA-N dimethylselenoniopropionate Natural products CCC(O)=O XBDQKXXYIPTUBI-UHFFFAOYSA-N 0.000 description 4
- KHMOASUYFVRATF-UHFFFAOYSA-J tin(4+);tetrachloride;pentahydrate Chemical compound O.O.O.O.O.Cl[Sn](Cl)(Cl)Cl KHMOASUYFVRATF-UHFFFAOYSA-J 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001257 Nb alloy Inorganic materials 0.000 description 2
- 229910000583 Nd alloy Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- VVTQWTOTJWCYQT-UHFFFAOYSA-N alumane;neodymium Chemical compound [AlH3].[Nd] VVTQWTOTJWCYQT-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- UVLYPUPIDJLUCM-UHFFFAOYSA-N indium;hydrate Chemical compound O.[In] UVLYPUPIDJLUCM-UHFFFAOYSA-N 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 235000019260 propionic acid Nutrition 0.000 description 2
- IUVKMZGDUIUOCP-BTNSXGMBSA-N quinbolone Chemical compound O([C@H]1CC[C@H]2[C@H]3[C@@H]([C@]4(C=CC(=O)C=C4CC3)C)CC[C@@]21C)C1=CCCC1 IUVKMZGDUIUOCP-BTNSXGMBSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- RICKKZXCGCSLIU-UHFFFAOYSA-N 2-[2-[carboxymethyl-[[3-hydroxy-5-(hydroxymethyl)-2-methylpyridin-4-yl]methyl]amino]ethyl-[[3-hydroxy-5-(hydroxymethyl)-2-methylpyridin-4-yl]methyl]amino]acetic acid Chemical compound CC1=NC=C(CO)C(CN(CCN(CC(O)=O)CC=2C(=C(C)N=CC=2CO)O)CC(O)=O)=C1O RICKKZXCGCSLIU-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- NCMAYWHYXSWFGB-UHFFFAOYSA-N [Si].[N+][O-] Chemical compound [Si].[N+][O-] NCMAYWHYXSWFGB-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- YZZNJYQZJKSEER-UHFFFAOYSA-N gallium tin Chemical compound [Ga].[Sn] YZZNJYQZJKSEER-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
- G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/80—Constructional details
- H10K59/805—Electrodes
- H10K59/8051—Anodes
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- Condensed Matter Physics & Semiconductors (AREA)
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- Thin Film Transistor (AREA)
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Abstract
The invention relates to a preparing method of a thin film transistor array substrate, a thin film transistor array substrate and a display device, and belongs to the displaying technical field. The preparing method comprises the following steps of: forming a gate electrode layer, a gate insulation layer, an active layer, a source and drain electrode layer, a passivation layer and a pixel electroed layer on the substrate, wherein the passivation layer forms a structure pattern comprising through holes through a composition technology, the pixel electrode layer is formed in the structure pattern region by a dripping mode, and the source and drain electrode layer is connected with the pixel electrode layer through the through holes. By the preparing method, the steps for forming the pixel electrode layer by the composition technology are reduced, the usage amount of a mask plate is reduced, the use ratio of the pixel electrode forming material is improved, and the production cost is reduced.
Description
Technical field
The invention belongs to Display Technique field, be specifically related to a kind of thin-film transistor array base-plate preparation method, thin-film transistor array base-plate and display unit.
Background technology
In recent years, Display Technique is developed fast, as thin-film transistor (Th i n Fi l mTrans istor: be called for short TFT) technology develops into present low-temperature polysilicon film transistor, metal oxide semiconductor films transistor etc. by original amorphous silicon film transistor.And luminescence technology is also by ORGANIC ELECTROLUMINESCENCE DISPLAYS (Organic Light-Emitting Diode: the be called for short OLED) technology that original liquid crystal display (Liquid Crystal Display: be called for short LCD) technical development is present.
Thin-film transistor, as the driving element of display unit, is directly connected to the developing direction of high performance flat display unit.Thin-film transistor generally comprises the gate electrode layer 2, gate insulator 3, active layer 4, source-drain electrode layer 6, passivation layer 7 and the pixel electrode layer 8 that are formed successively on substrate 1, and described source-drain electrode layer 6 is connected by via hole with described pixel electrode layer 8.Wherein, the TFT cutaway view that active layer 4 adopts amorphous silicon material to be formed as shown in Figure 1, is ohmic contact layer 51 above active layer; The TFT cutaway view that active layer 4 adopts metal oxide semiconductor material to be formed as shown in Figure 2, is etching barrier layer 52 above active layer.
In above-mentioned two kinds of thin-film transistors, pixel electrode layer all adopts tin indium oxide to be formed.In the preparation process of thin-film transistor, in order to form the pattern of pixel electrode layer, need first to form certain thickness tin indium oxide rete by sputtering mode, then by photoetching processes such as mask plate exposures by Graphic transitions on tin indium oxide rete, cause pixel electrode and form the waste of material.Meanwhile, in the preparation process of thin-film transistor array base-plate, the number of times of used mask plate is more, then production efficiency is lower, and production cost is higher.
Therefore, how to reduce the number of times of patterning processes in the preparation process of thin-film transistor array base-plate further, enhance productivity, improve the utilance that pixel electrode forms material, reducing production cost is problem demanding prompt solution in industry.
Summary of the invention
Technical problem to be solved by this invention is for above shortcomings in prior art, a kind of thin-film transistor array base-plate preparation method, thin-film transistor array base-plate and display unit are provided, this thin-film transistor array base-plate preparation method simplifies the production technology of thin-film transistor array base-plate, improves the utilance that pixel electrode forms material.
The technical scheme that solution the technology of the present invention problem adopts is this thin-film transistor array base-plate preparation method, comprise the following steps: on substrate, form gate electrode layer, gate insulator, active layer, source-drain electrode layer, passivation layer and pixel electrode layer, described passivation layer forms the structure plan comprising via hole by patterning processes, described pixel electrode layer is formed in structure plan region by instillation mode, and described source-drain electrode layer is connected by via hole with described pixel electrode layer.
Preferably, in described passivation layer, form the structure plan comprising via hole adopts following patterning processes to be formed: carry out exposure-processed with half-tone mask plate or gray mask plate to the photoresist above described passivation layer, correspond to the photoresist forming described via area place is complete exposure-processed, and correspond to the photoresist forming described pixel electrode layer region place is half exposure-processed.
Preferably, described method also comprises further: do described pixel electrode layer and solidify and annealing in process.
Preferably, material for the formation of described pixel electrode layer is the material containing phosphide element, tin element and oxygen element, the described material containing phosphide element, tin element and oxygen element is made colloidal sol or ink in advance and is poured in nozzle, is instiled in described structure plan region by nozzle.
Preferably, the material for the formation of described pixel electrode layer is tin indium oxide colloidal sol or ink, and described tin indium oxide colloidal sol or ink are obtained by following methods: by InCl
34H
2o and SnCl
45H
2o is in 1:(1-3) in the water-soluble solution of ratio;
Or, by In
2o
3and SnCl
45H
2o is in 1:(2-6) ratio is dissolved in C
2h
5in COOH.
Preferably, the temperature range of described pixel electrode layer annealing in process is 300-600 DEG C.
Further preferably, the thickness range of described pixel electrode layer is 20-150nm.
Preferably, described passivation layer adopts at least bi-material in Si oxide, silicon nitride, hafnium oxide, aluminum oxide to form individual layer rete or MULTILAYER COMPOSITE rete, and the thickness range of described passivation layer is 300-500nm.
A kind of thin-film transistor array base-plate, adopts above-mentioned thin-film transistor array base-plate preparation method to be formed.
A kind of display unit, comprises above-mentioned thin-film transistor array base-plate.
The invention has the beneficial effects as follows: adopt thin-film transistor array base-plate preparation method of the present invention, the formation of middle thin-film transistor array base-plate compared to existing technology, decrease the step adopting patterning processes to form pixel electrode layer, decrease the use amount of mask plate, improve the utilance that pixel electrode forms material, reduce production cost simultaneously.
Accompanying drawing explanation
Fig. 1 is the cutaway view (adopting amorphous silicon material to be formed with active layer) of thin-film transistor array base-plate in prior art;
Fig. 2 is the cutaway view (adopting metal oxide semiconductor material to be formed with active layer) of thin-film transistor array base-plate in prior art;
Fig. 3 is the cutaway view of thin-film transistor array base-plate in the embodiment of the present invention 1;
Fig. 4 is the preparation process figure of thin-film transistor array base-plate in Fig. 3;
Fig. 5 is the cutaway view of thin-film transistor array base-plate in the embodiment of the present invention 2;
Fig. 6 is the preparation process figure of thin-film transistor array base-plate in Fig. 5.
In figure: 1-substrate; 2-gate electrode layer; 3-gate insulator; 4-active layer; 51-ohmic contact layer; 52-etching barrier layer; 6-source-drain electrode layer; 7-passivation layer; 8-pixel electrode layer; 9-via hole; 10-nozzle.
Embodiment
For making those skilled in the art understand technical scheme of the present invention better, below in conjunction with the drawings and specific embodiments, thin-film transistor array base-plate preparation method of the present invention, thin-film transistor array base-plate and display unit are described in further detail.
A kind of thin-film transistor array base-plate preparation method, comprise the following steps: on substrate, form gate electrode layer, gate insulator, active layer, source-drain electrode layer, passivation layer, wherein, described passivation layer forms the structure plan comprising via hole by patterning processes, described pixel electrode layer is formed in structure plan region by instillation mode, and described source-drain electrode layer is connected by via hole with described pixel electrode layer.
A kind of thin-film transistor array base-plate, adopts above-mentioned thin-film transistor array base-plate preparation method to be formed.
A kind of display unit, comprises above-mentioned thin-film transistor array base-plate.
Embodiment 1:
As shown in Figure 3, the thin-film transistor array base-plate in the present embodiment is included in substrate 1(and is also substrate) upper formation gate electrode layer 2, gate insulator 3, active layer 4, source-drain electrode layer 6, passivation layer 7 and pixel electrode layer 8.Wherein, described passivation layer 7 forms the structure plan comprising via hole by patterning processes, described pixel electrode layer 8 is formed in structure plan region by instillation mode, and described source-drain electrode layer 6 is connected by via hole with described pixel electrode layer 8.
In the present embodiment, described active layer 4 adopts amorphous silicon material to be formed, accordingly, ohmic contact layer 51 is also formed above described active layer 4, described ohmic contact layer 51 adopts the amorphous silicon material of Doping Phosphorus element to be formed, and the exemplary cross sections of this thin-film transistor array base-plate as shown in Figure 3.
As shown in figs 4 a-4g, in the present embodiment, the preparation method of thin-film transistor array base-plate specifically comprises the steps:
S1) on substrate, gate electrode layer, gate insulator, active layer, source-drain electrode layer is formed successively.
In this step, as shown in fig. 4 a, first above substrate 1, gate electrode layer 2 is formed.The single or multiple lift composite laminate that described gate electrode layer 2 adopts at least one material in molybdenum (Mo), molybdenum niobium alloy (MoNb), aluminium (Al), aluminium neodymium alloy (AlNd), titanium (Ti) and copper (Cu) to be formed, be preferably molybdenum (Mo), aluminium (Al) or containing the individual layer rete of alloy composition of molybdenum (Mo), aluminium (Al) or MULTILAYER COMPOSITE rete, the thickness range of described gate electrode layer 2 is 100nm-500nm.
As shown in Figure 4 b, at the disposed thereon gate insulator 3 of gate electrode layer 2.Described gate insulator 3 adopts Si oxide (SiO
x), silicon nitride (S iN
x), hafnium oxide (HfO
x), silicon nitrogen oxide (SiON), aluminum oxide (AlO
x) etc. in one or both form MULTILAYER COMPOSITE retes.Such as: the structure of gate insulator 3 can for adopting SiN
x/ SiO
xthe laminated construction formed, also can for adopting SiN
x/ SiON/SiO
xthe laminated construction formed, the thickness range of gate insulator is 100-400nm, as SiN
x, SiO
xor each thicknesses of layers of SiON can do flexible adjustment according to design needs, repeats no more here.Described gate insulator 3 using plasma strengthens chemical vapour deposition technique (Plasma Enhanced Chemical Vapor Deposition is called for short PECVD) and is formed.
As illustrated in fig. 4 c, above gate insulator 3, active layer 4 is formed with.In the present embodiment, described active layer 4 adopts amorphous silicon material to be formed, and described amorphous silicon material strengthens chemical vapour deposition technique (PECVD) by using plasma and formed, and the thickness range of active layer 4 is 30-200nm.
As shown in figure 4d, accordingly, above active layer 4, ohmic contact layer 51 is formed.Described ohmic contact layer adopts the material of the amorphous silicon of Doping Phosphorus element, and formed by PECVD method, the thickness range of described ohmic contact layer is 30-100nm.
As shown in fig 4e, above described ohmic contact layer 51, source-drain electrode layer 6 is formed.The single or multiple lift composite laminate that described source-drain electrode layer 6 adopts at least one material in molybdenum (Mo), molybdenum niobium alloy (MoNb), aluminium (Al), aluminium neodymium alloy (AlNd), titanium (Ti) and copper (Cu) to be formed, be preferably molybdenum (Mo), aluminium (Al) or containing the individual layer rete of alloy composition of molybdenum (Mo), aluminium (Al) or MULTILAYER COMPOSITE rete, the thickness range of described source-drain electrode layer is 100-500nm.
S2) form passivation layer, in described passivation layer, formed the structure plan of described pixel electrode layer and described via hole by patterning processes simultaneously.
As shown in fig. 4f, above source-drain electrode layer 6, passivation layer 7 is formed.Wherein, described passivation layer 7 adopts Si oxide (SiO
x), silicon nitride (SiN
x), hafnium oxide (HfO
x), aluminum oxide (AlO
x) etc. at least bi-material form individual layer rete or MULTILAYER COMPOSITE rete, described passivation layer using plasma strengthens chemical vapour deposition technique (PECVD) and is formed, and the thickness range of described passivation layer is 300-500nm.
Wherein, described passivation layer 7 forms the structure plan comprising via hole and adopts following patterning processes to be formed: in described passivation layer, carry out exposure-processed with half-tone mask plate or gray mask plate to the photoresist above described passivation layer, correspond to the photoresist forming described via area place is complete exposure-processed, and correspond to the photoresist forming described pixel electrode layer region place is half exposure-processed.By adopting patterning processes to do patterned process to passivation layer 7, to form the structure plan of described pixel electrode layer and described via hole simultaneously.
Wherein, patterning processes generally includes the steps such as photoresist coating, exposure, development, etching, photoresist lift off.For the rete itself with photosensitive character, can omit and make with photoresist, now patterning processes can save the step of photoresist coating, etching, photoresist lift off.
In concrete preparation process: first, first above passivation layer 7, apply one deck photoresist, adopt half-tone mask plate or gray mask plate to do complete exposure-processed by correspond to the photoresist forming via hole 9 region, half exposure-processed is done to the photoresist of the deposition region forming pixel electrode layer; Then, etch at the passivation layer 7 that correspond to formation via hole 9 region, the control of etch period decides according to the thickness of concrete production technology and passivation layer, is advisable (now passivation layer 7 is not carved completely) with the degree of depth reaching design; Then, photoresist residual for half exposure area that correspond to formation pixel electrode layer 8 region is removed by cineration technics and dry etching method; Finally, doing overall etching by correspond to the region forming via hole and the region forming pixel electrode layer, while described via hole 9 has etched, forming the structure plan of pixel electrode layer.
S3) material for the formation of described pixel electrode layer is instiled in described structure plan region, to form described pixel electrode layer.
As shown in figure 4g, the material for the formation of described pixel electrode layer is instiled in structure plan region by nozzle 10, to form transparent pixel electrode layer 8.
Wherein, material for the formation of described pixel electrode layer is the material containing phosphide element, tin element and oxygen element, the described material containing phosphide element, tin element and oxygen element is made colloidal sol or ink in advance and is poured in nozzle, is instiled in described structure plan region by nozzle.Concrete, the material for the formation of described pixel electrode layer is tin indium oxide (ITO) colloidal sol or ink, and described tin indium oxide colloidal sol or ink are obtained by following methods: by InCl
34H
2o(tetra-trichloride hydrate indium) and SnCl
45H
2o(Tin tetrachloride pentahydrate) in 1:(1-3) in the water-soluble solution of ratio, be preferably InCl
34H
2o(tetra-trichloride hydrate indium) and SnCl
45H
2o(Tin tetrachloride pentahydrate) in the water-soluble solution of 1:1 ratio; Or, by In
2o
3(indium sesquioxide) and SnCl
45H
2o(Tin tetrachloride pentahydrate) in 1:(2-6) ratio is dissolved in C
2h
5in COOH (propionic acid), be preferably In
2o
3(indium sesquioxide) and SnCl
45H
2o(Tin tetrachloride pentahydrate) be dissolved in C in 1:2 ratio
2h
5in COOH (propionic acid).
S4) described pixel electrode layer is done solidify and annealing in process.
In this step, the pixel electrode layer 8 after shaping is done solidify and annealing in process.The temperature range of described pixel electrode layer 8 annealing in process is 300-600 DEG C, and this temperature, higher than the annealing temperature (230-300 DEG C) of pixel electrode layer in prior art, so that pixel electrode layer can crystallization better, obtains better electric conductivity simultaneously.
Wherein, the thickness range of described pixel electrode layer is 20-150nm.
A kind of display unit, comprises the thin-film transistor array base-plate adopting the present embodiment thin-film transistor array base-plate preparation method to be formed.
Embodiment 2:
The difference of the present embodiment and embodiment 1 is, the active layer 4 in the present embodiment thin-film transistor array base-plate adopts metal-oxide semiconductor (MOS) to be formed, and the exemplary cross sections of this thin-film transistor array base-plate as shown in Figure 5.
In the present embodiment, the preparation process of thin-film transistor array base-plate is as shown in Fig. 6 a-6g.
Wherein, as fig. 6 c, above described gate insulator 3, active layer 4 is formed with.In the present embodiment, described active layer 4 adopts metal-oxide semiconductor (MOS) to be formed, described metal-oxide semiconductor (MOS) adopts at least two kinds of elements by comprising in oxygen element (O) and indium (In), gallium (Ga), zinc (Zn), tin (Sn) to be formed (namely it must comprise oxygen element), described active layer adopts indium oxide gallium zinc (IGZO), indium zinc oxide (IZO), tin indium oxide (InSnO), indium oxide gallium tin (InGaSnO) to be formed, preferred IGZO and IZO.Described active layer is by sputtering mode or inkjet printing mode or colloidal sol spin coating mode and do annealing in process and formed, and annealing region is 200-500 DEG C, and the thickness range of described active layer is 10-100nm.
Accordingly, above described active layer, be also formed with etching barrier layer 52, described etching barrier layer adopts Si oxide (SiO
x), silicon nitride (SiN
x), hafnium oxide (HfO
x), aluminum oxide (AlO
x) at least two kinds of (two or three) materials form individual layer retes or MULTILAYER COMPOSITE rete, described etch stop layer thickness scope is 50-200nm.
The concrete preparation process of gate electrode layer 2, gate insulator 3, source-drain electrode layer 6 and passivation layer 7 in the present embodiment, comprises its material selected separately, corresponding thickness is identical with embodiment 1 respectively with generation type, repeat no more here.
In the present embodiment, in described gate insulator 3, described passivation layer 7 and described etching barrier layer 52, hydrogen content is less than or equal to 10%.When preparing above-mentioned three kinds of Rotating fields, need control the level of hydrogen content in equivalent layer, to ensure that it has good surface characteristic, preferably in above-mentioned three kinds of Rotating fields, hydrogen content is less than or equal to 10%.
A kind of display unit, comprises the thin-film transistor array base-plate adopting the present embodiment thin-film transistor array base-plate preparation method to be formed.
Here it should be understood that, the structure plan of pixel electrode layer and described via hole in thin-film transistor array base-plate described in embodiment 1,2, also can be used for the structure plan region as forming evaporation OLED, or formed print or ink-jet instillation PLED(Polymer Light-Emitting Diode, polymer LED) structure plan region.
Embodiment 1,2 by carrying out patterned process in the passivation layer of thin-film transistor array base-plate, form pixel electrode layer and the structure plan needed for via hole simultaneously, then instiled for the formation of the tin indium oxide colloidal sol of pixel electrode layer or ink in the structure plan region that formed in passivation layer to form pixel electrode layer by nozzle.The preparation method of middle thin-film transistor array base-plate compared to existing technology, thin-film transistor array base-plate preparation method in embodiment 1,2 decreases the step adopting patterning processes to form pixel electrode layer, decrease the use amount of mask plate, improve the utilance that pixel electrode layer forms material, reduce production cost simultaneously.
Be understandable that, the illustrative embodiments that above execution mode is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (9)
1. a thin-film transistor array base-plate preparation method, comprise the following steps: on substrate, form gate electrode layer, gate insulator, active layer, source-drain electrode layer, passivation layer and pixel electrode layer, it is characterized in that, described passivation layer forms the structure plan comprising via hole by patterning processes, described pixel electrode layer is formed in structure plan region by instillation mode, and described source-drain electrode layer is connected by via hole with described pixel electrode layer; Wherein: in described passivation layer, form the structure plan comprising via hole adopt following patterning processes to be formed: with half-tone mask plate or gray mask plate, exposure-processed is carried out to the photoresist above described passivation layer, correspond to the photoresist forming described via area place is complete exposure-processed, and correspond to the photoresist forming described pixel electrode layer region place is half exposure-processed.
2. method according to claim 1, is characterized in that, described method comprises further: do described pixel electrode layer and solidify and annealing in process.
3. method according to claim 2, it is characterized in that, material for the formation of described pixel electrode layer is the material containing phosphide element, tin element and oxygen element, the described material containing phosphide element, tin element and oxygen element is made colloidal sol or ink in advance and is poured in nozzle, is instiled in described structure plan region by nozzle.
4. method according to claim 3, is characterized in that, the material for the formation of described pixel electrode layer is tin indium oxide colloidal sol or ink, and described tin indium oxide colloidal sol or ink are obtained by following methods: by InCl
34H
2o and SnCl
45H
2o is in 1:(1-3) in the water-soluble solution of ratio;
Or, by In
2o
3and SnCl
45H
2o is in 1:(2-6) ratio is dissolved in C
2h
5in COOH.
5. method according to claim 2, is characterized in that, the temperature range of described pixel electrode layer annealing in process is 300-600 DEG C.
6. method according to claim 2, is characterized in that, the thickness range of described pixel electrode layer is 20-150nm.
7. method according to claim 1, it is characterized in that, described passivation layer adopts at least bi-material in Si oxide, silicon nitride, hafnium oxide, aluminum oxide to form individual layer rete or MULTILAYER COMPOSITE rete, and the thickness range of described passivation layer is 300-500nm.
8. a thin-film transistor array base-plate, is characterized in that, adopts the thin-film transistor array base-plate preparation method described in any one of claim 1-7 to be formed.
9. a display unit, is characterized in that, comprises thin-film transistor array base-plate according to claim 8.
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| CN201310064170.1A CN103151305B (en) | 2013-02-28 | 2013-02-28 | Thin film transistor array substrate, preparing method and display device |
| PCT/CN2013/074957 WO2014131242A1 (en) | 2013-02-28 | 2013-04-28 | Thin film transistor array substrate, preparation method and display device |
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| CN103456740B (en) | 2013-08-22 | 2016-02-24 | 京东方科技集团股份有限公司 | Pixel cell and manufacture method, array base palte and display unit |
| CN103489882A (en) * | 2013-10-17 | 2014-01-01 | 京东方科技集团股份有限公司 | Array substrate, preparation method for same and display device |
| CN103700673B (en) * | 2013-12-24 | 2017-07-04 | 京东方科技集团股份有限公司 | A kind of display device, array base palte and preparation method thereof |
| CN104538357B (en) * | 2015-01-13 | 2018-05-01 | 合肥京东方光电科技有限公司 | Make the method and array base palte of array base palte |
| CN105374852B (en) * | 2015-11-16 | 2019-10-11 | Tcl集团股份有限公司 | A kind of printed form active display and preparation method thereof of no pixel bank |
| CN105470282B (en) * | 2015-11-20 | 2020-03-31 | Tcl集团股份有限公司 | TFT-OLED (thin film transistor-organic light emitting diode) without pixel bank and preparation method |
| CN105336763B (en) * | 2015-11-26 | 2019-08-02 | Tcl集团股份有限公司 | A kind of active display and preparation method thereof |
| CN105489611A (en) * | 2015-11-26 | 2016-04-13 | Tcl集团股份有限公司 | Printed type light emitting display and manufacturing method therefor |
| CN105552103A (en) * | 2015-12-25 | 2016-05-04 | Tcl集团股份有限公司 | Printed light emitting display and manufacturing method thereof |
| CN108064415A (en) * | 2016-12-27 | 2018-05-22 | 深圳市柔宇科技有限公司 | Array substrate manufacturing method |
| CN106775108A (en) * | 2016-12-30 | 2017-05-31 | 武汉华星光电技术有限公司 | A kind of In Cell touch-control array base paltes and preparation method thereof |
| CN111129106A (en) * | 2020-01-20 | 2020-05-08 | 合肥京东方卓印科技有限公司 | OLED substrate, preparation method thereof, display panel and display device |
| CN111312810A (en) * | 2020-02-26 | 2020-06-19 | 合肥鑫晟光电科技有限公司 | Array substrate and manufacturing method thereof, display panel and display device |
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