WO2014110173A1 - Semi-conducteurs amorphes à haute performance - Google Patents

Semi-conducteurs amorphes à haute performance Download PDF

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WO2014110173A1
WO2014110173A1 PCT/US2014/010736 US2014010736W WO2014110173A1 WO 2014110173 A1 WO2014110173 A1 WO 2014110173A1 US 2014010736 W US2014010736 W US 2014010736W WO 2014110173 A1 WO2014110173 A1 WO 2014110173A1
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formula
semiconductor
amorphous
amorphous semiconductor
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Douglas A. Keszler
John F. WAGER III
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State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University
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    • H—ELECTRICITY
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    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0376—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02581—Transition metal or rare earth elements
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02669—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation inhibiting elements
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present disclosure concerns amorphous semiconductors, and methods for making and using the amorphous semiconductors.
  • Amorphous semiconductors such as amorphous hydrogenated silicon (a-Si:H) and amorphous oxide semiconductors (AOS), are important materials for making a variety of electronic components, such as thin-film transistors and photovoltaic devices.
  • Amorphous hydrogenated silicon is a highly covalent material, whereas amorphous oxide semiconductors are strongly ionic. The type of bonding affects the electron mobility ( ⁇ ⁇ ) of these two materials.
  • Amorphous hydrogenated silicon typically exhibits a low electron mobility, i.e., about 1 cm V " V 1 .
  • Amorphous oxide semiconductors In contrast to amorphous hydrogenated silicon, the mobility of an amorphous oxide semiconductor does not depend strongly on the degree of crystallinity because such materials have electrostatic, non-directional bonds.
  • Amorphous oxide semiconductors typically have higher mobilities than amorphous hydrogenated silicon due to conduction bands that arise from spherically symmetric 4s-, 5s-, or 6s-derived cation orbitals with large ionic radii. Spherically symmetric orbitals and large ionic radii combine to provide a high degree of wave function overlap between neighboring orbitals. This leads to more efficient electron transport through the amorphous microstructure, and hence higher electron mobility.
  • Amorphous oxide semiconductor thin-film transistors also are characterized by several attractive attributes, including low-temperature processability.
  • the optimal temperature range for post-deposition annealing of an amorphous oxide semiconductor channel layer is from approximately 300 °C to about 500 °C.
  • process temperatures in this range in conjunction with an appropriate high-quality, low-leakage gate insulator, optimized amorphous oxide semiconductor thin-film transistor performance would be expected to involve a near- zero threshold voltage, a channel electron mobility of approximately 10 and a sub-threshold swing approaching the theoretical limit of 60 mV/decade.
  • Amorphous oxide semiconductor thin-film transistors also can be produced having very large drain current on-to-off ratios (>10 6 ). As a result, the off current is essentially gate voltage independent since an amorphous oxide semiconductor is a unipolar material.
  • amorphous oxide semiconductor thin-film transistors Another attractive attribute of amorphous oxide semiconductor thin-film transistors is that low-resistance source/drain contacts are obtained by simply depositing a metal onto or under the amorphous oxide semiconductor channel layer (i.e., source/drain doping is not required). This leads to a simple process flow design for making thin-film transistors.
  • amorphous oxide semiconductor thin-film transistors appear promising for a variety of commercially important applications, such as pixel switches for active-matrix liquid-crystal displays, pixel switches and drivers for active-matrix, organic light-emitting diode displays, and back-end IC switching applications in which low-temperature processing is required.
  • High-performance amorphous semiconductors are disclosed.
  • their design involves selecting suitable cation(s), suitable anion(s), and, in some cases, suitable additive(s), for making desired amorphous semiconductors.
  • the cation(s), anion(s), and additive(s) are combined in appropriate stoichiometric amounts, thereby forming a mixture, and the mixture is processed to form the desired amorphous semiconductor.
  • Cations (C) are selected based on particular criteria, such as to form spherically symmetric 4s-, 5s-, or 6s-derived conduction bands and/or to preclude, or at least substantially preclude, crystallization and facilitate formation of an amorphous microstructure.
  • cations are typically selected that provide a closed shell configuration, i.e. an oxidation state that provides a filled or empty frontier orbital.
  • Additives (W) can also be incorporated into disclosed amorphous semiconductors as glass formers.
  • dopants and/or spectators can be used as additives.
  • C 1 , C2 , and C 3 are different cations; A 1 , A2 , and A 3 are different and W 3 are different additives; and the subscripts D, E, F, L, M, N, X, Y, Z indicate the number of atoms of each respective element, thereby specifying the target atomic composition of the amorphous semiconductor.
  • Exemplary amorphous semiconductors include, solely by way of example, Zn 4 Sb 2 Te, Zn 6 Sb 2 Te0 2 , Zn 2 Sb 2 Te 5 , Zn 3 In 3 AlAs6, Zn 3 Sn 3 As 2 P 4 , and Zn 2 Sn 4 P 4 Te 2 0 2 .
  • Chemical formulas, and hence target atomic compositions of the amorphous semiconductor conform to the ideal of simple, closed-shell solids in which the octet rule is satisfied (i.e., each atom has eight electrons in its valence shell, thus resulting in the same electronic configuration as a noble gas atom).
  • the amorphous semiconductor has a root-mean- square surface roughness over an area of 1 X 1 ⁇ of less than 3 nm, and in certain
  • amorphous semiconductors have an electron mobility of at least 50 cm 2 V - " 1 s - " 1 , and perhaps at least 100 cm 2 V - " 1 s - " 1. Certain disclosed amorphous semiconductors also typically have a hole mobility of at least 1 cm 2 V - " 1 s - " 1.
  • a person of ordinary skill in the art will readily appreciate the value of disclosed amorphous semiconductors.
  • Amorphous semiconductors can be used to make a variety of electronic devices, or components of electronic devices, such as thin-film transistors.
  • FIG. 1 is a schematic representation of electronic density states of a covalent and an ionic semiconductor, both having the same band gap, E G , where Ey denotes the top of the valence band and E c denotes the bottom of the conduction band.
  • FIG. 2 is graph of solid state energy (eV) for 60 elements arranged in descending energy order, where the dashed horizontal line at 4.5 eV denoted ⁇ (+/-) corresponds to the hydrogen donor/acceptor ionization energy, or, equivalently, the standard hydrogen electrode potential.
  • eV solid state energy
  • FIG. 3 is a schematic drawing illustrating one embodiment of a bottom-gate, coplanar electrode thin film transistor that can be made using disclosed embodiments of amorphous semiconductors.
  • FIG. 4 is a schematic drawing illustrating one embodiment of a bottom-gate, staggered electrode thin film transistor that can be made using disclosed embodiments of amorphous semiconductors.
  • FIG. 5 is a schematic drawing illustrating one embodiment of a top-gate, coplanar electrode thin film transistor that can be made using disclosed embodiments of amorphous semiconductors.
  • FIG. 6 is a schematic drawing illustrating one embodiment of a top-gate, staggered electrode thin film transistor that can be made using disclosed embodiments of amorphous semiconductors.
  • “Additive” refers to the addition of foreign species (e.g., atoms, ions, etc.) into an inorganic solid state structure (e.g., crystal lattice) of a semiconductor to achieve a desired characteristic, such as suppressing crystallization within the structure, producing an n-type or a p-type material, or facilitating formation of the solid state structure without appreciably contributing to the conduction band minimum or valence band maximum density of states.
  • foreign species e.g., atoms, ions, etc.
  • an inorganic solid state structure e.g., crystal lattice
  • a desired characteristic such as suppressing crystallization within the structure, producing an n-type or a p-type material, or facilitating formation of the solid state structure without appreciably contributing to the conduction band minimum or valence band maximum density of states.
  • “Spectator” refers to an additive whose solid state energy differs from ⁇ (+/-) by more than approximately 1.5 eV. As such, the energy levels of the spectator make little or no contribution to the characteristics of the electronic structure near the valence-band maximum (VBM) and the conduction-band minimum (CBM). The electronic characteristics of the VBM and CBM control hole (p type) and electron (n type) transport. Since the spectator does not directly contribute to VBM or CBM, it contributes to an amorphous semiconductor primarily as a structural modifier.
  • Amorphous refers to thin films that typically have an atomic force microscopy (AFM) surface root-mean-square roughness of less than approximately 3 nm when deposited onto a smooth solid surface.
  • AFM atomic force microscopy
  • amorphous describes a thin film that has an AFM of less than 1.5 nm when deposited onto a silicon wafer covered with a thermal oxide.
  • AFM atomic force microscopy
  • amorphous indicates a thin film having a root- mean- square surface roughness over an area of 1 x 1 ⁇ of less than
  • Conduction band is a band in which electrons can move freely in a solid, producing a net charge transport.
  • the conduction band may be the lowest unoccupied energy band in a material.
  • Covalent refers to a chemical bond that arises primarily as a consequence of electron sharing between neighboring atoms.
  • Electrode Mobility refers to how effectively an electron moves through a
  • Hele refers to a deficiency in valence electrons.
  • Ionic refers to a chemical bond that is predominantly electrostatic due to electron transfer from higher to lower energy frontier orbitals.
  • An "n-type semiconductor” has at least one donor that contributes free electrons.
  • a "p-type semiconductor” possesses at least one acceptor to produce “holes,” or electron deficiencies.
  • Substrate refers to a physical object operating as a basic workpiece or platform that is transformed by various process operations into a desired microelectronic configuration, such as by deposition of materials, such as amorphous semiconductors, onto the platform or workpiece to form components of a device, such as a thin-film transistor.
  • valence band refers to a band in which holes may move freely in a solid, producing a net charge transport.
  • the valence band may be the highest occupied energy band.
  • the present semiconductors are made by achieving an appropriate balance between covalent and ionic bonding and,
  • amorphous and crystalline microstructures concomitantly, amorphous and crystalline microstructures.
  • Chemical bonding is strongly ionic in amorphous oxide semiconductors and purely covalent in silicon. Ionic bonds are non- directional while covalent bonds are highly directional. Moderately large electron mobilities are obtained in amorphous oxide semiconductors - even with an amorphous microstructure - because of the non-directional nature of the ionic bonds. Improving the crystallinity of an amorphous oxide semiconductor would do little to improve mobility because of the ionic nature of the bonds. In contrast, high electron mobility in silicon is obtained only when a high degree of crystallinity is achieved. The mobility of hydrogenated amorphous silicon is approximately three orders of magnitude less than that of single crystal silicon due to covalent bonding and the strong contribution of p orbitals near the band edges (CBM and VBM).
  • Amorphous oxide semiconductors and silicon are limiting cases of ionic and covalent bonding, respectively.
  • the present invention designs new types of semiconductors with intermediate ionicity. More ionic materials should be more tolerant of a less crystalline microstructure.
  • disclosed embodiments of exemplary semiconductors increase the covalent character of the amorphous oxide semiconductor bond to (1) increase the mobility, but (2) retain a sufficient degree of ionic bonding to minimize bandtail state formation.
  • SSE solid state energy
  • FIG. 1 is an idealized representation of the electronic density of states of a covalent and an ionic semiconductor, both having the same band gap, E G .
  • E v denotes the top of the valence band, i.e., the energy band whose states are typically almost completely filled with electrons.
  • Ec denotes the bottom of the conduction band, i.e., the energy band whose states are typically almost completely empty in terms of electron occupancy.
  • Ionic bands are narrower than covalent bonds. An important consequence of having narrower bands is that the mobility tends to be smaller when the bands are narrower. This is true for both electrons moving near the bottom of the conduction band and for holes moving near the top of the valence band.
  • FIG. 1 Note that an ionic
  • one strategy for improving mobility involves modifying the amorphous oxide semiconductor composition so that it is more covalent.
  • amorphous oxide semiconductor choices i.e., those not containing copper and silver, are unipolar, n-type materials. These materials cannot be doped p-type, since the top of the valence band is oxygen- derived, resulting in an ionization potential that is simply too deep for p-type doping.
  • FIG. 2 provides solid state energy values for 60 elements arranged in descending energy order with respect to the vacuum level.
  • Solid state energy is assessed as an average electron affinity (for a cation, shown in blue) or an average ionization potential (for an anion, shown in red) for binary compounds having the atom under consideration as a constituent.
  • Error bars correspond to maximum and minimum values from the available data.
  • the dashed horizontal line at 4.5 eV corresponds to the hydrogen donor/acceptor ionization energy [ ⁇ (+/-)] or, equivalently, to the standard hydrogen electrode potential of electrochemistry as measured with respect to the vacuum level.
  • the oxygen solid state energy is located 7.7 eV below the vacuum level.
  • the ionization potential i.e., the energy of separation between the top of the valence band and the vacuum level, is expected to be approximately 7.7 eV for a material in which the valence band is oxygen-derived. This is 3.2 eV below the hydrogen donor/acceptor ionization energy [ ⁇ (+/-)] or, equivalently, to the standard hydrogen electrode potential of electrochemistry.
  • ⁇ (+/-) is a demarcation energy, distinguishing cation/anion behavior.
  • the ionization energy of a material is greater than approximately 1.5 eV below ⁇ (+/-), i.e., ⁇ -6 eV, it is difficult/impossible to dope this material p- type.
  • the electron affinity i.e., the energy difference between the bottom of the conduction band and the vacuum level, is more than approximately 1.5 eV above ⁇ (+/-), it is difficult/impossible to dope this material n-type.
  • one approach to preparing semiconductors according to the present invention to make amorphous p-type materials involves modifying an amorphous oxide semiconductor by partially/completely replacing oxygen with an anion having a solid state energy closer to ⁇ (+/-).
  • particularly useful candidate anions are Sb, As, Te, Se, P, and perhaps S.
  • Covalent materials have atoms in which both of their solid state energies are close to ⁇ (+/-). Materials are more ionic as their solid state energies differ more from ⁇ (+/-). Thus, ⁇ (+/-) is a demarcation energy that facilitates distinguishing between covalent and ionic bonding.
  • amorphous semiconductor cation selection is considered.
  • its solid state energy (SSE) should be separated from ⁇ (+/-) by no more than about 1.5 eV such that -4.7 eV ⁇ SSE(cation) ⁇ -3 eV.
  • SSE solid state energy
  • one disclosed strategy for designing disclosed embodiments of high-performance amorphous semiconductors comprises first selecting suitable cation(s) and numbers thereof.
  • Most embodiments select at least two cations to preclude, or at least substantially preclude, crystallization, thereby facilitating forming an amorphous micro structure.
  • suitable anions and numbers thereof are selected.
  • W Mg +2 , Ca +2 , Sr +2 , Ba +2 , B +3 , ⁇ 3 , Sc +3 , Y +3 , La +3 , Ce +3 , Ce +4 , O “2 , and F "1 .
  • Combining oxygen and one other anion provides an opportunity to exploit the advantages of air processing.
  • Including an additive with a lower solid state energy brings the top of the valence band closer to ⁇ (+/-), affording greater covalence, improved hole mobility, and opportunities for p-type doping.
  • the maximum processing temperature is a consideration for determining the application space for disclosed embodiments of the high-performance amorphous semiconductors. For electronics -grade plastic substrate applications, a maximum process temperature of
  • amorphous semiconductor materials satisfy a need for high-performance electronics on large-area glass substrates.
  • New amorphous semiconductors are determined based, at least in part, on the considerations discussed above. Such amorphous semiconductors also can be described with reference to various chemical formulas. A general chemical description of disclosed amorphous semiconductors is provided by Formula I:
  • C 1 , C2 , and C 3 are different cations; A 1 , A2 , and A 3 are different anions; W2", and W 3 are different additives; and subscripts D, E, F, L, M, N, X, Y, Z indicate the number of atoms of each element, thereby specifying the target atomic composition of the amorphous semiconductor.
  • Formula I can be expanded to more particularly describe combinations of elements used to form disclosed exemplary semiconductors.
  • Formula I can be expanded to expressly state numbers of cations, anions and additives, thus specifying the target amorphous semiconductor stoichiometry, as indicated by Formulas IA-IF.
  • the amorphous semiconductor composition is selected to provide electron mobilities greater than 50 cm 2 V - " 1 s - “ 1 , preferably greater than 100 cm 2 V- " 1 s- “ 1 , and hole mobilities greater than 10 cm 2 V - " 1 s - " 1.
  • Disclosed materials also have relatively low post-deposition annealing temperatures, such as an annealing temperature of 600 °C or less.
  • Disclosed embodiments of the amorphous semiconductor may be made by any process suitable for forming amorphous semiconductors currently known to those having ordinary skill in the art, or such methods as may be hereafter developed. Once formed, these materials can be used to make a variety of electronic devices.
  • amorphous semiconductors pertinent to this disclosure will be employed as thin films.
  • the thin film thickness can vary from approximately 10 nm to approximately 3 ⁇ , depending on the selected application.
  • Suitable thin film deposition techniques for synthesizing amorphous semiconductors pertinent to this disclosure include: physical vapor deposition (PVD) [e.g., thermal evaporation, electron-beam evaporation, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), DC magnetron sputtering, RF magnetron sputtering, ion beam sputtering, reactive sputtering];
  • PVD physical vapor deposition
  • MBE molecular beam epitaxy
  • PLD pulsed laser deposition
  • DC magnetron sputtering RF magnetron sputtering, ion beam sputtering, reactive sputtering
  • PVD physical vapor deposition
  • MBE molecular beam epitaxy
  • PLD pulsed laser de
  • CVD chemical vapor deposition
  • APCVD low-pressure chemical vapor deposition
  • PECVD plasma-enhanced chemical vapor deposition
  • RECVD remote plasma-enhanced chemical vapor deposition
  • MOCVD metal- organic chemical vapor deposition
  • MCVD mist chemical vapor deposition
  • CCSVT chemical closed-space vapor transport
  • ALD atomic layer deposition
  • PEALD plasma- enhanced atomic layer deposition
  • RPEALD remote plasma-enhanced atomic layer deposition
  • solution processing e.g., spin-coating synthesis, slot-coating deposition, capillary coating, sol-gel processing, prompt inorganic condensation (PIC), ink jet printing, gravure printing, chemical bath deposition (CBD)].
  • Thin film deposition may be accomplished at or near room temperature (i.e., without intentional heating of the substrate upon which the amorphous semiconductor is deposited) or the substrate may be intentionally heated to an elevated temperature during thin film deposition. If a substrate is heated during thin film deposition, the substrate temperature chosen will depend on the substrate selected and on the chemical and physical properties of the amorphous semiconductor being deposited. For electronics-grade plastic substrate applications, a maximum process temperature typically ranges from about 100 °C to about 300 °C; more typically from about 150 °C to about 250 °C. For glass substrate applications, a maximum process temperature typically ranges from about 250 °C to about 450 °C; more typically from about 300 °C to about 250 °C.
  • a maximum process temperature typically ranges from about 250 °C to about 650 °C; more typically from about 350 °C to about 600 °C.
  • a low temperature is desired, such as approximately less than about 500 °C.
  • Post-deposition annealing typically is used for the synthesis of amorphous
  • An elevated temperature often improves the electrical and/or optical properties of an as-deposited amorphous semiconductor thin film.
  • the post-deposition anneal may be undertaken in a relatively inert gaseous ambient (e.g., vacuum, argon, or nitrogen), a reducing gaseous ambient (e.g., hydrogen or a hydrogen-nitrogen mixture), a reactive gaseous ambient (e.g., oxygen or an overpressure of an anion-based gaseous species [e.g., a post-deposition anneal of Zn 3 In 3 AlAs 6 might be accomplished in an AsH 3 overpressure in order to compensate for an As deficiency in the as-deposited film, thereby improving the stoichiometry of the amorphous thin film; anion deficiency is a common problem witnessed in as-deposited thin films]), or an activated reactive gaseous species [e.g., plasma- activated nitrogen, oxygen, or an overpressure of an anion-based gaseous species; plasma
  • a post-deposition anneal can improve the electrical and/or optical properties of an as- deposited amorphous semiconductor thin film for a variety of reasons, such as modifying film stoichiometry, introducing additives into the film, reducing the concentration of defects in the film, and reshaping the valence and/or conduction band tail state densities of the film.
  • the amorphous semiconductor materials are then used to fabricate desired electronic devices.
  • Forming electronic devices requires fabrications processes for fabricating suitable structures from the disclosed amorphous semiconductors. Suitable fabrication processes include, but are not limited to, thin-film deposition techniques selected from sputtering, chemical vapor deposition (e.g. low-pressure, plasma-enhanced, and high density plasma), atomic layer deposition, electron beam deposition, sol-gel deposition, solution processing, thermal evaporation, or chemical bath deposition.
  • thin-film deposition techniques selected from sputtering, chemical vapor deposition (e.g. low-pressure, plasma-enhanced, and high density plasma), atomic layer deposition, electron beam deposition, sol-gel deposition, solution processing, thermal evaporation, or chemical bath deposition.
  • a thin film of a disclosed semiconductor material is deposited onto a suitable substrate using any suitable deposition technique.
  • the substrate may be made from any suitable material, including semiconducting materials, non- semiconducting materials, and combinations of semiconducting materials and non-semiconducting materials.
  • the substrate material optionally is an opaque material or a substantially transparent material.
  • Illustrative substrate materials include glass plate, flexible glass, silicon, plastic (e.g. electronics- grade plastic), particularly for structurally flexible devices, where suitable polymeric materials include polyester, polycarbonate, polyimide sheets and the like, ceramics, and thin metal sheets.
  • the thin film is deposited onto a substrate material to provide a material layer of desired thickness.
  • the deposited film typically has a thickness of from about 10 nm to about 100 nm, and more typically from about 30 nm to about 50 nm.
  • the thickness of the substrate also may vary.
  • the substrate thickness typically varies from about 1 ⁇ to at least about 1 cm, and more typically is from about 10 ⁇ to over 10 millimeters, with an exemplary thickness being from about 50 ⁇ to about 100 ⁇ , especially for a flexible plastic substrate, and from about 0.5 to about 10 millimeters for a rigid substrate, such as glass or silicon.
  • a maximum process temperature typically ranges from about 100 °C to about 300 °C; more typically from about 150 °C to about 250 °C.
  • a maximum process temperature typically ranges from about 250 °C to about 450 °C; more typically from about 300 °C to about 250 °C.
  • a maximum process temperature typically ranges from about 250 °C to about 650 °C; more typically from about 350 °C to about 600 °C.
  • low temperatures are desired, such as approximately less than about 500 °C.
  • semiconductor composition promotes or allows the use of low temperatures. In some embodiments, using a thermal annealing process is not required.
  • Metal lines, traces, wires, interconnects, conductors, signal paths and signaling mediums may provide the desired electrical connections.
  • Metal lines generally aluminum (Al), copper (Cu) or an alloy of Al and Cu, are conductors that provide signal paths for coupling or interconnecting, electrical circuitry.
  • Conductors other than metal, such as a transparent conducting oxide, may also be utilized.
  • amorphous semiconductors disclosed herein are useful for a variety of applications, particularly for manufacturing electronic devices.
  • Examples of electronic devices, or components of devices, that can be made according to this invention include, without limitation, transistors, such as a channel layer for a thin-film transistor or field-effect transistor;
  • photovoltaic s such as an absorber for a thin-film solar cell; pixel switches and drivers for active-matrix, liquid-crystal displays; active-matrix, light-emitting displays; electrophoretic displays; analog, digital, and/or power electronics for macroelectronics; radio-frequency identification tags; switches for use in integrated circuits that are fabricated near the back-end of an integrated circuit process; and other suitable devices.
  • Thin-film transistors are a particular class of components that will be made using disclosed embodiments of the amorphous semiconductors.
  • Various thin-film transistor architectures are possible, as illustrated in FIGS. 3-6, involving permutations of top/bottom gate and staggered/coplanar arrangement of S/D and G contacts. All known and hereafter developed transistor structures are within the scope of the present invention.
  • a thin- film transistor generally includes a substrate, a gate electrode, source electrode, drain electrode, and a dielectric layer in addition to the semiconducting layer.
  • a bottom gate thin-film transistor (TFT) device typically includes a gate electrode layer disposed on a substrate covered with a gate insulator layer.
  • a semiconductor layer comprising a disclosed embodiment of an amorphous semiconductor, is disposed over the gate insulator layer.
  • An n-type or p-type layer is disposed over the semiconductor layer.
  • a source-drain metal electrode layer is disposed thereon.
  • a passivation layer is subsequently formed thereon to produce the thin-film transistor device.
  • the gate electrode is an electrically conductive material. It can be a thin metal film, a conducting polymer film, a conducting film made from conducting ink or paste, or the substrate itself, for example heavily doped silicon.
  • Examples of gate electrode materials include, but are not limited to, aluminum, gold, silver, chromium, indium tin oxide, conductive polymers such as polystyrene sulfonate-doped poly(3,4-ethylenedioxythiophene) (PSS-PEDOT), and conducting ink/paste comprised of carbon black/graphite.
  • the gate electrode can be prepared by vacuum evaporation, sputtering of metals or conductive metal oxides, conventional lithography and etching, chemical vapor deposition, spin coating, casting or printing, or other deposition processes. Gate electrode thicknesses range from about 10 to about 200 nanometers for metal films and from about 1 to about 10 ⁇ for conductive polymers. Typical materials suitable for use as source and drain electrodes include those of the gate electrode materials such as aluminum, gold, silver, chromium, zinc, indium, conductive metal oxides such as zinc-gallium oxide, indium tin oxide, indium- antimony oxide, conducting polymers and conducting inks. Typical thicknesses of source and drain electrodes are, for example, from about 40 nanometers to about 1 ⁇ , including more specific thicknesses of from about 100 to about 400 nanometers.
  • the substrate may be a glass substrate, a plastic substrate, a polymer substrate, a metal substrate, or other suitable substrate suitable for forming a thin-film transistor.
  • the gate electrode layer may be fabricated from any suitable metallic materials, such as indium tin oxide (ITO), tin oxide (SnO), indium zinc oxide (IZO), indium tin zinc oxide ( ⁇ ), aluminum (Al), tungsten (W), chromium (Cr), germanium (Ge), tantalum (Ta), titanium (Ti), gold (Au), alloy of titanium (Ti) and gold (Au), alloy of tantalum (Ta) and gold (Au), alloy of germanium (Ge) and gold (Au), molybdenum (Mo), or combinations thereof.
  • Suitable materials for the gate insulator layer may be silicon oxide, silicon oxynitride (SiON), or silicon nitride (SiN), high-k materials, such as Hf0 2 , or other suitable materials.
  • the source-drain metal electrode layer may be fabricated using a metallic material.
  • the metallic material may be selected from copper (Cu), gold (Au), silver (Ag), aluminum(Al), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), cobalt (Co), tantalum (Ta), titanium (Ti), gold (Au), and alloys thereof.
  • the passivation layer may be fabricated by dielectric materials including silicon oxide silicon oxynitride (SiON), or silicon nitride (SiN), suitable polymer materials, such as polymethylmethacrylate (PMMA).
  • Typical materials suitable for use as source and drain electrodes include gold, silver, nickel, aluminum, platinum, conducting polymers, and conducting inks.
  • the electrode materials provide low contact resistance to the semiconductor.
  • Typical thicknesses are from about 40 nanometers to about 1 ⁇ with a more specific thickness being about 100 to about 400 nanometers.
  • the semiconductor channel width may be, for example, from about 5 ⁇ to about 5 millimeters, more typically from about 100 ⁇ to about 1 millimeter.
  • the semiconductor channel length may be, for example, from about 1 ⁇ to about 1 millimeter, and more typically from about 5 ⁇ to about 100 micrometers.
  • a barrier layer may also be deposited on top of the TFT to protect it from environmental conditions, such as light, oxygen and moisture, etc., which can degrade its electrical properties.
  • barrier layers are known in the art and may simply consist of an inorganic insulating layer or a polymer.
  • the various components of the thin-film transistor may be deposited upon the substrate in any order.
  • the gate electrode and the semiconducting layer should both be in contact with the gate dielectric layer, and the source and drain electrodes should both be in contact with the semiconducting layer.
  • “In any order” includes sequential and simultaneous formation.
  • the source electrode and the drain electrode can be formed
  • Top metal gate structure thin-film transistor devices typically include a metal gate electrode disposed on a backside of a substrate.
  • An insulator layer may be formed on an opposite side (e.g., front side) of the substrate.
  • a semiconductor layer comprising a disclosed embodiment of an amorphous semiconductor is disposed over the insulator layer.
  • a source-drain metal electrode layer is then disposed over the semiconductor layer to form the thin-film transistor device.
  • Another exemplary thin-film transistor device includes a semiconductor layer disposed on a substrate.
  • An insulator layer may be formed over the semiconductor layer in between a patterned source-drain metal electrode layer.
  • a gate electrode layer is disposed over the insulator layer to form the thin-film transistor device.
  • Yet another embodiment of a thin-film transistor device includes a buffer oxide layer disposed on a substrate.
  • a semiconductor layer comprising a disclosed semiconductor is disposed between a patterned source-drain metal electrode layer.
  • a gate insulator layer is then disposed over the semiconductor layer, followed by a metal gate electrode layer.
  • Yet another embodiment of a thin-film transistor device includes a gate insulator layer disposed on a substrate.
  • a layer comprising a disclosed semiconductor is disposed on the gate insulator layer.
  • a patterned source-drain electrode layer is then disposed on the semiconductor layer. Subsequently, a passivation layer is disposed on the patterned source-drain electrode layer.
  • Display devices also can be made using disclosed embodiments of amorphous semiconductors, or compositions comprising at least one amorphous semiconductor.
  • an exemplary display device might comprise plural thin-film transistors over a substrate; and a pixel electrode connected to the thin-film transistors.

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  • Crystallography & Structural Chemistry (AREA)
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Abstract

L'invention concerne des compositions pour la fabrication de semi-conducteurs amorphes. Des cations pour les semi-conducteurs amorphes sont choisis sur la base de critères particuliers, tels que pour former des bandes de conduction sphériquement symétriques dérivées 4s, 5s ou 6s, et/ou pour empêcher ou au moins sensiblement empêcher une cristallisation et faciliter la formation d'une microstructure amorphe. Pour certains modes de réalisation divulgués, les cations (C) sont typiquement choisis parmi C = Zn+2, Ga+3, As+3, As+5, In+3, Sn+2, Sn+4, Sb+3, Sb+5, Bi+3 et Bi+5, et les anions sont typiquement choisis parmi A = P-3, As-3, Sb -3, S -2, Se -2, Te -2 et Βi-3. Des additifs (W), tels que des formateurs de verre, des dopants, ou des spectateurs, peuvent également être incorporés dans les semi-conducteurs amorphes divulgués. Des additifs appropriés sont typiquement choisis parmi W = Mg+2, Ca+2, Sr+2, Ba+2, B+3, Al+3, Sc+3, Y+3, La+3, Ce+3, Ce+4, O-2 et F-1. Des semi-conducteurs amorphes peuvent être utilisés pour fabriquer divers dispositifs électroniques, ou des composants de ceux-ci, tels que des transistors en couche mince et des dispositifs photovoltaïques.
PCT/US2014/010736 2013-01-09 2014-01-08 Semi-conducteurs amorphes à haute performance WO2014110173A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090081826A1 (en) * 2007-09-26 2009-03-26 Cowdery-Corvan Peter J Process for making doped zinc oxide
EP2184109A1 (fr) * 2007-07-06 2010-05-12 M Technique Co., Ltd. Procédé de fabrication de nanoparticules par procédé de rotation à film ultra-mince forcé
US20110084240A1 (en) * 2009-10-13 2011-04-14 Carl Schell Variable Resistance Materials with Superior Data Retention Characteristics
US20110226330A1 (en) * 2008-08-23 2011-09-22 The Regents Of The University Of California Amorphous silicon solar cells
KR20120027046A (ko) * 2009-06-05 2012-03-20 가부시키가이샤 한도오따이 에네루기 켄큐쇼 광전 변환 디바이스 및 그 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2184109A1 (fr) * 2007-07-06 2010-05-12 M Technique Co., Ltd. Procédé de fabrication de nanoparticules par procédé de rotation à film ultra-mince forcé
US20090081826A1 (en) * 2007-09-26 2009-03-26 Cowdery-Corvan Peter J Process for making doped zinc oxide
US20110226330A1 (en) * 2008-08-23 2011-09-22 The Regents Of The University Of California Amorphous silicon solar cells
KR20120027046A (ko) * 2009-06-05 2012-03-20 가부시키가이샤 한도오따이 에네루기 켄큐쇼 광전 변환 디바이스 및 그 제조 방법
US20110084240A1 (en) * 2009-10-13 2011-04-14 Carl Schell Variable Resistance Materials with Superior Data Retention Characteristics

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