WO2014103844A1 - Système de capteur tactile - Google Patents

Système de capteur tactile Download PDF

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Publication number
WO2014103844A1
WO2014103844A1 PCT/JP2013/083961 JP2013083961W WO2014103844A1 WO 2014103844 A1 WO2014103844 A1 WO 2014103844A1 JP 2013083961 W JP2013083961 W JP 2013083961W WO 2014103844 A1 WO2014103844 A1 WO 2014103844A1
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WO
WIPO (PCT)
Prior art keywords
sensor panel
capacitance
drive
output
touch sensor
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Application number
PCT/JP2013/083961
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English (en)
Japanese (ja)
Inventor
岡田　厚志
高濱　健吾
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シャープ株式会社
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Filing date
Publication date
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Publication of WO2014103844A1 publication Critical patent/WO2014103844A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Definitions

  • the present invention relates to a touch sensor system including a sensor panel and an integrated circuit that drives the sensor panel, and more particularly to a narrow frame of the sensor panel.
  • Japanese Patent No. 4927216 discloses a touch sensor system including a sensor panel and an integrated circuit that controls the sensor panel.
  • the sensor panel includes M drive lines and L sense lines.
  • the M drive lines and the L sense lines are each connected to the integrated circuit. Therefore, in the sensor panel, each of the M drive lines and each of the L sense lines are connected to the integrated circuit outside the region where the M drive lines and the L sense lines are arranged. Wiring to be placed is arranged. As the sensor panel becomes larger, the number of drive lines and sense lines increases. As a result, the number of wirings increases. As a result, there is a problem that it is difficult to realize a narrow frame of the sensor panel.
  • An object of the present invention is to provide a touch sensor system capable of realizing a narrow frame of a sensor panel.
  • the touch sensor system includes a sensor panel and an integrated circuit.
  • the integrated circuit controls the sensor panel.
  • the integrated circuit includes a drive unit and an estimation unit.
  • the estimation unit estimates the capacitance value of the first capacitance string corresponding to the k1th drive line based on the inner product operation of the output sFirst and the code sequence di, and calculates the inner product operation of the output sSecond and the code sequence di Based on the above, the capacitance value of the second capacitance string corresponding to the k2nd drive line is estimated.
  • the drive unit is disposed on the sensor panel, and the estimation unit is disposed on a separately provided substrate in addition to the sensor panel.
  • liquid crystal display device In the liquid crystal display device according to the embodiment of the present invention, it is possible to realize a narrow frame of the sensor panel.
  • FIG. 1 is a circuit diagram illustrating a touch sensor system according to an embodiment of the present invention. It is a circuit diagram which shows the structure of the drive part shown in FIG. It is a figure for demonstrating the drive method of the sensor panel provided in the said touch sensor system. It is a timing chart for demonstrating the drive method of the said sensor panel. It is a figure for demonstrating the specific example of the orthogonal code series input into the sensor panel provided in the said touch sensor system. It is a figure for demonstrating the other specific example of the said orthogonal code sequence. It is a figure for demonstrating the other specific example of the said orthogonal code sequence.
  • the touch sensor system includes a sensor panel and an integrated circuit.
  • the integrated circuit controls the sensor panel.
  • the integrated circuit includes a drive unit and an estimation unit.
  • the estimation unit estimates the capacitance value of the first capacitance string corresponding to the k1th drive line based on the inner product operation of the output sFirst and the code sequence di, and calculates the inner product operation of the output sSecond and the code sequence di Based on the above, the capacitance value of the second capacitance string corresponding to the k2nd drive line is estimated.
  • the drive unit is disposed on the sensor panel, and the estimation unit is disposed on a separately provided substrate in addition to the sensor panel.
  • the drive line and the sense line are in an intersecting relationship, and therefore, among the wiring that connects the drive line and the drive unit and the wiring that connects the sense line and the estimation unit Either one needs to be routed along the outer edge of the sensor panel.
  • the first configuration since the drive unit is disposed on the sensor panel, it is necessary to route the wiring connecting the drive unit and the M drive lines along the outer edge of the sensor panel. Disappear.
  • the first configuration a narrower frame of the sensor panel can be realized as compared with the case where the driving unit is arranged on the substrate together with the estimation unit.
  • the driving unit includes a shift register and an XOR circuit in the first configuration.
  • the shift register is a cascade connection of a plurality of flip-flops.
  • the XOR circuit is connected to an intermediate tap provided in the shift register. Outputs of each of the plurality of flip-flops are connected to different drive lines in the M drive lines.
  • the circuit configuration of the drive unit is simplified. Therefore, it is possible to easily arrange the drive unit on the sensor panel.
  • the shift register operates with a two-phase clock in the second configuration. In this case, malfunction of the shift register can be suppressed.
  • FIG. 1 is a circuit diagram illustrating a configuration of a touch sensor system 1 according to an embodiment.
  • the touch sensor system 1 includes a sensor panel 2 and an integrated circuit 3 that controls the sensor panel 2.
  • the sensor panel 2 includes M drive lines DL1 to DLM arranged parallel to each other at a predetermined interval along the horizontal direction and a predetermined interval parallel to each other along a direction intersecting the drive lines. Arranged in a matrix of M rows ⁇ L columns between the L sense lines SL1 to SLL arranged in this manner, and the M drive lines DL1 to DLM and the L sense lines SL1 to SLL, respectively.
  • the integrated circuit 3 has a drive unit 4 connected to M drive lines DL1 to DLM.
  • FIG. 2 is a circuit diagram showing a configuration of the drive unit 4 of the integrated circuit 3.
  • the driving unit 4 includes a shift register 20 and XOR circuits 22A to 22C.
  • the shift register 20 is formed by cascading a plurality of flip-flops 24A to 24H.
  • the XOR circuits 22A to 22C are connected to intermediate taps provided in the shift register 20.
  • the number of XOR circuits 22A to 22C and the position of the intermediate tap in the shift register 20 are particularly limited as long as the M series signal can be generated in the drive unit 4. It is not limited.
  • the number of flip-flops 24 is set to the same number as the number of drive lines DL. That is, FIG. 2 shows the drive unit 4 in the case where eight drive lines DL1 to DL8 are provided. The drive lines DL1 to DL8 connected to the flip-flops 24A to 24H are different from each other.
  • a clock signal line 26 is connected to each of the plurality of flip-flops 24A to 24H. As a result, the clock signal ck flowing through the clock signal line 26 is input to each of the plurality of flip-flops 24A to 24H.
  • the clock signal line 26 is connected to a clock signal generator 32 (see FIG. 1) disposed on the substrate 30.
  • the clock signal generation unit 32 generates the clock signal ck.
  • a reset signal line 28 is connected to each of the plurality of flip-flops 24A to 24H. As a result, the reset signal rm flowing through the reset signal line 28 is input to each of the plurality of flip-flops 24A to 24H.
  • the reset signal line 28 is connected to a reset signal generator 34 (see FIG. 1) disposed on the substrate 30.
  • the reset signal generator 34 generates a reset signal rm.
  • the output of the flip-flop 24A is connected to the input of the flip-flop 24B and to the drive line DL2.
  • the output of the flip-flop 24B is connected to the input of the flip-flop 24C, one input of the XOR circuit 22A, and the drive line DL3.
  • the output of the flip-flop 24C is connected to the input of the flip-flop 24D, one input of the XOR circuit 22B, and the drive line DL4.
  • the output of the flip-flop 24D is connected to the input of the flip-flop 24E, one input of the XOR circuit 22C, and the drive line DL5.
  • the output of the flip-flop 24E is connected to the input of the flip-flop 24F and to the drive line DL6.
  • the output of the flip-flop 24F is connected to the input of the flip-flop 24G and connected to the drive line DL for seven.
  • the output of the flip-flop 24G is connected to the input of the flip-flop 24H and also connected to the drive line DL8.
  • the output of the flip-flop 24H is connected to the other input of the XOR circuit 22C.
  • the output of the XOR circuit 22C is connected to the other input of the XOR circuit 22B.
  • the output of the XOR circuit 22B is connected to the other input of the XOR circuit 22A.
  • the output of the XOR circuit 22A is connected to the input of the flip-flop 24A and to the drive line DL1.
  • the flip-flops 24A to 24H are initialized every time the reset signal rm is input. Each of the flip-flops 24A to 24H outputs the input data signal every time the clock signal ck is input. As a result, in the shift register 20, every time the clock signal ck is input, the data signal input to each of the flip-flops 24A to 24G is input to the subsequent flip-flops 24B to 24H. The data signal input to the flip-flop 24H is input to the flip-flop 24A via the XOR circuits 22A to 22C.
  • the data signals output from the flip-flops 24A to 24G are input not only to the subsequent flip-flops 24B to 24H but also to the drive lines DL2 to DL8.
  • the data signal output from the flip-flop 24H is input not only to the flip-flop 24A via the XOR circuits 22A to 22C but also to the drive line DL1.
  • the driving unit 4 can drive the M drive lines DL1 to DLM in parallel.
  • FIG. 3 is a block diagram illustrating a configuration of the estimation unit 5 of the integrated circuit 3.
  • the estimation unit 5 includes L analog integrators 6 connected to the L sense lines SL1 to SLL, a switch 7 connected to the L analog integrators 6, and an AD conversion connected to the switch 7.
  • the analog integrator 6 includes an operational amplifier having one input grounded, an integration capacitor of a capacitor Cint disposed between the output of the operational amplifier and the other input, a transistor coupled to the other input of the operational amplifier, This transistor and another transistor connected in parallel are included.
  • the integrated circuit 3 is provided with an application processing unit 11 that is connected to the inner product calculation unit 9 and executes gesture recognition processing (such as ARM) at 240 Hz.
  • gesture recognition processing such as ARM
  • FIG. 3 is a diagram for explaining a driving method of the sensor panel 2 provided in the touch sensor system 1.
  • the code sequence di is generated when the driving unit 4 repeatedly inputs the clock signal ck to each of the flip-flops 24A to 24H.
  • FIG. 4 is a timing chart for explaining a driving method of the sensor panel 2.
  • the integration signal Cint of the analog integrator 6 is reset by the reset signal, and each capacitance arranged in a matrix on the sensor panel 2 is also reset.
  • the reset means that the electric charge accumulated in the capacitor is discharged.
  • the drive lines DL1 to DLM are driven in parallel at Vref + V or Vref ⁇ V according to +1 or ⁇ 1 which is the value of the code sequence d11, d21, d31,. Charges of ⁇ CV corresponding to the elements ⁇ 1 of the code sequence are stored.
  • the analog integrator 6 reads out the signals for each sense line.
  • the output sequence vector sji is And When an inner product operation di ⁇ sj of the code sequence di and the output sequence vector sj is performed, the result is as follows.
  • the gain G becomes (1 / Cint).
  • Cip the first capacitance column Cip
  • i 1,..., M
  • the output sFirst (sp1, sp2,..., SpN) from the first capacitance string is integrated by the corresponding analog integrator 6 and output from the second capacitance string.
  • sSecond (sq1, sq2,..., sqN) is integrated by the analog integrator 6 provided correspondingly.
  • the switch 7 sequentially switches the analog integrators 6 corresponding to the sense lines SL1 to SLL, and supplies the AD converter 8 with the output from the capacitance string integrated by each analog integrator 6.
  • the output sp1 is read from the first capacitance string to the analog integrator 6 and integrated, and at the same time, the output sq1 from the second capacitance string is transferred to the other analog integrator 6.
  • the switch 7 is connected to the analog integrator 6 and supplies the output sp1 read and integrated to the ADC 8.
  • the switch 7 disconnects the connection with the analog integrator 6 and connects to the other analog integrator 6, and supplies the read and integrated output sq 1 to the ADC 8.
  • the output sp2 is read from the first capacitance string to the analog integrator 6 and integrated.
  • the output sq2 is read from the second capacitance string to the other analog integrator 6 and integrated. Is done.
  • the switch 7 is connected to the analog integrator 6 and supplies the output sp2 read and integrated to the ADC 8. Next, the switch 7 releases the connection with the analog integrator 6 and connects to the other analog integrator 6, and supplies the output sq ⁇ b> 2 read and integrated to the ADC 8. In this way, the output spN and the output sqN are sequentially supplied to the ADC 8 by the analog integrator 6 and the switch 7. Further, the analog integrators 6 of all the sense lines operate in parallel with driving of the drive lines.
  • the AD converter 8 performs AD conversion on the output from the capacitance string integrated by the analog integrator 6 and supplies the result to the inner product calculation unit 9.
  • the inner product calculation unit 9 refers to the data stored in the RAM 10 based on the inner product calculation of the output sFirst and the code sequence di, and refers to the first static line corresponding to the k1th drive line (1 ⁇ k1 ⁇ M). A capacitance value of the capacitance string is estimated, and the second capacitance string corresponding to the k2th drive line (k1 ⁇ k2, 1 ⁇ k1 ⁇ M) based on the inner product calculation of the output sSecond and the code sequence di The capacity value of is estimated.
  • the application processing unit 11 executes gesture recognition processing based on the capacitance value estimated by the inner product calculation unit 9, and generates a gesture command.
  • FIG. 5 is a diagram for explaining a specific example of orthogonal code sequences input to the sensor panel.
  • Specific examples of the orthogonal code sequence di having the length N include the following code sequences.
  • a Hadamard matrix that is a typical orthogonal code sequence is generated by the sylvester method shown in FIG.
  • a basic structure a basic unit of 2 rows ⁇ 2 columns is made.
  • the upper right, upper left, and lower left bits of the basic unit are the same, and the lower right is an inversion of these bits.
  • the above-mentioned 2 ⁇ 2 basic elements are synthesized as four blocks in the upper right, upper left, lower right, and lower left to create a code of a 4 ⁇ 4 bit array.
  • the lower right block is bit-inverted.
  • the code of the bit arrangement of 8 rows ⁇ 8 columns and 16 rows ⁇ 16 columns is generated in the same procedure.
  • the codes of the 16 rows ⁇ 16 columns bit array shown in FIG. 4 can be used as orthogonal code sequences.
  • the Hadamard matrix refers to a square matrix whose elements are either 1 or ⁇ 1 and whose rows are orthogonal to each other. That is, any two rows of the Hadamard matrix represent vectors that are perpendicular to each other.
  • a matrix obtained by arbitrarily extracting M rows from the Nth-order Hadamard matrix can be used (where M ⁇ N).
  • M ⁇ N a Hadamard matrix by a method other than the Sylvester method can also be applied to the present invention.
  • FIG. 6 is a diagram for explaining another specific example of the orthogonal code sequence
  • FIG. 7 is a diagram for explaining still another specific example of the orthogonal code sequence.
  • Hadamard matrices obtained by methods other than these Sylvester methods can also be used as orthogonal code sequences according to the present embodiment.
  • (1) First, the inner product matrix stored in the RAM 10 (FIG. 2) of the estimation unit 5 is reset to C′ij 0.
  • the L output voltages sjk read at time tk respectively read by the corresponding L analog integrators 6 are supplied to the AD converter 8 in order by the switch 7 to perform AD conversion, and the AD converter 8
  • the output voltage sjk at time tk that has been subjected to AD conversion by the above is supplied to the inner product calculation unit 9.
  • the output voltage sjk at time tk supplied to the inner product calculation unit 9 is It becomes.
  • the time is incremented (tk + 1) and the process returns to (1) until N times of processing corresponding to the length of the code sequence are performed. When the above processing is completed, the value of C′ij becomes the inner product calculation result.
  • the drive unit 4 is disposed on the sensor panel 2, and the estimation unit 5 is disposed on the substrate 30 provided separately from the sensor panel 2. Therefore, compared with the case where the drive part 4 is arrange
  • the M drive lines DL1 to DLM and the L sense lines SL1 to SLL intersect each other. Therefore, when the drive unit 4 is arranged on the substrate 30 together with the estimation unit 5, the wirings connecting the M drive lines DL1 to DLM and the drive unit 4 and the L sense lines SL1 to SLL and the estimation unit 5 It is necessary to route any of the wirings connecting the two along the outer edge of the sensor panel 2. On the other hand, in the present embodiment, since the drive unit 4 is disposed on the sensor panel 2, it is not necessary to route the wiring connecting the drive unit 4 and the M drive lines DL1 to DLM along the outer edge of the sensor panel 2. . As a result, in the present embodiment, it is possible to realize a narrow frame of the sensor panel 2 as compared with the case where the drive unit 4 is disposed on the substrate 30 together with the estimation unit 5.
  • the drive unit 4 includes a shift register 20 and XOR circuits 22A to 22C. Therefore, the circuit configuration of the drive unit 4 is simplified. As a result, the drive unit 4 can be easily arranged on the sensor panel 2.
  • the shift register 20 may operate with a two-phase clock. In this case, malfunction of the drive unit 4 can be suppressed.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Position Input By Displaying (AREA)

Abstract

La présente invention fournit un cadre rétréci pour un panneau capteur d'un système de capteur tactile doté d'un panneau capteur et d'un circuit intégré qui commande le panneau capteur. L'invention concerne en outre un panneau capteur et un circuit intégré qui commande le panneau capteur. Selon l'invention, le panneau capteur possède une rangée de première capacité électrostatique formée entre un nombre M de lignes de commande et une ligne de détection unique, et une rangée de seconde capacité électrostatique formée entre le nombre M de lignes de commande et une autre ligne de détection unique. Le circuit intégré possède une unité de commande et une unité d'estimation. L'unité de commande commande le nombre M de lignes de commande en parallèle sur la base de séquences de codage se coupant de longueur N, pour lesquelles chaque élément est configuré par addition ou soustraction de 1 respectivement pour la rangée de première capacité électrostatique et la rangée de seconde capacité électrostatique, et délivre la sortie de la rangée de première capacité électrostatique et la sortie de la rangée de seconde capacité électrostatique à un intégrateur analogique. L'unité de commande est disposée dans le panneau capteur.
PCT/JP2013/083961 2012-12-25 2013-12-18 Système de capteur tactile WO2014103844A1 (fr)

Applications Claiming Priority (2)

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JP2012280598 2012-12-25
JP2012-280598 2012-12-25

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005303499A (ja) * 2004-04-08 2005-10-27 Nippon Telegr & Teleph Corp <Ntt> 拡散符号生成回路および同期回路
JP2011233018A (ja) * 2010-04-28 2011-11-17 Sony Corp タッチ検出機能付き表示装置、駆動方法、および電子機器
JP4927216B1 (ja) * 2010-11-12 2012-05-09 シャープ株式会社 線形素子列値推定方法、静電容量検出方法、集積回路、タッチセンサシステム、及び電子機器
WO2012147634A1 (fr) * 2011-04-28 2012-11-01 シャープ株式会社 Dispositif d'entrée, procédé de détection de la position d'un contact tactile, et dispositif d'affichage équipé du dispositif d'entrée

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005303499A (ja) * 2004-04-08 2005-10-27 Nippon Telegr & Teleph Corp <Ntt> 拡散符号生成回路および同期回路
JP2011233018A (ja) * 2010-04-28 2011-11-17 Sony Corp タッチ検出機能付き表示装置、駆動方法、および電子機器
JP4927216B1 (ja) * 2010-11-12 2012-05-09 シャープ株式会社 線形素子列値推定方法、静電容量検出方法、集積回路、タッチセンサシステム、及び電子機器
WO2012147634A1 (fr) * 2011-04-28 2012-11-01 シャープ株式会社 Dispositif d'entrée, procédé de détection de la position d'un contact tactile, et dispositif d'affichage équipé du dispositif d'entrée

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