WO2014101780A1 - 一种硅上二氧化硅基的混合集成光电子芯片及其制作方法 - Google Patents

一种硅上二氧化硅基的混合集成光电子芯片及其制作方法 Download PDF

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Publication number
WO2014101780A1
WO2014101780A1 PCT/CN2013/090492 CN2013090492W WO2014101780A1 WO 2014101780 A1 WO2014101780 A1 WO 2014101780A1 CN 2013090492 W CN2013090492 W CN 2013090492W WO 2014101780 A1 WO2014101780 A1 WO 2014101780A1
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Prior art keywords
silicon
silicon dioxide
waveguide
optoelectronic chip
layer
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PCT/CN2013/090492
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English (en)
French (fr)
Inventor
周亮
曹小鸽
余向红
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武汉电信器件有限公司
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Priority to EP13867481.7A priority Critical patent/EP2940739B1/en
Priority to US14/758,416 priority patent/US9482831B2/en
Publication of WO2014101780A1 publication Critical patent/WO2014101780A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4256—Details of housings
    • G02B6/4257—Details of housings having a supporting carrier or a mounting substrate or a mounting plate
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/26—Optical coupling means
    • G02B6/30—Optical coupling means for use between fibre and thin-film device
    • G02B6/305—Optical coupling means for use between fibre and thin-film device and having an integrated mode-size expanding section, e.g. tapered waveguide
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/422—Active alignment, i.e. moving the elements in response to the detected degree of coupling or position of the elements
    • G02B6/4221—Active alignment, i.e. moving the elements in response to the detected degree of coupling or position of the elements involving a visual detection of the position of the elements, e.g. by using a microscope or a camera
    • G02B6/4224—Active alignment, i.e. moving the elements in response to the detected degree of coupling or position of the elements involving a visual detection of the position of the elements, e.g. by using a microscope or a camera using visual alignment markings, e.g. index methods
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
    • G02B6/4232—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using the surface tension of fluid solder to align the elements, e.g. solder bump techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0232—Optical elements or arrangements associated with the device
    • H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Definitions

  • the invention relates to a photonic integrated device technology, in particular to a silicon-on-silicon dioxide hybrid integrated optoelectronic chip and a manufacturing method thereof, and the invention can be applied to the splitting detection of multiple laser output light or multi-wavelength light source.
  • the integration degree of the chip is getting higher and higher, the size of the device is continuously shrinking, and the working speed of the device is continuously improved.
  • lasers based on III-V materials such as InP, GaAs, etc.
  • integrated electroabsorption modulation lasers have evolved from chip research to mass production, and their packaged devices have been used as mature light sources for optical communication.
  • the rate can range from a few hundred megabits per second to tens of tens of megabits per second.
  • silicon-based optical waveguide devices such as optical beam splitters and AWGs in optical passive devices have long been commercialized due to their simple process, low optical transmission loss, and easy coupling with optical fibers.
  • Passive waveguide materials include silicon dioxide, silicon dioxide on silicon, silicon on insulator, and the like.
  • the III-V laser and the silicon-based waveguide device are integrated on one chip, which not only reduces the device cost but also utilizes the high performance of each component, and becomes the inevitable development direction of the integrated optoelectronic chip.
  • the flip-chip electronic chip on the silicon-based waveguide material is currently the most feasible technology road. This is because the silicon material can not only grow a variety of silicon dioxide waveguides from it, but also has a thermal conductivity close to that of the metal, which is an ideal laser heat. Shen material. Therefore, silicon material is an ideal substrate material for hybrid integration of lasers and silicon-based waveguides.
  • the technical problem to be solved by the present invention is to provide a silicon-on-silicon dioxide-based hybrid integrated optoelectronic chip and a manufacturing method thereof.
  • the hybrid integrated chip utilizes a mature silicon-based material process to design a boss and a concave on a silicon substrate.
  • the slot and the high refractive index silica waveguide structure facilitate the alignment coupling of light.
  • the present invention fabricates a high frequency electrode and a flip chip bump structure under the bump, so that the active optoelectronic chip can transmit both high frequency signals and DC drive signals, and can achieve precise alignment.
  • the present invention provides a silicon-on-silicon dioxide-based hybrid integrated optoelectronic chip comprising a silicon substrate having a platform, a land and a groove on the surface of the silicon substrate, wherein the groove is provided with a silica waveguide element.
  • the boss protrudes from the surface of the platform, the platform
  • the surface is provided with a discontinuous metal electrode layer, the surface of the metal electrode layer is provided with a bump bump, and an active optoelectronic chip is disposed above the bump and the bump.
  • the longitudinal direction of the silicon dioxide waveguide element comprises a silicon dioxide substrate layer, a silicon dioxide waveguide layer and a silicon dioxide over cladding layer in sequence; the silicon dioxide waveguide layer includes a waveguide region in the lateral direction, close to the active optoelectronic chip.
  • the boss comprises a horizontal alignment boss and a vertical alignment boss, and the horizontal alignment boss and the vertical alignment boss have the same height, both of which are ⁇ 100 ⁇ .
  • the number and horizontal position of the horizontal alignment bosses are determined by alignment marks on the active optoelectronic chip, relative positions of the active optoelectronic chip waveguides, and the height of the vertical alignment bosses is determined by the silicon dioxide waveguide.
  • the vertical position of the silicon dioxide waveguide layer of the component is determined, the vertical alignment bump being located in the middle of the active optoelectronic chip.
  • the thickness of the metal electrode layer is 0.2 ⁇ ! ⁇ 3 ⁇
  • the metal electrode layer includes a DC electrode region, an AC electrode region, a ground electrode region, and an alignment pattern electrode region; the boss is between the DC electrode region and the AC electrode region, and the DC electrode region and the AC electrode A bump is formed on the electrode region, and is contacted with the DC electrode and the AC electrode of the active optoelectronic chip through the bump; the front alignment mark of the active optoelectronic chip and the horizontal alignment of the bump or the metal electrode layer The alignment mark is aligned; the back surface electrode of the active optoelectronic chip is connected to the ground electrode region of the metal electrode layer.
  • the silicon dioxide waveguide element has an outer end surface inclined by 5 ° to 45 ° from the vertical direction.
  • the invention provides a silicon-based silicon-based hybrid integrated optoelectronic chip manufacturing method, comprising the following steps: Step 1: fabricating a silicon substrate, and fabricating a silicon dioxide waveguide element in a groove of the silicon substrate;
  • Step two forming a metal electrode layer on the silicon substrate
  • Step 3 preparing a bump bump on the DC electrode region and the AC electrode region of the metal electrode layer
  • Step 4 Connect the active optoelectronic chip above the bump and the vertical alignment boss.
  • the silicon dioxide waveguide device is fabricated by a silicon dioxide thermal bonding process or a silicon dioxide growth process.
  • the first step comprises the following steps: Step 1: forming a bump on the surface of the silicon substrate;
  • Step 2 making a groove on one side of the boss of the silicon substrate
  • Step 3 growing a silicon dioxide bonding layer at the bottom of the groove, and fabricating the silicon dioxide waveguide element into the groove structure by a silica thermal bonding process, and melting the bonding layer into the silicon dioxide waveguide element Silicon oxide waveguide layer
  • the piece has an outer end face that is inclined by 5 ° to 45 ° from the vertical.
  • the first step comprises the following steps: Step 1: growing a silicon dioxide substrate layer and a silicon dioxide waveguide layer on the surface of the silicon substrate, and The silicon oxide waveguide layer is etched away to form a reserved area;
  • Step 2 growing an overcladding layer over the remaining silica waveguide layer
  • Step 3 etching the silicon dioxide substrate layer to the surface of the silicon substrate in the reserved region to form a bump.
  • the invention provides a silica-based hybrid integrated optoelectronic chip on silicon and a manufacturing method thereof, which adopts a multi-step process such as material growth, thermo-oxygen bonding, flip chip mounting and photolithography alignment to ensure waveguides of different materials. Efficient optical coupling between devices reduces light reflection between waveguide ends. High-frequency electrodes are fabricated between the horizontal and vertical alignment bosses, and the flip-chip process facilitates the transmission of high-frequency signals, thereby improving the integration between devices. At the same time, the design of the process can achieve both chip-level probe testing and subsequent gold wire ball or wedge process, making it easy to package and mass-produce hybrid integrated chips.
  • FIG. 1 is a schematic structural view of a silicon-on-silicon hybrid integrated optoelectronic chip provided by the present invention
  • FIGS. 3a to 3e are diagrams showing a silicon dioxide waveguide on a silicon using a silicon dioxide growth process in the present invention. Schematic diagram of the flow; Figure 4 a and Figure 4b are side and top views of the structure of the high frequency electrode on silicon;
  • Figure 5 is a schematic view of a bump formed on a high frequency electrode
  • Figure 6a is a schematic front view of the active optoelectronic chip
  • Figure 6b is a schematic diagram of the back structure of the active optoelectronic chip
  • Figure 6c is a schematic side view of the active optoelectronic chip
  • FIG. 7 is a schematic diagram of coupling alignment and electrode overlap of the active optoelectronic chip after flip-chip bonding with the high-frequency electrode.
  • the present invention provides a silicon-on-silicon dioxide-based hybrid integrated optoelectronic chip, the structure comprising: a silicon substrate 1 which is a silicon substrate of a silicon-based waveguide structure; the surface of the silicon substrate 1 has a platform 8.
  • the groove 10 and the plurality of bosses wherein the boss is a boss structure protruding from the surface of the platform 8, the groove is a groove structure concavely embedded under the platform 8; the silicon dioxide waveguide element 2 is located at the silicon liner In the groove 10 of the bottom 1; a metal electrode layer 3, the metal electrode layer 3 is formed on the surface of the platform 8 of the silicon substrate 1 by the metal electrode layer 3 ; the bump 4 is formed, and the bump 4 is made in part of the metal Above the electrode layer 3; an active optoelectronic chip 5, which is located above the bumps 4 and the bumps.
  • the silicon substrate 1 is a high-resistivity silicon material, and the metal electrode layer 3 can be fabricated to achieve low-loss high-frequency transmission and a good thermal conductivity.
  • the present invention is formed with a boss, a land 8 and a recess 10 on the silicon substrate 1.
  • the platform 8 is a silicon underlayer after the first silicon etching, and the recess 10 is a second silicon etching to form the bottom layer of the recess 10.
  • the boss includes a horizontal alignment boss 6 and a vertical alignment boss 7.
  • the horizontal alignment boss 6 is the same height as the vertical alignment boss 7, and is ⁇ ! ⁇ 100 ⁇ . Alignment of the cross-sectional pattern of the horizontal alignment boss 6 can be performed during the fabrication of the silicon dioxide waveguide to achieve the fixation of the position of the silicon dioxide waveguide layer relative to the horizontal alignment boss 6. In the lithography of the metal electrode layer 3, the cross-sectional pattern of the horizontal alignment bump 6 can be used to overlap the alignment mark to realize the position of the metal electrode layer 3 and the bump bump 4 thereon and the active photoelectron The electrode positions of the chip 5 are overlapped to facilitate electrical interconnection.
  • the alignment pattern can also be used to achieve alignment with a special pattern on the surface of the chip.
  • the horizontal alignment of the silicon dioxide waveguide element 2 and the active optoelectronic chip 5 in the horizontal direction can be achieved in parallel alignment for high-efficiency coupling; in the vertical direction, the tantalum bumps 4 need only be fabricated in A specific region of the metal electrode layer 3, specifically the DC electrode region 25 of the metal electrode layer 3 and the AC electrode region 26, ensures good contact with the active optoelectronic chip 5 during the mounting process.
  • the cross-sectional pattern of the horizontal alignment boss 6 is the same as or complementary to the alignment marks on the waveguide lithography plate, the metal electrode layer 3 and the active optoelectronic chip 5, as a reference position for optical coupling and electrical interconnection, such as active
  • the alignment marks on the optoelectronic chip 5 are cross-aligned marks, and the same horizontal alignment boss 6 cross-section is a cross, and the complementary cross-sectional pattern is four squares filling the four corners of the cross.
  • the position is aligned with respect to the horizontal alignment of the boss 6.
  • alignment marks on the waveguide lithography plate are aligned with the cross-sectional pattern of the horizontal alignment bump 6 to achieve alignment of the metal electrode layer 3 with respect to the horizontal direction. Fixing of the boss 6 to achieve metal
  • the electrode layer 3 and the position of the bump 4 on it overlap with the electrode position of the active optoelectronic chip 5, facilitating electrical interconnection.
  • the alignment pattern can also be used to achieve alignment with the alignment pattern on the front side of the active optoelectronic chip 5.
  • the silicon dioxide waveguide layer and the active optoelectronic chip 5 waveguide can be aligned in parallel for high-efficiency coupling; in the vertical direction, the bump bump 4 only needs to be fabricated.
  • the DC electrode region 25 and the AC electrode region 26 of the metal electrode layer 3 a good electrical interconnection between the active optoelectronic chip 5 and the metal electrode layer 3 is ensured.
  • the horizontal position is determined by the relative position of the alignment mark on the active optoelectronic chip 5 and the waveguide of the active optoelectronic chip 5 The number of alignment marks on the source photoelectronic chip 5 is determined.
  • the vertical alignment boss 7 is used for the height alignment of the laser or detector waveguide with the silicon dioxide waveguide layer. Due to the material growth and bonding process, the vertical position of the silicon dioxide waveguide layer is relative to the silicon substrate 1.
  • the platform 8 is fixed so that the position of the silica waveguide layer is also fixed relative to the vertical position of the vertical alignment boss 7.
  • the surface of the active optoelectronic chip 5 can be closely aligned with the vertical alignment boss 7, so that the optical coupling alignment between the waveguides in the vertical direction can be realized with high precision, thereby avoiding The effect of the error of the height of the bump 4 on the optical coupling.
  • the vertical alignment bosses 7 are correspondingly located at the central portion of the active optoelectronic chip 5 at horizontal relative positions, symmetrically distributed on both sides of the light-emitting or light-injecting waveguide of the active optoelectronic chip 5, and should not be connected to any metal electrode layer 3.
  • the vertical alignment boss 7 is a structure in which a plurality of cylinders or square columns are favorable for supporting the chip, and the cross-sectional area of a single vertical alignment boss is 100 ⁇ 2 to 40000 ⁇ 2 2 , and the number of vertical alignment bosses is 4 to 10, The specific number is determined by the ratio of the area of the central portion of the active optoelectronic chip 5 to the cross-sectional area of the single boss.
  • the height of the vertical alignment land is determined by the vertical position of the silicon dioxide waveguide layer.
  • the silica waveguide element 2 includes a silicon dioxide substrate layer 13, a silicon dioxide waveguide layer 14, and a silicon dioxide over cladding layer 15.
  • the silicon dioxide waveguide layer 14 is located above the silicon dioxide substrate layer 13.
  • the silicon dioxide waveguide layer 14 includes a general waveguide region 17, a coupling region 16 adjacent to the active optoelectronic chip, and a coupling region 18 adjacent the optical fiber.
  • the silica waveguide layer 14 is a high refractive index silica, the silica substrate layer 13 has the same refractive index as the material of the silica over cladding layer 15, and the refractive index and the dioxide of the material of the silica waveguide layer 14 are the same. 5% ⁇ 2.
  • the refractive index difference between the refractive index of the silicon substrate layer 13 and the upper cladding layer of the silica layer is 0.5% ⁇ 2. 5%.
  • the waveguide width of the coupling region 16 near the active optoelectronic chip is narrower than that of the general waveguide region, and is 3 m to 7 Mffl ; the waveguide width of the coupling region 18 near the optical fiber is wider than the general waveguide region, which is 6 ⁇ ! ⁇ 10 ⁇ .
  • the coupling region 16 adjacent to the active optoelectronic chip has a small waveguide width, and the high refractive index difference ensures that a small spot is formed near the coupling region 16 of the active optoelectronic chip for achieving high efficiency with the active optoelectronic chip 5.
  • the coupling region 18 adjacent the fiber has a larger waveguide width for increasing the spot diameter for efficient optical coupling to the fiber.
  • the coupling region 16 adjacent to the active optoelectronic chip and the outer end surface 19 of the coupling region 18 adjacent to the optical fiber are both inclined ends of 5 ° to 45 °
  • the tilting direction is the horizontal or vertical direction of the vertical wave deriving light or the center axis of the light incident to reduce the influence of the reflection of the waveguide end face on the active optoelectronic chip 5.
  • the distance between the outer surface of the coupling region 16 of the silicon dioxide waveguide element 2 adjacent to the active optoelectronic chip and the outer surface of the active optoelectronic chip 5 or the outer side of the optical waveguide is the maximum of the end face reflected light entering the active optoelectronic chip 5
  • the spacing is selected such that the maximum extent of the reflected light from the outer side of the coupling region 16 of the silicon dioxide waveguide element 2 adjacent to the active optoelectronic chip deviates from the exit of the active optoelectronic chip 5 or into the end face of the optical waveguide while the coupling
  • the near-field spot of the active optoelectronic chip 5 at the outer side of the region is identical or close to the spot size of the coupling region 16 near the active optoelectronic chip, the far-field divergence angle of the active optoelectronic chip 5 and the coupling region 16 close to the active optoelectronic chip.
  • the maximum incident angle is uniform or close, and high coupling
  • the thickness of the metal electrode layer 3 is 0.2 ⁇ ! ⁇ 3 ⁇ , is a multilayer metal structure, such as Ti/Pt/Au layer structure.
  • the metal electrode layer 3 is formed on the land 8 of the silicon substrate 1 and the multilayer structure of the metal electrode layer 3 is in good contact with the silicon substrate 1 and the bumps 4.
  • the metal electrode layer 3 is a metal electrode of a special structure, and includes a DC electrode region 25, an AC electrode region 26, a ground electrode region 27, and an alignment pattern electrode region 28, which are laterally distributed electrode structures.
  • the DC electrode region 25 and the AC electrode region 26 are located directly under the DC electrode 29 and the AC electrode 30 of the active optoelectronic chip 5, and the bumps 4 are formed on the DC electrode region 25 and the AC electrode region 26, respectively.
  • the DC and AC signals are applied to the active optoelectronic chip 5, and the DC electrode region 25 and the AC electrode region 26 have extension electrodes extending to the end of the platform 8 away from the boss, facilitating the connection between the chip package and the package. Gold wire interconnects.
  • the ground electrode region 27 is located at the end of the platform 8 away from the direction of the silicon land, and is connected to the back electrode of the active optoelectronic chip 5 by a gold wire lead.
  • the alignment pattern electrode regions 28 are aligned with the horizontal alignment bosses 6 in the bosses as previously described.
  • the tantalum bump layer comprises a plurality of tantalum bumps, and a metal transition layer prepared by using a material between the metal electrode layer 3 and the III-V laser or the detector is selected, and the material has a melting point of less than 400 ° C.
  • the metal material which is fusible and has good adhesion to the electrode metal such as AuSn, PbSn, SnAgCu, etc., after being fabricated on the metal electrode layer 3, has a thickness slightly higher than that of the surface of the boss for later pressing.
  • the bump bump 4 is formed only on the DC electrode region 25 and the AC electrode region 26 of the metal electrode layer 3 at the time of fabrication, and the number is determined by the area of the metal electrode layer 3 and the size ratio of the bump 4, which can be implanted.
  • the ball bump and the reflow process produce the bump bump 4, and the bump bump 4 should not overflow the DC electrode region 25 of the metal electrode layer 3 during the ball implantation and reflow process, and during the subsequent active photoelectron chip 5 patching process. And an alternating electrode region 26.
  • the active optoelectronic chip 5 is a waveguide type III-V laser or detector having a DC electrode, an AC electrode and an alignment mark on the front side, a ground electrode on the back surface, and a light exiting or optical waveguide in the middle.
  • the front DC and AC electrode regions are respectively in contact with the DC electrode region 25 of the metal electrode layer 3 and the AC electrode region 26 through the bumps 4, and after contacting the bumps 4, the alignment marks of the front surface are the same as the metal electrode layers.
  • Alignment mark of 3 or horizontal alignment of boss 6 for alignment using a combination of thermal reflow ⁇ and flip-chip compression The process forms an alloy between the front DC and AC electrode layers of the active optoelectronic chip 5 and the bumps 4, and is pressed down until the front surface of the active optoelectronic chip 5 is in contact with the silicon vertical alignment boss 7, which ensures low
  • the contact resistance also fixes the coupling position of the active optoelectronic chip 5 to the light exiting or into the optical waveguide.
  • the back electrode is connected to the ground electrode region 27 of the metal electrode layer 3 by a gold wire ball or a wedge.
  • the silicon-on-silicon hybrid integrated optoelectronic chip proposed by the invention can be used for single or multi-channel laser or detector chip and silicon on silicon waveguide device (such as beam splitter, beam combiner, AWG, etc.) Mixed integration between multi-channel optical transceivers for integrated TOSA or ROSA devices.
  • the hybrid integrated optoelectronic chip adopts III-V laser or detector chip and silicon-based waveguide device respectively, which utilizes the characteristics of active and passive performance of different material devices, and has the advantages of mature process and excellent performance of the unit chip.
  • the invention also provides the above-mentioned silicon-based silicon-based hybrid integrated optoelectronic chip manufacturing method, which specifically comprises the following steps:
  • Step 1 A silicon substrate is fabricated, and a silicon dioxide waveguide element is formed in the recess 10 of the silicon substrate.
  • the silicon dioxide waveguide element 2 can be fabricated by a silicon dioxide bonding process or a silicon dioxide growth process such as the well-prepared silica waveguide element 2, a silicon dioxide bonding process can be employed in the fabrication; A good silica waveguide material 2 can be fabricated using a silicon dioxide growth process.
  • the specific preparation steps are as follows:
  • Step 1 On the surface of the silicon substrate 1, a bump on the silicon substrate 1 is formed by a common photolithography and silicon etching process.
  • the bump includes a horizontal alignment boss 6 and a vertical alignment boss. 7, the first silicon etching, the etching depth is ⁇ ! ⁇ ⁇ , that is, the height of the horizontal alignment boss 6 and the vertical alignment boss 7 formed after etching is ⁇ to 100Mm.
  • the specific etching depth is determined by the height relationship between the silicon dioxide waveguide layer and the light-injecting or outgoing optical waveguide of the active optoelectronic chip 5 relative to the surface of the silicon substrate 1, ensuring the light entering of the silicon dioxide waveguide layer and the active optoelectronic chip 5. Or the height of the outgoing waveguide is flush.
  • a flat platform 8 and a boss above the platform 8 are formed, and a first photoresist layer 9 remaining in the first silicon etching remains above the land.
  • the cross-sectional pattern of the horizontal alignment boss 6 is the same as or complementary to the alignment marks on the waveguide lithography plate, the metal electrode layer 3 and the active optoelectronic chip 5, as a reference position for optical coupling and electrical interconnection, such as an active optoelectronic chip.
  • the alignment mark on the 5 is the alignment mark of the cross, and the same horizontal alignment boss cross-section pattern is a cross, and the complementary cross-sectional pattern is four squares filling the four corners of the cross.
  • the vertical alignment bosses 7 are located at horizontal opposite positions of the active optoelectronic chip 5 symmetrically distributed on both sides of the light-emitting or light-injecting waveguide of the active optoelectronic chip 5, and should not be connected to any metal electrode layer 3, vertical pair
  • the quasi-protrusion 7 is a structure in which a plurality of cylinders or square columns are favorable for supporting the chip.
  • the cross-sectional area of a single vertical alignment boss is 100Mffl 2 to 40000Mffl 2 , and the number of vertical alignment bosses is 4 to 10, and the specific number is
  • the central area of the active optoelectronic chip 5 (the substrate area intermediate the DC electrode of the active optoelectronic chip 5 and the alternating current electrode) is determined by the ratio of the cross-sectional area of a single vertical alignment boss.
  • Step 2 Make a groove 10 on the surface of the platform 8, and the groove 10 is the second silicon etching, see Fig. 2b.
  • the photoresist 9 remaining in the first silicon etching is removed, and the second photoresist layer 1 is formed on the substrate 8 and the bumps by ordinary photolithography.
  • the thickness of the photoresist layer is greater than the height of the bumps.
  • the second photoresist layer 11 after the second silicon etching is retained.
  • the depth of the groove 10 is loo ⁇ 1500l3 ⁇ 4, which is determined by the distance between the silicon dioxide waveguide layer and the bottom surface of the silicon dioxide element and the distance between the silicon dioxide waveguide layer and the surface of the silicon platform 8.
  • the groove 10 is a rectangular groove having a width and a length greater than the width and length of the silica waveguide element 2, a groove side wall of the groove 10 away from the land 8 and two other concaves adjacent to the side groove side wall.
  • the side walls of the groove are all scribe area reserved. After the entire hybrid integrated wafer fabrication is completed, the dicing reserved area will be removed, so that the groove 10 will only be close to the groove side wall of the boss 6 and the platform 8 side, as shown in FIG. 3b. .
  • Step 3 A silica waveguide element 2 is fabricated using a silica thermal bonding process.
  • the silicon oxide bonding layer 12 is grown on the surface of the recess 10 by thermal oxidation or plasma enhanced chemical vapor deposition (PECVD). The thickness of the bonding layer is 0. ⁇ ! ⁇ lMffl, see Figure 2c.
  • PECVD plasma enhanced chemical vapor deposition
  • the silicon dioxide bonding layer 12 is again used to fabricate the fabricated silicon dioxide waveguide element 2 by a high temperature thermal bonding process. In the recess 10 of the silicon substrate 1, the silicon dioxide bonding layer 12 is melted into the silicon oxide substrate layer 13.
  • the well-formed silicon dioxide waveguide element 2 structure comprises a silicon dioxide substrate layer 13, a silicon dioxide waveguide layer 14 and a silicon dioxide over cladding layer 15, wherein the silicon dioxide substrate layer 13 is located at the bottom of the recess 10, and the silicon dioxide
  • the waveguide layer 14 is an elongated structure that is perpendicular to the bottom of the recess 10 near the sidewalls of the recess.
  • the thickness of the silicon dioxide substrate layer 13 is 50 ⁇ !
  • the thickness of the silica waveguide layer 14 is 3 ⁇ ! ⁇ 50 ⁇
  • the thickness of the silica overcladding layer 15 is 50 ⁇ ! ⁇ 1000Mm.
  • the silicon dioxide waveguide layer 14 laterally includes a coupling region 16 adjacent the active optoelectronic chip, a general waveguide region 17 and a fiber coupling region 18 adjacent the fiber. 5% ⁇ 2. 5% ⁇ 5% ⁇ 2. 5% 5% 5% ⁇ 2. 5%
  • the silicon dioxide substrate layer 13 and the silicon dioxide over cladding layer 15 have the same refractive index.
  • the waveguide width of the waveguide region 17 is 6 ⁇ ⁇ !
  • Step 1 A silicon dioxide waveguide element 2 is fabricated, as shown in Fig. 3a.
  • the silicon dioxide substrate layer 13 and the silicon dioxide waveguide layer 14 are grown on the entire silicon substrate 1 by plasma enhanced chemical vapor deposition (PECVD) using a silicon dioxide growth process, and a gas such as decane can be simultaneously injected during growth.
  • PECVD plasma enhanced chemical vapor deposition
  • the mixture is waveguide doped to form a doped silica waveguide layer 14.
  • the silicon dioxide waveguide layer 14 is formed by a common photolithography and silicon dioxide etching process, and the silicon dioxide is etched to the silicon dioxide substrate layer 13, and the waveguide layer on the side of the silicon dioxide wave is also engraved.
  • a reserved area 20 having a length of 500 ⁇ m to 1500 ⁇ is reserved until the silicon dioxide substrate layer 13 is etched.
  • the silicon dioxide waveguide layer 14 includes a coupling region 16 adjacent to the active optoelectronic chip, a general waveguide region 17 and a coupling region 18 adjacent the optical fiber.
  • the waveguide region 17 has a waveguide width of 6 ⁇ ⁇ ⁇ 9 ⁇ ⁇ ;
  • the coupling region 16 near the active optoelectronic chip has a narrower waveguide width than the general waveguide region 17, which is 3 111 ⁇ 7
  • the coupling region 18 near the optical fiber has a wider waveguide width than the general waveguide.
  • Zone 17 is wider, 8 ⁇ ⁇ ! ⁇ 10 ⁇ .
  • the thickness of the silicon dioxide substrate layer 13 is 50 ⁇ ! ⁇ ⁇
  • the thickness of the silica waveguide layer 14 is 3 ⁇ ! ⁇ 50Mm.
  • Step 2 Fabrication of the upper cladding and inclined end faces of the silica.
  • PECVD plasma enhanced chemical vapor deposition
  • the upper cladding layer 15 of the upper portion of the silicon dioxide waveguide layer 14 is protected by ordinary photolithography, and a portion of the upper cladding layer 15 is etched away on the reserved region 20 by a silicon dioxide etching process. Up to the silicon oxide substrate layer 13, the remaining third photoresist layer 21 above the etched silicon cladding layer 15 remains, see Fig. 3c.
  • an end face polishing process is employed to form inclined end faces 19 on both sides of the silica waveguide layer 14.
  • the outer end face 19 of the coupling region 18 adjacent to the optoelectronic chip and the vicinity of the optical fiber 18 are inclined end faces of 5 to 45 degrees from the vertical direction, and the outer end faces are perpendicular to the wave-extracting light or the center axis of the light.
  • the thickness of the silicon dioxide cladding 15 is from 50 ⁇ m to 1000 ⁇ m.
  • Step 3 Make the horizontal alignment boss 6 and the vertical alignment boss 7.
  • the upper cladding layer 15 and its underlying waveguide structure are protected by a fourth photoresist layer 22 and the position and shape of the silicon dioxide alignment bumps are defined, using conventional photolithography and silicon dioxide.
  • the silicon dioxide substrate layer 13 is etched up to the surface of the silicon substrate 1, and a silicon dioxide vertical alignment bump 23 and a silicon dioxide horizontal alignment bump 24 are formed, see Fig. 3d.
  • the position and shape of the silicon dioxide horizontal alignment boss 24 and the silicon dioxide vertical alignment boss 23 and (i) the horizontal alignment convex described in the step 1 of the silicon dioxide waveguide element 2 fabricated by the silicon dioxide bonding process The position of the table 6 and the vertical alignment boss 7 coincides with the shape.
  • Retaining the fourth photoresist layer 22 after etching and changing the silicon The etching process continues to etch the silicon substrate 1 with a etch depth of ⁇ ! ⁇ lOOMffl, see Figure 3e. Due to the protection and self-alignment of the residual fourth photoresist layer 22, a vertical alignment boss 7 and a boss level will be formed at the lower portion of the silicon dioxide vertical alignment boss 23 and the silicon dioxide horizontal alignment boss 24.
  • the silicon dioxide vertical alignment boss 23 prepared by the method is aligned with the horizontal alignment of the silicon dioxide 24, the cross-sectional shape is aligned with the vertical alignment boss 7, and the horizontal alignment of the boss 6 is also the same.
  • the position of the vertical alignment boss 7 and the land horizontal alignment 6 described in the step 1 in the silicon dioxide waveguide element 2 by the silicon dioxide bonding process is identical to the cross-sectional shape.
  • the total height of the silicon dioxide vertical alignment boss 23 and the silicon dioxide horizontal alignment boss 24 and the vertical alignment boss 7 and the horizontal alignment of the boss 6 are lOMff1 ⁇ 100 ⁇ , and the specific height is determined by the silicon dioxide waveguide layer 14
  • the height relationship of the incoming or outgoing optical waveguide of the active optoelectronic chip 5 with respect to the surface of the silicon substrate 1 determines that the incoming or outgoing optical waveguides of the silicon dioxide waveguide layer 14 and the active optoelectronic chip 5 are of a high level.
  • the remaining third photoresist layer 21 and the fourth photoresist layer 22 are removed.
  • Step 2 Make a metal electrode layer 3.
  • the silicon dioxide waveguide region 14 is protected by a photoresist and a metal electrode pattern is defined, and the horizontal alignment bump 6 is aligned with the alignment mark on the metal electrode lithography plate, and ordinary lithography is used.
  • Metal sputtering layer 3 is formed on the platform 8 by metal sputtering and evaporation and metal stripping processes, see Figures 4a and 4b. 2 ⁇ ! The thickness of the metal electrode layer 3 is 0. 2 ⁇ ! ⁇ 3 ⁇ , is a multilayer metal structure, such as Ti/Pt/Au layer structure.
  • the metal electrode layer 3 is formed on the silicon platform 8, and the multilayer structure of the metal electrode layer 3 needs to have good contact with the silicon substrate 1 and the bumps 4.
  • the metal electrode layer 3 is a metal electrode of a special structure including a direct current electrode region 25, an alternating current electrode region 26, a ground electrode region 27, and an alignment pattern electrode region 28.
  • the DC electrode region 25 and the AC electrode region 26 are located directly under the DC electrode 29 and the AC electrode 30 of the optoelectronic chip to form a bump bump 4 on the DC electrode region 25 and the AC electrode region 26 for respectively applying DC and AC signals.
  • the DC electrode region 25 and the AC electrode region 26 have elongated electrodes extending to the end of the platform 8 away from the boss to facilitate interconnection of the gold wires between the chip package and the package.
  • the ground electrode region 27 is located at the end of the platform 8 away from the direction of the silicon boss, and is connected to the back electrode of the optoelectronic chip by a gold wire lead.
  • the alignment pattern electrode regions 28 are aligned for alignment with the horizontal alignment bosses 6 as previously described.
  • Step 3 Make a bump 4 on the metal electrode layer 3, align the metal electrode alignment mark 28 or the silicon horizontal alignment boss 6 with the calibration mark of the ball bumping ball machine, using the ball and The reflow process produces a bump 4, see Figure 5.
  • the number of the bumps 4 formed only on the DC electrode region 25 and the AC electrode region 26 of the metal electrode layer 3 is determined by the ratio of the area of the metal electrode and the size of the bump 4, and the bumps 4 are in the ball implantation and reflow process.
  • the DC electrode region 25 and the AC electrode region 26 of the metal electrode layer 3 should not overflow.
  • Step 4 Connect the active optoelectronic chip 5.
  • the active optoelectronic chip 5 is a waveguide type III-V laser or detector having a DC electrode 29, an AC electrode 30 and an alignment mark 31 on the front side, a light-emitting or light-inlet waveguide 32 in the middle, and a ground electrode 33 on the back surface.
  • the lower portion of the front electrode is the front surface 34, see Figs. 6a to 6c.
  • the stage 6 is aligned with the alignment mark 31 on the active optoelectronic chip 5, and the metal electrode layer 3 of the active optoelectronic chip 5 is formed on the bump 4 by a combination of thermal reflow and flip-chip bonding. , see Figure 7.
  • the front DC electrode 29 and the AC electrode 30 are in contact with the DC electrode region 25 of the metal electrode layer 3 and the upper portion of the AC electrode region 26 and the bumps 4, respectively. After contacting the bump 4, the alignment mark of the front surface is aligned with the alignment pattern electrode area 28 alignment mark or the horizontal alignment boss 6, and a combination of hot reflow ⁇ and flip-chip pressing is adopted.
  • the front side DC electrode 29 and the alternating current electrode 30 of the active optoelectronic chip 5 are alloyed with the bumps 4 and pressed down until the front surface 34 of the active optoelectronic chip 5 is aligned with the silicon perpendicularly to the land 7 with reference to FIG.

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Abstract

提供一种硅上二氧化硅基的混合集成光电子芯片及其制作方法。所述混合集成光电子芯片包括硅衬底（1），所述硅衬底（1）表面具有平台（8）、凸台（6，7）和凹槽（10）；所述凹槽（10）中设置有二氧化硅波导元件（2），所述凸台（6，7）凸出于所述平台（8）表面，所述平台（8）表面设置有不连续的金属电极层（3）；所述金属电极层（3）的表面设置有焊料凸点（4），所述焊料凸点（4）和凸台（6，7）上方设置有有源光电子芯片（5）。所述制作方法采用了材料生长、热氧键合、倒装贴片和光刻对准等多步工艺，保证了不同材料波导器件间的高效光耦合，减少了波导端面间的光反射。在对准凸台（6，7）间制作有交流电极区（26）构成的高频电极，利用倒装焊工艺利于高频信号的传输，提高了器件间的集成度。同时该工艺的设计既可实现芯片级的探针测试，又可用于后续的金丝球焊或楔焊工艺，易于实现混合集成芯片的封装和量产。

Description

一种硅上二氧化硅基的混合集成光电子芯片及其制作方法 技术领域
本发明涉及光子集成器件技术领域具体为一种硅上二氧化硅基的混合集成光电子芯片及其 制作方法， 本发明可应用于多个激光器输出光的合波或多波长光源的分光探测中。
背景技术
随着微纳光电集成技术的不断发展， 芯片的集成度越来越高， 器件的尺寸不断縮小， 而器件 的工作速率则不断提高。
在光有源器件方面， 基于 III-V族材料 （如 InP， GaAs等） 的激光器以及集成的电吸收调制 激光器已从芯片研究发展到大批量生产， 其封装器件已作为成熟光源应用于光通信、 光医疗等光 电领域， 速率可从几百兆比特每秒至几十几十千兆比特每秒。
与此同时， 光无源器件中基于硅基的光波导器件， 如光分束器、 AWG等， 由于其工艺简单、 光传输损耗低、 易于同光纤耦合等特点， 早已实现商用化。 无源波导材料包括二氧化硅、 硅上二 氧化硅、 绝缘体上硅等多种材料。
随着未来光电子技术的发展， 将 III-V族的激光器同硅基的波导器件集成在一个芯片上， 既 降低了器件成本又利用了各元件的高性能， 成为了集成光电子芯片的必然发展方向， 其中在硅基 波导材料上倒装悍光电子芯片是目前最可行的技术路 这是由于硅材料不仅能从其上生长多种 二氧化硅波导， 而且其导热系数接近金属， 是理想的激光器热沉材料。 因此硅材料是激光器同硅 基波导实现混合集成的理想衬底材料。
由于材料特性的不同， 其混合集成存在多个难点， 其中就包括激光器或探测器波导同二氧化 硅波导的光耦合对准问题， 激光器或探测器的高频信号加载或传输问题、 工艺复杂且成本高以及 集成器件的散热等。 因此， 急需一种工艺简单、有效、合理的混合集成芯片设计来解决上述问题。 发明内容
本发明所要解决的技术问题为提供一种硅上二氧化硅基的混合集成光电子芯片及其制作方 法， 该混合集成芯片利用成熟的硅基材料工艺， 设计了硅衬底上的凸台、 凹槽以及高折射率的二 氧化硅波导结构， 易于实现光的对准耦合。 同时本发明在凸台下制作高频电极和倒装悍料凸点结 构， 使有源光电子芯片既能传输高频信号又能加载直流驱动信号， 并能够实现精确对准。
本发明提供一种硅上二氧化硅基的混合集成光电子芯片， 包括硅衬底， 所述硅衬底表面具有 平台、 凸台和凹槽， 所述凹槽中设置有二氧化硅波导元件， 所述凸台凸出于平台表面， 所述平台 表面设置有不连续的金属电极层， 所述金属电极层的表面设置有悍料凸点， 所述的悍料凸点和凸 台上方设置有有源光电子芯片。
进一步地， 二氧化硅波导元件的纵向依次包括二氧化硅衬底层、 二氧化硅波导层和二氧化硅 上包层； 所述的二氧化硅波导层横向依次包括波导区、靠近有源光电子芯片的耦合区和靠近光纤 的耦合区； 靠近有源光电子芯片的耦合区的波导宽度为 3 m-7 m; 靠近光纤的耦合区的波导宽度 为 6Μπι - 10Μπι。
进一步地， 所述凸台包括水平对准凸台与垂直对准凸台， 所述水平对准凸台与垂直对准凸台 的高度相等， 均为 ΙθΜπι 〜100Μπι。
进一步地， 所述水平对准凸台的个数与水平位置由有源光电子芯片上的对准标记、有源光电 子芯片波导的相对位置决 所述垂直对准凸台的高度由二氧化硅波导元件的二氧化硅波导层的 垂直位置决定， 所述垂直对准凸台位于有源光电子芯片的中部。
进一步地， 所述金属电极层的厚度为 0. 2ΜΠ！〜 3Μπι， 所述金属电极层包括直流电极区、 交流 电极区、 地线电极区和对准图形电极区； 所述凸台处于直流电极区和交流电极区之间， 所述直流 电极区和交流电极区上方制作有悍料凸点， 通过悍料凸点与有源光电子芯片的直流电极、交流电 极接触； 所述有源光电子芯片的正面对准标记与水平对准凸台或金属电极层的对准标记对准； 所 述的有源光电子芯片的背面电极与金属电极层的地线电极区连接。
进一步地， 所述的二氧化硅波导元件具有与竖直方向倾斜 5 ° 〜45 ° 的外部端面。
本发明提供一种硅上二氧化硅基的混合集成光电子芯片的制作方法， 包括以下几个步骤： 步骤一： 制作硅衬底， 并在硅衬底的凹槽中制作二氧化硅波导元件；
步骤二： 在硅衬底上制作金属电极层；
步骤三： 在金属电极层的直流电极区和交流电极区上方制作悍料凸点；
步骤四： 在悍料凸点、 垂直对准凸台上方悍接有源光电子芯片。
进一步地，所述的步骤一中制作二氧化硅波导元件采用二氧化硅热键合工艺或二氧化硅生长 工艺。
进一步地，当采用二氧化硅热键合工艺制作二氧化硅波导元件时，步骤一包括以下几个步骤 步骤 1 : 硅衬底的表面制作凸台；
步骤 2 : 在硅衬底的凸台的一侧制作凹槽；
步骤 3: 在凹槽的底部生长二氧化硅键合层， 将二氧化硅波导元件采用二氧化硅热键合工艺 制作到凹槽结构中， 使键合层熔入二氧化硅波导元件的二氧化硅衬底层中， 并使二氧化硅波导元 件具有与竖直方向倾斜 5 ° 〜45 ° 的外部端面。
进一步地， 当采用二氧化硅生长工艺制作二氧化硅波导元件时， 步骤一包括以下几个步骤： 步骤 1: 在硅衬底表面生长二氧化硅衬底层和二氧化硅波导层， 并将二氧化硅波导层刻蚀掉 一部分， 形成预留区；
步骤 2 : 在保留的二氧化硅波导层上方生长上包层；
步骤 3 : 在保留区刻蚀二氧化硅衬底层至硅衬底的表面， 形成凸台。
本发明具有的优点在于：
本发明提供一种硅上二氧化硅基的混合集成光电子芯片及其制作方法， 采用了材料生长、 热 氧键合、 倒装贴片和光刻对准等多步工艺， 保证了不同材料波导器件间的高效光耦合， 减少了波 导端面间的光反射。在水平和竖直对准凸台间制作有高频电极， 利用倒装悍工艺利于高频信号的 传输， 提高了器件间的集成度。 同时该工艺的设计既可实现芯片级的探针测试， 又可用于后续的 金丝球悍或楔悍工艺， 易于实现混合集成芯片的封装和量产。 附图说明
图 1为本发明提供的硅上二氧化硅基的混合集成光电子芯片的结构示意图；
图 2a〜图 2c为本发明中采用二氧化硅键合工艺制作硅上二氧化硅波导元件的流程示意图； 图 3a〜图 3e为本发明中采用二氧化硅生长工艺制作硅上二氧化硅波导流程示意图； 图 4 a和图 4b 为制作硅上高频电极的结构侧视与俯视图；
图 5 为高频电极上制作悍料凸点示意图；
图 6 a为有源光电子芯片的正面结构示意图；
图 6 b为有源光电子芯片的背面结构示意图；
图 6 c为有源光电子芯片的侧视结构示意图；
图 7为有源光电子芯片与高频电极倒装悍接后的耦合对准及电极重叠示意图。
图中： 1-硅衬底； 2-二氧化硅波导元件； 3-金属电极层； 4-悍料凸点； 5-有源光电子芯片； 6-水平对准凸台； 7-垂直对准凸台； 8-平台； 9-第一光刻胶层； 10-凹槽； 11-第二光刻胶层； 12- 二氧化硅键合层； 13-二氧化硅衬底层； 14-二氧化硅波导层； 15-二氧化硅上包层； 16-靠近有源 光电子芯片的耦合区； 17-—般波导区； 18-靠近光纤的耦合区； 19-外部端面； 20-预留区； 21- 第三光刻胶层； 22-第四光刻胶层； 23-二氧化硅垂直对准凸台； 24-二氧化硅水平对准凸台； 25- 直流电极区； 26-交流电极区； 27-地线电极区； 28-对准图形电极区； 29-直流电极； 30-交流电 极； 31-对准标记； 32-出光或入光波导； 33-地线电极； 34-正表面。 具体实施方式
下面结合附图和具体实施例对本发明作进一步说明， 以使本领域的技术人员可以更好的理解 本发明并能予以实施， 但所举实施例不作为对本发明的限定。
本发明提供一种硅上二氧化硅基的混合集成光电子芯片， 其结构包括： 硅衬底 1， 该硅衬底 1为硅基波导结构的硅衬底； 该硅衬底 1的表面具有平台 8、 凹槽 10和多个凸台， 其中凸台为凸 出于平台 8表面的凸台结构， 凹槽为凹嵌于平台 8下方的凹槽结构； 二氧化硅波导元件 2， 位于 硅衬底 1的凹槽 10中； 金属电极层 3， 该金属电极层 3制作于硅衬底 1的平台 8表面部分金属 电极层 3 ; 悍料凸点 4， 该悍料凸点 4制作在部分金属电极层 3上方； 有源光电子芯片 5， 该有 源光电子芯片 5位于悍料凸点 4和凸台的上方。
所述的硅衬底 1为高电阻率硅材料， 制作金属电极层 3后能实现低损耗的高频传输， 同时还 具有良好的热导系数。 本发明在硅衬底 1上制作有凸台、 平台 8和凹槽 10。 其中平台 8为第一 次硅刻蚀后制作出凸台后的硅底层， 凹槽 10为第二次硅刻蚀后制作出凹槽 10底层。
所述的凸台包括有水平对准凸台 6与垂直对准凸台 7。 水平对准凸台 6与垂直对准凸台 7的 高度相同， 均为 Ιθμπ！〜 100μπι。 在二氧化硅波导的制作过程中可以利用此水平对准凸台 6的截面 图形进行对准， 用以实现二氧化硅波导层位置相对于水平对准凸台 6的固定。 在金属电极层 3 的光刻中， 可利用此水平对准凸台 6的截面图形实现与对准标记重叠， 用以实现金属电极层 3 及其上的悍料凸点 4位置与有源光电子芯片 5的电极位置相重叠， 方便实现电学互连。 此外， 在 有源光电子芯片 5的倒装贴片中， 也可利用此对准图形与芯片表面的特殊图形实现对准。 这样， 通过水平对准凸台 6在水平方向上二氧化硅波导元件 2与有源光电子芯片 5波导能达到平行对 准， 实现高效耦合； 在垂直方向上， 悍料凸点 4只需制作在金属电极层 3的特定区域， 具体为金 属电极层 3的直流电极区 25和交流电极区 26， 即可保证贴片过程中与有源光电子芯片 5的良好 接触。
所述水平对准凸台 6的截面图形与波导光刻版、金属电极层 3和有源光电子芯片 5上的对准 标记相同或互补， 作为光耦合及电互连的基准位置， 如有源光电子芯片 5上的对准标记截面为十 字的对准标记， 则相同的水平对准凸台 6截面图形为十字， 互补的截面图形为填补十字四角空白 的四个方块。 在用普通光刻制作二氧化硅波导元件 2的结构时， 可利用波导光刻版上的对准标记 同此水平对准凸台 6的截面图形进行对准， 用以实现二氧化硅波导层位置相对于水平对准凸台 6 的固定。 在用普通光刻制作金属电极层 3时， 利用波导光刻版上的对准标记同此水平对准凸台 6 的截面图形进行对准， 用以实现金属电极层 3位置相对于水平对准凸台 6的固定， 用以实现金属 电极层 3及其上的悍料凸点 4位置与有源光电子芯片 5的电极位置重叠， 方便实现电学互连。此 夕卜， 在有源光电子芯片 5的倒装贴片中， 也可利用此对准图形与有源光电子芯片 5正面的对准图 形实现对准。 这样， 通过水平对准凸台 6， 在水平方向上， 二氧化硅波导层与有源光电子芯片 5 波导能达到平行对准， 实现高效耦合； 在垂直方向上， 悍料凸点 4只需制作在金属电极层 3的直 流电极区 25和交流电极区 26， 即可保证有源光电子芯片 5同金属电极层 3间的良好电互联。 因 水平对准凸台 6需同有源光电子芯片 5上的对准标记对准其水平位置由有源光电子芯片 5上的 对准标记同有源光电子芯片 5波导的相对位置决 个数由有源光电子芯片 5上的对准标记个数 决定。
所述垂直对准凸台 7用于激光器或探测器波导同二氧化硅波导层在高度上的对齐由于采用 材料生长和键合工艺， 二氧化硅波导层的垂直位置相对于硅衬底 1的平台 8是固定的， 因此二氧 化硅波导层位置相对于垂直对准凸台 7的垂直位置也固定。 在有源光电子芯片 5的贴片过程中， 可将有源光电子芯片 5的表面紧贴对准垂直对准凸台 7， 即可高精度的实现垂直方向上的波导间 光耦合对准， 避免了悍料凸点 4高度的误差对光耦合的影响。 垂直对准凸台 7在水平相对位置上 对应位于有源光电子芯片 5的中部， 对称分布于有源光电子芯片 5的出光或入光波导的两侧， 并 不应与任何金属电极层 3相连， 垂直对准凸台 7为多根圆柱或方柱等利于支撑芯片的结构， 单个 垂直对准凸台 Ί的截面积 100μω2〜40000μπι2， 垂直对准凸台 7个数有 4〜10个， 具体个数由有源 光电子芯片 5的中部面积同单个凸台的截面积比例决定垂直对准凸台 Ί高度是由二氧化硅波导 层的垂直位置决定的。
所述二氧化硅波导元件 2包括二氧化硅衬底层 13、 二氧化硅波导层 14和二氧化硅上包层 15。 二氧化硅波导层 14位于二氧化硅衬底层 13上方， 二氧化硅波导层 14包括一般波导区 17、 靠近有源光电子芯片的耦合区 16和靠近光纤的耦合区 18。 二氧化硅波导层 14为高折射率的二 氧化硅， 二氧化硅衬底层 13与二氧化硅上包层 15的材料的折射率相同， 二氧化硅波导层 14的 材料的折射率与二氧化硅衬底层 13、 二氧化硅上包层 15的折射率之间的折射率差为 0. 5%〜 2. 5%。 靠近有源光电子芯片的耦合区 16的波导宽度比一般波导区窄， 为 3 m〜7Mffl; 靠近光纤的 耦合区 18的波导宽度比一般波导区宽， 为 6Μπ！〜 10μιπ。
靠近有源光电子芯片的耦合区 16具有较小的波导宽度， 结合高的折射率差能保证靠近有源 光电子芯片的耦合区 16形成较小的光斑， 用以实现与有源光电子芯片 5的高效光耦合。 靠近光 纤的耦合区 18具有较大的波导宽度， 是为了增大光斑直径， 用以实现与光纤的高效光耦合。 靠 近有源光电子芯片的耦合区 16和靠近光纤的耦合区 18的外部端面 19均为 5 ° 〜45 ° 的倾斜端 面， 倾斜方向为垂直波导出光或入光中心轴的横向或纵向， 用以减少波导端面反射对有源光电子 芯片 5的影响。 二氧化硅波导元件 2中靠近有源光电子芯片的耦合区 16的外表面同有源光电子 芯片 5出光或入光波导的外部侧面之间的间距为无端面反射光进入有源光电子芯片 5的最佳间 距， 该间距的选择原则为， 二氧化硅波导元件 2的靠近有源光电子芯片的耦合区 16的外部侧面 反射光的最大范围偏离有源光电子芯片 5出光或入光波导端面 同时在该耦合区的外部侧面处有 源光电子芯片 5的近场光斑与靠近有源光电子芯片的耦合区 16光斑尺寸一致或接近， 有源光电 子芯片 5的远场发散角与靠近有源光电子芯片的耦合区 16的最大入射角一致或接近， 即可实现 高耦合效率的同时， 避免反射光对有源光电子芯片 5性能的影响。
所述金属电极层 3厚度为 0. 2ΜΠ！〜 3Μπι， 为多层金属结构， 如 Ti/Pt/Au层结构。 该金属电极 层 3制作在硅衬底 1的平台 8上金属电极层 3的多层结构需同硅衬底 1及悍料凸点 4有良好的 接触。 该金属电极层 3为特殊结构的金属电极， 包括直流电极区 25、 交流电极区 26、 地线电极 区 27和对准图形电极区 28， 该四个区为横向分布的电极结构。 直流电极区 25和交流电极区 26 位于有源光电子芯片 5的直流电极 29及交流电极 30的正下方， 在所述的直流电极区 25和交流 电极区 26上制作悍料凸点 4， 分别用于将直流和交流电信号加载到有源光电子芯片 5上， 直流 电极区 25和交流电极区 26均有延长电极， 延伸到平台 8上远离凸台方向的末端， 便于同芯片封 装管壳间的金丝引线互连。 地线电极区 27位于平台 8上远离硅凸台方向的末端， 用金丝引线同 有源光电子芯片 5的背面电极连接。 对准图形电极区 28如前所述， 同凸台中的水平对准凸台 6 对准。
所述悍料凸点层包括多个悍料凸点， 选择以金属电极层 3和 III-V族激光器或探测器间之间 的材料制备的金属过渡层， 其材料为熔点低于 400°C的易熔悍接且与电极金属有良好附着性的金 属材料， 如 AuSn、 PbSn、 SnAgCu等材料， 制作于金属电极层 3上后， 其厚度要求略高于凸台的 表面， 以便后期压制。 悍料凸点 4在制作时仅制作于金属电极层 3的直流电极区 25和交流电极 区 26上， 个数由金属电极层 3的面积和悍料凸点 4的大小比例决定， 可采用植球和回流工艺制 作悍料凸点 4， 悍料凸点 4在植球和回流工艺过程中， 以及后续有源光电子芯片 5贴片过程中， 均不应溢出金属电极层 3的直流电极区 25和交流电极区 26。
所述有源光电子芯片 5为波导型的 III-V族激光器或探测器， 其正面有直流电极、 交流电极 和对准标记， 背面有地电极， 中部有出光或入光波导。 正面的直流、 交流电极区通过悍料凸点 4 与金属电极层 3的直流电极区 25、 交流电极区 26分别接触， 接触到悍料凸点 4后， 将正面的对 准标记同金属电极层 3的对准标记或水平对准凸台 6进行对准采用热回流悍和倒装压悍的结合 工艺， 将有源光电子芯片 5的正面直流和交流电极层同悍料凸点 4间形成合金， 并下压直至有源 光电子芯片 5的正面同硅垂直对准凸台 7接触， 既保证了低的接触电阻， 又固定了有源光电子芯 片 5出光或入光波导的耦合位置。背面电极通过金丝球悍或楔悍连接到金属电极层 3的地线电极 区 27上。
本发明提出的一种硅上二氧化硅基的混合集成光电子芯片可用于单路或多路激光器或探测 器芯片同硅上二氧化硅波导器件（如分束器、 合束器、 AWG等） 间的混合集成， 用于多通道光收 发集成化的 T0SA或 ROSA器件中。 该混合集成光电子芯片分别采用 III-V族激光器或探测器芯片 和硅基波导器件， 利用了不同材料器件在有源和无源性能上的特点， 具有单元芯片工艺成熟、 性 能优异的优势。
本发明还提供上述的硅上二氧化硅基的混合集成光电子芯片的制作方法， 具体包括以下几 个步骤：
步骤一： 制作硅衬底， 并在硅衬底的凹槽 10中制作二氧化硅波导元件。
因制作二氧化硅波导元件 2可采用二氧化硅键合工艺或二氧化硅生长工艺如已有制作完好 的二氧化硅波导元件 2， 则制作中可采用二氧化硅键合工艺； 如没有制作完好的二氧化硅波导元 件 2则制作中可采用二氧化硅生长工艺。当采用二氧化硅键合工艺制作二氧化硅波导元件 2时， 具体制备步骤如下：
(一） 采用二氧化硅键合工艺制作二氧化硅波导元件
步骤 1: 在硅衬底 1表面， 采用普通光刻和硅刻蚀工艺制作硅衬底 1上的凸台， 参看图 2a， 该凸台包括有水平对准凸台 6与垂直对准凸台 7， 即进行第一次硅刻蚀， 刻蚀深度为 ΙθΜπ！ 〜 ΙΟΟμπι, 也即刻蚀后形成的水平对准凸台 6和垂直对准凸台 7的高度为 Ιθμιπ 〜100Mm。 该具体刻 蚀深度由二氧化硅波导层和有源光电子芯片 5的入光或出光波导相对于硅衬底 1表面的高度关系 决定， 保证二氧化硅波导层和有源光电子芯片 5的入光或出光波导的高度相平齐。 第一次硅刻蚀 后形成平整的平台 8以及位于平台 8上方的凸台，且凸台上方保留有第一次硅刻蚀残余的第一光 刻胶层 9。
水平对准凸台 6的截面图形与波导光刻版、金属电极层 3和有源光电子芯片 5上的对准标记 相同或互补， 作为光耦合及电互连的基准位置， 如有源光电子芯片 5上的对准标记截面为十字的 对准标记， 则相同的水平对准凸台截面图形为十字， 互补的截面图形为填补十字四角空白的四个 方块。 因水平对准凸台 6需同光电子芯片上对准标记对准， 其水平位置由光电子芯片上的对准标 记同光电子芯片波导的相对位置决定， 个数由光电子芯片上的对准标记个数决定。 垂直对准凸台 7在水平相对位置上位于有源光电子芯片 5的中音 对称分布于有源光电子芯 片 5出光或入光波导的两侧， 并不应与任何金属电极层 3相连， 垂直对准凸台 7为多根圆柱或方 柱等利于支撑芯片的结构， 单个垂直对准凸台的截面积 100Mffl2〜40000Mffl2， 垂直对准凸台个数有 4〜10个， 具体个数由有源光电子芯片 5的中部面积（有源光电子芯片 5的直流电极与交流电极 中间的衬底区） 同单个垂直对准凸台的截面积比例决定。
步骤 2: 在平台 8表面制作凹槽 10， 此次制作凹槽 10即为第二次硅刻蚀， 参看图 2b。 首先 去除第一次硅刻蚀残余的光刻胶 9， 在平台 8以及凸台上方采用普通光刻制作第二光刻胶层 1 1， 该光刻胶层的厚度大于凸台的高度， 以保护凸台区 （6、 7 ) 并定义凹槽 10边界， 再采用硅刻蚀 工艺在第二光刻胶层 11和平台 8的一侧制作凹槽 10， 刻蚀深度为 lOOMffl 〜1500μπι， 该刻蚀深度 大于第二光刻胶层 11的厚度。 保留第二次硅刻蚀后的第二光刻胶层 11。 凹槽 10深度为 loo 〜1500l¾具体由二氧化硅波导层同二氧化硅元件底面的距离和二氧化硅波导层同硅平台 8表面 的距离共同决定。 凹槽 10为矩形凹槽， 宽度和长度均大于二氧化硅波导元件 2的宽度与长度， 凹槽 10中远离平台 8的凹槽侧壁以及相邻该侧凹槽侧壁的另外两个凹槽侧壁均为划片预留区。 在整个混合集成晶圆制作完成后划片工艺中， 将去除该划片预留区， 这样凹槽 10将仅余靠近凸 台 6、 平台 8—侧的凹槽侧壁， 如图 3b所示。
步骤 3: 制作二氧化硅波导元件 2， 采用二氧化硅热键合工艺。 在凹槽 10的表面采用热氧化 或等离子体增强化学气相沉积（PECVD)生长二氧化硅键合层 12， 该键合层厚度为 0. Οΐμπ！〜 lMffl, 参看图 2c。 其次去除步骤 2中的第二次硅刻蚀后的第二光刻胶层 1 1， 再次利用二氧化硅键合层 12将制作完好的二氧化硅波导元件 2采用高温热键合工艺制作到硅衬底 1的凹槽 10中， 使二氧 化硅键合层 12熔入二氧化硅衬底层 13中。 同时， 移动二氧化硅波导元件 2， 直至二氧化硅波导 元件 2靠近设计的靠近有源光电子芯片的耦合区 16端面紧贴凹槽 10靠近凸台方向的凹槽侧壁。 制作完好的二氧化硅波导元件 2结构包括二氧化硅衬底层 13、 二氧化硅波导层 14和二氧化硅上 包层 15， 其中二氧化硅衬底层 13位于凹槽 10的底部， 二氧化硅波导层 14为垂直于凹槽 10底 部靠近凹槽侧壁的长条形结构。 二氧化硅衬底层 13的厚度为 50ΜΠ！〜 ΙΟΟΟμιπ, 二氧化硅波导层 14 的厚度为 3μπ！〜 50Μπι， 二氧化硅上包层 15的厚度为 50Μπ！〜 1000Mm。 二氧化硅波导层 14横向包括 靠近有源光电子芯片的耦合区 16、 一般波导区 17和靠近光纤的光纤耦合区 18。 二氧化硅波导层 1 为高折射率的二氧化硅， 二氧化硅波导层 14同二氧化硅衬底层 13、 二氧化硅上包层 15的折 射率差为 0. 5%〜2. 5%， 二氧化硅衬底层 13与二氧化硅上包层 15的材料折射率相同。 一般波导 区 17的波导宽度为 6Μπ！〜 9)¾靠近有源光电子芯片的耦合区 16波导宽度比一般波导区 17更窄， 为 3Μπ！〜 7Mffl; 靠近光纤的耦合区 18波导宽度比一般波导区 17更宽， 为 8Μπ！〜 10Mm。 靠近有源光 电子芯片的耦合区 16和靠近光纤的耦合区 18的外侧端面 19均为与竖直方向呈 5 ° 至 45 ° 夹角 的倾斜端面， 且与垂直波导出光或入光中心轴相垂直。
(二） 采用二氧化硅生长工艺制作二氧化硅波导元件
步骤 1 : 制作二氧化硅波导元件 2， 如图 3a。 采用二氧化硅生长工艺， 在整个硅衬底 1上采 用等离子体增强化学气相沉积 （PECVD ) 生长二氧化硅衬底层 13和二氧化硅波导层 14， 在生长 时可采用同步注入锗烷等气体混合物进行波导掺杂制作掺杂二氧化硅波导层 14。 再利用普通光 刻和二氧化硅刻蚀工艺制作出二氧化硅波导层 14， 二氧化硅刻蚀到二氧化硅衬底层 13为止， 且 将二氧化硅波导出光面一侧的波导层也刻蚀到二氧化硅衬底层 13为止， 预留出长度为 500μπι 〜 1500ΜΠ1的预留区 20。 二氧化硅波导层 14为高折射率的二氧化硅， 二氧化硅波导层 14同二氧化 硅衬底层 13、 二氧化硅上包层 15的折射率差为 0. 5%〜2. 5%。 二氧化硅波导层 14包括靠近有源 光电子芯片的耦合区 16、 一般波导区 17和靠近光纤的耦合区 18。 一般波导区 17的波导宽度为 6Μπι 〜9Μπι; 靠近有源光电子芯片的耦合区 16波导宽度比一般波导区 17更窄， 为3 111〜7|¾; 靠 近光纤的耦合区 18波导宽度比一般波导区 17更宽， 为 8Μπ！〜 10Μπι。 二氧化硅衬底层 13的厚度 为 50Μπ！〜 ΙΟΟΟμιπ, 二氧化硅波导层 14的厚度为 3Μπ！〜 50Mm。
步骤 2: 二氧化硅上包层与倾斜端面的制作。 在二氧化硅波导层 14和预留区 20上方继续采 用等离子体增强化学气相沉积（PECVD ) 生长二氧化硅上包层 15， 然后进行高温热退火， 参看图 3b。 采用普通光刻保护二氧化硅波导层 14上部的二氧化硅上包层 15， 而在预留区 20上采用二 氧化硅刻蚀工艺刻蚀掉部分上包层 15， 刻蚀至裸露出二氧化硅衬底层 13为止， 保留刻蚀后二氧 化硅上包层 15上方残余的第三光刻胶层 21， 参看图 3c。 再采用端面抛光工艺， 在二氧化硅波导 层 14的两侧制作倾斜端面 19。 靠近光电子芯片耦合区 16和靠近光纤的耦合区 18外部端面 19 均为与竖直方向呈 5 ° 至 45 ° 的倾斜端面， 且该外部端面与波导出光或入光中心轴垂直。 二氧化 硅包层 15的厚度为 50μιπ 〜1000μιπ。
步骤 3: 制作水平对准凸台 6和垂直对准凸台 7。 在二氧化硅预留区 20上， 用第四光刻胶层 22保护上包层 15及其下层波导结构并定义二氧化硅对准凸台的位置与形状， 采用普通光刻和二 氧化硅刻蚀工艺， 刻蚀二氧化硅衬底层 13直至硅衬底 1的表面， 制作出二氧化硅垂直对准凸台 23和二氧化硅水平对准凸台 24， 参看图 3d。 二氧化硅水平对准凸台 24与二氧化硅垂直对准凸 台 23的位置与形状与 （一） 采用二氧化硅键合工艺制作二氧化硅波导元件 2中步骤 1描述的水 平对准凸台 6、 垂直对准凸台 7的位置与形状一致。 保留刻蚀后残余第四光刻胶层 22， 并改换硅 刻蚀工艺继续对硅衬底 1进行硅刻蚀， 刻蚀深度为 ΙθΜπ！〜 lOOMffl, 参看图 3e。 由于残余第四光刻 胶层 22的保护与自对准， 在二氧化硅垂直对准凸台 23与二氧化硅水平对准凸台 24的下部将形 成垂直对准凸台 7、 凸台水平对准 6， 该方法制作的二氧化硅垂直对准凸台 23与二氧化硅水平对 准凸台 24位置、 截面形状与垂直对准凸台 7、 凸台水平对准 6—致， 也同采用二氧化硅键合工 艺制作二氧化硅波导元件 2中步骤 1中描述的垂直对准凸台 7、 凸台水平对准 6的位置与截面形 状一致。 二氧化硅垂直对准凸台 23与二氧化硅水平对准凸台 24与垂直对准凸台 7、 凸台水平对 准 6的总高度为 lOMffl 〜100μιπ， 具体高度由二氧化硅波导层 14和有源光电子芯片 5的入光或出 光波导的相对于硅衬底 1表面的高度关系决定， 保证二氧化硅波导层 14和有源光电子芯片 5的 入光或出光波导高度平齐。 最后去除残余的第三光刻胶层 21与第四光刻胶层 22。
步骤二： 制作金属电极层 3。
在硅衬底 1表面， 用光刻胶保护二氧化硅波导区 14并定义金属电极图形， 利用水平对准凸 台 6同金属电极光刻版上的对准标记进行对准， 采用普通光刻、金属溅射和蒸发以及金属剥离工 艺， 在平台 8上制作金属电极层 3， 参看图 4a和 4b。 金属电极层 3厚度为 0. 2ΜΠ！〜 3Μπι， 为多层 金属结构， 如 Ti/Pt/Au层结构。 该金属电极层 3制作在硅平台 8上， 金属电极层 3的多层结构 需同硅衬底 1及悍料凸点 4有良好的接触。 该金属电极层 3为特殊结构的金属电极， 包括直流电 极区 25、 交流电极区 26、 地线电极区 27和对准图形电极区 28。 直流电极区 25和交流电极区 26 位于光电子芯片的直流电极 29及交流电极 30的正下方在直流电极区 25和交流电极区 26上制 作悍料凸点 4， 分别用于将直流和交流电信号加载到有源光电子芯片 5上， 直流电极区 25和交 流电极区 26均有延长电极， 延伸到平台 8上远离凸台方向的末端， 便于同芯片封装管壳间的金 丝引线互连。 地线电极区 27位于平台 8上远离硅凸台方向的末端， 用金丝引线同光电子芯片背 面电极连接。 对准图形电极区 28如前所述， 用于同水平对准凸台 6对准。
步骤三： 在金属电极层 3上制作悍料凸点 4， 将金属电极对准标记 28或硅水平对准凸台 6 同悍料凸点植球机的校准标记进行对准， 采用植球和回流工艺制作悍料凸点 4， 参看图 5。 悍料 凸点 4仅制作于金属电极层 3的直流电极区 25和交流电极区 26上个数由金属电极面积和悍料 凸点 4大小比例决定， 悍料凸点 4在植球和回流工艺过程中， 以及后续有源光电子芯片 5贴片过 程中， 均不应溢出金属电极层 3的直流电极区 25和交流电极区 26。
步骤四： 悍接有源光电子芯片 5。 有源光电子芯片 5为波导型的 III-V族激光器或探测器， 其正面有直流电极 29、 交流电极 30和对准标记 31， 中部有出光或入光波导 32， 背面有地线电 极 33， 正面电极下部即为正表面 34， 参看图 6a〜图 6c。 利用对准图形电极区 28或水平对准凸 台 6同有源光电子芯片 5上的对准标记 31进行对准， 采用热回流悍和倒装压悍的结合工艺， 将 有源光电子芯片 5的金属电极层 3制作在悍料凸点 4上， 参看图 7。 正面的直流电极 29和交流 电极 30同金属电极层 3的直流电极区 25和交流电极区 26悍料凸点 4的上部分别接触。 接触到 悍料凸点 4后， 将正面的对准标记同对准图形电极区 28对准标记或水平对准凸台 6进行对准， 采用热回流悍和倒装压悍的结合工艺， 将有源光电子芯片 5的正面直流电极 29和交流电极 30 同悍料凸点 4间形成合金并下压直至有源光电子芯片 5的正表面 34同硅垂直对准凸台 7接角 参看图 1。
步骤:五： 用金丝将有源光电子芯片 5的背面地电极 33与金属电极层 3上的地线电极区 27 连接起来， 如图 1所示。
以上所述实施例仅是为充分说明本发明而所举的较佳的实施例， 本发明的保护范围不限于 此。 本技术领域的技术人员在本发明基础上所作的等同替代或变换， 均在本发明的保护范围之 内。 本发明的保护范围以权利要求书为准。

Claims

权利要求书
1、一种硅上二氧化硅基的混合集成光电子芯片， 其特征在于： 包括硅衬底， 所述硅衬底表面具 有平台、 凸台和凹槽， 所述凹槽中设置有二氧化硅波导元件， 所述凸台凸出于平台表面， 所述 平台表面设置有不连续的金属电极层， 所述金属电极层的表面设置有悍料凸点， 所述的悍料凸 点和凸台上方设置有有源光电子芯片。
2、根据权利要求 1所述的硅上二氧化硅基的混合集成光电子芯片， 其特征在于： 二氧化硅波导 元件的纵向依次包括二氧化硅衬底层、 二氧化硅波导层和二氧化硅上包层； 所述的二氧化硅波 导层横向依次包括波导区、 靠近有源光电子芯片的耦合区和靠近光纤的耦合区； 靠近有源光电 子芯片的耦合区的波导宽度为 3 m〜7 m; 靠近光纤的耦合区的波导宽度为 6 m〜10 m。
3、根据权利要求 2所述的硅上二氧化硅基的混合集成光电子芯片， 其特征在于： 所述凸台包括 水平对准凸台与垂直对准凸台， 所述水平对准凸台与垂直对准凸台的高度相等， 均为 ΙθΜπ！ 〜 100Μπι。
4、根据权利要求 3所述的硅上二氧化硅基的混合集成光电子芯片， 其特征在于： 所述水平对准 凸台的个数与水平位置由有源光电子芯片上的对准标记、有源光电子芯片波导的相对位置决定， 所述垂直对准凸台的高度由二氧化硅波导元件的二氧化硅波导层的垂直位置决定， 所述垂直对 准凸台位于有源光电子芯片的中部。
5、根据权利要求 3所述的硅上二氧化硅基的混合集成光电子芯片， 其特征在于： 所述金属电极 层的厚度为 0. 2Μπ！〜 3μιπ， 所述金属电极层包括直流电极区、 交流电极区、 地线电极区和对准图 形电极区； 所述凸台处于直流电极区和交流电极区之间， 所述直流电极区和交流电极区上方制 作有悍料凸点， 通过悍料凸点与有源光电子芯片的直流电极、 交流电极接触； 所述有源光电子 芯片的正面对准标记与水平对准凸台或金属电极层的对准标记对准； 所述的有源光电子芯片的 背面电极与金属电极层的地线电极区连接。
6、根据权利要求 1所述的硅上二氧化硅基的混合集成光电子芯片， 其特征在于： 所述的二氧化 硅波导元件具有与竖直方向倾斜 5 ° 〜45 ° 的外部端面。
7、 一种硅上二氧化硅基的混合集成光电子芯片的制作方法， 其特征在于， 包括以下几个步骤: 步骤一： 制作硅衬底， 并在硅衬底的凹槽中制作二氧化硅波导元件；
步骤二： 在硅衬底上制作金属电极层； 步骤三： 在金属电极层的直流电极区和交流电极区上方制作悍料凸点；
步骤四： 在悍料凸点、 垂直对准凸台上方悍接有源光电子芯片。
8、根据权利要求 7所述的硅上二氧化硅基的混合集成光电子芯片的制作方法， 其特征在于，所 述的步骤一中制作二氧化硅波导元件采用二氧化硅热键合工艺或二氧化硅生长工艺。
9、根据权利要求 8所述的硅上二氧化硅基的混合集成光电子芯片的制作方法， 其特征在于， 当 采用二氧化硅热键合工艺制作二氧化硅波导元件时， 步骤一包括以下几个步骤：
步骤 1 : 硅衬底的表面制作凸台；
步骤 2 : 在硅衬底的凸台的一侧制作凹槽；
步骤 3 : 在凹槽的底部生长二氧化硅键合层， 将二氧化硅波导元件采用二氧化硅热键合工艺制 作到凹槽结构中， 使键合层熔入二氧化硅波导元件的二氧化硅衬底层中， 并使二氧化硅波导元 件具有与竖直方向倾斜 5 ° 〜45 ° 的外部端面。
10、 根据权利要求 8所述的硅上二氧化硅基的混合集成光电子芯片的制作方法， 其特征在于， 当采用二氧化硅生长工艺制作二氧化硅波导元件时， 步骤一包括以下几个步骤：
步骤 1 : 在硅衬底表面生长二氧化硅衬底层和二氧化硅波导层， 并将二氧化硅波导层刻蚀掉一 部分， 形成预留区；
步骤 2 : 在保留的二氧化硅波导层上方生长上包层；
步骤 3 : 在保留区刻蚀二氧化硅衬底层至硅衬底的表面， 形成凸台。
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