WO2014101642A1

WO2014101642A1 - Video playing apparatus and method

Info

Publication number: WO2014101642A1
Application number: PCT/CN2013/088624
Authority: WO
Inventors: 严卫健; 刘俊秀; 王雅君
Original assignee: 深圳艾科创新微电子有限公司
Priority date: 2012-12-28
Filing date: 2013-12-05
Publication date: 2014-07-03
Also published as: CN104782118A; CN104782118B; CN103916612A

Abstract

The present invention proposes a video playing apparatus and method. The apparatus comprises: a line buffer control unit, used to receive input first video data; a line buffer unit, used to buffer the first video data written by the line buffer control unit, where storage space of the line buffer unit is storage space of at least 2n lines; a first weighting unit, used to read the first video data in the line buffer unit, and perform first weighting processing on the first video data to acquire played second video data in the vertical direction; a point buffer unit, used to buffer the second video data written by the first weighting unit; a second weighting unit, used to read the second video data in the point buffer unit, and perform second weighting processing on the second video data to acquire played third video data in the horizontal direction; a locking unit, used to buffer the third video data written by the second weighting unit; and a clock generation unit, used to acquire an input clock of the first video data, send the input clock to the line buffer control unit for use as a write clock for the line buffer control unit, acquire a playing clock according to the input clock and a playing proportion, and send the playing clock to the line buffer unit, the point buffer unit, and the locking unit for use as a read/write clock for the line buffer unit, the point buffer unit, and the locking unit.

Description

Video zooming device and method

Technical field

The present invention belongs to the field of video processing technologies, and in particular, to a video scaling apparatus and method. Background technique

In the design of a conventional video zooming device, it includes a scaling of any ratio in the horizontal direction and the vertical direction. The easiest way to achieve scaling is to directly scale the pixels in the horizontal direction to reduce the length of the line, or to enlarge the length of the line by copying the pixels; to discard or copy the line data in the vertical direction to achieve scaling . This scaling process does not perform any filtering processing, so the video image may be severely distorted or even deformed, which is unacceptable in video processing.

Interpolation processing can solve the above problem of video image distortion. In the horizontal direction, the interpolation process performs weighting operation on consecutive pixels to obtain new pixel points. In the implementation, only a few consecutive pixels need to be stored. The interpolation process in the vertical direction performs weighting operations on corresponding pixels of consecutive rows in the vertical direction, which requires several rows of line buffers to store adjacent lines of video data. However, only the line buffer is not enough, because after storing a few lines of video data, a weighting operation is required, and the operation of the next line can be continued after the line is output. This has a problem for continuous video data streams, that is, the line buffer must wait for the operation of a line of video data to be output before accepting the video data input of the next line. However, the input is continuous. If the rate of the line buffer output is inconsistent with the input, the input data will be lost or staggered, resulting in distortion of the video image. Since the input rate of the video data stream is inconsistent with the display output rate, it is necessary to store the input video data first in the design. In the case that the output display video refresh rate is consistent with the input, that is, the field frequency is consistent, it is guaranteed that the entire field data is stored without losing data. A need to store hundreds of lines of video data, so that a large SDRAM (Synchronous Dynamic Random Access Memory) is required for storage, which takes up a large amount of chip area, resulting in a large increase in cost. Summary of the invention

The object of the present invention is to solve at least one of the above technical problems to some extent.

SUMMARY OF THE INVENTION Accordingly, a first object of the present invention is to provide a video scaling apparatus which uses at least 2n line buffer units of a storage space as a buffer and fault tolerance for video data, achieving excellent video processing effects and reducing costs.

To this end, a second object of the present invention is to propose a video scaling method.

To this end, a third object of the present invention is to propose a storage medium. In order to achieve the above object, a video scaling apparatus according to a first aspect of the present invention includes: a line buffer control unit, configured to receive input first video data; and a line buffer unit, configured to buffer the line buffer control unit to write The first video data, wherein a storage space of the line buffer unit is a storage space of at least 2 η rows, where η is a number of pixels required for each interpolation process in the scaling process, and each row of the storage space is a size of the storage space required for the first video data of each line; a first weighting unit, configured to read the first video data in the line buffer unit, and perform the first video data a first weighting process to obtain second video data that is scaled in a vertical direction; a dot buffer unit, configured to buffer the second video data written by the first weighting unit; and a second weighting unit, configured to read Decoding the second video data in the buffer unit, and performing second weighting processing on the second video data to obtain the third video number after being scaled in the horizontal direction a latch unit, configured to buffer the third video data written by the second weighting unit; and a clock generating unit, configured to acquire an input clock of the first video data, and send the input clock to The line buffer control unit acquires a scaling clock according to the write clock of the line buffer control unit, and obtains a scaling clock according to the input clock and the scaling ratio, and sends the scaling clock to the line buffer unit, the dot buffer unit, and the lock The memory unit serves as a read/write clock for the line buffer unit, the dot buffer unit, and the latch unit.

The video scaling apparatus according to the embodiment of the present invention uses a line buffer unit of at least 2n storage spaces as a buffer and fault tolerance of video data, and provides a configurable scaling clock in a proportionally adjustable manner, at an input clock, input video data, and a scaling clock. A dynamic balance is achieved between the output video data and the excellent video zoom processing effect. In addition, the SDRAM does not need to occupy a large amount of chip area, and the added amount is only much smaller than the chip occupied by the entire video data. The 2 η row buffer unit greatly reduces the cost of the entire chip, and at the same time enables real-time arbitrary scale video scaling.

In an embodiment of the present invention, the storage space of the line buffer unit is a storage space of 2n+1 rows. In an embodiment of the present invention, the clock generating unit is further configured to acquire an input clock of the first video data, acquire a first product of the input clock and a scaling ratio, and use the first product as The scaling clock; wherein, the scaling ratio = (the number of vertical lines of the third video data * the number of horizontal pixels of the third video data) / (the number of vertical lines of the first video data * The number of horizontal pixels of the first video data).

In an embodiment of the present invention, the method further includes: a correction unit, configured to monitor a read/write state of the row buffer unit, and perform correction when the read/write state is abnormal.

In an embodiment of the present invention, the method further includes: a timing unit, configured to generate a row read control signal according to the scaled clock, wherein the row read control signal has a total length of one cycle from the row a time required for reading a row of data according to the scaling ratio in the buffer unit, wherein if the low level interval/high level interval of the row read control signal is a blanking interval, the high level interval is A line of valid data is read from the line buffer unit according to the scaling ratio in the /low level interval. In an embodiment of the present invention, the correcting unit is further configured to perform correction according to one or more of the following rules: adjusting the timing unit to adjust a total length of one period of the row read control signal; Or adjusting the period/frequency of the scaled clock by adjusting the clock generating unit; or adjusting the scaling.

In an embodiment of the present invention, the adjusting the timing unit to adjust the total length of the line read control signal for one cycle is: adjusting a length of the blanking interval of the read control signal.

In an embodiment of the invention, the adjusting the scaling ratio is specifically: adjusting a scaling ratio in a vertical direction.

In an embodiment of the present invention, the correcting unit is specifically configured to perform correction by adjusting one or more of the following rules: if the read operation is too fast to catch up with the write operation, adjust the timing unit to The duration of the blanking interval corresponding level signal in the read control signal is increased by a first preset time period, and if the write operation is too fast to catch up with the read operation, adjusting the timing unit to read the line The duration of the blanking interval corresponding to the level signal in the control signal is decreased by a first preset time period; or if the read operation is too fast to catch up with the write operation, adjusting the clock generating unit to increase the period of the scaling clock a second preset time period / reducing the frequency of the zoom clock by a second preset value, if the write operation is too fast to catch up with the read operation, adjusting the clock generation unit to reduce the period of the zoom clock by a second Presetting a time period / increasing the frequency of the zoom clock by a second preset value; or if the read operation is too fast to catch up with the write operation, reducing the zoom ratio by a preset threshold to reduce Read from the line buffer unit step size data, if the write operation is too fast leading to catch up the read operation, then the zoom ratio increases to increase the predetermined threshold step size from the line buffer unit reads the data.

In an embodiment of the present invention, the method further includes: a field filtering unit, configured to filter the first video data input into the line buffer control unit.

In order to achieve the above object, the video scaling method of the second aspect of the present invention includes the following steps: S1: acquiring an input clock of the input first video data, and acquiring a scaling clock according to the input clock and the scaling ratio;

S2: determining whether the vertical scaling m in the vertical direction is greater than n, where n is the number of pixels required for each interpolation process in the scaling process; S3: if yes, further determining whether m is a non-integer; S31: No, the first video data of the n rows is written every time the data is written into the line buffer unit, and the first video data of the mn line is discarded, wherein the storage space of the line buffer unit is a storage space of at least 2 η rows, wherein a size of the storage space per row is a size of a storage space required for each row of the first video data; S32: If yes, storing the first video of each row After the data, discard the first video data of the Iml-n line, and accumulate the fractional part of mn to obtain the accumulated value, and when the accumulated value reaches 1, discard the first video data of the lml-n+1 line And clearing the accumulated number, and repeating the S32 every time the n-line of the first video data is stored; S4: If not, writing each time data is written to the line buffer unit The first video data of n lines; S5: pair n The first video data of the row is subjected to a first weighting process to obtain a scaled second view in the vertical direction Frequency data; S6: performing second weighting processing on the second video data to obtain third video data that is scaled in the horizontal direction; S7: outputting the third video data.

The video scaling method of the embodiment of the present invention uses a line buffer unit of at least 2n storage spaces as a buffer and fault tolerance of video data, and provides a configurable scaling clock in a proportionally adjustable manner, at an input clock, input video data, and a scaling clock. A dynamic balance is achieved between the output video data and the excellent video scaling effect.

In an embodiment of the present invention, the step S1 includes: acquiring a first product of the input clock and a scaling ratio, and using the first product as the scaling clock; wherein, the scaling ratio is The number of vertical lines of the third video data * the number of horizontal pixels of the third video data) I (the number of vertical lines of the first video data * the number of horizontal pixels of the first video data).

In one embodiment of the invention, the read data operations in steps S3 and S4 and the write data operations in S5 are performed synchronously for different row address spaces.

In an embodiment of the present invention, the method further includes the steps of: monitoring a read/write status of the line buffer unit, and performing correction when the read/write status is abnormal.

In an embodiment of the present invention, the method further includes the following steps: generating a row read control signal according to the scaled clock, wherein a total length of one period of the row read control signal is from the row buffer unit according to the scaling The time required to read a row of data in a ratio, wherein if the low-level interval/high-level interval of the row read control signal is a blanking interval, then according to the high-level interval/low-level interval The scaling reads a row of valid data from the line buffer unit.

In one embodiment of the invention, the correction is performed according to one or more of the following rules: adjusting the total length of one period of the row read control signal; or adjusting the period/frequency of the scaled clock; or adjusting the The vertical scaling.

In an embodiment of the invention, the adjusting the total length of the read control signal for one cycle is specifically: adjusting a length of the blanking interval of the read control signal.

In an embodiment of the present invention, the correcting according to one or more of the following rules specifically includes: if the read operation is too fast to catch up with the write operation, then the blanking interval in the row read control signal The duration of the corresponding level signal is increased by the first preset time period, and if the write operation is too fast to catch up with the read operation, the duration of the blanking interval corresponding level signal in the line read control signal is decreased. a preset time period; or if the read operation is too fast to catch up with the write operation, increasing the period of the zoom clock by a second preset time period / decreasing the frequency of the zoom clock by a second preset value, if If the write operation is too fast to catch up with the read operation, then the zoom clock will be Decreasing the second preset time period by // increasing the frequency of the zoom clock by a second preset value; or if the read operation is too fast to catch up with the write operation, reducing the zoom ratio by a preset threshold to reduce the Describe the step size of the data read by the cache unit. If the write operation is too fast to catch up with the read operation, the scaling is increased by a preset threshold to increase the step size of reading data from the line buffer unit.

In an embodiment of the present invention, before step S1, the method further comprises: performing vertical filtering on the first video data.

In order to achieve the above object, a storage medium according to an embodiment of the third aspect of the present invention is for storing an application for performing a video scaling method according to an embodiment of the second aspect of the present invention.

The additional aspects and advantages of the invention will be set forth in part in the description which follows. DRAWINGS

The above and/or additional aspects and advantages of the present invention will become apparent and readily understood from

1 is a schematic diagram of a prior art video zooming apparatus;

2 is a structural block diagram of a video scaling apparatus according to an embodiment of the present invention;

3 is a schematic diagram of interpolation points in a bicubic interpolation algorithm used in an embodiment of the present invention;

4 is a schematic diagram of an interpolation step size in a bicubic interpolation algorithm used in an embodiment of the present invention;

FIG. 5 is a schematic diagram of image size changes before and after scaling of a video according to an embodiment of the present invention; FIG.

6 is a schematic structural diagram of the first weighting unit 104 and/or the second weighting unit 107;

FIG. 7 is a structural block diagram of a video zooming apparatus according to another embodiment of the present invention; FIG.

FIG. 8 is a structural block diagram of a video zooming apparatus according to still another embodiment of the present invention; FIG.

FIG. 9 is a flowchart of a video zooming method according to an embodiment of the present invention. detailed description

The embodiments of the present invention are described in detail below, and the examples of the embodiments are illustrated in the drawings, wherein the same or similar reference numerals are used to refer to the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the drawings are intended to be illustrative of the invention and are not to be construed as limiting.

In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present invention, it should be noted that the terms "connected" and "connected" should be understood broadly, and may be mechanically connected or electrically connected, for example, unless otherwise specifically defined and defined. Connected, they can also be connected indirectly through an intermediary. For the field of general The specific meaning of the above terms in the present invention can be understood by a person skilled in the art. Further, in the description of the present invention, "multiple" means two or more unless otherwise stated.

Any process or method description in the flowcharts or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a particular logical function or process. And the scope of the preferred embodiments of the invention includes additional implementations, in which the functions may be performed in a substantially simultaneous manner or in an opposite order depending on the functions involved, in the order shown or discussed. These and other aspects of the embodiments of the present invention will be apparent from the following description and appended claims. In the description and drawings, specific embodiments of the embodiments of the invention are disclosed This limit. Rather, the invention is to cover all modifications, modifications and equivalents within the spirit and scope of the appended claims.

In order to solve the current video scaling process, a large SDRAM is required to store video data, which leads to a large amount of chip area, and thus the cost is greatly increased. The storage structure of the video data needs to be simplified.

1 is a schematic diagram of a prior art video zooming device. As shown in FIG. 1, the prior art video scaling apparatus includes: a two-line FIFO (First Input First Output) buffer 1-1, six line buffers (Linel to Line6) 1-2, shifting Shift register 1-3 and phase locked loop (PLL, Phase Locked Loop) l-4. The buffer 1-1 and the six line buffers 1-2 of the two-line FIFO buffer the video data input in real time, and cooperate with the configurable zoom clock outputted by the phase locked loop 1-4 to complete the video scaling. Specifically, the input video data is input to the six line buffers 1-2 through the buffer 1-1 of the FIFO, and is input to the shift registers 1-3 through the weighting processing in the vertical direction, and is horizontally oriented. The weighting process on the output outputs the final scaled video data scaler output. Where clk_video represents the input clock, clk_scale represents the scaling clock, and phase-locked loops 1-4 are used to output a configurable scaling clock clk_scale based on the input clock clk_video.

However, the above method has the following problems: Due to a total of six line buffers, the processing effect is not good enough to meet the real-time requirements. For example, if double legislative interpolation is used, four lines of video data are required for the scaling operation. After processing one line of video data output, at most two lines of buffered data are ready, so the real-time requirements of the video cannot be met.

To this end, embodiments of the present invention propose a video scaling apparatus and method. The video scaling device uses multiple buffers to buffer real-time input video data. The details are described below with reference to the drawings.

FIG. 2 is a structural block diagram of a video scaling apparatus according to an embodiment of the present invention. As shown in FIG. 2, the video scaling device includes: a line buffer control unit 102, a line buffer unit 103, a first weighting unit 104, a dot buffer unit 106, a second weighting unit 107, a latch unit 108, and a clock generating unit 105.

Specifically, the line buffer control unit 102 is configured to receive the input first video data. For example, input means lose The first video data entered.

The line buffer unit 103 is configured to cache the first video data written by the line buffer control unit 102, wherein the storage space of the line buffer unit 103 is a storage space of at least 2 η rows, where η is the time of each interpolation processing in the scaling process. The number of pixels required, the size of each line of storage is the size of the storage space required for the first video data per line.

For example, if the binomial method is used for interpolation, an unknown pixel point is calculated by interpolation of 4 known pixel points, as shown in FIG. 3, taking the scaling ratio of 5:4 as an example, assuming that the position of the pixel to be interpolated is at 0. Point, the pixel to be interpolated is calculated by interpolation of 4 pixels around it. The position of 0 o'clock is always between Ρ2, Ρ3 o'clock, and 0 o'clock can coincide with Ρ2 o'clock. The value of the inserted zero point is determined by the following formula (1):

0 = Pl*hl + P2*h2 + P3*h3 + P4*h4 ( 1 )

Among them, P1 ~ P4 are the original pixel points, hi ~! 4 is the corresponding coefficient. Here, the coefficients are determined by a lookup table. Each corresponding coefficient corresponds to a 256 X 8 bit table, so a total of 4 X 256 X 8 bit memory cells are needed to store the coefficients. The zoom ratio is the step size of the double-cubic interpolation. pace: pace =5/4 =1.25 ο The unit distance between the original pixel points is 1, and the relationship between the original pixel point and the newly interpolated new pixel point is shown in Fig. 4.

In one embodiment of the present invention, the storage space of the line buffer unit 103 is a storage space of 2n+1 rows. In one embodiment of the present invention, if the double-pair method is used for interpolation, η is equal to 4, and the storage space of the line buffer unit 103 is at least 8 lines of storage space. Preferably, in another embodiment of the present invention, the storage space of the line buffer unit 103 is 9 lines of storage space.

Specifically, the operation of the line buffer unit 103 of the embodiment of the present invention is illustrated by taking a 9 line buffer as an example. The line buffer unit 103 includes 9 line buffers, that is, a storage space (Linel to Line9) for sequentially storing input. Video data, while four of the nine line buffers provide data for bicubic interpolation operations in the field direction (ie, vertical direction). According to the timing of outputting video data, when video data output is required, four line buffers are inevitably used for output. At this time, another five line buffers can be used to continue storing the input video data. The line frequency of the input video data and the line frequency of the output video data determine the input and output timing of the 9 line buffers. In one embodiment of the present invention, taking the magnification in the vertical direction as an example, the time for outputting one line of video data is twice that of inputting one line of video data, so that the output of one line of video data is inevitably already stored in 2 Line video data to 2 line buffers, as the next line of video data output, you can use the next 4 line buffers to buffer the input video data, including 2 lines of buffer that have stored video data Device. It should be understood that which four line buffers are used depends on the step size of the field direction (i.e., scaling), which will be described in detail in subsequent embodiments.

It should also be understood that the above embodiment is described by using a double-brain method interpolation example. In the specific implementation process, other interpolation algorithms may also be used, and the interpolation algorithm is not limited herein.

In addition, the line buffer control unit 102 provides a read/write start signal and a read/write clock by the line buffer unit 103. (i.e., input clock) The cache control of the line buffer unit 103 is implemented.

To ensure that the line buffer unit 103 can perform read and write processing at the same time, and perform scaling processing at an arbitrary scale, the storage space of the line buffer unit 103 is at least 2 η rows. It should be understood that the storage space of the line buffer unit 103 is not limited to 2 η rows. For example, it can be 2η+1 rows, 2η+2 rows. In one embodiment of the present invention, the size of the storage space of the row buffer unit 103 needs to comprehensively consider the occupied area and meet the requirements of any scaling. When the space is larger, the timing requirement is lower because the remaining line buffer is available. The device is used for fault-tolerant processing to ensure a certain error tolerance range, making the input and output easier to balance. At the same time, in the video data format, the line blanking area and the field blanking area do not transmit effective display data, and the mechanism of adjustable output blanking area length is added, so that the balance adjustment is more flexible, but of course, when the storage space When it is larger than 2η, the occupied chip area is larger.

The first weighting unit 104 is configured to read the first video data in the line buffer unit 103, and perform a first weighting process on the first video data to obtain the second video data that is scaled in the vertical direction.

The dot buffer unit 106 is configured to buffer the second video data written by the first weighting unit.

The second weighting unit 107 is configured to read the second video data in the point buffer unit 106, and perform a second weighting process on the second video data to obtain the third video data that is scaled in the horizontal direction.

The latch unit 108 is configured to buffer the third video data (output) written by the second weighting unit 107.

The clock generating unit 105 is configured to acquire an input clock of the first video data, and send the input clock to the line buffer control unit 102 as a write clock of the line buffer control unit 102, and obtain a scaling clock according to the input clock and the scaling ratio, and The scaling clock is sent to the line buffer unit 103, the dot buffer unit 106, and the latch unit 108 as the read/write clocks of the line buffer unit 103, the dot buffer unit 106, and the latch unit 108.

In an embodiment of the present invention, the clock generating unit 105 is further configured to acquire an input clock of the first video data, and obtain a first product of the input clock and the scaling, and use the first product as a scaling clock; wherein, the scaling ratio = (the number of vertical lines of the third video data * the number of horizontal pixels of the third video data) I (the number of vertical lines of the first video data * the number of horizontal pixels of the first video data). The third video data is video data (output) output by the video scaling device. More specifically, in one embodiment of the present invention, the clock generating unit 105 includes two multipliers, or a three-input multiplier, for example, realizing the input clock clk_video with horizontal scaling in the horizontal direction and vertical scaling in the vertical direction. Multiplying the ratios yields the scaling clock clk_ _SCa le, as shown in equation (2):

" , Hpixel'Vpixel' „ , _λ

Elk _ scale = x x elk _ video ( 2 )

Hpixel Vpixel

Wherein, Hpixel represents the horizontal pixel number of the first video data (ie, the input video data), Vpixel represents the vertical line number of the first video data (ie, the input video data); Hpixel ' represents the third video data (ie, the output video) Data) The number of horizontal pixels, Vpixel ' represents the number of vertical lines of the third video data (ie, the output video data), and the ratio of Hpixel to Hpixel ' is the horizontal scaling in the horizontal direction, Vpixel and Vpixel ' The ratio is the vertical scaling in the vertical direction, and the product of the horizontal scaling and the vertical scaling is the scaling.

Further, the clock generating unit further proportionally adjustable by a phase-locked loop, the output clock can be configured to achieve, the structure of the input clock clk_ _V ide ₀ and scaling may be configured to obtain the proper scaling clock clk_scale 105 ₀

As shown in the schematic diagram of FIG. 5, the input video data is outputted by the video scaling apparatus according to the embodiment of the present invention. Of course, FIG. 5 is only a reduced schematic diagram, and the output video data may be any ratio. Zoom in or out on video data. According to formula (2), clk_scale is larger than clk_video when the output video resolution (Hpixel' X Vpixel' ) is greater than the input video resolution (Hpixel x Vpixel), and clk_scale is smaller than clk_video when the output video resolution is less than the input video resolution. .

In addition, in an embodiment of the present invention, the clock generating unit 105 can also implement a configurable scaling clock through a proportionally adjustable phase-locked loop. The structure is fixed according to the input clock frequency and the input signal resolution. And the output resolution should be a known fixed value corresponding to the display requirement. The frequency of the output clock can be calculated proportionally (that is, the frequency of the scaled clock). Due to the configurability of the output clock, an appropriate clock frequency value can be obtained. This allows the input and output rates to reach a certain balance to some extent.

A schematic diagram of the structure of the first weighting unit 104 and/or the second weighting unit 107 is shown in FIG. As shown in FIG. 6, in an embodiment of the present invention, the first weighting unit 104 and/or the second weighting unit 107 includes a weighting coefficient subunit, n multipliers, and an adder, and the weighting coefficient subunit outputs n. The coefficients Coefl to Coefn are corresponding to the input n video data P1 to Pn, and are input to the corresponding n multipliers, and the obtained n products are input to the adder to obtain weighted output data Pout, where n is a natural number , determined by the scaling algorithm, for example, when using double cube for interpolation, then n=4, the specific weighting formula is as in equation (3):

Pout = Pl*Coefl + P2*Coef2 + P3*Coef3 + P4*Coef4 ( 3 ) In addition, if the values of n are different, different coefficients are stored in the weighting coefficient subunit according to specific needs, and the weighting coefficient subunit may be a lookup table. The storage unit is not specifically limited herein.

FIG. 7 is a structural block diagram of a video scaling apparatus according to another embodiment of the present invention. As shown in FIG. 7, the video scaling apparatus includes: a line buffer control unit 102, a line buffer unit 103, a first weighting unit 104, a dot buffer unit 106, The second weighting unit 107, the latch unit 108, the clock generating unit 105, the correcting unit 109, and the timing unit 110. Specifically, the correcting unit 109 is configured to monitor the read/write status of the line buffer unit 103, and perform correction when the read/write status is abnormal.

In one embodiment of the present invention, the storage space of 2n+1 rows constitutes a storage ring, and the row buffer unit 103 determines the number of rows of the storage space to be read at a time according to the first weighting process, and reads the storage space according to the scaling ratio and the last time. The first line position determines the first line position of the next read storage space. For example, if the first weighting process is a double-legislation interpolation algorithm, the number of rows of the storage space at one time is 4 rows; for example, if the scaling ratio is 5/4 or 1.25, if the storage space is read first The line position is the first line, and the video data of the first line to the fourth line is read. At this time, it can be determined that the first line position of the next read storage space is the second line. It should be understood that the example is only for convenience. The line buffer unit 103 determines the read/write process according to the scaling ratio, and is not intended to limit the scope of protection of the embodiments of the present invention.

However, due to the differences and errors of various video sources, there will be a small deviation. For example, if the computer with the same output resolution is 800x600, there will be an error between the computers of different brands, that is, the total number of points per line and the total number of lines per field may have a delta error. However, since the detected resolution is the same, the theoretical Hpixel' and Vpixel' are set, and thus the image is disordered, so that the read/write of the line buffer unit 103 is abnormal. Here, the set point error is Δ _Χ , the line error is A y , the actual total point number is Hpixel' + Δ χ, and the actual vertical total line number is Vpixel' + A y. In the embodiment of the present invention, the correction unit 109 can achieve the correct effect by adjusting Hpixel' without detecting Δ χ, A y .

For example, the correcting unit 109 monitors the read and write status of the nine line buffers in one field. When which line buffer reads and writes at the same time, it indicates that read and write confusion has occurred, and the configured Hpixel 'has to be corresponding. Adjustment. Only knowing whether reading too fast or writing too fast can make adjustments in the corresponding direction. Each of the 9 line buffers in the output timing is read to obtain 1 line of output, and the data of which 4 lines of buffer is read is determined according to the accumulation of the scaling (step size). Since the starting position of each field is the same, that is, when reading the 4 line buffers of 1, 2, 3, 4, the 7th line buffer is written, and when the read and write operations occur simultaneously, it is a write operation. Catch up with the read operation or the read operation to catch up with the write operation to determine whether it is reading too fast or writing too fast.

In an embodiment of the present invention, the timing unit 110 is configured to generate a row read control signal according to the scaling clock, and the total length of the row read control signal for one cycle is required to read a row of data from the row buffer unit 103 according to the scaling ratio. Time, wherein, if the low-level interval/high-level interval of the row read control signal is a blanking interval, a row is validly read from the row buffer unit according to the scaling ratio in the high-level interval/low-level interval. data.

Specifically, in an embodiment of the present invention, the correcting unit 109 is further configured to correct the read/write abnormality according to one or more of the following rules:

(1) The total length of one cycle of the control signal is read by adjusting the timing unit 110 to adjust the line. In one embodiment of the present invention, the adjustment of the timing unit 110 to adjust the total length of one cycle of the row read control signal is specifically: adjusting the length of the blanking interval of the read control signal.

Specifically, in an embodiment of the present invention, if the read operation is too fast to catch up with the write operation, the timing unit 110 is adjusted to increase the duration of the blanking interval corresponding level signal in the row read control signal by the first pre- The time period is set. If the write operation is too fast to catch up with the read operation, the adjustment timing unit 110 reduces the duration of the blanking interval corresponding level signal in the line read control signal by the first preset time period.

More specifically, the storage space constitutes a storage ring, and the read and write operations are simultaneously present in the storage ring. If the read operation and the write operation are balanced, there is no conflict between the read and write operations. If the read operation is too fast to catch up with the write operation, a read-write conflict occurs, that is, the read of the first video data from the line buffer unit 103 for processing to output the third video data is too fast to catch up. The write operation of the incoming buffer unit 103, therefore, the read data is too fast, so that the cache unit corresponding to the read data is the same as the cache unit corresponding to the write data, or the cache unit corresponding to the read data corresponds to the cache that has not yet written data. Unit, at this time, it is necessary to adjust the factors affecting the reading speed to match the reading speed and the writing speed to maintain the balance of the read and write operations, and increase the duration of the corresponding level signal of the blanking interval in the line read control signal by the first pre- Set the time period to reduce the reading speed; similarly, if the write operation is too fast to catch up with the read operation, the read/write conflict will also occur, and the duration of the blanking interval corresponding level signal in the control signal will be read. Increasing the first preset time period reduces the time required to read a line, thereby speeding up the reading speed.

The first preset time period may be a user setting or a default setting, and by such repeated adjustment, the output timing and the input timing may be balanced.

(2) The period/frequency of the scaling clock is adjusted by adjusting the clock generating unit 105.

Specifically, in an embodiment of the present invention, if the read operation is too fast to catch up with the write operation, the adjustment clock generation unit 105 increases the period of the scaling clock by a second predetermined period of time / reduces the frequency of the scaling clock. The second preset value, if the write operation is too fast to catch up with the read operation, the adjustment clock generation unit 105 decreases the period of the zoom clock by a second preset time period / increases the frequency of the zoom clock by a second preset value.

The second preset time period can be set by the user or set by default. Through such repeated adjustments, the output timing and the input timing can be balanced.

(3) Adjust the zoom ratio.

In an embodiment of the invention, the scaling is specifically: adjusting the scaling of the vertical direction, that is, adjusting the scaling of the field direction.

Specifically, in one embodiment of the present invention, if the read operation is too fast to catch up with the write operation, the scaling is decreased by the preset threshold to reduce the step size of reading data from the line buffer unit 103, if the write operation is too fast As a result of catching up with the read operation, the scaling is increased by a preset threshold to increase the step size of reading data from the line buffer unit 103, thereby speeding up the read operation. More specifically, if the scaling in the vertical direction is larger than the number of pixels required for each interpolation processing in the scaling processing, the first video data of a part of the number of lines must be discarded each time data is written to the line buffer unit 103. The number of rows to be discarded is the difference between the number of pixels and the scaling in the vertical direction (as described in the method embodiment below). Therefore, the balance between the output timing and the input timing can be achieved by adjusting the scaling.

Thereby, the correcting unit 109 adjusts the read/write operation until the simultaneous read/write operation abnormality does not occur. At this point, the automatic calibration is completed.

The video zooming device of the embodiment of the invention has an automatic correction function, and when the input video data format (the number of lines or points) is slightly deviated from the standard format, it can still be correctly corrected automatically.

FIG. 8 is a structural block diagram of a video scaling apparatus according to still another embodiment of the present invention. As shown in FIG. 8, the video scaling apparatus includes: a field filtering unit 101, a line buffer control unit 102, a line buffer unit 103, a first weighting unit 104, a dot buffer unit 106, a second weighting unit 107, a latch unit 108, and a clock. The generating unit 105, the correcting unit 109, and the timing unit 110.

Specifically, the field filtering unit 101 is configured to filter the first video data in the input line buffer control unit 102.

In the video zooming apparatus of the embodiment of the present invention, after the field filtering unit performs the buffering and scaling processing of the field direction, the distortion of the video image is reduced, and a better zooming effect is obtained, in particular, the reduction ratio of the field direction (vertical direction) is greater than n. time.

In order to implement the above embodiments, the present invention also proposes a video scaling method.

FIG. 9 is a flowchart of a video zooming method according to an embodiment of the present invention.

As shown in Figure 9, the video scaling method includes the following steps:

S101: Acquire an input clock of the input first video data, and obtain a zoom clock according to an input clock and a scaling ratio.

Specifically, in an embodiment of the present invention, S101 specifically includes: acquiring a first product of an input clock and a scaling ratio, and using the first product as the scaling clock; wherein, the scaling ratio = (the vertical of the third video data) Number of rows * horizontal pixel number of the third video data) I (the number of vertical lines of the first video data * the number of horizontal pixels of the first video data), wherein the third video data (ie, the output video data will be implemented later) The ratio of the number of vertical lines of the first video data to the number of vertical lines of the first video data is a vertical scaling ratio, and the ratio of the horizontal pixel number of the third video data to the horizontal pixel number of the first video data is a horizontal scaling. Specifically, the calculation process can refer to the formula (2) described in the above device embodiment.

S102: Determine whether the vertical scaling ratio m in the vertical direction is greater than n, where n is the number of pixels required for each interpolation process in the scaling process. Wherein, the first scaling ratio m is calculated as shown in the following formula (3),

Vpixel' , ,

m =— (3 )

Vpixel S103: If yes, further determine whether m is a non-integer.

S1031: If it is an integer, the first video data of n rows is written every time data is written into the row buffer unit, and the first video data of the mn row is discarded, wherein the storage space of the row buffer unit is at least 2η The storage space of the row, wherein the size of each row of storage space is the size of the storage space required for the first video data of each row.

In one embodiment of the invention, the storage space of the row buffer unit is 2n+1 rows of storage space.

S1032: If it is a non-integer, after storing the first video data of the η line, discard the first video data of the Iml-n line, and accumulate the fractional part of mn to obtain the accumulated value, and when the accumulated value reaches 1, discard the lml The first video data of the -n+1 line, and the accumulated number is cleared, and S1032 is repeatedly executed every time the first video data of n lines is stored.

Among them, Iml means rounding up m.

S104: If no, the first video data of n lines is written each time data is written to the line buffer unit. S105: Perform first weighting processing on the first video data of the n rows to obtain the second video data that is scaled in the vertical direction.

S106: Perform second weighting processing on the second video data to obtain third video data that is scaled in the horizontal direction.

S107: Output third video data.

In one embodiment of the invention, the read data operations in steps S103 and S104 and the write data operations in S105 are synchronized for different row address spaces.

In an embodiment of the present invention, the method further includes: (not shown): monitoring the read/write status of the line buffer unit, and performing correction when the read/write status is abnormal.

In an embodiment of the present invention, the storage space of 2n+1 rows constitutes a storage ring, and the row buffer unit determines the number of rows of the storage space to be read at a time according to the first weighting process, and according to the scaling ratio and the last reading of the storage space. The first line position determines the first line position of the next read storage space. For example, if the first weighting process is a double-legislation interpolation algorithm, the number of rows of the storage space at one time is 4 rows; for example, if the scaling ratio is 5/4 or 1.25, if the storage space is read first The line position is the first line, and the video data of the first line to the fourth line is read. At this time, it can be determined that the first line position of the next read storage space is the second line. It should be understood that the example is only for convenience. The line buffer unit determines the read/write process according to the scaling ratio, and is not intended to limit the scope of protection of the embodiments of the present invention.

In an embodiment of the present invention, the method further includes the steps of: generating a row read control signal according to the scaling clock, The total length of one cycle of the row read control signal is the time required to read one row of data from the row buffer unit according to the scaling ratio, wherein if the low level interval/high level interval of the row read control signal is the blanking interval , a line of valid data is read from the line buffer unit according to the scaling ratio in the high level interval/low level interval.

Specifically, in one embodiment of the invention, the read and write anomalies are corrected in accordance with one or more of the following rules:

(1) Adjust the total length of one cycle of the line read control signal.

In one embodiment of the invention, the adjustment of the total length of the line read control signal for one cycle is specifically: adjusting the length of the blanking interval of the read control signal.

Specifically, in an embodiment of the present invention, if the read operation is too fast to catch up with the write operation, the duration of the blanking interval corresponding level signal in the row read control signal is increased by the first preset time period, if If the write operation is too fast to catch up with the read operation, the duration of the blanking interval corresponding level signal in the line read control signal is decreased by the first preset time period.

More specifically, the storage space constitutes a storage ring, and the read and write operations are simultaneously present in the storage ring. If the read operation and the write operation are balanced, there is no conflict between the read and write operations. If the read operation is too fast to catch up with the write operation, a read-write conflict occurs, that is, the read of the first video data from the line buffer unit for processing to output the third video data is too fast, causing the write to catch up. The write operation of the row buffer unit, therefore, the read data is too fast, so that the cache unit corresponding to the read data is the same as the cache unit corresponding to the write data, or the cache unit corresponding to the read data corresponds to the cache unit that has not yet written the data. At this time, it is necessary to adjust the factors affecting the reading speed to match the reading speed and the writing speed to maintain the balance of the read and write operations, and increase the duration of the blanking interval corresponding level signal in the line read control signal by the first preset time. The segment can reduce the reading speed; similarly, if the write operation is too fast to catch up with the read operation, the read/write conflict will also occur, and the duration of the corresponding level signal of the blanking interval in the line read control signal is increased. A preset period of time reduces the time required to read a line, thereby speeding up the reading.

( 2) Adjust the period/frequency of the zoom clock.

Specifically, in an embodiment of the present invention, in an embodiment of the present invention, if the read operation is too fast to catch up with the write operation, the period of the zoom clock is increased by the second preset time period/the clock will be scaled The frequency is decreased by the second preset value, and if the write operation is too fast to catch up with the read operation, the period of the zoom clock is decreased by the second preset time period / the frequency of the zoom clock is increased by the second preset value.

(3) Adjust the zoom ratio. In an embodiment of the invention, the scaling is specifically: adjusting the scaling of the vertical direction, that is, adjusting the scaling of the field direction.

Specifically, in an embodiment of the present invention, if the read operation is too fast to catch up with the write operation, the zoom ratio is decreased by a preset threshold to reduce the step size of reading data from the line buffer unit, if the write operation is too fast To catch up with the read operation, the scaling is increased by a preset threshold to increase the step size of reading data from the line buffer unit, thereby speeding up the read operation.

More specifically, if the scaling in the vertical direction is larger than the number of pixels required for each interpolation processing in the scaling process, the first video data of a part of the number of lines must be discarded each time data is written to the line buffer unit, The number of rows to be discarded is the difference between the number of pixels and the vertical scaling. Therefore, the balance between the output timing and the input timing can be achieved by adjusting the scaling.

Therefore, the read/write operation can be adjusted until the simultaneous read/write operation is abnormal, and the automatic correction function can be realized. When the input video data format (the number of lines or the number of points) is slightly deviated from the standard format, the automatic correction can still be performed automatically. Corrected it back.

In an embodiment of the present invention, before the step S1, (not shown) is further included: the first video data is filtered in the vertical direction.

Therefore, the buffering and scaling processing in the field direction after filtering will reduce the distortion of the video image and obtain a better scaling effect, especially when the reduction ratio of the field direction (vertical direction) is larger than n.

In order to implement the above embodiments, the present invention further provides a storage medium for storing an application, and the application is used in the video scaling method according to any of the embodiments of the present invention.

Any process or method description in the flowcharts or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a particular logical function or process. And the scope of the preferred embodiments of the invention includes additional implementations, in which the functions may be performed in a substantially simultaneous manner or in an opposite order depending on the functions involved, in the order shown or discussed. It will be understood by those skilled in the art to which the embodiments of the present invention pertain.

The logic and/or steps represented in the flowchart or otherwise described herein, for example, may be considered as an ordered list of executable instructions for implementing logical functions, and may be embodied in any computer readable medium, Used in conjunction with, or in conjunction with, an instruction execution system, apparatus, or device (eg, a computer-based system, a system including a processor, or other system that can fetch instructions and execute instructions from an instruction execution system, apparatus, or device) Or use with equipment. For the purposes of this specification, a "computer-readable medium" can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by the instruction execution system, apparatus, or device, or in conjunction with the instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer readable media include the following: electrical connections (electronic devices) having one or more wires, portable computer disk cartridges (magnetic devices), Random Access Memory (RAM), Read Only Memory (ROM), Erasable Editable Read Only Memory (EPROM or Flash Memory), fiber optic devices, and Portable Optical Disk Read Only Memory (CDROM). Furthermore, the computer readable medium may even be a paper or other suitable medium on which the program can be printed, as it may be optically scanned, for example by paper or other medium, followed by editing, interpretation or, if appropriate, other suitable The method proceeds to obtain the program electronically and then store it in computer memory.

It should be understood that portions of the invention may be implemented in hardware, software, firmware or a combination thereof. In the above-described embodiments, multiple steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented with any one or combination of the following techniques well known in the art: having logic gates for implementing logic functions on data signals Discrete logic circuits, application specific integrated circuits with suitable combinational logic gates, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

One of ordinary skill in the art can understand that all or part of the steps carried by the method of implementing the above embodiments can be completed by a program to instruct related hardware, and the program can be stored in a computer readable storage medium. When executed, one or a combination of the steps of the method embodiments is included.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. The integrated modules, if implemented in the form of software functional modules and sold or used as stand-alone products, may also be stored in a computer readable storage medium.

The above-mentioned storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means specific features described in connection with the embodiment or example. A structure, material or feature is included in at least one embodiment or example of the invention. In the present specification, the schematic representation of the above terms does not necessarily mean the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.

While the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art The scope of the invention is defined by the appended claims and their equivalents.

Claims

claims

1. A video zoom device, characterized in that it includes:

A line cache control unit, configured to receive the input first video data;

A line cache unit, used to cache the first video data written by the line cache control unit, wherein the storage space of the line cache unit is at least 2n lines of storage space, where n is each time in the scaling process The number of pixels required for interpolation processing, and the size of the storage space in each row is the size of the storage space required for the first video data in each row;

A first weighting unit configured to read the first video data in the line cache unit and perform a first weighting process on the first video data to obtain the second video data scaled in the vertical direction;

A point cache unit configured to cache the second video data written by the first weighting unit;

A second weighting unit, configured to read the second video data in the point buffer unit and perform a second weighting process on the second video data to obtain the third video data after scaling in the horizontal direction;

a latch unit for buffering the third video data written by the second weighting unit; and a clock generation unit for obtaining the input clock of the first video data and sending the input clock to the The line cache control unit uses the write clock as the line cache control unit, obtains the scaling clock according to the input clock and scaling ratio, and sends the scaling clock to the line cache unit, point cache unit and latch The unit serves as the read and write clock for the line cache unit, point cache unit and latch unit.

2. The video scaling device according to claim 1, wherein the storage space of the line cache unit is a storage space of 2n+1 lines.

3. The video scaling device according to claim 2, wherein the clock generation unit is further configured to obtain the input clock of the first video data, and obtain the first product of the input clock and the scaling ratio, and use the first product as the scaling clock;

Wherein, the scaling ratio = (number of vertical lines of the third video data * number of horizontal pixels of the third video data) / (number of vertical lines of the first video data * number of horizontal pixels of the first video data) number of horizontal pixels).

4. The video scaling device according to claim 3, further comprising:

A correction unit, the correction unit is used to monitor the read and write status of the line cache unit, and perform correction when the read and write status is abnormal.

5. The video scaling device according to claim 4, further comprising:

a timing unit, the timing unit is used to generate a row read control signal according to the scaling clock, the total length of one cycle of the row reading control signal is to read one row of data from the row buffer unit according to the scaling ratio The required time, wherein, if the low level interval/high level interval of the row read control signal is the blanking interval, Then, within the high-level interval/low-level interval, one line of valid data is read from the line cache unit according to the scaling ratio.

6. The video scaling device according to claim 5, wherein the correction unit is further configured to perform correction according to one or more of the following rules:

By adjusting the timing unit to adjust the total length of one cycle of the row read control signal; or by adjusting the clock generation unit to adjust the cycle/frequency of the scaling clock; or

Adjust the scaling.

7. The video scaling device according to claim 6, wherein the adjustment of the timing unit to adjust the total length of one cycle of the read control signal is specifically: adjusting the amplitude of the read control signal. The length of the hidden interval.

8. The video scaling device according to claim 6, wherein the adjusting the scaling ratio specifically includes: adjusting the scaling ratio in the vertical direction.

9. The video scaling device according to claim 7 or 8, characterized in that the correction unit is specifically configured to perform correction by adjusting one or more of the following rules:

If the read operation is too fast and causes the write operation to be caught up, the timing unit is adjusted to increase the duration of the level signal corresponding to the blanking interval in the row read control signal by a first preset time period. If the write operation If the read operation is caught up too quickly, the timing unit is adjusted to reduce the duration of the level signal corresponding to the blanking interval in the row read control signal by a first preset time period; or

If the read operation is too fast and causes the write operation to be caught up, the clock generation unit is adjusted to increase the period of the scaled clock by a second preset time period/reduce the frequency of the scaled clock by a second preset value. If the write operation is If the operation is too fast and the read operation is caught up, the clock generation unit is adjusted to reduce the period of the scaled clock by a second preset time period // and increase the frequency of the scaled clock by a second preset value; or

If the read operation is too fast and causes the write operation to be caught up, then the scaling ratio is reduced by a preset threshold to reduce the step size of reading data from the row cache unit. If the write operation is too fast and the read operation is caught up, all the steps are reduced. The scaling ratio is increased by a preset threshold to increase the step size of reading data from the line cache unit.

10. The video scaling device according to any one of claims 1 to 6, further comprising: a field filtering unit configured to filter the first video data input into the line buffer control unit. .

11. A video scaling method, characterized by including the following steps:

S1: Obtain the input clock of the input first video data, and obtain the scaling clock according to the input clock and scaling ratio;

S2: Determine whether the vertical scaling ratio m in the vertical direction is greater than n, where n is the number of pixels required for each interpolation process in the scaling process; S3: If yes, then further determine whether m is a non-integer;

S31: If not, write n rows of the first video data each time data is written to the line cache unit, and discard m-n rows of the first video data, where the line cache unit The storage space is at least 2n rows of storage space, wherein the size of the storage space for each row is the size of the storage space required for each row of the first video data;

S32: If yes, then after each n rows of the first video data are stored, discard the 1ml-n rows of the first video data, and accumulate the decimal part of m-n to obtain a cumulative value. When the cumulative value reaches 1 When , discard the first video data of 1ml-n+1 lines, clear the accumulated number to zero, and repeat S32 every time n lines of first video data are stored;

S4: If not, write the first video data of n rows each time data is written to the row cache unit; S5: Perform a first weighting process on the first video data of n rows to obtain vertical The second video data after scaling in the direction;

S6: Perform a second weighting process on the second video data to obtain the third video data scaled in the horizontal direction;

S7: Output the third video data.

12. The video scaling method according to claim 11, wherein the step S1 includes: obtaining the first product of the input clock and the scaling ratio, and using the first product as the scaling clock; wherein , the scaling ratio = (the number of vertical lines of the third video data * the number of horizontal pixels of the third video data) / (the number of vertical lines of the first video data * the number of horizontal pixels of the first video data) number of pixels).

13. The video scaling method according to claim 11, wherein the data reading operations in steps S3 and S4 and the data writing operations in S5 are performed synchronously for different row address spaces.

14. The video scaling method according to claim 13, further comprising the following steps: monitoring the read and write status of the line cache unit, and making corrections when the read and write status is abnormal.

15. The video scaling method according to claim 14, further comprising the following steps: generating a line read control signal according to the scaling clock, the total length of one cycle of the line read control signal being from the The time required to read one row of data in the row cache unit according to the scaling ratio, where, if the low level interval/high level interval of the row read control signal is a blanking interval, then in the high level In the interval/low-level interval, one line of valid data is read from the line cache unit according to the scaling ratio.

16. The video scaling method according to claim 15, characterized in that the correction is performed according to one or more of the following rules:

adjust the total length of one cycle of the row read control signal; or

adjust the period/frequency of said scaling clock; or Adjust the vertical scaling.

17. The video scaling method according to claim 16, wherein the adjusting the total length of one cycle of the read control signal specifically means: adjusting the length of the blanking interval of the read control signal.

18. The video scaling method according to claim 16, wherein the adjusting the scaling ratio specifically includes: adjusting the scaling ratio in the vertical direction.

19. The video scaling method according to claim 17 or 18, wherein the correction according to one or more of the following rules specifically includes:

If the read operation is too fast and the write operation is caught up, the duration of the level signal corresponding to the blanking interval in the row read control signal is increased by a first preset time period. If the write operation is too fast and the read operation is caught up. operation, then reduce the duration of the level signal corresponding to the blanking interval in the row read control signal by a first preset time period; or if the read operation is too fast and causes the write operation to catch up, then the scaling clock The cycle of is increased by a second preset time period/the frequency of the scaling clock is reduced by a second preset value. If the write operation is too fast and causes the read operation to be caught up, the cycle of the scaling clock is reduced by a second preset time. segment/increase the frequency of the scaling clock by a second preset value; or

20. The video scaling method according to any one of claims 11 to 19, characterized in that, before step S1, it further includes:

Perform vertical filtering on the first video data.

21. A storage medium, characterized in that it is used to store an application program, and the application program is used to execute the video scaling method according to any one of claims 11 to 19.