WO2014094622A1 - Touch control electrode structure and manufacturing process therefor - Google Patents

Touch control electrode structure and manufacturing process therefor Download PDF

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Publication number
WO2014094622A1
WO2014094622A1 PCT/CN2013/089878 CN2013089878W WO2014094622A1 WO 2014094622 A1 WO2014094622 A1 WO 2014094622A1 CN 2013089878 W CN2013089878 W CN 2013089878W WO 2014094622 A1 WO2014094622 A1 WO 2014094622A1
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layer
electrode
etching
optical layer
etching optical
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PCT/CN2013/089878
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French (fr)
Chinese (zh)
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刘振宇
李禄兴
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宸鸿光电科技股份有限公司
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Publication of WO2014094622A1 publication Critical patent/WO2014094622A1/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412Digitisers structurally integrated in a display
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices

Abstract

A manufacturing process for a touch control electrode structure, comprising the steps of: S1: forming an electrode layer on a substrate; S2: forming a first anti-etching optical layer; S3: etching the electrode layer, wherein the electrode layer located in a non-etching area comprises: more than two first electrode blocks arranged in a first direction, adjacent first electrode blocks being electrically connected via a first conductor; and more than two second electrode blocks arranged in a second direction, the second electrode blocks being respectively arranged on both sides of the first conductor; S4: forming a second anti-etching optical layer, and forming a hollow area corresponding to the second anti-etching optical layer on each of the second electrode blocks; S5: etching the first anti-etching optical layer in the hollow area, so as to form a through hole; and S6: forming a line layer, the line layer being located on the second anti-etching optical layer and being electrically connected to the adjacent second electrode blocks via the hollow area and the through hole. The touch control electrode structure formed using the above-mentioned process has a better visual effect, short processing time and high process efficiency.

Description

触控电极结构及其制造工艺 技术领域  Touch electrode structure and manufacturing process thereof
本发明涉及触控技术, 特别是涉及一种触控电极结构及其制造工艺。 背景技术  The present invention relates to touch technology, and in particular to a touch electrode structure and a manufacturing process thereof. Background technique
传统的触控电极结构制造工艺中, 最主要的歩骤包括电极结构的形成和线 路层的形成, 在这两个歩骤中, 分别需要用到用于定义电极图形的掩膜和用于 定义线路层连接区域的掩膜。 在传统的制造工艺中, 掩膜在完成以上制程歩骤 之后, 一般都需要额外的歩骤去除。  In the conventional touch electrode structure manufacturing process, the most important steps include the formation of an electrode structure and the formation of a circuit layer. In these two steps, a mask for defining an electrode pattern and a definition are respectively required. A mask for the connection area of the circuit layer. In conventional manufacturing processes, the mask typically requires additional step removal after completing the above process steps.
另一方面, 为了使得触控电极结构在应用于触控显示装置时具有良好的视 觉效果, 在形成触控感测电极结构之后, 触控电极结构上通常需要增加额外的 光学层, 以调节触控装置的显示效果。  On the other hand, in order to make the touch electrode structure have a good visual effect when applied to the touch display device, after the touch sensing electrode structure is formed, an additional optical layer is usually required on the touch electrode structure to adjust the touch. The display effect of the control device.
因此传统的触控电极结构制造工艺不但流程繁琐, 而且在显示效果的调整 方面需要付出额外的成本。 发明公开  Therefore, the conventional touch electrode structure manufacturing process is not only cumbersome, but also requires additional cost in adjusting the display effect. Invention disclosure
基于此, 有必要提供一种触控电极结构的制造工艺, 其具有较少的工艺歩 骤且较好的视觉效果。  Based on this, it is necessary to provide a manufacturing process of a touch electrode structure which has fewer process steps and better visual effects.
此外, 还提供一种触控电极结构。  In addition, a touch electrode structure is also provided.
一种触控电极结构的制造工艺, 包括歩骤:  A manufacturing process of a touch electrode structure, comprising:
S1 : 形成一电极层于一基板上;  S1: forming an electrode layer on a substrate;
S2: 形成一第一防蚀刻光学层于该电极层上;  S2: forming a first anti-etching optical layer on the electrode layer;
S3: 蚀刻未被该第一防蚀刻光学层遮挡的该电极层, 经蚀刻后的该电极层 分为一蚀刻区与一非蚀刻区, 且位于该非蚀刻区的电极层包含:  S3: etching the electrode layer not blocked by the first anti-etching optical layer, the etched electrode layer is divided into an etched region and a non-etched region, and the electrode layer located in the non-etched region comprises:
至少两个以上的沿第一方向排列的第一电极块, 相邻的该些第一电极块通 过一第一导线电性连接;  At least two or more first electrode blocks arranged along the first direction, and the adjacent first electrode blocks are electrically connected by a first wire;
至少两个以上的沿第二方向排列的第二电极块, 该些第二电极块分别设置 于该第一导线两侧;  At least two or more second electrode blocks arranged along the second direction, the second electrode blocks being respectively disposed on two sides of the first wire;
S4 : 形成一第二防蚀刻光学层于该第一防蚀刻光学层和该基板上, 且对应 于各第二电极块上的该第二防蚀刻光学层形成有镂空区域; S4: forming a second anti-etching optical layer on the first anti-etching optical layer and the substrate, and corresponding The second anti-etching optical layer on each of the second electrode blocks is formed with a hollow region;
S5 : 蚀刻该镂空区域处的该第一防蚀刻光学层, 形成贯穿孔贯穿该第一防 蚀刻光学层;  S5: etching the first anti-etching optical layer at the hollow region, forming a through hole penetrating the first anti-etching optical layer;
S6: 形成一线路层, 该线路层位于该第二防蚀刻光学层上, 且通过该镂空 区域与该贯穿孔电性连接相邻的第二电极块。  S6: forming a circuit layer, the circuit layer is located on the second anti-etching optical layer, and electrically connecting the adjacent second electrode block to the through hole through the hollow region.
一种触控电极结构, 包括:  A touch electrode structure comprising:
一基板;  a substrate;
一电极层, 设置于该基板上, 且该电极层分为一蚀刻区与一非蚀刻区, 其 中该非蚀刻区的电极层包含: 至少两个以上的沿第一方向排列的第一电极块, 相邻的该些第一电极块通过第一导线电性连接; 至少两个以上的沿第二方向排 列的第二电极块, 所述第二电极块分别设置于该第一导线两侧;  An electrode layer is disposed on the substrate, and the electrode layer is divided into an etched region and a non-etched region, wherein the electrode layer of the non-etched region comprises: at least two or more first electrode blocks arranged along the first direction The adjacent first electrode blocks are electrically connected by the first wire; at least two or more second electrode blocks arranged along the second direction, the second electrode blocks are respectively disposed on two sides of the first wire;
一第一防蚀刻光学层, 设置于该非蚀刻区的电极层上, 且该第一防蚀刻光 学层对应于该些第二电极块的位置形成有贯穿孔;  a first anti-etching optical layer is disposed on the electrode layer of the non-etching region, and the first anti-etching optical layer is formed with a through hole corresponding to the positions of the second electrode blocks;
一第二防蚀刻光学层, 设置于该第一防蚀刻光学层与该基板上, 且该第二 防蚀刻光学层对应于该贯穿孔的位置形成有镂空区域;  a second anti-etching optical layer is disposed on the first anti-etching optical layer and the substrate, and the second anti-etching optical layer is formed with a hollow region corresponding to the position of the through hole;
一线路层, 设置于该第二防蚀刻光学层上, 且该线路层通过该镂空区域及 该贯穿孔电性连接相邻的第二电极块。  A circuit layer is disposed on the second anti-etching optical layer, and the circuit layer is electrically connected to the adjacent second electrode block through the hollow region and the through hole.
以下结合附图和具体实施例对本发明进行详细描述, 但不作为对本发明的 限定。 附图简要说明  The invention is described in detail below with reference to the accompanying drawings and specific embodiments, but not to limit the invention. BRIEF DESCRIPTION OF THE DRAWINGS
图 1为第一实施例的触控电极结构的制造工艺流程图;  1 is a flow chart showing a manufacturing process of the touch electrode structure of the first embodiment;
图 2a〜图 2f为图 1所示工艺流程图中各个歩骤所对应的触控电极结构俯视 图; 图 2a' 〜图 2f 分别为图 2a〜图 2f沿 A-A'方向的剖视图;  2a to 2f are top views of the touch electrode structure corresponding to each step in the process flow chart shown in Fig. 1; Fig. 2a' to Fig. 2f are cross-sectional views taken along line A-A' of Fig. 2a to Fig. 2f, respectively;
图 2g 为第一实施例的触控电极结构蚀刻区与非蚀刻区的电极层的层级结 构图;  2G is a hierarchical structure diagram of the electrode layer of the touch electrode structure etched region and the non-etched region of the first embodiment;
图 3a为第二实施例的触控电极结构的俯视图; 图 3a'为图 3a沿 A-A'方向 的剖视图;  3a is a plan view of the touch electrode structure of the second embodiment; FIG. 3a' is a cross-sectional view taken along line A-A' of FIG. 3a;
图 4为另一实施例的触控电极结构的制造工艺流程图;  4 is a flow chart showing a manufacturing process of a touch electrode structure according to another embodiment;
图 5a〜图 5e为图 4所示工艺流程图中各个歩骤所对应的触控电极结构俯视 图; 图 5a' 〜图 5e' 分别为图 5a〜图 5e沿 A-A'方向的剖视图。 实现本发明的最佳方式 5a to 5e are top views of the touch electrode structure corresponding to each step in the process flow chart shown in FIG. Figure 5a' to Figure 5e' are cross-sectional views taken along line A-A' of Figures 5a to 5e, respectively. The best way to implement the invention
如图 1所绘示, 为一实施例的触控电极结构的制造工艺流程图。 该制造工 艺流程包括以下歩骤。  FIG. 1 is a flow chart showing a manufacturing process of the touch electrode structure of an embodiment. The manufacturing process includes the following steps.
S101 : 形成一电极层于一基板上。 参考图 2a, 和图 2a, 电极层 130a形成 于基板 110上。 其中基板 110可以是玻璃基板或者聚对苯二甲酸类塑料  S101: Form an electrode layer on a substrate. Referring to Figures 2a, and 2a, an electrode layer 130a is formed on the substrate 110. The substrate 110 may be a glass substrate or a polyphthalic plastic.
( Polyethylene terephthalate, PET)基板。基板 110可为平面或者曲面形状, 以适应不同的触控产品。 基板 110还可为硬质基板或可扰式基板。 电极层 130a 可以采用纳米银丝(Si lver Nano-Wire, S而)层、 碳纳米管(Carbon nanotube , CNT)层、 石墨烯 ( Graphene ) 层、 高分子导电 ( Conduct ive Polymer ) 层以及 氧化金属(IT0、 AZ0…… Gel)层等可透视的材料。 形成电极层 130的方式可以采 用沉积、 溅射等工艺。  (Polyethylene terephthalate, PET) substrate. The substrate 110 can be planar or curved to accommodate different touch products. The substrate 110 can also be a rigid substrate or a disturbable substrate. The electrode layer 130a may be a nano silver wire (Silver Nano-Wire, S) layer, a carbon nanotube (CNT nanotube) layer, a graphene layer, a conductive ive polymer layer, and a metal oxide layer. A material that can be seen through (IT0, AZ0... Gel) layers. The electrode layer 130 may be formed by a deposition, sputtering or the like.
S102 : 形成一保护层于该电极层上。 对于纳米银丝等易被氧化的材料, 保 护层 140将电极层 130a与空气隔离, 进而有助于提高电极层 130a的抗氧化能 力。 同时, 由于纳米银丝材料自身具有一定的疏密度, 保护层 140可通过纳米 银丝的间隙与基板接触, 通过选用与基板 110有较佳附着力的材料, 有助于提 高纳米银丝在基板 110的附着力。 保护层的材料采用可透视的绝缘材料, 如二 氧化硅。 保护层的厚度为 50nm至 500nm。  S102: forming a protective layer on the electrode layer. For a material that is easily oxidized such as nanosilver, the protective layer 140 isolates the electrode layer 130a from the air, thereby contributing to an increase in the oxidation resistance of the electrode layer 130a. At the same time, since the nano-silver material itself has a certain density, the protective layer 140 can contact the substrate through the gap of the nano-silver wire, and the material with better adhesion to the substrate 110 is selected to help improve the nano-silver wire on the substrate. The adhesion of 110. The material of the protective layer is made of a see-through insulating material such as silica. The protective layer has a thickness of 50 nm to 500 nm.
S103 : 形成一第一防蚀刻光学层于该保护层上。 参考图 2b ' 和图 2b , 将 第一防蚀刻光学层 150形成于保护层 140上。 第一防蚀刻光学层 150具有图案 化的形状, 其用于在电极层 130a上定义出导电电极图形。 该第一防蚀刻光学层 150可以采用压克力聚合物 (Acrylate Polymer ) 和环氧树脂 (Epoxide Resin) 等可透视的绝缘材料制成。 形成第一防蚀刻光学层 150的方式可以采用印刷 ( printing) 工艺。 第一防蚀刻光学层的厚度为 0. 05 um至 5蘭。  S103: forming a first anti-etching optical layer on the protective layer. Referring to Figures 2b' and 2b, a first anti-etching optical layer 150 is formed on the protective layer 140. The first anti-etching optical layer 150 has a patterned shape for defining a conductive electrode pattern on the electrode layer 130a. The first anti-etching optical layer 150 may be made of a see-through insulating material such as Acrylate Polymer and Epoxide Resin. The manner in which the first anti-etching optical layer 150 is formed may employ a printing process. The thickness of the first anti-etching optical layer is from 0.05 um to 5 Å.
S104: 蚀刻未被该第一防蚀刻光学层遮挡的该电极层, 经蚀刻后的该电极 层分为一蚀刻区与一非蚀刻区。 参考图 2c ' 和图 2c , 对图 2b ' 和图 2b中的 电极层 130a进行蚀刻,形成图 2c和图 2c ' 所示的电极层 130 在蚀刻过程中, 由于保护层 140的厚度较薄, 蚀刻液可渗透保护层 140对电极层 130a进行蚀 亥 lj。 图 2c ' 和图 2c所示的电极层 130b分为蚀刻区 M和非蚀刻区 N。 在本实施 例中,蚀刻电极层 130采用不完全蚀刻的工艺 即在确保蚀刻区 M的电极层 130b 与非蚀刻区 N的电极层 130b电性绝缘的前提下, 仅蚀刻掉部分蚀刻区 M的电 极。采用不完全蚀刻的工艺, 可避免蚀刻区 M与非蚀刻区 N的电极层色差过大。 在另一实施例中, 可采用完全蚀刻的工艺。 非蚀刻区 N的电极层 130b包含: 至 少两个以上的沿第一方向排列的第一电极块 132, 相邻的第一电极块 132通过 第一导线 134电性连接; 至少两个以上的沿第二方向排列的第二电极块 136, 第二电极块 136分别设置于第一导线 134两侧。 图中仅示出非蚀刻区 N的电极 层 130b的部分电极块, 实际的电极层 130b应包含更多电极块。 由于第一防蚀 刻光学层 150的遮挡, 经过蚀刻后, 电极层 130最终形成与第一防蚀刻光学层 150所定义的图形相同的电极结构。 图 2c ' 和图 2c中, 第一电极块 132、 第一 导线 134以及第二电极块 136均位于第一防蚀刻光学层 150下。 S104: etching the electrode layer that is not blocked by the first anti-etching optical layer, and the etched electrode layer is divided into an etched region and a non-etched region. Referring to FIG. 2c' and FIG. 2c, the electrode layer 130a of FIG. 2b' and FIG. 2b is etched to form the electrode layer 130 shown in FIG. 2c and FIG. 2c'. During the etching process, since the thickness of the protective layer 140 is thin, The etchant permeable protective layer 140 etches the electrode layer 130a. The electrode layer 130b shown in Fig. 2c' and Fig. 2c is divided into an etched region M and a non-etched region N. In this implementation In the example, the etching electrode layer 130 etches only the electrode of the partial etching region M by the process of incomplete etching, that is, while ensuring that the electrode layer 130b of the etching region M is electrically insulated from the electrode layer 130b of the non-etching region N. With the process of incomplete etching, the chromatic aberration of the electrode layers of the etched region M and the non-etched region N can be prevented from being excessive. In another embodiment, a fully etched process can be employed. The electrode layer 130b of the non-etched region N includes: at least two or more first electrode blocks 132 arranged in the first direction, and the adjacent first electrode blocks 132 are electrically connected by the first wires 134; at least two or more edges The second electrode block 136 and the second electrode block 136 are respectively disposed on the two sides of the first wire 134. Only a partial electrode block of the electrode layer 130b of the non-etched region N is shown in the drawing, and the actual electrode layer 130b should contain more electrode blocks. Due to the occlusion of the first anti-etching optical layer 150, after etching, the electrode layer 130 finally forms the same electrode structure as that defined by the first anti-etching optical layer 150. In FIG. 2c' and FIG. 2c, the first electrode block 132, the first wire 134, and the second electrode block 136 are both located under the first anti-etching optical layer 150.
S105 : 形成一第二防蚀刻光学层于该保护层与该第一防蚀刻光学层上。 参 考图 2d' 和图 2d, 在蚀刻形成电极层 130b之后, 在整个基板 210之上再覆盖 形成第二防蚀刻光学层 160, 第二防蚀刻光学层 160形成于第一防蚀刻光学层 150和保护层 140之上, 且对应于各第二电极块 136上的第二防蚀刻光学层 160 形成有镂空区域 162。第二防蚀刻光学层 160可以采用压克力聚合物(Acrylate Polymer ) 和环氧树脂 (Epoxide Resin ) 等可透视的绝缘材料制成。 第二防蚀 刻光学层 160的厚度为 0. 05 um至 5蘭。  S105: forming a second anti-etching optical layer on the protective layer and the first anti-etching optical layer. Referring to FIG. 2d' and FIG. 2d, after the electrode layer 130b is formed by etching, a second anti-etching optical layer 160 is formed over the entire substrate 210, and the second anti-etching optical layer 160 is formed on the first anti-etching optical layer 150. Above the protective layer 140, and corresponding to the second anti-etching optical layer 160 on each of the second electrode blocks 136, a hollow region 162 is formed. The second anti-etching optical layer 160 may be made of a see-through insulating material such as Acrylate Polymer and Epoxide Resin. The thickness of the second anti-etching optical layer 160 is from 0.05 um to 5 Å.
S106蚀刻该些镂空区域处的该第一防蚀刻光学层和该保护层。参考图 2e ' 和图 2e, 通过蚀刻镂空区域 162处的第一防蚀刻光学层 150和保护层 140, 可 在第一防蚀刻光学层 150和保护层 140上形成贯穿孔 152。 贯穿孔 152形成并 贯穿于第一防蚀刻光学层 150和保护层 140, 使得第二电极块 136部分外露。 需说明的是, 对于单一第二电极块 136而言, 镂空区域 162和贯穿孔 152的数 目可根据第二电极块 136的大小作调整, 并不限定于图示中的数量。 另镂空区 域 162和贯穿孔 152的亦可为圆形等形状, 不限于图示中的方形。  S106 etches the first anti-etch optical layer and the protective layer at the hollow regions. Referring to Figures 2e' and 2e, through holes 152 may be formed in the first anti-etching optical layer 150 and the protective layer 140 by etching the first anti-etching optical layer 150 and the protective layer 140 at the cutout region 162. The through holes 152 are formed and penetrated through the first anti-etching optical layer 150 and the protective layer 140 such that the second electrode block 136 is partially exposed. It should be noted that, for a single second electrode block 136, the number of the hollow regions 162 and the through holes 152 can be adjusted according to the size of the second electrode block 136, and is not limited to the number in the figure. The cutout area 162 and the through hole 152 may also have a circular shape or the like, and are not limited to the square shape in the drawing.
S107: 形成一线路层。 参考图 2f ' 和图 2f , 线路层 170形成于第二防蚀 刻光学层 160上, 并通过镂空区域 162以及贯穿孔 152与位于非蚀刻区的第二 电极块 136电性连接。线路层 170可采用氧化铟锡等可透视的导电材料、 或银、 铝等金属材料、 或钼铝钼等合金材料。  S107: Form a circuit layer. Referring to FIG. 2f' and FIG. 2f, a wiring layer 170 is formed on the second anti-etching optical layer 160, and is electrically connected to the second electrode block 136 located in the non-etching region through the hollow region 162 and the through holes 152. The wiring layer 170 may be a see-through conductive material such as indium tin oxide, or a metal material such as silver or aluminum, or an alloy material such as molybdenum aluminum molybdenum.
同时参考图 2c、 图 2f ' 和图 2f 所示, 经过上述工艺所得到的触控电极结 构, 包括:基板 110; 电极层 130b, 设置于该基板 110上, 且电极层 130b分为 蚀刻区 M与非蚀刻区 N, 其中非蚀刻区 N的电极层包含: 至少两个以上的沿第 一方向排列的第一电极块 132, 相邻的该些第一电极块 132通过第一导线 134 电性连接; 至少两个以上的沿第二方向排列的第二电极块 136, 所述第二电极 块 136分别设置于该第一导线 134两侧; 保护层 140, 设置于该电极层 130b上; 第一防蚀刻光学层 150, 设置于非蚀刻区 N的保护层上, 且第一防蚀刻光学层 150与保护层 140对应于第二电极块 136的位置形成有贯穿孔 152; 第二防蚀刻 光学层 160, 设置于保护层 140与第一防蚀刻光学层 150上, 且第二防蚀刻光 学层 160对应于贯穿孔 152的位置形成有镂空区域 162; 线路层 170, 设置于第 二防蚀刻光学层 160上, 且线路层 170通过镂空区域 162及贯穿孔 152电性连 接相邻的第二电极块 136。 本实施例触控电极结构各部件的其它特性, 在形成 工艺中已详述, 故此处不再赘述。 Referring to FIG. 2c, FIG. 2f' and FIG. 2f, the touch electrode junction obtained by the above process is obtained. The electrode layer 130b is disposed on the substrate 110, and the electrode layer 130b is divided into an etched region M and a non-etched region N, wherein the electrode layer of the non-etched region N comprises: at least two or more a first electrode block 132 arranged in one direction, the adjacent first electrode blocks 132 are electrically connected by a first wire 134; at least two or more second electrode blocks 136 arranged in a second direction, the second The electrode blocks 136 are respectively disposed on the two sides of the first wire 134; the protective layer 140 is disposed on the electrode layer 130b; the first anti-etching optical layer 150 is disposed on the protective layer of the non-etched region N, and the first anti-etching The optical layer 150 and the protective layer 140 are formed with a through hole 152 at a position corresponding to the second electrode block 136; the second anti-etching optical layer 160 is disposed on the protective layer 140 and the first anti-etching optical layer 150, and the second anti-etching The optical layer 160 is formed with a hollow region 162 corresponding to the position of the through hole 152. The circuit layer 170 is disposed on the second anti-etching optical layer 160, and the circuit layer 170 is electrically connected to the adjacent portion through the hollow region 162 and the through hole 152. Two electrode blocks 136. Other characteristics of the components of the touch electrode structure of this embodiment have been described in detail in the forming process, and therefore will not be described herein.
请同时参考图 2f ' 、 图 2f和图 2g, 采用本发明的工艺形成的触控电极结 构, 电极层 130b蚀刻区 M上形成有保护层 140、 第二防蚀刻光学层 160 ; 非蚀 刻区 N上形成有保护层 140、 第一防蚀刻光学层 150、 第二防蚀刻光学层 160。 通过调节保护层 14(X第一防蚀刻光学层 15(X第二防蚀刻光学层 160的折射率, 可减轻蚀刻后蚀刻区 Μ和非蚀刻区 Ν存在的外观差异。 在一实施例中, 第一防 蚀刻光学层 150的折射率至少比保护层 140的折射率大 0. 1, 第二防蚀刻光学 层 160的折射率至少比第一防蚀刻光学层 150的折射率大 0. 1。 保护层 140、 第 一防蚀刻光学层 150、 第二防蚀刻光学层 160的折射率可根据不同电极层材料 的折射率作调整。 另, 保护层 140的厚度可为至 50nm至 500nm, 该厚度范围可 确保在蚀刻电极层 130a时, 蚀刻液较易渗透; 第一防蚀刻光学层 150和第二防 蚀刻光学层 160的厚度可为为 0. 05um至 5um, 该厚度范围有利于确保整体触控 电极结构的光穿透率。 此外, 相比于传统的制造工艺, 本实施例的工艺流程中 没有涉及去除用于定义电极层的电极图形的掩膜的歩骤以及去除用于定义贯穿 孔位置掩膜的歩骤, 因此工艺歩骤会更少, 制程的时间也会更短, 可以提高该 工艺的效率。  Referring to FIG. 2f', FIG. 2f and FIG. 2g, the touch electrode structure formed by the process of the present invention, the protective layer 140 and the second anti-etching optical layer 160 are formed on the etched region M of the electrode layer 130b; the non-etched region N A protective layer 140, a first anti-etching optical layer 150, and a second anti-etching optical layer 160 are formed thereon. By adjusting the refractive index of the protective layer 14 (X first anti-etching optical layer 15 (X second anti-etching optical layer 160), the difference in appearance of the etching region and the non-etching region after etching can be alleviated. In an embodiment, 1。 The refractive index of the first anti-etching optical layer 150 is at least 0.11 greater than the refractive index of the first anti-etching optical layer 150. The refractive index of the protective layer 140, the first anti-etching optical layer 150, and the second anti-etching optical layer 160 may be adjusted according to the refractive index of the different electrode layer materials. In addition, the protective layer 140 may have a thickness of up to 50 nm to 500 nm. The thickness of the first anti-etching optical layer 150 and the second anti-etching optical layer 160 may be 0. 05um to 5um, which is advantageous for ensuring the overall touch. The light transmittance of the electrode structure is controlled. Further, compared with the conventional manufacturing process, the process of the present embodiment does not involve the step of removing the mask for defining the electrode pattern of the electrode layer and the removal. Define the position of the mask through-hole ho step, so the process will be less ho step, the process time will be shorter, can improve the efficiency of the process.
进一歩参考图 3a' 和图 3a, 在本发明的另一实施例中, 在形成如图 2f和 图 2f ' 的触控电极结构之后, 可更进一歩形成一光学调整层 180覆盖于线路层 170上。 光学调整层 180可为单层结构或多层复合的结构。 一方面, 光学调整 层 180可用于保护整体的触控结构; 另一方面, 光学调整层 180亦可起到调节 线路层 170以及整体触控结构光学外观的作用。 光学调整层 180的厚度为 0. 05 um至 5薦。 光学调整层 280采用可以采用压克力聚合物 (Acrylate Polymer ) 和环氧树脂 (Epoxide Resin) 等可透视的绝缘材料制成。 Referring to FIG. 3a' and FIG. 3a, in another embodiment of the present invention, after forming the touch electrode structure of FIG. 2f and FIG. 2f', an optical adjustment layer 180 may be further formed to cover the circuit layer. 170 on. The optical adjustment layer 180 may be a single layer structure or a multilayer composite structure. On the one hand, optical adjustment The layer 180 can be used to protect the overall touch structure; on the other hand, the optical adjustment layer 180 can also function to adjust the optical appearance of the circuit layer 170 and the overall touch structure. The thickness of the optical adjustment layer 180 is 0.05 um to 5 recommended. The optical adjustment layer 280 is made of a see-through insulating material such as Acrylate Polymer and Epoxide Resin.
如图 4所绘示, 为另一实施例的触控电极结构的制造工艺流程图。 该制造 工艺流程包括以下歩骤。  FIG. 4 is a flow chart showing a manufacturing process of the touch electrode structure of another embodiment. The manufacturing process flow includes the following steps.
S201 : 形成一电极层于一基板上。 参考图 5a, 和图 5a, 电极层 230a形成 于基板 210上。 其中基板 210可以是玻璃基板或者聚对苯二甲酸类塑料  S201: Form an electrode layer on a substrate. Referring to Figures 5a, and 5a, an electrode layer 230a is formed on the substrate 210. The substrate 210 may be a glass substrate or a polyphthalic plastic.
( Polyethylene terephthalate, PET)基板。基板 110可为平面或者曲面形状, 以适应不同的触控产品。 基板 110还可为硬质基板或可扰式基板。 电极层 230a 可以采用纳米银丝(Si lver Nano-Wire, SNW)层、 碳纳米管(Carbon nanotube , CNT)层、 石墨烯 ( Graphene ) 层、 高分子导电 ( Conduct ive Polymer ) 层以及 氧化金属(IT0、 AZ0…… Gel)层等可透视的材料。 形成电极层 130的方式可以采 用沉积、 溅射等工艺。  (Polyethylene terephthalate, PET) substrate. The substrate 110 can be planar or curved to accommodate different touch products. The substrate 110 can also be a rigid substrate or a disturbable substrate. The electrode layer 230a may be a nano silver wire (Silver Nano-Wire, SNW) layer, a carbon nanotube (CNT nanotube) layer, a graphene layer, a conductive ive polymer layer, and an oxidized metal ( A material that can be seen through such as IT0, AZ0... Gel) layers. The electrode layer 130 may be formed by a deposition, sputtering or the like.
S202 : 形成一第一防蚀刻光学层于该电极上。 参考图 5a' 和图 5a , 与图 S202: Form a first anti-etching optical layer on the electrode. Refer to Figure 5a' and Figure 5a, and Figure
1所绘示的工艺流程不同之处在于, 当电极层采用氧化金属(IT0、 AZ0…… Gel) 层等抗氧化能力和附着力较好的材料时, 可省略形成保护层的歩骤, 即直接形 成第一防蚀光学层于电极层。 第一防蚀刻光学层 250具有图案化的形状, 其用 于在电极层 230a上定义出导电电极图形。第一防蚀刻光学层 250的其它特性与 前述实施例相同, 此处不再赘述。 The process flow shown in 1 is different. When the electrode layer is made of a metal oxide (IT0, AZ0... Gel) layer and other materials having good oxidation resistance and adhesion, the step of forming a protective layer may be omitted. The first anti-etching optical layer is directly formed on the electrode layer. The first anti-etching optical layer 250 has a patterned shape for defining a conductive electrode pattern on the electrode layer 230a. Other characteristics of the first anti-etching optical layer 250 are the same as those of the foregoing embodiment, and are not described herein again.
S203 : 蚀刻未被该第一防蚀刻光学层遮挡的该电极层, 经蚀刻后的该电极 层分为一蚀刻区与一非蚀刻区。 参考图 5b ' 和图 5b , 对图 5a' 和图 5a中的 电极层 230a进行蚀刻, 形成图 5b, 和图 5b所示的电极层 230b。 5b ' 和图 5b 所示的电极层 230b分为蚀刻区 M和非蚀刻区 N。 蚀刻电极层 230a可采用完全 蚀刻或不完全蚀刻的工艺。 非蚀刻区 N的电极层 230b包含: 至少两个以上的沿 第一方向排列的第一电极块 232, 相邻的第一电极块 232通过第一导线 234电 性连接; 至少两个以上的沿第二方向排列的第二电极块 236, 第二电极块 236 分别设置于第一导线 234两侧。 图中仅示出非蚀刻区 N的电极层 230b的部分电 极块, 实际的电极层 230b应包含更多电极块。 由于第一防蚀刻光学层 250的遮 挡, 经过蚀刻后, 电极层 230b最终形成与第一防蚀刻光学层 250所定义的图形 相同的电极结构。 图 5b ' 和图 5b中, 第一电极块 232、 第一导线 234以及第二 电极块 236均位于第一防蚀刻光学层 250下。 S203: etching the electrode layer not blocked by the first anti-etching optical layer, and the etched electrode layer is divided into an etched region and a non-etched region. Referring to Figures 5b' and 5b, the electrode layer 230a of Figures 5a' and 5a is etched to form the electrode layer 230b shown in Figures 5b, and 5b. The electrode layer 230b shown in 5b' and FIG. 5b is divided into an etched region M and a non-etched region N. The etching electrode layer 230a may employ a process of complete etching or incomplete etching. The electrode layer 230b of the non-etched region N includes: at least two or more first electrode blocks 232 arranged in the first direction, and the adjacent first electrode blocks 232 are electrically connected by the first wires 234; at least two or more edges The second electrode block 236 and the second electrode block 236 are arranged on the two sides of the first wire 234. Only a partial electrode block of the electrode layer 230b of the non-etched region N is shown in the drawing, and the actual electrode layer 230b should contain more electrode blocks. Due to the occlusion of the first anti-etching optical layer 250, after etching, the electrode layer 230b finally forms a pattern defined by the first anti-etching optical layer 250. The same electrode structure. In FIG. 5b' and FIG. 5b, the first electrode block 232, the first wire 234, and the second electrode block 236 are both located under the first anti-etching optical layer 250.
S204: 形成一第二防蚀刻光学层于该第一防蚀刻光学层和该基板上。 参考 图 5c ' 和图 5c, 在蚀刻形成电极层 230b之后, 在整个基板 210之上再覆盖形 成第二防蚀刻光学层 260, 第二防蚀刻光学层 260形成于第一防蚀刻光学层 250 和基板 210上, 且对应于各第二电极块 236上的第二防蚀刻光学层 260形成有 镂空区域 262。 第二防蚀刻光学层 260的其它特性与前述实施例相同, 此处不 再赘述。  S204: Form a second anti-etching optical layer on the first anti-etching optical layer and the substrate. Referring to FIG. 5c' and FIG. 5c, after the electrode layer 230b is formed by etching, a second anti-etching optical layer 260 is formed over the entire substrate 210, and the second anti-etching optical layer 260 is formed on the first anti-etching optical layer 250 and A hollowed out region 262 is formed on the substrate 210 and corresponding to the second anti-etching optical layer 260 on each of the second electrode blocks 236. Other characteristics of the second anti-etching optical layer 260 are the same as those of the previous embodiment, and will not be described again here.
S205 : 蚀刻该镂空区域处的该第一防蚀刻光学层。 参考图 5d ' 和图 5d , 通过蚀刻镂空区域 262处的第一防蚀刻光学层 250, 可在第一防蚀刻光学层 250 上形成贯穿孔 252。 贯穿孔 252形成并贯穿于第一防蚀刻光学层 250, 使得第二 电极块 236部分外露。 镂空区域 262和贯穿孔 252的其它特性与前述实施例相 同, 此处不再赘述。  S205: etching the first anti-etching optical layer at the hollow region. Referring to Figures 5d' and 5d, a through via 252 can be formed in the first etch-resistant optical layer 250 by etching the first etch-resistant optical layer 250 at the vacant region 262. The through hole 252 is formed and penetrates through the first anti-etching optical layer 250 such that the second electrode block 236 is partially exposed. Other features of the cutout region 262 and the through hole 252 are the same as those of the previous embodiment, and are not described herein again.
S206: 形成一线路层。 参考图 5e ' 和图 5e , 线路层 270形成于第二防蚀 刻光学层 260上, 并通过镂空区域 262及贯穿孔 252电性连接相邻的第二电极 块 136。 线路层 270的其它特性与前述实施例相同, 此处不再赘述。  S206: Form a circuit layer. Referring to FIG. 5e' and FIG. 5e, the wiring layer 270 is formed on the second etch-resistant optical layer 260, and is electrically connected to the adjacent second electrode block 136 through the hollow region 262 and the through hole 252. Other characteristics of the circuit layer 270 are the same as those of the previous embodiment, and are not described herein again.
同时参考图 5b、 图 5e ' 和图 5e所示, 经过上述工艺所得到的触控电极结 构, 包括:基板 210; 电极层 230b, 设置于该基板 210上, 且电极层 230b分为 蚀刻区 M与非蚀刻区 N, 其中非蚀刻区 N的电极层包含: 至少两个以上的沿第 一方向排列的第一电极块 232, 相邻的该些第一电极块 232通过第一导线 234 电性连接; 至少两个以上的沿第二方向排列的第二电极块 236, 所述第二电极 块 236分别设置于该第一导线 234两侧; 第一防蚀刻光学层 250, 设置于非蚀 刻区 N的电极层 230b上, 且第一防蚀刻光学层 250对应于第二电极块 236的位 置形成有贯穿孔 252; 第二防蚀刻光学层 260, 设置于第一防蚀刻光学层 250与 基板 210上, 且第二防蚀刻光学层 260对应于贯穿孔 252的位置形成有镂空区 域 262; 线路层 270, 设置于第二防蚀刻光学层 260上, 且线路层 270通过镂空 区域 262及贯穿孔 252电性连接相邻的第二电极块 236。 另, 在另一实施例中, 亦可进一歩在线路层 270形成一光学调整层。 本实施例触控电极结构各部件的 其它特性, 在形成工艺中已详述, 故此处不再赘述。  Referring to FIG. 5b, FIG. 5e' and FIG. 5e, the touch electrode structure obtained by the above process includes: a substrate 210; an electrode layer 230b disposed on the substrate 210, and the electrode layer 230b is divided into an etching region M. And the non-etching region N, wherein the electrode layer of the non-etching region N comprises: at least two or more first electrode blocks 232 arranged in the first direction, and the adjacent first electrode blocks 232 are electrically connected through the first wires 234 Connecting at least two second electrode blocks 236 arranged in a second direction, the second electrode blocks 236 are respectively disposed on two sides of the first wire 234; the first etching resistant optical layer 250 is disposed in the non-etching region On the electrode layer 230b of the N, the first anti-etching optical layer 250 is formed with a through hole 252 corresponding to the position of the second electrode block 236; the second anti-etching optical layer 260 is disposed on the first anti-etching optical layer 250 and the substrate 210. Upper, and the second anti-etching optical layer 260 is formed with a hollowed out region 262 corresponding to the position of the through hole 252; the wiring layer 270 is disposed on the second anti-etching optical layer 260, and the wiring layer 270 passes through the hollowed out region 262. And the through hole 252 is electrically connected to the adjacent second electrode block 236. In addition, in another embodiment, an optical adjustment layer may be formed on the circuit layer 270. Other characteristics of the components of the touch electrode structure of this embodiment have been described in detail in the forming process, and therefore will not be described herein.
上述各实施例中, 电极层的电极采用方形的电极块电连接而成, 在其他实 施例中, 电极块还是是棱形、 五边形或者六边形等。 In each of the above embodiments, the electrodes of the electrode layer are electrically connected by square electrode blocks, and In the embodiment, the electrode block is also a prism, a pentagon or a hexagon.
以上所述实施例仅表达了本发明的几种实施方式, 其描述较为具体和详 细, 但并不能因此而理解为对本发明专利范围的限制。 应当指出的是, 对于本 领域的普通技术人员来说, 在不脱离本发明构思的前提下, 还可以做出若干变 形和改进, 这些都属于本发明的保护范围。 因此, 本发明专利的保护范围应以 所附权利要求为准。  The above-mentioned embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.
工业应用性 Industrial applicability
本发明通过调节第一防蚀刻光学层和第二防蚀刻层的折射率, 可减轻蚀刻 后蚀刻区和非蚀刻区存在的外观差异。 此外, 相比于传统的制造工艺, 本实施 例的工艺流程中没有涉及去除用于定义电极层的电极图形的掩膜以及去除用于 定义线路层连接区域的掩摸的歩骤, 因此工艺歩骤会更少, 制程的时间也会更 短, 可以提高该工艺的效率。  The present invention can alleviate the difference in appearance of the etched and non-etched regions after etching by adjusting the refractive indices of the first anti-etching optical layer and the second anti-etching layer. In addition, compared with the conventional manufacturing process, the process flow of the present embodiment does not involve removing the mask for defining the electrode pattern of the electrode layer and removing the mask for defining the connection region of the circuit layer, so the process 歩Fewer meetings and shorter process times can increase the efficiency of the process.

Claims

权利要求书 Claim
1. 一种触控电极结构的制造工艺, 其特征在于, 包括歩骤: A manufacturing process of a touch electrode structure, characterized in that it comprises:
S1 : 形成一电极层于一基板上;  S1: forming an electrode layer on a substrate;
S2 : 形成一第一防蚀刻光学层于该电极层上;  S2: forming a first anti-etching optical layer on the electrode layer;
S3: 蚀刻未被该第一防蚀刻光学层遮挡的该电极层, 经蚀刻后的该电极层 分为一蚀刻区与一非蚀刻区, 且位于该非蚀刻区的电极层包含:  S3: etching the electrode layer not blocked by the first anti-etching optical layer, the etched electrode layer is divided into an etched region and a non-etched region, and the electrode layer located in the non-etched region comprises:
至少两个以上的沿第一方向排列的第一电极块,相邻的该些第一电极块通 过一第一导线电性连接;  At least two or more first electrode blocks arranged along the first direction, and the adjacent first electrode blocks are electrically connected by a first wire;
至少两个以上的沿第二方向排列的第二电极块, 该些第二电极块分别设置 于该第一导线两侧;  At least two or more second electrode blocks arranged along the second direction, the second electrode blocks being respectively disposed on two sides of the first wire;
S4: 形成一第二防蚀刻光学层于该第一防蚀刻光学层和该基板上, 且对应 于各第二电极块上的该第二防蚀刻光学层形成有镂空区域;  S4: forming a second anti-etching optical layer on the first anti-etching optical layer and the substrate, and forming a hollow region corresponding to the second anti-etching optical layer on each of the second electrode blocks;
S5: 蚀刻该镂空区域处的该第一防蚀刻光学层, 形成贯穿孔贯穿该第一防 蚀刻光学层;  S5: etching the first anti-etching optical layer at the hollow region, forming a through hole penetrating the first anti-etching optical layer;
S6: 形成一线路层, 该线路层位于该第二防蚀刻光学层上, 且通过该镂空 区域与该贯穿孔电性连接相邻的第二电极块。  S6: forming a circuit layer, the circuit layer is located on the second anti-etching optical layer, and electrically connecting the adjacent second electrode block to the through hole through the hollow region.
2. 根据权利要求 1所述的触控电极结构的制造工艺, 其特征在于, 所述 歩骤 S2更包含形成一保护层于该电极层上的歩骤,所述歩骤 S4形成的第二防 蚀刻光学层形成于该第一防蚀刻光学层和该保护层上, 且所述歩骤 S5形成的 贯穿孔贯穿该保护层。  The manufacturing process of the touch electrode structure according to claim 1, wherein the step S2 further comprises a step of forming a protective layer on the electrode layer, and the step S4 is formed by a second step. An anti-etching optical layer is formed on the first anti-etching optical layer and the protective layer, and a through hole formed in the step S5 penetrates through the protective layer.
3. 根据权利要求 1所述的触控电极结构的制造工艺, 其特征在于, 更包 括形成一光学调整层于该线路层上的歩骤。  3. The manufacturing process of the touch electrode structure according to claim 1, further comprising the step of forming an optical adjustment layer on the circuit layer.
4. 根据权利要求 1所述的触控电极结构的制造工艺, 其特征在于, 所述 歩骤 S1采用沉积、 溅射的工艺。  4. The manufacturing process of the touch electrode structure according to claim 1, wherein the step S1 employs a deposition and sputtering process.
5. 根据权利要求 1所述的制造工艺, 其特征在于, 所述歩骤 S4采用不完 全蚀刻的工艺。  The manufacturing process according to claim 1, wherein the step S4 employs a process of incomplete etching.
6. 根据权利要求 1所述的制造工艺, 其特征在于, 形成所述第一防蚀刻 光学层与所述第二防蚀刻光学层采用印刷工艺。  6. The manufacturing process according to claim 1, wherein the forming the first anti-etching optical layer and the second anti-etching optical layer are performed by a printing process.
7. 一种触控电极结构, 其特征在于, 包括: 一基板; A touch electrode structure, comprising: a substrate;
一电极层, 设置于该基板上, 且该电极层分为一蚀刻区与一非蚀刻区, 其 中该非蚀刻区的电极层包含: 至少两个以上的沿第一方向排列的第一电极块, 相邻的该些第一电极块通过第一导线电性连換 至少两个以上的沿第二方向排 列的第二电极块, 所述第二电极块分别设置于该第一导线两侧;  An electrode layer is disposed on the substrate, and the electrode layer is divided into an etched region and a non-etched region, wherein the electrode layer of the non-etched region comprises: at least two or more first electrode blocks arranged along the first direction The adjacent first electrode blocks are electrically connected to the at least two second electrode blocks arranged in the second direction by the first wire, and the second electrode blocks are respectively disposed on two sides of the first wire;
一第一防蚀刻光学层, 设置于该非蚀刻区的电极层上, 且该第一防蚀刻光 学层对应于该些第二电极块的位置形成有贯穿孔;  a first anti-etching optical layer is disposed on the electrode layer of the non-etching region, and the first anti-etching optical layer is formed with a through hole corresponding to the positions of the second electrode blocks;
一第二防蚀刻光学层, 设置于该第一防蚀刻光学层与该基板上, 且该第二 防蚀刻光学层对应于该贯穿孔的位置形成有镂空区域;  a second anti-etching optical layer is disposed on the first anti-etching optical layer and the substrate, and the second anti-etching optical layer is formed with a hollow region corresponding to the position of the through hole;
一线路层, 设置于该第二防蚀刻光学层上, 且该线路层通过该镂空区域及 该贯穿孔电性连接相邻的第二电极块。  A circuit layer is disposed on the second anti-etching optical layer, and the circuit layer is electrically connected to the adjacent second electrode block through the hollow region and the through hole.
8. 根据权利要求 7所述的触控电极结构, 其特征在于, 所述电极层上更 形成有一保护层, 且该保护层设置于该电极层与该第一防蚀刻光学层之间。  The touch electrode structure according to claim 7, wherein a protective layer is further formed on the electrode layer, and the protective layer is disposed between the electrode layer and the first anti-etching optical layer.
9. 根据权利要求 7所述的触控电极结构, 其特征在于, 所述线路层上设 置有一光学调整层。  9. The touch electrode structure according to claim 7, wherein an optical adjustment layer is disposed on the circuit layer.
10. 根据权利要求 8所述的触控电极结构, 其特征在于, 所述保护层的厚 度为 50nm至 500nm。  The touch electrode structure according to claim 8, wherein the protective layer has a thickness of 50 nm to 500 nm.
11. 根据权利要求 8所述的触控电极结构, 其特征在于, 所述第一防蚀刻 光学层的折射率至少比所述保护层的折射率大 0. 1。  The refractive index of the first anti-etching optical layer is at least 0.11 greater than the refractive index of the protective layer.
12. 根据权利要求 7或 11所述的触控电极结构, 其特征在于, 所述第二 防蚀刻光学层的折射率至少比所述第一防蚀刻光学层的折射率大 0. 1。  The refractive index of the second anti-etching optical layer is at least 0.11 greater than the refractive index of the first anti-etching optical layer. The touch-proof electrode structure according to claim 7 or 11, wherein the refractive index of the second anti-etching optical layer is at least 0.1.
13. 根据权利要求 7所述的触控电极结构, 其特征在于, 所述第一防蚀刻 光学层的厚度为 0. 05um至 5蘭。  The thickness of the first anti-etching optical layer is 0.05 um to 5 Å.
14. 根据权利要求 7所述的触控电极结构, 其特征在于, 所述第二防蚀刻 光学层的厚度为 0. 05um至 5蘭。  The thickness of the second anti-etching optical layer is 0.05 um to 5 Å.
15. 根据权利要求 7所述的触控电极结构, 其特征在于, 所述线路层采用 可透视的导电材料、 金属材料、 或合金材料、 或前述之组合。  The touch electrode structure according to claim 7, wherein the circuit layer is made of a see-through conductive material, a metal material, or an alloy material, or a combination thereof.
16. 根据权利要求 7所述的触控电极结构, 其特征在于, 所述第一防蚀刻 光学层材料和所述第二防蚀刻光学层材料为压克力聚合物或环氧树脂。  The touch electrode structure according to claim 7, wherein the first anti-etching optical layer material and the second anti-etching optical layer material are an acrylic polymer or an epoxy resin.
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