TW201545215A - Method of manufacturing microstructures of metal lines - Google Patents
Method of manufacturing microstructures of metal lines Download PDFInfo
- Publication number
- TW201545215A TW201545215A TW103118566A TW103118566A TW201545215A TW 201545215 A TW201545215 A TW 201545215A TW 103118566 A TW103118566 A TW 103118566A TW 103118566 A TW103118566 A TW 103118566A TW 201545215 A TW201545215 A TW 201545215A
- Authority
- TW
- Taiwan
- Prior art keywords
- metal
- layer
- metal line
- substrate
- trench
- Prior art date
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/34—Pretreatment of metallic surfaces to be electroplated
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/48—After-treatment of electroplated surfaces
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/047—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using sets of wires, e.g. crossed wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
- H01B13/00—Apparatus or processes specially adapted for manufacturing conductors or cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/282—Applying non-metallic protective coatings for inhibiting the corrosion of the circuit, e.g. for preserving the solderability
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/02—Local etching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
- G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
- G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
- G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
- G06F2203/04112—Electrode mesh in capacitive digitiser: electrode for touch sensing is formed of a mesh of very fine, normally metallic, interconnected lines that are almost invisible to see. This provides a quite large but transparent electrode surface, without need for ITO or similar transparent conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0108—Transparent
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10053—Switch
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/12—Using specific substances
- H05K2203/121—Metallo-organic compounds
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
- H05K3/16—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation by cathodic sputtering
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
Abstract
Description
本案係關於一種微結構之製法，尤指一種金屬線路微結構之製法。This case relates to a method of fabricating a microstructure, and more particularly to a method of fabricating a metal line microstructure.
目前，觸控技術已廣泛地應用於各種電子產品之觸控顯示裝置中，以便於使用者利用觸控方式操控該電子產品的作動。習用的觸控面板為了使其觸控區域的電極不易被視認，通常採用氧化銦錫(ITO)來形成透明電極。但隨著觸控面板之應用逐漸朝大尺寸之方向發展，使用氧化銦錫透明電極之技術 存在著 電阻較大、觸控回應速度較慢，需多道製程步驟以及製作成本較高等技術問題，因此金屬線路(或稱金屬網格(Metal Mesh))於是被發展以取代氧化銦錫透明電極之應用。At present, the touch technology has been widely applied to touch display devices of various electronic products, so that the user can control the operation of the electronic product by using a touch control method. Conventional touch panels generally use indium tin oxide (ITO) to form transparent electrodes in order to make the electrodes of the touch area difficult to be visually recognized. However, as the application of the touch panel gradually develops toward a large size, the technology of using an indium tin oxide transparent electrode has technical problems such as large resistance, slow touch response speed, multiple process steps, and high production cost. Therefore, metal lines (or metal meshes) have been developed to replace the use of indium tin oxide transparent electrodes.
相較於使用氧化銦錫透明電極，利用金屬線路當作導體之技術具有電阻較小、導電性較佳、反應速度較快以及製作成本較低等優點。現有製作金屬線路之方法主要係採用印刷製程，直接在基板上印刷上所需金屬線路圖案，然而採用印刷製程製作金屬線路的精細度控制不易，且難以製作出具5μm以下線寬之金屬線路，如此將使金屬線路的性能表現、透光率以及線路不可視率無法進一步地提升。此外，採用印刷製程需使用到模板，而模板的製備及清洗成本亦會增加製作金屬線路之成本，且模板經多次印刷操作後會因變形而影響印刷精確度，模板需時常替換亦會增加整體成本。再則，如欲製作出具5μm以下線寬之金屬線路，其製作成本勢必會大幅增加且亦會面臨精確度控制不易及線路過細所產生之斷線等良率問題。 更甚者， 使用銀，鋁或銅作為金屬線路的材料時亦會面臨氧化的問題，如欲防止氧化的發生亦會增加了製程的難度與成本。Compared with the use of indium tin oxide transparent electrodes, the technology using metal lines as conductors has the advantages of less resistance, better conductivity, faster reaction speed, and lower fabrication cost. The existing method for fabricating a metal line mainly uses a printing process to directly print a desired metal line pattern on a substrate. However, the fineness control of the metal line by the printing process is not easy, and it is difficult to produce a metal line having a line width of 5 μm or less. The performance, light transmittance, and line invisibility of the metal line will not be further improved. In addition, the use of the printing process requires the use of a template, and the cost of the preparation and cleaning of the template will also increase the cost of the metal circuit, and the template will affect the printing accuracy due to the deformation after multiple printing operations, and the template will need to be replaced frequently. Overall cost. Furthermore, if a metal line having a line width of 5 μm or less is to be produced, the manufacturing cost thereof is inevitably increased, and there is also a problem that the accuracy is not easily controlled and the line is too thin to cause a yield failure. What's more, the use of silver, aluminum or copper as the material of the metal circuit also faces the problem of oxidation. To prevent the occurrence of oxidation, the difficulty and cost of the process are also increased.
有鑑於此，實有必要發展一種金屬線路微結構之製法，以解決前述現有技術所遭遇之種種問題。In view of this, it is necessary to develop a method for fabricating a metal line microstructure to solve the problems encountered in the prior art described above.
本案之目的在於提供一種金屬線路微結構之製法，其可以較低成本製備更細微化之金屬線路，且於應用於觸控面板時可以提升金屬線路之透光率及不可視率。The purpose of the present invention is to provide a method for manufacturing a metal line microstructure, which can prepare a finer metal line at a lower cost, and can improve the light transmittance and invisibility rate of the metal line when applied to a touch panel.
本案之另一目的在於提供一種金屬線路微結構之製法，其製作金屬線路的精細度較易控制，可製備具5μm以下線寬之金屬線路，可以提升產品良率，並可防止金屬線路氧化的發生。Another object of the present invention is to provide a method for manufacturing a metal line microstructure, which is easy to control in the fineness of the metal line, and can prepare a metal line having a line width of 5 μm or less, which can improve the product yield and prevent oxidation of the metal line. occur.
本案之另一目的在於提供一種適用於觸控面板之金屬線路微結構之製法，其可利用同一製程步驟同時於基板上形成觸控面板之可視觸控區域及引線區域之金屬線路。Another object of the present invention is to provide a method for fabricating a metal line microstructure of a touch panel, which can simultaneously form a metal touch line of a visible touch area and a lead area of the touch panel on the substrate by using the same process step.
為達上述目的，本案之一較佳實施態樣為提供一種金屬線路微結構之製法，包括步驟：(a)提供基板；(b)形成晶種層於基板之表面上；(c)形成光阻層於晶種層之表面上，且進行曝光及微影製程以於光阻層中形成溝槽圖案，其中溝槽圖案具有特定溝槽寬度；(d)以電鍍方式將金屬導電層填入溝槽圖案；以及(e)移除光阻層及移除未為金屬導電層接觸與連接之晶種層之部分，以形成金屬線路微結構。In order to achieve the above object, a preferred embodiment of the present invention provides a method for fabricating a metal line microstructure, comprising the steps of: (a) providing a substrate; (b) forming a seed layer on a surface of the substrate; and (c) forming light. Blocking on the surface of the seed layer, and performing an exposure and lithography process to form a trench pattern in the photoresist layer, wherein the trench pattern has a specific trench width; (d) filling the metal conductive layer by electroplating a trench pattern; and (e) removing the photoresist layer and removing portions of the seed layer that are not in contact and connected to the metal conductive layer to form a metal line microstructure.
為達上述目的，本案之另一較佳實施態樣為提供一種金屬線路微結構之製法，包括步驟：(a)提供基板；(b)形成晶種層於基板之表面上；(c)形成光阻層於晶種層之表面上，且進行曝光與微影製程以於光阻層中形成溝槽圖案，其中溝槽圖案具有特定溝槽寬度；(d)以電鍍方式將金屬導電層填入溝槽圖案；(e)將抗氧化層填入溝槽圖案，且抗氧化層形成於金屬導電層上；以及(f)移除光阻層及移除未為金屬導電層接觸與連接之晶種層之部分，以形成金屬線路微結構。In order to achieve the above object, another preferred embodiment of the present invention provides a method for fabricating a metal line microstructure, comprising the steps of: (a) providing a substrate; (b) forming a seed layer on a surface of the substrate; (c) forming a photoresist layer on the surface of the seed layer, and performing an exposure and lithography process to form a trench pattern in the photoresist layer, wherein the trench pattern has a specific trench width; (d) filling the metal conductive layer by electroplating Into the trench pattern; (e) filling the anti-oxidation layer into the trench pattern, and the anti-oxidation layer is formed on the metal conductive layer; and (f) removing the photoresist layer and removing the contact and connection of the non-metal conductive layer A portion of the seed layer to form a metal line microstructure.
為達上述目的，本案之又一較佳實施態樣為提供一種金屬線路微結構之製法，包括步驟：(a)提供基板；(b)形成晶種層於基板之表面上；(c)形成光阻層於晶種層之表面上，且進行曝光與微影製程以於光阻層中形成第一溝槽圖案及第二溝槽圖案，其中第一溝槽圖案具有第一特定溝槽寬度，第二溝槽圖案具有第二特定溝槽寬度，第二特定溝槽寬度係大於第一特定溝槽寬度；(d)將金屬導電層分別填入第一溝槽圖案及第二溝槽圖案；以及(e)移除光阻層及移除未為金屬導電層接觸與連接之晶種層之部分，以形成第一金屬線路微結構及第二金屬線路微結構。In order to achieve the above object, another preferred embodiment of the present invention provides a method for fabricating a metal line microstructure, comprising the steps of: (a) providing a substrate; (b) forming a seed layer on a surface of the substrate; (c) forming The photoresist layer is on the surface of the seed layer, and performing an exposure and lithography process to form a first trench pattern and a second trench pattern in the photoresist layer, wherein the first trench pattern has a first specific trench width The second trench pattern has a second specific trench width, the second specific trench width being greater than the first specific trench width; (d) filling the metal conductive layer into the first trench pattern and the second trench pattern, respectively And (e) removing the photoresist layer and removing portions of the seed layer that are not in contact and connected to the metal conductive layer to form the first metal line microstructure and the second metal line microstructure.
1‧‧‧觸控面板1‧‧‧ touch panel
11、31‧‧‧基板11, 31‧‧‧ substrate
12、32‧‧‧晶種層12, 32‧‧‧ seed layer
13、33‧‧‧光阻層13, 33‧‧‧ photoresist layer
14‧‧‧溝槽圖案14‧‧‧ Groove pattern
34、35‧‧‧第一溝槽圖案、第二溝槽圖案34, 35‧‧‧ first groove pattern, second groove pattern
15、36、37‧‧‧金屬導電層15, 36, 37‧‧‧Metal conductive layer
17‧‧‧抗氧化層17‧‧‧Antioxidant layer
16、18‧‧‧金屬線路微結構16, 18‧‧‧Metal line microstructure
W1‧‧‧第一特定溝槽寬度W 1 ‧‧‧first specific groove width
W2‧‧‧第二特定溝槽寬度W 2 ‧‧‧second specific groove width
38‧‧‧第一金屬線路微結構38‧‧‧First metal line microstructure
39‧‧‧第二金屬線路微結構39‧‧‧Second metal line microstructure
S20、S21、S22、S23、S24、S40、S41、S42、S43、S44、S45、S60、S61、S62、S63、S64‧‧‧流程步驟S20, S21, S22, S23, S24, S40, S41, S42, S43, S44, S45, S60, S61, S62, S63, S64‧‧‧ process steps
第1A圖至第1E圖係顯示本案第一較佳實施例之金屬線路微結構製法之結構流程示意圖。1A to 1E are schematic views showing the structure of the metal line microstructure manufacturing method of the first preferred embodiment of the present invention.
第2圖係為本案第一較佳實施例之金屬線路微結構製法之步驟流程圖。Figure 2 is a flow chart showing the steps of the method for fabricating the metal line microstructure of the first preferred embodiment of the present invention.
第3A圖至第3F圖係顯示本案第二較佳實施例之金屬線路微結構製法之結構流程示意圖。3A to 3F are schematic views showing the structure of the metal line microstructure manufacturing method of the second preferred embodiment of the present invention.
第4圖係為本案第二較佳實施例之金屬線路微結構製法之步驟流程圖。Figure 4 is a flow chart showing the steps of the metal line microstructure manufacturing method of the second preferred embodiment of the present invention.
第5A圖至第5E圖係顯示本案第三較佳實施例之金屬線路微結構製法之結構流程示意圖。5A to 5E are schematic views showing the structure of the metal line microstructure manufacturing method of the third preferred embodiment of the present invention.
第6圖係為本案第三較佳實施例之金屬線路微結構製法之步驟流程圖。Figure 6 is a flow chart showing the steps of the metal line microstructure manufacturing method of the third preferred embodiment of the present invention.
第7圖係為本案第三較佳實施例之製法應用於形成一觸控面板之金屬線路之示意圖。Figure 7 is a schematic view showing the application of the third preferred embodiment of the present invention to a metal circuit for forming a touch panel.
體現本案特徵與優點的一些典型實施例將在後段的說明中詳細敘述。應理解的是本案能夠在不同的態樣上具有各種的變化，其皆不脫離本案的範圍，且其中的說明及圖式在本質上係當作說明之用，而非用於限制本案。Some exemplary embodiments embodying the features and advantages of the present invention are described in detail in the following description. It is to be understood that the present invention is capable of various modifications in the various aspects of the present invention, and the description and drawings are intended to be illustrative and not limiting.
第1A圖至第1E圖係顯示本案第一較佳實施例之金屬線路微結構製法之結構流程示意圖；以及第2圖係為本案第一較佳實施例之金屬線路微結構製法之步驟流程圖。本案之金屬線路微結構製法包括下述步驟，首先，如第1A圖及第2圖所示，於步驟S20中，提供基板11，其中該基板11 係為透明基板、可撓式基板或可撓式透明基板，且基板11之厚度可介於但不限於20 μm至800μm之間。1A to 1E are schematic diagrams showing the structure of a method for fabricating a metal line microstructure according to a first preferred embodiment of the present invention; and FIG. 2 is a flow chart showing the steps of a method for fabricating a metal line microstructure according to a first preferred embodiment of the present invention. . The metal line microstructure manufacturing method of the present invention comprises the following steps. First, as shown in FIG. 1A and FIG. 2, in step S20, a substrate 11 is provided, wherein the substrate 11 is a transparent substrate, a flexible substrate or a flexible substrate. A transparent substrate, and the thickness of the substrate 11 may be, but not limited to, between 20 μm and 800 μm.
於一些實施例中，基板11之材料可選自聚對苯二甲酸乙二酯（Polyethylene terephthalatem，PET）、聚醚亞醯胺（Polyetherimide，PEI）、聚苯碸（Polyphenylensulfon，PPSU）、聚酰亞胺（Polyimide，PI）、聚萘二甲酸乙二醇酯 (Polyethylene naphthalate，PEN)、環烯烴類共聚物 ( Cyclic olefin copolymer，COC)、液晶高分子聚合物 (Liquid Crystal Polymer，LCP)、玻璃或其組合等，且不以此為限。於本實施例中，該基板11以可 撓式透明基板為較佳， 且其材料以聚對苯二甲酸乙二酯為較佳，其具有 耐衝擊、不易破碎、透光率較高等特性 。In some embodiments, the material of the substrate 11 may be selected from the group consisting of polyethylene terephthalate (PET), polyetherimide (PEI), polyphenylensulfon (PPSU), and polyacyl. Polyimide (PI), Polyethylene naphthalate (PEN), Cyclic olefin copolymer (COC), Liquid Crystal Polymer (LCP), Glass Or a combination thereof, etc., and is not limited thereto. In the present embodiment, the substrate 11 is preferably a flexible transparent substrate, and the material thereof is preferably polyethylene terephthalate, which has the characteristics of impact resistance, non-breaking, and high light transmittance.
接著，如第1B圖及第2圖所示，於步驟S21中，形成一晶種層12(seed layer)於基板11之一表面。於一些實施例中，可利用沉積法形成金屬膜於基板11之表面上以作為晶種層12，其中沉積法包括但不限於濺鍍法或蒸鍍法，且以濺鍍法為較佳。晶種層12具有良好的導電性及與基板11之附著性，其可作為連結非金屬材質之基板11與後續電鍍金屬導電層之介面，作為後續電鍍步驟之起始層，可提升微結構之強度及導電性。此外，晶種層12之厚度可介於5 nm至100nm之間，但不以此為限，其厚度可視實際應用需求而調整。於一些實施例中，晶種層12可為金屬或金屬合金，較佳可選自鉻/金金屬膜(Cr under Au metal film)、鈦/金金屬膜(Ti under Au metal film)、鈦/銅金屬膜(Ti under Cu metal film)、銅/銅金屬膜或鈦鎢/金金屬膜(Ti-W under Au)等，但不以此為限。Next, as shown in FIGS. 1B and 2, in step S21, a seed layer 12 is formed on one surface of the substrate 11. In some embodiments, a metal film may be formed on the surface of the substrate 11 by a deposition method as the seed layer 12, wherein the deposition method includes, but is not limited to, sputtering or evaporation, and sputtering is preferred. The seed layer 12 has good electrical conductivity and adhesion to the substrate 11, and can serve as an interface between the non-metallic substrate 11 and the subsequent electroplated metal conductive layer as a starting layer for the subsequent electroplating step, which can enhance the microstructure. Strength and electrical conductivity. In addition, the thickness of the seed layer 12 may be between 5 nm and 100 nm, but not limited thereto, and the thickness thereof may be adjusted according to actual application requirements. In some embodiments, the seed layer 12 can be a metal or a metal alloy, preferably selected from the group consisting of a Cr under Au metal film, a Ti under Au metal film, and a titanium/metal film. Ti under Cu metal film, copper/copper metal film or titanium tungsten/gold metal film (Ti-W under Au), etc., but not limited thereto.
然後，如第1C圖及第2圖所示，於步驟S22中，形成光阻層13於晶種層12之表面上，且進行曝光及微影製程以於光阻層13中形成溝槽圖案14並暴露部分之晶種層12，其中該曝光及微影製程係將光罩上的圖案轉移至光阻層13並形成該溝槽圖案14。於本實施例中，光阻層13可為濕膜光阻或乾膜光阻，其分別可利用例如塗佈方式或貼覆方式將光阻層13形成於晶種層12之表面上。此外，光阻層13所使用之光阻可包括正型光阻或負型光阻 ，其中正型光阻與負型光阻之應用與原理係為現有技術，於此不再贅述。於此步驟中，可利用例如但不限於光罩圖案設計及曝光量、曝光時間等條件的控制，以形成具有特定溝槽寬度及特定溝槽深度之溝槽圖案14 。於本實施例中，溝槽圖案14之特定溝槽寬度可介於1μm至20μm之間，其中該特定溝槽寬度以介於1μm至5μm之間為較佳，且以3μm以下為更佳。此外，溝槽圖案14之特定溝槽深度可介於0.1μm至20μm之間，且以介於0.1μm至2μm之間為較佳。Then, as shown in FIG. 1C and FIG. 2, in step S22, a photoresist layer 13 is formed on the surface of the seed layer 12, and an exposure and lithography process is performed to form a trench pattern in the photoresist layer 13. And exposing a portion of the seed layer 12, wherein the exposure and lithography process transfers the pattern on the reticle to the photoresist layer 13 and forms the trench pattern 14. In this embodiment, the photoresist layer 13 may be a wet film photoresist or a dry film photoresist, and the photoresist layer 13 may be formed on the surface of the seed layer 12 by, for example, coating or coating, respectively. In addition, the photoresist used in the photoresist layer 13 may include a positive photoresist or a negative photoresist. The application and principle of the positive photoresist and the negative photoresist are prior art and will not be described herein. In this step, control of conditions such as, but not limited to, reticle pattern design and exposure amount, exposure time, and the like may be utilized to form the trench pattern 14 having a specific trench width and a specific trench depth. In the present embodiment, the specific groove width of the groove pattern 14 may be between 1 μm and 20 μm, wherein the specific groove width is preferably between 1 μm and 5 μm, and more preferably 3 μm or less. Further, the specific groove depth of the trench pattern 14 may be between 0.1 μm and 20 μm, and preferably between 0.1 μm and 2 μm.
之後，如第1D圖及第2圖所示，於步驟S23中，以電鍍方式將 金屬導電層15 填入 溝槽圖案14 ，其中金屬導電層15係與暴露於溝槽圖案14底部之該晶種層12之部分接觸與連接。於本實施例中，採用電鍍方式將金屬導電層15填入 溝槽圖案14 具有形成速度較快且較易控制金屬導電層15厚度等優點，且對於成形之金屬導電層15無需進行後續之處理步驟，有利於製程步驟之簡化。於一些實施例中，金屬導電層15的材料可選自銅、金、銀、 鋁、鎢、鐵、鎳、鉻、鈦、鉬、銦、錫或其至少任二者以上所組成的複合材料。 於一些實施例中，金屬導電層15之厚度可介於0.1μm至20μm之間，且以介於0.1μm至2μm之間為較佳，並以介於0.1μm至0.5μm之間為更佳。Thereafter, as shown in FIG. 1D and FIG. 2, in step S23, the metal conductive layer 15 is filled in the trench pattern 14 by electroplating, wherein the metal conductive layer 15 is exposed to the crystal exposed to the bottom of the trench pattern 14. Part of the layer 12 is in contact and connected. In the present embodiment, the filling of the metal conductive layer 15 into the trench pattern 14 by electroplating has the advantages of faster formation speed and easier control of the thickness of the metal conductive layer 15, and the subsequent processing of the formed metal conductive layer 15 is not required. The steps facilitate the simplification of the process steps. In some embodiments, the material of the metal conductive layer 15 may be selected from the group consisting of copper, gold, silver, aluminum, tungsten, iron, nickel, chromium, titanium, molybdenum, indium, tin, or a composite thereof. . In some embodiments, the thickness of the metal conductive layer 15 may be between 0.1 μm and 20 μm, and preferably between 0.1 μm and 2 μm, and more preferably between 0.1 μm and 0.5 μm. .
然後，如第1E圖及第2圖所示，於步驟S24中，移除光阻層13及移除未為該金屬導電層 15接觸與連接之該晶種層12之部分(即光阻層13原覆蓋之該晶種層12之 部分) ，以形成金屬線路微結構16。於一些實施例中，移除光阻層13之方式可依據光阻層13為濕膜光阻或乾膜光阻而分別採用蝕刻方式或剝離方式實現。此外，移除 未與金屬導電層 15接觸與連接之晶種層12之該部分的方式可採用蝕刻方式實現，且不以此為限。於本實施例中，所製作完成之金屬線路微結構16其線寬係對應於溝槽圖案14之該特定溝槽寬度，換言之，金屬線路微結構16之線寬亦可介於1μm至20μm之間，其中金屬線路微結構16之線寬範圍以介於1μm至5μm之間為較佳，且以3μm以下為更佳。由於金屬線路微結構16之線寬可以藉由溝槽圖案14之該特定溝槽寬度而控制於1μm至5μm之間，特別是可控制於3μm以下，因此當應用於觸控面板之可視觸控區域之金屬線路(或金屬網格)時，可使其更細微化，且可提升金屬線路之透光率及不可視率。此外，金屬線路微結構16之線寬亦可控制介於1μm至20μm之間，例如介於5μm至20μm之間，藉此亦可應用於觸控面板之非觸控區域之金屬線路，換言之，可作為觸控面板邊緣區域之金屬引線線路。此外，金屬線路微結構16之高度亦可對應於溝槽圖案14之深度而可介於0.1μm至20μm之間，藉此可依據阻抗值之要求而調整金屬線路微結構16之高度以控制所形成之金屬線路的穩定性。Then, as shown in FIG. 1E and FIG. 2, in step S24, the photoresist layer 13 is removed and the portion of the seed layer 12 that is not in contact and connected to the metal conductive layer 15 is removed (ie, the photoresist layer) 13 is partially covered by the seed layer 12 to form a metal line microstructure 16. In some embodiments, the manner in which the photoresist layer 13 is removed may be implemented by etching or stripping, respectively, depending on whether the photoresist layer 13 is a wet film photoresist or a dry film photoresist. In addition, the manner of removing the portion of the seed layer 12 that is not in contact with and connected to the metal conductive layer 15 can be achieved by etching, and is not limited thereto. In this embodiment, the completed metal line microstructure 16 has a line width corresponding to the specific groove width of the trench pattern 14, in other words, the line width of the metal line microstructure 16 may also be between 1 μm and 20 μm. The line width of the metal line microstructures 16 is preferably between 1 μm and 5 μm, and more preferably 3 μm or less. Since the line width of the metal line microstructures 16 can be controlled between 1 μm and 5 μm by the specific groove width of the trench pattern 14, in particular, it can be controlled below 3 μm, so when applied to a touch panel When the metal circuit (or metal mesh) of the area is used, it can be made finer and the transmittance and invisibility of the metal line can be improved. In addition, the line width of the metal line microstructure 16 can also be controlled between 1 μm and 20 μm, for example, between 5 μm and 20 μm, thereby being applicable to the metal line of the non-touch area of the touch panel, in other words, It can be used as a metal lead line in the edge area of the touch panel. In addition, the height of the metal line microstructures 16 may also correspond to the depth of the trench patterns 14 and may be between 0.1 μm and 20 μm, whereby the height of the metal line microstructures 16 may be adjusted according to the requirements of the impedance values to control the The stability of the formed metal circuit.
第3A圖至第3F圖係顯示本案第二較佳實施例之金屬線路微結構製法之結構流程示意圖；以及第4圖係為本案第二較佳實施例之金屬線路微結構製法之步驟流程圖。本案之金屬線路微結構製法包括下述步驟，首先，如第3A圖及第4圖所示，於步驟S40中，提供基板11，其中該基板11 係為透明基板、可撓式基板或可撓式透明基板，且基板11之厚度可介於但不限於20 μm至800μm之間。3A to 3F are schematic diagrams showing the structure of the metal line microstructure manufacturing method of the second preferred embodiment of the present invention; and FIG. 4 is a flow chart showing the steps of the metal line microstructure manufacturing method of the second preferred embodiment of the present invention. . The metal line microstructure manufacturing method of the present invention comprises the following steps. First, as shown in FIG. 3A and FIG. 4, in step S40, a substrate 11 is provided, wherein the substrate 11 is a transparent substrate, a flexible substrate or a flexible substrate. A transparent substrate, and the thickness of the substrate 11 may be, but not limited to, between 20 μm and 800 μm.
於一些實施例中，基板11之材料可選自聚對苯二甲酸乙二酯（Polyethylene terephthalatem，PET）、聚醚亞醯胺（Polyetherimide，PEI）、聚苯碸（Polyphenylensulfon，PPSU）、聚酰亞胺（Polyimide，PI）、聚萘二甲酸乙二醇酯 (Polyethylene naphthalate，PEN)、環烯烴類共聚物 ( Cyclic olefin copolymer，COC)、液晶高分子聚合物 (Liquid Crystal Polymer，LCP)、玻璃或其組合等，且不以此為限。於本實施例中，該基板11以可 撓式透明基板為較佳， 且其材料以聚對苯二甲酸乙二酯為較佳，其具有 耐衝擊、不易破碎、透光率較高等特性 。In some embodiments, the material of the substrate 11 may be selected from the group consisting of polyethylene terephthalate (PET), polyetherimide (PEI), polyphenylensulfon (PPSU), and polyacyl. Polyimide (PI), Polyethylene naphthalate (PEN), Cyclic olefin copolymer (COC), Liquid Crystal Polymer (LCP), Glass Or a combination thereof, etc., and is not limited thereto. In the present embodiment, the substrate 11 is preferably a flexible transparent substrate, and the material thereof is preferably polyethylene terephthalate, which has the characteristics of impact resistance, non-breaking, and high light transmittance.
接著，如第3B圖及第4圖所示，於步驟S41中，形成一晶種層12(seed layer)於基板11之一表面。於一些實施例中，可利用沉積法形成金屬膜於基板11之表面上以作為晶種層12，其中沉積法包括但不限於濺鍍法或蒸鍍法，且以濺鍍法為較佳。晶種層12具有良好的導電性及與基板11之附著性，其可作為連結非金屬材質之基板11與後續電鍍金屬導電層之介面，作為後續電鍍步驟之起始層，可提升微結構之強度及導電性。此外，晶種層12之厚度可介於5 nm至100nm之間，但不以此為限，其厚度可視實際應用需求而調整。於一些實施例中，晶種層12為金屬或金屬合金，較佳可選自鉻/金金屬膜(Cr under Au metal film)、鈦/金金屬膜(Ti under Au metal film)、鈦/銅金屬膜(Ti under Cu metal film)、銅/銅金屬膜或鈦鎢/金金屬膜(Ti-W under Au)等，但不以此為限。Next, as shown in FIGS. 3B and 4, in step S41, a seed layer 12 is formed on one surface of the substrate 11. In some embodiments, a metal film may be formed on the surface of the substrate 11 by a deposition method as the seed layer 12, wherein the deposition method includes, but is not limited to, sputtering or evaporation, and sputtering is preferred. The seed layer 12 has good electrical conductivity and adhesion to the substrate 11, and can serve as an interface between the non-metallic substrate 11 and the subsequent electroplated metal conductive layer as a starting layer for the subsequent electroplating step, which can enhance the microstructure. Strength and electrical conductivity. In addition, the thickness of the seed layer 12 may be between 5 nm and 100 nm, but not limited thereto, and the thickness thereof may be adjusted according to actual application requirements. In some embodiments, the seed layer 12 is a metal or a metal alloy, preferably selected from the group consisting of a Cr under Au metal film, a Ti under Au metal film, and a titanium/copper film. Ti under Cu metal film, copper/copper metal film or titanium tungsten/gold metal film (Ti-W under Au), etc., but not limited thereto.
然後，如第3C圖及第4圖所示，於步驟S42中，形成光阻層13於晶種層12之表面上，且進行曝光及微影製程以於光阻層13中形成溝槽圖案14並暴露部分之晶種層12，其中該曝光及微影製程係將光罩上的圖案轉移至光阻層13並形成該溝槽圖案14。於本實施例中，光阻層13可為濕膜光阻或乾膜光阻，其分別可利用例如塗佈方式或貼覆方式將光阻層13形成於晶種層12之表面上。此外，光阻層13所使用之光阻可包括正型光阻或負型光阻 ，其中正型光阻與負型光阻之應用與原理係為現有技術，於此不再贅述。於此步驟中，可利用例如但不限於光罩圖案設計及曝光量、曝光時間等條件的控制，以形成具有特定溝槽寬度及特定溝槽深度之溝槽圖案14 。於本實施例中，溝槽圖案14之特定溝槽寬度可介於1μm至20μm之間，其中該特定溝槽寬度以介於1μm至5μm之間為較佳，且以3μm以下為更佳。此外，溝槽圖案14之特定溝槽深度可介於0.1μm至20μm之間，且以介於0.1μm至2μm之間為較佳。Then, as shown in FIG. 3C and FIG. 4, in step S42, a photoresist layer 13 is formed on the surface of the seed layer 12, and an exposure and lithography process is performed to form a trench pattern in the photoresist layer 13. And exposing a portion of the seed layer 12, wherein the exposure and lithography process transfers the pattern on the reticle to the photoresist layer 13 and forms the trench pattern 14. In this embodiment, the photoresist layer 13 may be a wet film photoresist or a dry film photoresist, and the photoresist layer 13 may be formed on the surface of the seed layer 12 by, for example, coating or coating, respectively. In addition, the photoresist used in the photoresist layer 13 may include a positive photoresist or a negative photoresist. The application and principle of the positive photoresist and the negative photoresist are prior art and will not be described herein. In this step, control of conditions such as, but not limited to, reticle pattern design and exposure amount, exposure time, and the like may be utilized to form the trench pattern 14 having a specific trench width and a specific trench depth. In the present embodiment, the specific groove width of the groove pattern 14 may be between 1 μm and 20 μm, wherein the specific groove width is preferably between 1 μm and 5 μm, and more preferably 3 μm or less. Further, the specific groove depth of the trench pattern 14 may be between 0.1 μm and 20 μm, and preferably between 0.1 μm and 2 μm.
之後，如第3D圖及第4圖所示，於步驟S43中，以電鍍方式將 金屬導電層15 填入 溝槽圖案14 ，其中金屬導電層15係與暴露於溝槽圖案14底部之該晶種層12之部分接觸與連接。於本實施例中，採用電鍍方式將金屬導電層15填入溝槽圖案14具有形成速度較快且較易控制金屬導電層15厚度等優點，且對於成形之金屬導電層15無需進行後續之處理步驟，有利於製程步驟之簡化。於一些實施例中，金屬導電層15的材料可選自銅、金、銀、 鋁、鎢、鐵、鎳、鉻、鈦、鉬、銦、錫或其至少任二者以上所組成的複合材料。 於一些實施例中，金屬導電層15之厚度可介於0.1μm至20μm之間，且以介於0.1μm至2μm之間為較佳，並以介於0.1μm至0.5μm之間為更佳。Thereafter, as shown in FIG. 3D and FIG. 4, in step S43, the metal conductive layer 15 is filled into the trench pattern 14 by electroplating, wherein the metal conductive layer 15 is exposed to the crystal exposed to the bottom of the trench pattern 14. Part of the layer 12 is in contact and connected. In the present embodiment, the filling of the metal conductive layer 15 into the trench pattern 14 by electroplating has the advantages of faster formation speed and easier control of the thickness of the metal conductive layer 15, and the subsequent processing of the formed metal conductive layer 15 is not required. The steps facilitate the simplification of the process steps. In some embodiments, the material of the metal conductive layer 15 may be selected from the group consisting of copper, gold, silver, aluminum, tungsten, iron, nickel, chromium, titanium, molybdenum, indium, tin, or a composite thereof. . In some embodiments, the thickness of the metal conductive layer 15 may be between 0.1 μm and 20 μm, and preferably between 0.1 μm and 2 μm, and more preferably between 0.1 μm and 0.5 μm. .
然後，如第3E圖及第4圖所示，於步驟S44中，將抗氧化層17填入溝槽圖案14 ，且該抗氧化層17形成於金屬導電層15上。於一些實施例中，抗氧化層17可為抗氧化金屬層，且抗氧化層17可包含酚醛樹脂、感光化合物、有機有色高分子染料、無機有色染料以及溶劑，但並不以此為限，其中無機有色染料係包含金屬成分。抗氧化層17可為但不限於黑色，且可用以保護金屬導電層、避免金屬導電層氧化及改變金屬線路之色澤，以使金屬線路之不可視率更為提升。Then, as shown in FIGS. 3E and 4, in step S44, the oxidation resistant layer 17 is filled in the trench pattern 14, and the oxidation resistant layer 17 is formed on the metal conductive layer 15. In some embodiments, the oxidation resistant layer 17 may be an oxidation resistant metal layer, and the oxidation resistant layer 17 may include, but is not limited to, a phenolic resin, a photosensitive compound, an organic colored polymeric dye, an inorganic colored dye, and a solvent. Among them, the inorganic colored dye contains a metal component. The anti-oxidation layer 17 can be, but is not limited to, black, and can be used to protect the metal conductive layer, avoid oxidation of the metal conductive layer, and change the color of the metal line to further improve the invisibility of the metal line.
然後，如第3F圖及第4圖所示，於步驟S45中，移除光阻層13及移除未為該金屬導電層 15接觸與連接之該晶種層12之部分(即光阻層13原覆蓋之該晶種層12之 部分) ，以形成金屬線路微結構18。於一些實施例中，移除光阻層13之方式可依據光阻層13為濕膜光阻或乾膜光阻而分別採用蝕刻方式或剝離方式實現。此外，移除 未與金屬導電層 15接觸與連接之晶種層12之該部分的方式可採用蝕刻方式實現，且不以此為限。於本實施例中，所製作完成之金屬線路微結構18其線寬係對應於溝槽圖案14之該特定溝槽寬度，換言之，金屬線路微結構18之線寬亦可介於1μm至20μm之間，其中金屬線路微結構18之線寬範圍以介於1μm至5μm之間為較佳，且以3μm以下為更佳。由於金屬線路微結構18之線寬可以藉由溝槽圖案14之該特定溝槽寬度而控制於1μm至5μm之間，特別是可控制於3μm以下，因此當應用於觸控面板之可視觸控區域之金屬線路(或金屬網格)時，可使其更細微化，且可提升金屬線路之透光率及不可視率。此外，金屬線路微結構18之線寬亦可控制介於1μm至20μm之間，例如介於5μm至20μm之間，藉此亦可應用於觸控面板之非觸控區域之金屬線路，換言之，可作為觸控面板邊緣區域之金屬引線線路。此外，金屬線路微結構18之高度亦可對應於溝槽圖案14之深度而可介於0.1μm至20μm之間，藉此可依據阻抗值之要求而調整金屬線路微結構18之高度以控制所形成之金屬線路的穩定性。Then, as shown in FIG. 3F and FIG. 4, in step S45, the photoresist layer 13 is removed and the portion of the seed layer 12 that is not in contact and connected to the metal conductive layer 15 is removed (ie, the photoresist layer) 13 is partially covered by the seed layer 12 to form a metal line microstructure 18. In some embodiments, the manner in which the photoresist layer 13 is removed may be implemented by etching or stripping, respectively, depending on whether the photoresist layer 13 is a wet film photoresist or a dry film photoresist. In addition, the manner of removing the portion of the seed layer 12 that is not in contact with and connected to the metal conductive layer 15 can be achieved by etching, and is not limited thereto. In this embodiment, the completed metal line microstructure 18 has a line width corresponding to the specific groove width of the trench pattern 14, in other words, the line width of the metal line microstructure 18 may also be between 1 μm and 20 μm. The line width of the metal line microstructure 18 is preferably between 1 μm and 5 μm, and more preferably 3 μm or less. Since the line width of the metal line microstructure 18 can be controlled between 1 μm and 5 μm by the specific groove width of the trench pattern 14 , in particular, it can be controlled below 3 μm, so when it is applied to the touch panel When the metal circuit (or metal mesh) of the area is used, it can be made finer and the transmittance and invisibility of the metal line can be improved. In addition, the line width of the metal line microstructure 18 can also be controlled between 1 μm and 20 μm, for example, between 5 μm and 20 μm, thereby being applicable to the metal line of the non-touch area of the touch panel, in other words, It can be used as a metal lead line in the edge area of the touch panel. In addition, the height of the metal line microstructure 18 may also correspond to the depth of the trench pattern 14 and may be between 0.1 μm and 20 μm, whereby the height of the metal line microstructure 18 may be adjusted according to the impedance value to control the location. The stability of the formed metal circuit.
第5A圖至第5E圖係顯示本案第三較佳實施例之金屬線路微結構製法之結構流程示意圖；以及第6圖係為本案第三較佳實施例之金屬線路微結構製法之步驟流程圖。本案之金屬線路微結構製法包括下述步驟，首先，如第5A圖及第6圖所示，於步驟S60中，提供基板31，其中該基板31 係為透明基板、可撓式基板或可撓式透明基板，且基板31之厚度可介於但不限於20 μm至800μm之間。5A to 5E are schematic diagrams showing the structure of the metal line microstructure manufacturing method of the third preferred embodiment of the present invention; and FIG. 6 is a flow chart showing the steps of the metal line microstructure manufacturing method of the third preferred embodiment of the present invention. . The metal line microstructure manufacturing method of the present invention comprises the following steps. First, as shown in FIG. 5A and FIG. 6, in step S60, a substrate 31 is provided, wherein the substrate 31 is a transparent substrate, a flexible substrate or a flexible substrate. The transparent substrate, and the thickness of the substrate 31 may be between, but not limited to, between 20 μm and 800 μm.
於一些實施例中，基板31之材料可選自聚對苯二甲酸乙二酯（Polyethylene terephthalatem，PET）、聚醚亞醯胺（Polyetherimide，PEI）、聚苯碸（Polyphenylensulfon，PPSU）、聚酰亞胺（Polyimide，PI）、聚萘二甲酸乙二醇酯 (Polyethylene naphthalate，PEN)、環烯烴類共聚物 ( Cyclic olefin copolymer，COC)、液晶高分子聚合物 (Liquid Crystal Polymer，LCP)、玻璃或其組合等，且不以此為限。於本實施例中，該基板31以可 撓式透明基板為較佳， 且其材料以聚對苯二甲酸乙二酯為較佳，其具有 耐衝擊、不易破碎、透光率較高等特性 。In some embodiments, the material of the substrate 31 may be selected from the group consisting of polyethylene terephthalate (PET), polyetherimide (PEI), polyphenylensulfon (PPSU), and polyacyl. Polyimide (PI), Polyethylene naphthalate (PEN), Cyclic olefin copolymer (COC), Liquid Crystal Polymer (LCP), Glass Or a combination thereof, etc., and is not limited thereto. In the present embodiment, the substrate 31 is preferably a flexible transparent substrate, and the material thereof is preferably polyethylene terephthalate, which has the characteristics of impact resistance, non-breaking, and high light transmittance.
接著，如第5B圖及第6圖所示，於步驟S61中，形成一晶種層32(seed layer)於基板31之一表面。於一些實施例中，可利用沉積法形成金屬膜於基板31之表面上以作為晶種層32，其中沉積法包括但不限於濺鍍法或蒸鍍法，且以濺鍍法為較佳。晶種層32具有良好的導電性及與基板31之附著性，其可作為連結非金屬材質之基板31與後續電鍍金屬導電層之介面，作為後續電鍍步驟之起始層，可提升微結構之強度及導電性。此外，晶種層32之厚度可介於5 nm至100nm之間，但不以此為限，其厚度可視實際應用需求而調整。於一些實施例中，晶種層32為金屬或金屬合金，較佳可選自鉻/金金屬膜(Cr under Au metal film)、鈦/金金屬膜(Ti under Au metal film)、鈦/銅金屬膜(Ti under Cu metal film)、銅/銅金屬膜或鈦鎢/金金屬膜(Ti-W under Au)等，但不以此為限。Next, as shown in FIGS. 5B and 6, in step S61, a seed layer 32 is formed on one surface of the substrate 31. In some embodiments, a metal film may be formed on the surface of the substrate 31 by a deposition method as the seed layer 32, wherein the deposition method includes, but is not limited to, sputtering or evaporation, and sputtering is preferred. The seed layer 32 has good electrical conductivity and adhesion to the substrate 31, and can serve as an interface between the non-metallic substrate 31 and the subsequent electroplated metal conductive layer as a starting layer for the subsequent electroplating step, which can enhance the microstructure. Strength and electrical conductivity. In addition, the thickness of the seed layer 32 may be between 5 nm and 100 nm, but not limited thereto, and the thickness thereof may be adjusted according to actual application requirements. In some embodiments, the seed layer 32 is a metal or a metal alloy, preferably selected from the group consisting of a Cr under Au metal film, a Ti under Au metal film, and a titanium/copper film. Ti under Cu metal film, copper/copper metal film or titanium tungsten/gold metal film (Ti-W under Au), etc., but not limited thereto.
然後，如第5C圖及第6圖所示，於步驟S62中，形成光阻層33於晶種層32之表面上，且進行曝光及微影製程以於光阻層33中形成第一溝槽圖案34及第二溝槽圖案35並暴露部分之晶種層32，其中該曝光及微影製程係將光罩上的圖案轉移至光阻層33並形成該第一溝槽圖案34及該第二溝槽圖案35。於本實施例中，光阻層33可為濕膜光阻或乾膜光阻，其分別可利用例如塗佈方式或貼覆方式將光阻層33形成於晶種層32之表面上。此外，光阻層33所使用之光阻可包括正型光阻或負型光阻 ，其中正型光阻與負型光阻之應用與原理係為現有技術，於此不再贅述。於此步驟中，可利用例如但不限於光罩圖案設計及曝光量、曝光時間等條件的控制，以形成具有第一特定溝槽寬度 W 1 之 第一溝槽圖案34、 第二特定溝槽寬度 W 2 之 第二溝槽圖案35 及特定溝槽深度，且 第二特定溝槽寬度W 2 係大於第一特定溝槽寬度W 1 。於本實施例中， 第一特定溝槽寬度 W 1 及 第二特定溝槽寬度 W 2 可介於1μm至20μm之間，其中該 第一特定溝槽寬度 W 1 以介於1μm至5μm之間為較佳，且以3μm以下為更佳。該 第二特定溝槽寬度 W 2 以介於5μm至20μm之間為較佳。此外，特定溝槽深度可介於0.1μm至20μm之間，且以介於0.1μm至2μm之間為較佳。Then, as shown in FIG. 5C and FIG. 6, in step S62, a photoresist layer 33 is formed on the surface of the seed layer 32, and an exposure and lithography process is performed to form a first trench in the photoresist layer 33. The groove pattern 34 and the second groove pattern 35 expose a portion of the seed layer 32, wherein the exposure and lithography process transfers the pattern on the mask to the photoresist layer 33 and forms the first trench pattern 34 and the The second groove pattern 35. In the present embodiment, the photoresist layer 33 may be a wet film photoresist or a dry film photoresist, and the photoresist layer 33 may be formed on the surface of the seed layer 32 by, for example, coating or coating, respectively. In addition, the photoresist used in the photoresist layer 33 may include a positive photoresist or a negative photoresist. The application and principle of the positive photoresist and the negative photoresist are prior art and will not be described herein. In this step, control of conditions such as, but not limited to, reticle pattern design and exposure amount, exposure time, etc., may be utilized to form a first trench pattern 34 having a first specific trench width W 1 , a second specific trench The second trench pattern 35 of the width W 2 and the specific trench depth, and the second specific trench width W 2 is greater than the first specific trench width W 1 . In this embodiment, the first specific trench width W 1 and the second specific trench width W 2 may be between 1 μm and 20 μm, wherein the first specific trench width W 1 is between 1 μm and 5 μm. More preferably, it is preferably 3 μm or less. The second specific groove width W 2 is preferably between 5 μm and 20 μm. Further, the specific groove depth may be between 0.1 μm and 20 μm, and preferably between 0.1 μm and 2 μm.
之後，如第5D圖及第6圖所示，於步驟S63中，以電鍍方式分別將 金屬導電層 36及37填入第一溝槽圖案34及第二溝槽圖案35，其中 金屬導電層 36及37係與暴露於第一溝槽圖案34及第二溝槽圖案35底部之該晶種層32之部分接觸與連接。於本實施例中，採用電鍍方式分別將 金屬導電層 36及37填入第一溝槽圖案34及第二溝槽圖案35具有形成速度較快且較易控制 金屬導電層 36及37厚度等優點，且對於成形之 金屬導電層 36及37無需進行後續之處理步驟，有利於製程步驟之簡化。於一些實施例中， 金屬導電層 36及37的材料可為相同或不同，且可選自銅、金、銀、 鋁、鎢、鐵、鎳、鉻、鈦、鉬、銦、錫或其至少任二者以上所組成的複合材料。 於一些實施例中， 金屬導電層 36及37之厚度可介於0.1μm至20μm之間，且以介於0.1μm至2μm之間為較佳，並以介於0.1μm至0.5μm之間為更佳。Then, as shown in FIG. 5D and FIG. 6, in step S63, the metal conductive layers 36 and 37 are respectively filled into the first trench pattern 34 and the second trench pattern 35 by electroplating, wherein the metal conductive layer 36 And the 37 series is in contact with and connected to portions of the seed layer 32 exposed to the bottom of the first trench pattern 34 and the second trench pattern 35. In this embodiment, the filling of the metal conductive layers 36 and 37 into the first trench pattern 34 and the second trench pattern 35 by electroplating respectively has the advantages of faster formation speed and easier control of the thickness of the metal conductive layers 36 and 37. The subsequent processing steps are not required for the formed metal conductive layers 36 and 37, which facilitates the simplification of the process steps. In some embodiments, the materials of the metal conductive layers 36 and 37 may be the same or different, and may be selected from copper, gold, silver, aluminum, tungsten, iron, nickel, chromium, titanium, molybdenum, indium, tin or at least A composite material composed of two or more. In some embodiments, the thickness of the metal conductive layers 36 and 37 may be between 0.1 μm and 20 μm, and preferably between 0.1 μm and 2 μm, and between 0.1 μm and 0.5 μm. Better.
然後，如第5E圖及第6圖所示，於步驟S64中，移除光阻層33及移除未為該金屬導電層 36及37接觸與連接之該晶種層32之部分(即光阻層33原覆蓋之該晶種層32之 部分) ，以分別形成 第一金屬線路微結構38及第二金屬線路微結構 39。於一些實施例中，移除光阻層33之方式可依據光阻層33為濕膜光阻或乾膜光阻而分別採用蝕刻方式或剝離方式實現。此外，移除 未與金屬導電層 36及37接觸與連接之晶種層32之該部分的方式可採用蝕刻方式實現，且不以此為限。於本實施例中，所製作完成之 第一金屬線路微結構38及第二金屬線路微結構 39其線寬係對應於第一溝槽圖案34及第二溝槽圖案35之該第一特定溝槽寬度 W 1 及該第二特定溝槽寬度 W 2 ，換言之， 第一金屬線路微結構38及第二金屬線路微結構39 之線寬亦可介於1μm至20μm之間，其中 第一金屬線路微結構38 之線寬範圍以介於1μm至5μm之間為較佳，且以3μm以下為更佳。由於 第一金屬線路微結構38 之線寬可以第一溝槽圖案34之第一特定溝槽寬度 W 1 而控制於1μm至5μm之間，特別是可控制於3μm以下，因此可應用於觸控面板之可視觸控區域之金屬線路(或金屬網格)，使其更細微化，且可提升金屬線路之透光率及不可視率。此外， 第二金屬線路微結構39 之線寬亦可控制介於1μm至20μm之間，且以介於5μm至20μm之間為較佳，因此可應用於觸控面板之非觸控區域之金屬線路，換言之，可作為觸控面板邊緣區域之金屬引線線路。此外， 第一金屬線路微結構38及第二金屬線路微結構39 之高度亦可對應於第一溝槽圖案34及第二溝槽圖案35之深度而可介於0.1μm至20μm之間，藉此可依據阻抗值之要求而調整 第一金屬線路微結構38及第二金屬線路微結構39 之高度以控制所形成之金屬線路的穩定性。Then, as shown in FIG. 5E and FIG. 6, in step S64, the photoresist layer 33 is removed and portions of the seed layer 32 that are not in contact and connected to the metal conductive layers 36 and 37 are removed (ie, light). The resist layer 33 is originally covered by the seed layer 32 to form a first metal line microstructure 38 and a second metal line microstructure 39, respectively. In some embodiments, the manner in which the photoresist layer 33 is removed may be implemented by etching or stripping, respectively, depending on whether the photoresist layer 33 is a wet film photoresist or a dry film photoresist. In addition, the manner of removing the portion of the seed layer 32 that is not in contact with and connected to the metal conductive layers 36 and 37 can be achieved by etching, and is not limited thereto. In this embodiment, the first metal line microstructure 38 and the second metal line microstructure 39 are formed to have a line width corresponding to the first specific groove of the first groove pattern 34 and the second groove pattern 35. The groove width W 1 and the second specific groove width W 2 , in other words, the line width of the first metal line microstructure 38 and the second metal line microstructure 39 may also be between 1 μm and 20 μm, wherein the first metal line The line width of the microstructure 38 is preferably between 1 μm and 5 μm, and more preferably 3 μm or less. Since the line width of the first metal line microstructure 38 can be controlled between 1 μm and 5 μm, and particularly can be controlled below 3 μm, the first specific groove width W 1 of the first trench pattern 34 can be applied to the touch. The metal lines (or metal mesh) of the visible touch area of the panel make it more subtle and can improve the transmittance and invisibility of the metal lines. In addition, the line width of the second metal line microstructure 39 can also be controlled between 1 μm and 20 μm, and preferably between 5 μm and 20 μm, so that the metal can be applied to the non-touch area of the touch panel. The line, in other words, can be used as a metal lead line in the edge area of the touch panel. In addition, the heights of the first metal line microstructures 38 and the second metal line microstructures 39 may also correspond to the depths of the first trench patterns 34 and the second trench patterns 35, and may be between 0.1 μm and 20 μm. This adjusts the height of the first metal line microstructure 38 and the second metal line microstructure 39 to control the stability of the formed metal line in accordance with the requirements of the impedance value.
第7圖係為 本案第三較佳實施例之製法應用於形成一觸控面板之金屬線路之示意 圖。如第7圖所示， 形成 之 第一金屬線路微結構38及第二金屬線路微結構39係分別位 於 觸控面板1之可視觸控區域及非觸控區域，其中可視觸控區域 之 第一金屬線路微結構3 8 係可控制於1μm至5μm之間，特別是可控制於3μm以下，藉此可使其更細微化，且可提升金屬線路之透光率及不可視率，而非觸控區域 之 第二金屬線路微結構3 9 可控制在5μm至20μm之間，用以作為觸控面板邊緣區域之金屬引線線路。此外，如第5A圖至第5E圖、第6圖及第7圖所示，本案 之金屬線路微結構之製法可利用同一製程步驟同時於基板上形成第一金屬線路微結構38及第二金屬線路微結構39，以分別作為觸控面板1之可視觸控區域之金屬線路及非觸控區域之金屬引線線路，藉此可簡化觸控面板1之製程步驟並降低製作成本。Figure 7 is a schematic view showing the application of the third preferred embodiment of the present invention to a metal circuit for forming a touch panel. As shown in FIG. 7 , the first metal line microstructure 38 and the second metal line microstructure 39 are respectively located in the visible touch area and the non-touch area of the touch panel 1 , wherein the first of the visible touch areas The metal line microstructure 3 8 system can be controlled between 1 μm and 5 μm, in particular, can be controlled below 3 μm, thereby making it more compact and improving the transmittance and invisibility of the metal line instead of touch. The second metal line microstructure 3 9 of the region can be controlled between 5 μm and 20 μm for use as a metal lead line in the edge region of the touch panel. In addition, as shown in FIG. 5A to FIG. 5E, FIG. 6 and FIG. 7, the metal wiring microstructure of the present invention can simultaneously form the first metal line microstructure 38 and the second metal on the substrate by the same process step. The line structure 39 is used as a metal line of the visible touch area of the touch panel 1 and a metal lead line of the non-touch area, thereby simplifying the manufacturing process of the touch panel 1 and reducing the manufacturing cost.
綜上所述，本案 提供一種 金屬線路微結構之製法，其可以較低成本製備更細微化之金屬線路，且於應用於觸控面板時可以提升金屬線路之透光率及不可視率。 此外，本案 金屬線路微結構之製法，其製作金屬線路的精細度較易控制，可製備具5μm以下線寬之金屬線路，可以提升產品良率，並可防止金屬線路氧化的發生。再則，本案金屬線路微結構之製法，其可利用同一製程步驟同時於基板上形成觸控面板之可視觸控區域及引線區域之金屬線路。In summary, the present invention provides a method for fabricating a metal line microstructure, which can prepare a more fine metal line at a lower cost, and can improve the light transmittance and invisibility rate of the metal line when applied to a touch panel. In addition, in the method of manufacturing the metal line microstructure of the present invention, the fineness of the metal circuit is relatively easy to control, and a metal line having a line width of 5 μm or less can be prepared, which can improve product yield and prevent oxidation of the metal line. Furthermore, in the method for fabricating the metal line microstructure of the present invention, the same process step can be used to simultaneously form the visible touch area of the touch panel and the metal line of the lead area on the substrate.
本案得由熟習此技術之人士任施匠思而為諸般修飾，然皆不脫如附申請專利範圍所欲保護者。This case has been modified by people who are familiar with the technology, but it is not intended to be protected by the scope of the patent application.
S20至S24‧‧‧本案之金屬線路微結構製法之流程步驟 S20 to S24‧‧‧ Process steps for the metal structure micro-structure method of this case
Claims (13)
(a)提供一基板；
(b)形成一晶種層於該基板之一表面上；
(c)形成一光阻層於該晶種層之該表面上，且進行一曝光及微影製程以於該光阻層中形成一溝槽圖案，其中該溝槽圖案具有一特定溝槽寬度；
(d)以電鍍方式將一金屬導電層填入該溝槽圖案；以及
(e)移除該光阻層及移除未為該金屬導電層接觸與連接之該晶種層之部分，以形成該金屬線路微結構。A method for fabricating a metal line microstructure, comprising the steps of:
(a) providing a substrate;
(b) forming a seed layer on a surface of the substrate;
(c) forming a photoresist layer on the surface of the seed layer, and performing an exposure and lithography process to form a trench pattern in the photoresist layer, wherein the trench pattern has a specific trench width ;
(d) filling a metal conductive layer into the trench pattern by electroplating;
(e) removing the photoresist layer and removing portions of the seed layer that are not in contact and connected to the metal conductive layer to form the metal line microstructure.
(a)提供一基板；
(b)形成一晶種層於該基板之一表面上；
(c)形成一光阻層於該晶種層之該表面上，且進行一曝光與微影製程以於該光阻層中形成一溝槽圖案，其中該溝槽圖案具有一特定溝槽寬度；
(d)以電鍍方式將一金屬導電層填入該溝槽圖案；
(e)將一抗氧化層填入該溝槽圖案，且該抗氧化層形成於該金屬導電層上；以及
(f)移除該光阻層及移除未為該金屬導電層接觸與連接之該晶種層之部分，以形成該金屬線路微結構。A method for fabricating a metal line microstructure, comprising the steps of:
(a) providing a substrate;
(b) forming a seed layer on a surface of the substrate;
(c) forming a photoresist layer on the surface of the seed layer, and performing an exposure and lithography process to form a trench pattern in the photoresist layer, wherein the trench pattern has a specific trench width ;
(d) filling a metal conductive layer into the trench pattern by electroplating;
(e) filling an anti-oxidation layer into the trench pattern, and the anti-oxidation layer is formed on the metal conductive layer;
(f) removing the photoresist layer and removing portions of the seed layer that are not in contact and connected to the metal conductive layer to form the metal line microstructure.
(a)提供一基板；
(b)形成一晶種層於該基板之一表面上；
(c)形成一光阻層於該晶種層之該表面上，且進行一曝光與微影製程以於該光阻層中形成一第一溝槽圖案及一第二溝槽圖案，其中該第一溝槽圖案具有一第一特定溝槽寬度，該第二溝槽圖案具有一第二特定溝槽寬度，該第二特定溝槽寬度係大於該第一特定溝槽寬度；
(d)將一金屬導電層分別填入該第一溝槽圖案及該第二溝槽圖案；以及
(e)移除該光阻層及移除未為該金屬導電層接觸與連接之該晶種層之部分，以形成一第一金屬線路微結構及一第二金屬線路微結構。A method for fabricating a metal line microstructure, comprising the steps of:
(a) providing a substrate;
(b) forming a seed layer on a surface of the substrate;
(c) forming a photoresist layer on the surface of the seed layer, and performing an exposure and lithography process to form a first trench pattern and a second trench pattern in the photoresist layer, wherein The first trench pattern has a first specific trench width, and the second trench pattern has a second specific trench width, the second specific trench width being greater than the first specific trench width;
(d) filling a metal conductive layer into the first trench pattern and the second trench pattern, respectively;
(e) removing the photoresist layer and removing portions of the seed layer that are not in contact and connected to the metal conductive layer to form a first metal line microstructure and a second metal line microstructure.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103118566A TW201545215A (en) | 2014-05-28 | 2014-05-28 | Method of manufacturing microstructures of metal lines |
| US14/329,009 US20150345042A1 (en) | 2014-05-28 | 2014-07-11 | Method of manufacturing microstructures of metal lines |
| JP2014148581A JP2015225650A (en) | 2014-05-28 | 2014-07-22 | Method for manufacturing fine structure of metal wiring line |
| KR1020140108229A KR20150136973A (en) | 2014-05-28 | 2014-08-20 | Method of manufacturing microstructures of metal lines |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103118566A TW201545215A (en) | 2014-05-28 | 2014-05-28 | Method of manufacturing microstructures of metal lines |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201545215A true TW201545215A (en) | 2015-12-01 |
Family
ID=54701081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW103118566A TW201545215A (en) | 2014-05-28 | 2014-05-28 | Method of manufacturing microstructures of metal lines |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20150345042A1 (en) |
| JP (1) | JP2015225650A (en) |
| KR (1) | KR20150136973A (en) |
| TW (1) | TW201545215A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110021461A (en) * | 2019-03-06 | 2019-07-16 | 苏州蓝沛光电科技有限公司 | The production method of transparent conductive film structure |
| WO2020073157A1 (en) * | 2018-10-08 | 2020-04-16 | 日本光电子化学株式会社 | Manufacturing method for second electrode circuit layer |
| CN111355026A (en) * | 2020-03-03 | 2020-06-30 | 安徽精卓光显技术有限责任公司 | Transparent antenna, manufacturing method thereof and electronic equipment |
| CN112584623A (en) * | 2019-09-27 | 2021-03-30 | 恒煦电子材料股份有限公司 | Method for manufacturing electroplated metal wire |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018047608A1 (en) * | 2016-09-08 | 2018-03-15 | 富士フイルム株式会社 | Conductive film production method, conductive film, touch panel sensor, antenna, fingerprint authentication, and touch panel |
| CN106406628A (en) * | 2016-11-17 | 2017-02-15 | 武汉华星光电技术有限公司 | Touch screen and manufacturing method thereof |
| KR20190089206A (en) | 2017-02-27 | 2019-07-30 | 후지필름 가부시키가이샤 | METHOD FOR MANUFACTURING CONDUCTIVE FILM, |
| WO2019065782A1 (en) * | 2017-09-29 | 2019-04-04 | 富士フイルム株式会社 | Conductive film, touch panel sensor, touch panel, and method for producing conductive film |
| JPWO2020137178A1 (en) * | 2018-12-27 | 2021-11-18 | パナソニックＩｐマネジメント株式会社 | Inspection method and manufacturing method of film body, touch sensor and touch sensor |
| CN110379322A (en) * | 2019-07-15 | 2019-10-25 | 深圳市华星光电半导体显示技术有限公司 | Display panel, display module and display device |
| JPWO2021171718A1 (en) | 2020-02-28 | 2021-09-02 | ||
| CN114300356B (en) * | 2021-12-07 | 2024-03-19 | 华东光电集成器件研究所 | Preparation method of microstructure metal pin for avalanche diode |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4927505A (en) * | 1988-07-05 | 1990-05-22 | Motorola Inc. | Metallization scheme providing adhesion and barrier properties |
| JP3038953B2 (en) * | 1991-02-28 | 2000-05-08 | ソニー株式会社 | Wiring formation method |
| JP2001217248A (en) * | 2000-02-04 | 2001-08-10 | Nec Corp | Method for forming wiring of semiconductor device |
| JP2003209415A (en) * | 2002-01-11 | 2003-07-25 | Murata Mfg Co Ltd | Forming method for metal wiring |
| KR100570856B1 (en) * | 2003-04-02 | 2006-04-12 | 삼성전기주식회사 | Method for fabricating the multi layer PCB in parallel |
| US7541275B2 (en) * | 2004-04-21 | 2009-06-02 | Texas Instruments Incorporated | Method for manufacturing an interconnect |
| JP5047504B2 (en) * | 2005-02-05 | 2012-10-10 | 三星電子株式会社 | Method for manufacturing dual damascene wiring of semiconductor device using via capping protective film |
| JP4738959B2 (en) * | 2005-09-28 | 2011-08-03 | 東芝モバイルディスプレイ株式会社 | Method for forming wiring structure |
| JP5145671B2 (en) * | 2006-08-24 | 2013-02-20 | 凸版印刷株式会社 | Method for manufacturing electromagnetic wave shielding member, electromagnetic wave shielding member, and image display device |
| JP2010040693A (en) * | 2008-08-04 | 2010-02-18 | Nippon Telegr & Teleph Corp <Ntt> | Method for forming pattern |
| US8334202B2 (en) * | 2009-11-03 | 2012-12-18 | Infineon Technologies Ag | Device fabricated using an electroplating process |
| US20120009777A1 (en) * | 2010-07-07 | 2012-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | UBM Etching Methods |
| US9190325B2 (en) * | 2010-09-30 | 2015-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | TSV formation |
| US8580687B2 (en) * | 2010-09-30 | 2013-11-12 | Infineon Technologies Ag | Semiconductor structure and method for making same |
| KR20120056051A (en) * | 2010-11-24 | 2012-06-01 | 삼성전자주식회사 | Method for manufacturing semiconductor package and the semiconductor package manufactured using the method |
| KR20140057047A (en) * | 2012-11-02 | 2014-05-12 | 삼성전기주식회사 | Touch screen panel and portable electronic apparatus having the same |
| US20140174791A1 (en) * | 2012-12-26 | 2014-06-26 | Unimicron Technology Corp. | Circuit board and manufacturing method thereof |
-
2014
- 2014-05-28 TW TW103118566A patent/TW201545215A/en unknown
- 2014-07-11 US US14/329,009 patent/US20150345042A1/en not_active Abandoned
- 2014-07-22 JP JP2014148581A patent/JP2015225650A/en active Pending
- 2014-08-20 KR KR1020140108229A patent/KR20150136973A/en not_active Application Discontinuation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020073157A1 (en) * | 2018-10-08 | 2020-04-16 | 日本光电子化学株式会社 | Manufacturing method for second electrode circuit layer |
| CN110021461A (en) * | 2019-03-06 | 2019-07-16 | 苏州蓝沛光电科技有限公司 | The production method of transparent conductive film structure |
| CN110021461B (en) * | 2019-03-06 | 2020-05-12 | 苏州蓝沛光电科技有限公司 | Method for manufacturing transparent conductive film structure |
| CN112584623A (en) * | 2019-09-27 | 2021-03-30 | 恒煦电子材料股份有限公司 | Method for manufacturing electroplated metal wire |
| CN111355026A (en) * | 2020-03-03 | 2020-06-30 | 安徽精卓光显技术有限责任公司 | Transparent antenna, manufacturing method thereof and electronic equipment |
| CN111355026B (en) * | 2020-03-03 | 2023-02-03 | 安徽精卓光显技术有限责任公司 | Transparent antenna, manufacturing method thereof and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2015225650A (en) | 2015-12-14 |
| KR20150136973A (en) | 2015-12-08 |
| US20150345042A1 (en) | 2015-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW201545215A (en) | Method of manufacturing microstructures of metal lines | |
| TWI584059B (en) | Method for manufacturing transparent photomask, transparent photomask manufactured by the method and method for manufacturing conductive mesh pattern using the transparent photomask | |
| KR102056928B1 (en) | Touch screen panel and method for manufacturing the same | |
| WO2018157814A1 (en) | Touch screen manufacturing method, touch screen ,and display device | |
| US7335538B2 (en) | Method for manufacturing bottom substrate of liquid crystal display device | |
| TW201419069A (en) | Structure and manufacturing method for the same | |
| WO2016045278A1 (en) | Ogs touch panel substrate and manufacturing method therefor, and related device | |
| TW202004460A (en) | Touch panel with transparent flexible electrodes and manufacturing methods thereof | |
| DE202011052063U1 (en) | electrode connection | |
| JP6070675B2 (en) | Method for producing transparent conductive substrate and touch panel sensor | |
| KR20130022170A (en) | Touch panel and its manufacturing method | |
| TW201419965A (en) | Method for manufacturing circuit | |
| WO2014094624A1 (en) | Touch control electrode structure and manufacturing process therefor | |
| TWI605361B (en) | Electrode substrate and touch panel | |
| KR101368994B1 (en) | Method of Preparing Pad for Touch Panel | |
| CN111722742A (en) | Transparent conductive film and preparation method thereof | |
| KR101647307B1 (en) | Single layered touch panel and method for preparing the same | |
| KR101551859B1 (en) | Method for Etching Using Metal Layer as Etching Resist | |
| CN105278709A (en) | Manufacturing method of metal circuit micro-structures | |
| WO2014094622A1 (en) | Touch control electrode structure and manufacturing process therefor | |
| CN105824467A (en) | Large-window touch panel and manufacturing method thereof | |
| JP6358488B2 (en) | Method for producing offset printing cliché and offset printing cliché | |
| KR101826599B1 (en) | Single layered touch panel and method for preparing the same | |
| KR102251870B1 (en) | Touch window | |
| KR102551528B1 (en) | Stack structure and touch sensor |