WO2014079657A1 - Verfahren zur herstellung eines anschlussbereichs eines optoelektronischen halbleiterchips - Google Patents
Verfahren zur herstellung eines anschlussbereichs eines optoelektronischen halbleiterchips Download PDFInfo
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- WO2014079657A1 WO2014079657A1 PCT/EP2013/072507 EP2013072507W WO2014079657A1 WO 2014079657 A1 WO2014079657 A1 WO 2014079657A1 EP 2013072507 W EP2013072507 W EP 2013072507W WO 2014079657 A1 WO2014079657 A1 WO 2014079657A1
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- WIPO (PCT)
- Prior art keywords
- layer
- seed layer
- semiconductor chip
- optoelectronic semiconductor
- seed
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 175
- 230000005693 optoelectronics Effects 0.000 title claims abstract description 88
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 62
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 31
- 238000000151 deposition Methods 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 338
- 238000000034 method Methods 0.000 claims description 51
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 46
- 238000003892 spreading Methods 0.000 claims description 39
- 230000007480 spreading Effects 0.000 claims description 39
- 230000004888 barrier function Effects 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 25
- 230000008021 deposition Effects 0.000 claims description 23
- 229910052763 palladium Inorganic materials 0.000 claims description 23
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 16
- 229910052737 gold Inorganic materials 0.000 claims description 16
- 239000010931 gold Substances 0.000 claims description 16
- 150000002739 metals Chemical class 0.000 claims description 10
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 239000012790 adhesive layer Substances 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052742 iron Inorganic materials 0.000 claims description 3
- 229910052703 rhodium Inorganic materials 0.000 claims description 3
- 239000010948 rhodium Substances 0.000 claims description 3
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 claims description 3
- 238000004070 electrodeposition Methods 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims 1
- 238000002161 passivation Methods 0.000 description 17
- 150000001875 compounds Chemical class 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 5
- 230000005670 electromagnetic radiation Effects 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- -1 nitride compound Chemical class 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 238000010025 steaming Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000032683 aging Effects 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 239000003638 chemical reducing agent Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000003595 spectral effect Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910000480 nickel oxide Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000006479 redox reaction Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
Definitions
- a method for producing a connection region of an optoelectronic semiconductor chip is specified.
- optoelectronic semiconductor chip can be produced, which is characterized by a particularly good corrosion resistance.
- Semiconductor chip is, for example, in the wafer composite. That is, a multiplicity of optoelectronic semiconductor chips may be provided, wherein in each case at least one connection region is produced by means of the method for each semiconductor chip of the wafer composite.
- the optoelectronic semiconductor chip is, for example, a light-emitting diode chip.
- Optoelectronic semiconductor chip can be adapted to operate in the electromagnetic radiation from the
- the optoelectronic semiconductor chip has for it a semiconductor body based on, for example, a III-V compound semiconductor material.
- a III-V compound semiconductor material has at least one element of the third main group such as B, Al, Ga, In, and a fifth main group element such as N, P, As.
- the third main group such as B, Al, Ga, In
- a fifth main group element such as N, P, As.
- III-V compound semiconductor material means the group of binary, ternary or quaternary compounds which
- At least one element from the third main group and at least one element from the fifth main group for example, nitride and phosphide compound semiconductors.
- Such a binary, ternary or quaternary compound may also have, for example, one or more dopants and additional constituents.
- the semiconductor body may be based on a nitride compound semiconductor material.
- “Based on nitride compound semiconductor material” means in
- the semiconductor body or at least a part thereof, particularly preferably at least one active zone and / or a growth substrate wafer, a nitride compound semiconductor material, preferably Al n Ga m In ] __ n _ m N comprises or consists of, wherein 0 ⁇ n ⁇ 1, 0 ⁇ m ⁇ 1 and n + m ⁇ 1.
- this material does not necessarily have to have a mathematically exact composition according to the above formula. Rather, it may, for example, have one or more dopants and additional constituents.
- a seed layer is formed or exposed on an outer surface of the optoelectronic semiconductor chip. That is, in a certain, limited area of the outer surface of the
- Optoelectronic semiconductor chips is the attachment or exposure of a seed layer.
- the seed layer is already present in the optoelectronic semiconductor chip and by removing material over the
- Seed layer the seed layer is exposed so that it is freely accessible on the outer surface of the optoelectronic semiconductor chip.
- the seed layer is after formation or exposure on the outer surface of the optoelectronic
- the seed layer then serves as a start layer for forming the attachment region at the seed layer.
- the Contact layer sequence comprises at least two layers which are formed with mutually different materials, in particular with mutually different metals.
- the contact layer sequence is deposited at least partially without current. That is, at least one layer of the
- Contact layer sequence are applied by electroless deposition on the seed layer.
- the deposition of the seed layer is applied by electroless deposition on the seed layer.
- Oxidizing agents are present in a solution, so that the deposition is carried out by a redox reaction of different noble metals.
- the seed layer is formed with a metal which allows the electroless deposition of nickel on the seed layer. That is, the seed layer in particular allows one
- the seed layer offers good starting properties for the autocatalytic nickel deposition.
- the contact layer sequence comprises as the first, the seed layer
- Contact layer sequence comprises at least one nickel layer, the nickel layer directly adjacent to the seed layer and is applied to the seed layer, for example, by an autocatalytic deposition process.
- the contact layer sequence has its seed layer
- the contact layer sequence becomes on its side facing away from the seed layer of a contact surface
- Semiconductor chip can be produced. About the
- Contact surface can be electrical current through the
- Contact layer sequence are impressed into the optoelectronic semiconductor chip and there stimulate the generation of electromagnetic radiation, for example.
- connection region of the optoelectronic semiconductor chip is formed by the seed layer, the contact layer sequence and the contact layer terminating contact surface.
- the contact surface is formed by an outer surface of the outermost layer of the contact layer sequence, which faces away from the seed layer.
- the method comprises the following steps:
- the seed layer is formed with a metal which allows the electroless deposition of nickel on the seed layer
- the contact layer sequence comprises a nickel layer as the first layer facing the seed layer
- the contact layer sequence on its side facing away from the seed layer has a contact surface over which the Optoelectronic semiconductor chip is electrically contacted.
- Pads formed (locally: Pads), which are strongly limited locally, since the emission area of the
- Pad should be, so as much as possible
- connection areas are subject to high demands with regard to their adhesion to the optoelectronic semiconductor chip, their aging stability, their connectivity and their contact resistance
- Aging stability are particularly preferably used precious metals such as gold or platinum to form the terminal areas.
- precious metals such as gold or platinum
- these expensive materials can often only be used partially because the connection area is initially formed over a large area, for example by sputtering or steaming, and then by a
- Structuring step is at least partially removed again. This results in high costs.
- connection region by electroless deposition only selectively there on the optoelectronic semiconductor chip, where it remains in the finished optoelectronic semiconductor chip. This makes it possible to reduce the material costs.
- an electroless deposition process is used to form the terminal region. A connection area made with this method is characterized by its good
- Terminal area which is produced by the electroless deposition process, by a high layer conformity of the layers of the contact layer sequence and a high
- a seed layer is used, which allows the electroless deposition of nickel.
- Connection area are applied directly to the semiconductor body. In addition, it is possible that the
- Terminal area laterally spaced from the semiconductor body is arranged.
- the seed layer is formed with one of the following metals or consists of one of the following metals: nickel, rhodium, palladium, cobalt, iron, gold.
- Palladium are particularly well suited to the electroless deposition of a nickel layer on the seed layer
- the contact layer sequence is characterized by the following sequence of metals formed or consists of the following sequence of metals: nickel, palladium, gold. That is, the contact layer sequence includes, for example, a nickel layer, a
- the nickel layer is that layer which directly follows the seed layer and which directly adjoins the seed layer.
- the palladium layer can be applied directly to the nickel layer and border directly on the nickel layer on the side of the nickel layer facing away from the seed layer.
- the gold layer can be applied directly to the palladium layer and directly adjoin the palladium layer on the side of the palladium layer facing away from the nickel layer. The palladium layer facing away from the outer surface of the gold layer then forms the contact surface of the
- the contact surface is designed to be wire-contactable. That is, the contact surface can be contacted by a wire bonding process, that is, for example, by wire bonding.
- the wire can be formed with gold or aluminum.
- Gold layer is formed, is particularly suitable for
- the seed layer is applied to the optoelectronic semiconductor chip by one of the following materials on the outer surface of the optoelectronic semiconductor chip: steaming, Sputtering, electroless plating, electrochemical deposition. That is, in the case where the seed layer is formed on the outer surface of the optoelectronic semiconductor chip, that is, the seed layer is not exposed, for example, one of the above-mentioned production methods for forming the seed layer is used.
- a passivation layer is locally removed on the outer surface of the optoelectronic semiconductor chip using a mask layer and the deposition of the seed layer is carried out using the same mask layer prior to the application of the seed layer.
- the mask layer is applied to the passivation layer, for example.
- a window can be produced in the mask layer, through which the passivation layer located below the mask layer in the region of the window is selectively removed.
- a layer of the optoelectronic semiconductor chip is then exposed, via which the optoelectronic semiconductor chip can be electrically contacted. At this exposed outer surface of the
- Seed layer for example, in the window of the mask layer
- the contact layer sequence which can be applied by electroless deposition, are applied using the pre-existing mask layer.
- the mask layer can be removed or remain as an additional passivation material in the optoelectronic semiconductor chip.
- the seed layer is present in the optoelectronic semiconductor chip and the seed layer is exposed by locally removing material arranged above the seed layer.
- an electrically insulating passivation layer is present on the outer surface of the optoelectronic semiconductor chip above the seed layer.
- Contacting layer sequence is exposed.
- the exposure of the seed layer may also be by alternative methods, such as by laser ablation without the use of a mask layer.
- the seed layer In the case of a seed layer which is already present in the optoelectronic semiconductor chip, it is possible for the seed layer to be located below a semiconductor body of the semiconductor body
- Semiconductor body comprises an active area. In active
- the seed layer is integrated in the layer stack of the optoelectronic semiconductor chip and can be below the
- a seed layer which is integrated in this way in the optoelectronic semiconductor chip, can there in addition to their function as seed layer for the formation of
- Contact layer sequence further functions such as the function of an adhesion-promoting layer, a
- Semiconductor chip can be used.
- the seed layer prefferably be an electrically conductive layer which forms part of a current spreading layer of the optoelectronic layer
- the seed layer is compared to methods with which the semiconductor body of the optoelectronic semiconductor chip is structured,
- a mesa etching with hot acid which has a temperature of greater than 100 ° C.
- phosphoric acid having a temperature of greater than 160 ° C, for example 170 ° C
- the seed layer is resistant to this patterning process.
- a seed layer formed with palladium has this etch resistance. With such a seed layer, it is possible to structure the semiconductor body completely wet-chemically.
- the optoelectronic semiconductor chip has a
- the current spreading layer is electrically connected to a p-type semiconductor region below the p-type
- the current spreading layer is preferably connected in an electrically conductive manner to the seed layer and thus to the connection region produced by the method described here, so that contacting of the
- the seed layer is part of a layer stack of the current spreading layer.
- the current spreading layer is then formed in this case of at least two layers, of which the seed layer on the side facing the semiconductor body
- the seed layer is covered on its side facing the semiconductor body by a barrier layer.
- the seed layer is not on an outer surface of the
- the barrier layer can prevent undesired diffusion processes between the mirror layer and the current spreading layer. That is, the barrier layer takes over
- Mirror layer can then, for example, with a for
- Migration prone material such as silver are formed. That is, the layer sequence under the semiconductor body of the optoelectronic semiconductor chip can then from the
- Semiconductor body can be seen as follows: Semiconductor body, mirror layer, barrier layer, seed layer, further layers of the current spreading layer.
- the current spreading layer on the outer surface of the current spreading layer on the outer surface of the current spreading layer
- Seed layer is applied to the exposed area of the
- the exposed area of the current spreading layer may then be formed by the barrier layer.
- the seed layer does not extend below the semiconductor body, but is only selectively generated from the outside.
- Seed layer can, for example, on the
- the optoelectronic semiconductor chip comprises a through-connection which extends through the active region of the semiconductor body and a connection means with one
- Semiconductor region of the semiconductor body is electrically connected.
- the via then extends through the
- Connecting means which is formed for example with a solder material, is electrically conductively connected via the plated-through hole to the n-conductive semiconductor region and serves to energize the semiconductor body from its n-conductive side.
- the seed layer is part of the layer stack of
- Semiconductor body of the optoelectronic semiconductor chip can, for example, laterally of the semiconductor body
- the ⁇ be exposed.
- the ⁇ may be exposed.
- the ⁇ may be exposed.
- the ⁇ may be exposed.
- the ⁇ may be exposed.
- the ⁇ may be exposed.
- the current spreading layer can in this case be a barrier layer facing the semiconductor body, the seed layer, a current-carrying layer and a
- Bonding layer include.
- the adhesion-promoting layer is then the semiconductor body of the semiconductor chip
- the barrier layer applied to the seed layer is characterized by good adhesion to dielectric layers and can
- the metal with which the seed layer is formed to be etched selectively wet-chemically.
- the barrier layer can be removed. If the barrier layer is formed with a metal prone to oxidation, for example, then the
- Barrier layer preferably opened shortly before the deposition of the contact layer sequence.
- the barrier layer may allow the use of cheaper, oxidation-prone metals for the seed layer.
- FIG. 1 shows an optoelectronic semiconductor chip 100, on the outer surface 100a of which there is a connection region 70 which is provided with a method described here
- the optoelectronic semiconductor chip 100 is, for example, a light-emitting diode chip.
- the semiconductor chip 100 comprises a semiconductor body 1.
- the semiconductor body 1 is based, for example, on a nitride-based
- the semiconductor body 1 comprises an n-type
- the optoelectronic semiconductor chip further comprises a mirror layer 2.
- the mirror layer 2 is provided with a highly conductive and reflective metal such as
- the mirror layer 2 is in electrically conductive contact with the p-type semiconductor region 13.
- the semiconductor chip 100 further includes a
- the current spreading layer 3 is arranged on the underside of the mirror layer 2 facing away from the semiconductor body 1 and extends in the lateral direction in a region in which the semiconductor body 1 is removed, for example, by a mesa etching.
- the lateral direction is a direction to the
- Growth direction of the semiconductor body is perpendicular.
- the semiconductor chip 100 further includes a
- Passivation layer 4 which electrically isolates the current spreading layer 3 from a connecting means 8, which may be, for example, a solder material.
- the connecting means 8 is electrically conductively connected to the n-type semiconductor region 11 via a via 5, which may be formed with the same material as the connecting means 8.
- the via 5 is electrically insulated laterally by the passivation layer 4 from the current spreading layer 3, the mirror layer 2, the p-type semiconductor region 13 and the active region 12.
- the via 5 extends through the active region 12 to the n-type semiconductor region.
- the semiconductor chip 100 further includes a carrier 9, which is connected via the connecting means 8 with the remaining components of the semiconductor chip.
- a contact of the Semiconductor chips 100 can on the n-side, for example via the carrier 9, which is formed in this case electrically conductive.
- An electrically insulating passivation layer 4 also extends along the flanks and the carrier 9
- the passivation layer 4 is removed in places. For example, the
- Passivation layer 4 which is formed with a dielectric material such as SiN or S1O2, are opened by means of a mask layer, not shown. In the opening is on the outer surface 100a the
- the seed layer 6 is formed for example with palladium and has a
- Contact layer sequence 7 applied which in the present case a nitride layer 71, a palladium layer 72 and a
- Gold layer 73 includes. At the seed layer 6 side facing away from the contact layer sequence 7, the
- Contact surface 7a is for wire bonding of
- the seed layer 6 and the contact layer sequence 7 with the contact surface 7a form the connection region 70, which is produced by means of a method described here.
- the optoelectronic semiconductor chip 100 is manufactured by means of two separate lithographic masks for structuring the mirror layer 2 and the current spreading layer 3.
- the seed layer 6 is deposited after the opening of the dielectric passivation layer 4 and consists in the present case of a thin palladium layer.
- FIG. 2 shows an optoelectronic semiconductor chip 100, in which the connection region 70 is produced by means of a method described here, wherein the seed layer 6 is already in the semiconductor chip 100 and is exposed before the application of the contact layer sequence 7. Also the
- Optoelectronic semiconductor chip 100 of FIG. 2 is manufactured with two separate lithographic masks for structuring the mirror layer 2 and the current spreading layer 3.
- the seed layer 6 is part of the current spreading layer.
- the current spreading layer comprises a
- Adhesive layer 31 which adjoins the passivation layer 4 and an adhesion to the passivation layer 4
- the adhesion promoting layer 31 may
- the current spreading layer 3 further comprises the following materials: titanium, chromium, aluminum, ZnO, ITO or other TCO (Transparent Conductive Oxide) materials.
- the current spreading layer 3 further comprises the following materials: titanium, chromium, aluminum, ZnO, ITO or other TCO (Transparent Conductive Oxide) materials.
- the Current-carrying layer 32 may be formed, for example, with one of the following materials: gold, aluminum, copper.
- the current-carrying layer 32 follows the seed layer 6, which may be formed, for example, with palladium, nickel, iron, rhodium, cobalt or gold.
- the barrier layer 33 is applied, which is formed for example with TiWN.
- Barrier layer 33 has good adhesion to dielectric layers and can be etched selectively wet-chemically, for example, into palladium.
- a barrier layer with TiWN is resistant to hot phosphoric acid, so that it is not attacked during a mesa etching to pattern the semiconductor body 1.
- the barrier layer 33 forms a diffusion barrier between the mirror layer 2 and the remaining layers of the current spreading layer 3.
- Seed layer 6 is used, then the formation of a
- Nickel oxide layer containing an autocatalytic reaction Nickel oxide layer containing an autocatalytic reaction
- Current spreading layer 3 is TiWN as the barrier layer 33,
- Adhesive layer 31 The layer stack for forming the current spreading layer 3, as described in connection with FIG. 2, can also be used in the exemplary embodiment of FIG. 1, wherein the seed layer 6 is then not arranged in the layer stack of the current spreading layer 3 and the
- Barrier layer 33 follows directly.
- the barrier layer can be palladium-activated by a suitable chemical process.
- the mirror layer 2 and the current spreading layer 3 in this embodiment are structured in common via a single lithographic mask.
- the mirror layer 2 the
- connection area 70 the connection area 70
- Barrier layer 33 which is formed with TiWN, as special advantageous since it can be etched wet-chemically selectively to a seed layer 6, which is formed for example with palladium.
- a method for producing a connection region 70, as described here, can also be used for other optoelectronic semiconductor chips, in which the connection region 70 is applied directly to the semiconductor body 1, for example.
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Abstract
Description
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/646,704 US9461211B2 (en) | 2012-11-21 | 2013-10-28 | Method for producing a connection region of an optoelectronic semiconductor chip |
DE112013005579.1T DE112013005579A5 (de) | 2012-11-21 | 2013-10-28 | Verfahren zur Herstellung eines Anschlussbereichs eines optoelektronischen Halbleiterchips |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102012111245.2A DE102012111245A1 (de) | 2012-11-21 | 2012-11-21 | Verfahren zur Herstellung eines Anschlussbereichs eines optoelektronischen Halbleiterchips |
DE102012111245.2 | 2012-11-21 |
Publications (1)
Publication Number | Publication Date |
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WO2014079657A1 true WO2014079657A1 (de) | 2014-05-30 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/EP2013/072507 WO2014079657A1 (de) | 2012-11-21 | 2013-10-28 | Verfahren zur herstellung eines anschlussbereichs eines optoelektronischen halbleiterchips |
Country Status (4)
Country | Link |
---|---|
US (1) | US9461211B2 (de) |
KR (1) | KR20150087352A (de) |
DE (2) | DE102012111245A1 (de) |
WO (1) | WO2014079657A1 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102447089B1 (ko) * | 2015-12-16 | 2022-09-26 | 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 | 자외선 발광소자 및 발광소자 패키지 |
DE102018120490A1 (de) * | 2018-08-22 | 2020-02-27 | Osram Opto Semiconductors Gmbh | Optoelektronisches halbleiterbauelement mit einer halbleiterkontaktschicht und verfahren zur herstellung des optoelektronischen halbleiterbauelements |
WO2020073295A1 (zh) * | 2018-10-11 | 2020-04-16 | 厦门市三安光电科技有限公司 | 一种发光二极管元件及其制作方法 |
JP6845483B2 (ja) * | 2018-11-26 | 2021-03-17 | 日亜化学工業株式会社 | 発光素子の製造方法 |
Citations (5)
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US20080032434A1 (en) * | 2006-08-07 | 2008-02-07 | Epistar Corporation | Method for making a light emitting diode by electroless plating |
WO2010012267A1 (de) | 2008-07-29 | 2010-02-04 | Osram Opto Semiconductors Gmbh | Optoelektronischer halbleiterchip und optoelektronisches bauteil |
DE102010009717A1 (de) * | 2010-03-01 | 2011-09-01 | Osram Opto Semiconductors Gmbh | Leuchtdiodenchip |
EP2402995A2 (de) * | 2010-07-01 | 2012-01-04 | LG Innotek Co., Ltd. | Lichtemittierende Vorrichtung und Beleuchtungseinheit |
EP2472602A2 (de) * | 2011-01-03 | 2012-07-04 | Semileds Optoelectronics Co., Ltd. | Vertikaler Leuchtdiodenchip (VLED) und Herstellungsverfahren |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
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DE102007022947B4 (de) * | 2007-04-26 | 2022-05-05 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronischer Halbleiterkörper und Verfahren zur Herstellung eines solchen |
ATE503037T1 (de) * | 2008-10-17 | 2011-04-15 | Atotech Deutschland Gmbh | Spannungsreduzierte ni-p/pd-stapel für waferoberfläche |
DE102009010480A1 (de) * | 2009-02-25 | 2010-09-02 | Samsung Electro-Mechanics Co., Ltd., Suwon | Halbleiter-Lichtemissionsvorrichtung, Verfahren zum Herstellen derselben und Halbleiter-Lichtemissionsvorrichtungs-Baugruppe, die diese verwendet |
KR100969126B1 (ko) * | 2009-03-10 | 2010-07-09 | 엘지이노텍 주식회사 | 발광 소자 |
DE102009060749B4 (de) * | 2009-12-30 | 2021-12-30 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronischer Halbleiterchip |
DE102010045390A1 (de) * | 2010-09-15 | 2012-03-15 | Osram Opto Semiconductors Gmbh | Optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung eines optoelektronisches Halbleiterbauteils |
-
2012
- 2012-11-21 DE DE102012111245.2A patent/DE102012111245A1/de not_active Withdrawn
-
2013
- 2013-10-28 KR KR1020157016223A patent/KR20150087352A/ko not_active Application Discontinuation
- 2013-10-28 WO PCT/EP2013/072507 patent/WO2014079657A1/de active Application Filing
- 2013-10-28 DE DE112013005579.1T patent/DE112013005579A5/de active Pending
- 2013-10-28 US US14/646,704 patent/US9461211B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080032434A1 (en) * | 2006-08-07 | 2008-02-07 | Epistar Corporation | Method for making a light emitting diode by electroless plating |
WO2010012267A1 (de) | 2008-07-29 | 2010-02-04 | Osram Opto Semiconductors Gmbh | Optoelektronischer halbleiterchip und optoelektronisches bauteil |
DE102010009717A1 (de) * | 2010-03-01 | 2011-09-01 | Osram Opto Semiconductors Gmbh | Leuchtdiodenchip |
EP2402995A2 (de) * | 2010-07-01 | 2012-01-04 | LG Innotek Co., Ltd. | Lichtemittierende Vorrichtung und Beleuchtungseinheit |
EP2472602A2 (de) * | 2011-01-03 | 2012-07-04 | Semileds Optoelectronics Co., Ltd. | Vertikaler Leuchtdiodenchip (VLED) und Herstellungsverfahren |
Also Published As
Publication number | Publication date |
---|---|
KR20150087352A (ko) | 2015-07-29 |
DE102012111245A1 (de) | 2014-05-22 |
DE112013005579A5 (de) | 2015-08-27 |
US20150295137A1 (en) | 2015-10-15 |
US9461211B2 (en) | 2016-10-04 |
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