WO2014075267A1 - Procédé de traitement de décodage et décodeur - Google Patents

Procédé de traitement de décodage et décodeur Download PDF

Info

Publication number
WO2014075267A1
WO2014075267A1 PCT/CN2012/084675 CN2012084675W WO2014075267A1 WO 2014075267 A1 WO2014075267 A1 WO 2014075267A1 CN 2012084675 W CN2012084675 W CN 2012084675W WO 2014075267 A1 WO2014075267 A1 WO 2014075267A1
Authority
WO
WIPO (PCT)
Prior art keywords
sequence
decoding
matrix
turbo code
likelihood ratio
Prior art date
Application number
PCT/CN2012/084675
Other languages
English (en)
Chinese (zh)
Inventor
熊杰
魏岳军
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP12888467.3A priority Critical patent/EP2838204B1/fr
Priority to PCT/CN2012/084675 priority patent/WO2014075267A1/fr
Priority to CN201280028136.2A priority patent/CN104025459B/zh
Publication of WO2014075267A1 publication Critical patent/WO2014075267A1/fr
Priority to US14/488,168 priority patent/US9214958B2/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1108—Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/296—Particular turbo code structure
    • H03M13/2966—Turbo codes concatenated with another code, e.g. an outer block code
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3707—Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/45—Soft decoding, i.e. using symbol reliability information
    • H03M13/451—Soft decoding, i.e. using symbol reliability information using a set of candidate code words, e.g. ordered statistics decoding [OSD]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/613—Use of the dual code
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Definitions

  • Embodiments of the present invention relate to communication technologies, and in particular, to a decoding processing method and a decoder. Background technique
  • the Turbo code is a forward error correction channel coding and decoding technology.
  • the encoder is composed of two recursive cyclic convolutional codes and is connected in parallel by an interleaver.
  • the feedback iterative decoding method is adopted.
  • the Turbo code iterative decoding method assisted by the list Viterbi algorithm in the prior art is mainly based on the original Turbo iterative decoding, and the iterative output softness is used to perform the list watts.
  • the ratio algorithm outputs multiple optimal paths, and the Cyclical Redundancy Check (CRC) performs error frame detection and early termination or suboptimal path output.
  • CRC Cyclical Redundancy Check
  • Embodiments of the present invention provide a Turbo code decoding method and device to improve decoding gain.
  • an embodiment of the present invention provides a decoding processing method, including:
  • a matrix G c is generated in conjunction with the cyclic redundancy check CRC generation matrix G crc . m , and obtaining a log likelihood ratio sequence output by the Turbo code decoder;
  • the CRC-assisted Turbo code iterative sorting statistical decoding is performed by using the joint generation matrix G ⁇ m and the log likelihood ratio value sequence, and the decoding processing result is obtained.
  • the specific implementation is: Taking a log likelihood ratio sequence output by the Turbo code decoder, including:
  • the log likelihood ratio of each iteration output is accumulated to obtain the accumulated log likelihood ratio sequence.
  • the specific implementation is: using the joint generation matrix G e . m and the log likelihood ratio sequence, performing CRC-assisted Turbo code iterative sorting statistical decoding, and obtaining decoding processing results, including:
  • Obtaining a reliability sequence by taking an absolute value of the log likelihood ratio value in the log likelihood ratio sequence; sorting a log likelihood ratio absolute value in the reliability sequence, and obtaining, according to the correspondence relationship, Sorted joint generation matrix O ⁇ Gc ⁇ ) and hard decision sequence OC);
  • Gaussian elimination is performed on the sorted joint generation matrix OG ⁇ m ⁇ , and the Gaussian-eliminated matrix G gauss and the matrix 0 2 are obtained , and according to the correspondence relationship and the matrix 0 2 , the hardened again is obtained.
  • Sequence 0 2 ( OJCQ ) is performed on the sorted joint generation matrix OG ⁇ m ⁇ , and the Gaussian-eliminated matrix G gauss and the matrix 0 2 are obtained , and according to the correspondence relationship and the matrix 0 2 , the hardened again is obtained.
  • Sequence 0 2 ( OJCQ )
  • the rouge 1 is the original information sequence length.
  • the method further includes:
  • the decoding process and the Euclidean distance of the information sequence received by the Turbo code decoder are less than a preset decision threshold, the decision is passed, and the decoding result is output;
  • the performing bit flipping decoding includes:
  • the preset determination threshold is determined by:
  • an embodiment of the present invention provides a decoder, including:
  • Receiver used to obtain the Turbo code generation matrix G tob . And cyclic redundancy check, CRC generator matrix G crc combined generator matrix G ⁇ m, and acquires the number of Turbo code decoder likelihood ratio sequence output;
  • the processor is configured to perform CRC-assisted Turbo code iterative sorting statistical decoding by using the joint generation matrix G ⁇ m and the log likelihood ratio value sequence, and obtain a decoding processing result.
  • the specific implementation is: the receiver is specifically configured to:
  • the log likelihood ratio of each iteration output is accumulated to obtain the accumulated log likelihood ratio sequence.
  • Obtaining a reliability sequence by taking an absolute value of the log likelihood ratio value in the log likelihood ratio sequence; sorting a log likelihood ratio absolute value in the reliability sequence, and obtaining, according to the correspondence relationship, Sorted joint generation matrix O ⁇ Gc ⁇ ) and hard decision sequence OC);
  • Gaussian elimination is performed on the sorted joint generation matrix O ⁇ Gc ⁇ , and the Gaussian-eliminated matrix G gauss and the matrix 0 2 are obtained , and are sorted according to the correspondence and the matrix 0 2 .
  • Hard judgment sequence 0 2 OJCQ ) ; Obtaining a statistically decoded codeword according to the pre-K m column of the hard decision sequence 0 2 ( OJCQ ) and the Gaussian-erased matrix G GAUSS, and performing reverse sequence rearrangement to obtain a decoding result dK 1 ( o 2 - c ) ) , the ⁇ is the length of the original information sequence.
  • the processor is further specifically configured to:
  • the decoding process and the Euclidean distance of the information sequence received by the Turbo code decoder are less than a preset decision threshold, the decision is passed, and the decoding result is output;
  • the decoding module is specifically configured to:
  • the processor is further configured to:
  • the Turbo code decoding method and the decoder provided by the embodiment of the present invention obtain the Turbo code generation matrix G tob by acquiring the Turbo code decoding method. Coupling the matrix G ⁇ m with the cyclic redundancy check CRC generation matrix G crc , and obtaining the log likelihood ratio sequence output by the Turbo code decoder, using the joint generation matrix G ⁇ m and the log likelihood ratio sequence
  • the CRC-assisted Turbo code iterative sorting statistical decoding is performed to obtain the decoding processing result, which can improve the decoding performance of the Turbo code and obtain a higher decoding gain than the prior art.
  • Embodiment 1 is a schematic flowchart of Embodiment 1 of a decoding processing method according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of an encoding process according to an embodiment of the present invention.
  • Embodiment 3 is a schematic flowchart of Embodiment 2 of a decoding processing method according to an embodiment of the present invention
  • Embodiment 4 is a schematic flowchart of Embodiment 3 of a decoding processing method according to an embodiment of the present invention
  • FIG. 5 is a schematic flowchart of Embodiment 4 of a decoding processing method according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram 1 of a decoding performance curve of a decoding processing method according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram 2 of a decoding performance curve of a decoding processing method according to an embodiment of the present invention
  • FIG. 8 is a decoding processing method according to an embodiment of the present invention
  • FIG. 9 is a schematic diagram of a decoding performance curve of a decoding processing method according to an embodiment of the present invention
  • FIG. 10 is a schematic diagram of a decoding performance curve of a decoding processing method according to an embodiment of the present invention
  • FIG. FIG. 12 is a schematic structural diagram of a decoder according to an embodiment of the present invention
  • FIG. 13 is a schematic structural diagram of Embodiment 2 of a decoder according to an embodiment of the present invention.
  • the technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. example. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
  • the decoding processing method in the embodiment of the present invention can be applied to decoding at the receiving end in the communication system.
  • a Long Term Evolution (LTE) communication system is taken as an example to describe a Turbo code decoding method, but the embodiment of the present invention is not limited thereto, and is restored by using Turbo code decoding.
  • the data can be decoded by the Turbo code of the embodiment of the present invention. The law is implemented.
  • Embodiment 1 is a schematic flowchart of Embodiment 1 of a decoding processing method according to an embodiment of the present invention, as shown in FIG.
  • S102 Perform a CRC-assisted Turbo code iterative sorting statistical decoding by using a joint generation matrix (3 ⁇ 111 and a log likelihood ratio sequence) to obtain a decoding processing result.
  • the CRC code is performed before the turbo code is encoded.
  • the output of the Turbo code encoder is actually a Turbo-CRC concatenated code.
  • the encoding process is shown in Figure 2.
  • the CRC generation matrix is considered together with the Turbo code generation matrix, and participates in decoding together, so that the decoding is converted into a cascading coding mode.
  • step S101 the Turbo code in the LTE communication system is formed by paralleling two recursive system volume integral quantity codes, and the generator polynomial of the single recursive system volume integral quantity code is:
  • K is the length of the information sequence to be encoded
  • / ⁇ is the unit matrix of the first K column after Gaussian elimination
  • D is the polynomial variable
  • U ⁇ ⁇ is the matrix after column exchange according to the interleaver interleave address.
  • G crc ] ( 5 )
  • X is the unit array of Gaussian elimination in the front row
  • m x24 is obtained by sequentially shifting the generator polynomial shown in equation ( 4 ).
  • the joint generation matrix of the final CRC code and Turbo code is:
  • the output value is the log likelihood ratio order of the information ⁇ 1.
  • the log likelihood ratio sequence of the information can be obtained by a conventional iterative decoding algorithm.
  • the conventional iterative decoding algorithm includes Maximum A Posteriori (MAP) and other Turbo code decoding algorithms with soft output, such as Soft-Output Viterbi Algorithm (SOVA). )Wait.
  • the Turbo code decoding method provided by the embodiment of the present invention is applicable to all iterative decoding capable of implementing soft input and output.
  • the MAP algorithm is a commonly used Turbo decoding algorithm, and the MAP algorithm includes a simplified MAP algorithm and a Max-Log-MAP algorithm.
  • the log likelihood ratio sequence is used as the soft output of the iterative decoding described above, and the log likelihood ratio value is a likelihood probability value rather than the determined binary sequences 0 and 1.
  • step S102 the embodiment of the present invention may perform the CRC-assisted Turbo code iterative sorting statistical decoding and obtain the decoding after the Turbo code iterative decoding ends, using the joint generation matrix G ⁇ m and the log likelihood ratio sequence. process result.
  • the main process is to obtain the hard-case sequence C according to the log-likelihood ratio sequence, and obtain the reliability sequence by taking the absolute value of the log-likelihood ratio in the log-likelihood ratio sequence; the log-likelihood ratio in the reliability sequence is absolutely
  • the values are sorted in descending order, and according to the corresponding relationship, the joint generation matrix O ⁇ Gc ⁇ ) and the hard decision sequence ( ⁇ (C) after descending sorting are obtained; Gaussian elimination is performed on the sorted joint generation matrix ( ⁇ (Gc ⁇ ),
  • the Gaussian elimination is specifically to eliminate the front K m column into a unit matrix, and obtain the Gaussian elimination matrix G gauss ; and because the linear correlation occurs between the columns of the matrix in the Gaussian elimination process, the linear correlation columns are further reduced in order.
  • Sorting adjustment obtaining the sorting pattern 0 2 .
  • OJCQ hard-sequenced hard-sentence sequence 0 2
  • VC hard-sentence sequence 0 2
  • the coded code is obtained by sorting and decoding, and then the reverse order is rearranged to obtain the decoding result.
  • a possible implementation manner of acquiring Turbo code decoding is: acquiring the first inner iteration number of the component decoder of the turbo code decoder The sequence of log likelihood ratios output after iterative decoding.
  • a commonly used Turbo code decoder consists of two identical soft input soft output component decoders, an interleaver and a corresponding deinterleaver.
  • the embodiment of the present invention can obtain a log likelihood ratio sequence of any of the component decoders of the turbo code decoder.
  • a maximum number of iterations is set.
  • the first iteration number can be the maximum number of iterations.
  • the component decoder is obtained for the last time. Iterative log likelihood ratio sequence.
  • Another possible implementation manner is: after the component decoder passes the iterative decoding of the second inner iteration number, the log likelihood ratio of each iteration output is accumulated, and the accumulated log likelihood ratio sequence is obtained. Ij.
  • the output log likelihood ratio sequence will become more accurate and reliable, but for the case where the Turbo iterative decoding algorithm cannot be successfully decoded, each bit Soft information symbols often oscillate as the number of iterations increases. The oscillation of soft information will greatly affect the accuracy of the reliability sequence.
  • the soft volume of each iteration is accumulated.
  • the second fixed iteration number can be an integer greater than or equal to 1, and the accumulated amplitude is a more effective reliability measurement information, which can overcome the oscillation phenomenon and increase the decoding accuracy.
  • FIG. 3 is a schematic flowchart diagram of Embodiment 2 of a decoding processing method according to an embodiment of the present invention.
  • the joint generation matrix G e is used .
  • the m and log likelihood ratio sequences are subjected to CRC-assisted Turbo code iterative sorting statistical decoding to obtain decoding processing results, as shown in FIG. 3, including The following steps:
  • the codeword obtained by Turbo code coding is 3K+12, wherein the first K bits are the information sequence generated by the encoder, the other two K bits are the information generated by the encoder, and the last 12 bits are codes.
  • the number of columns of the information sequence received by the component decoder of the turbo code decoder is 3K+12, after the component decoder After intra-iterative decoding, the number of columns of the log likelihood ratio sequence of the output information bits is also a log-likelihood ratio sequence of ⁇ .. Ik, L k+1 ... L 2k , L 2k+1 ..
  • the log likelihood ratio sequence of the output soft is not a post-judgment binary, but a likelihood probability value
  • the specific process of the hard decision is: if the log likelihood ratio is greater than or equal to 0, the information bit value in the corresponding hard decision sequence C is 1, and if the log likelihood ratio is less than 0, the corresponding hard decision sequence C The information bit value is 0.
  • the log likelihood ratio value in the log likelihood ratio sequence has a correspondence relationship with the information bit value in the hard decision sequence.
  • the log likelihood ratio sequence, the hard decision sequence, and the columns of the joint generation matrix G ⁇ m have a corresponding relationship.
  • the source of the reliability data is mainly the magnitude of the log likelihood ratio, and the log likelihood ratio has positive and negative points. Therefore, the log likelihood ratio in the log likelihood ratio sequence is Take the absolute value and get the reliability sequence.
  • the log likelihood ratio absolute value in the reliability sequence can be sorted, and the log likelihood ratio in the reliability sequence is sorted in descending order to obtain the sorted pattern Oi. .
  • the corresponding pair generates the matrix G e . m and the hard decision sequence C are sorted to obtain the sorted joint generation matrix O Gc ⁇ n) and the hard decision sequence OC
  • step S304 since the pre-K m column is the original information sequence length, the final decoding result needs to obtain the decoding result of the pre-K m , and therefore, Gaussian elimination is performed on the sorted joint generation matrix ( ⁇ (G ⁇ )). , the former ⁇ column is eliminated into a unit matrix, and the Gaussian elimination matrix G gauss is obtained . Since the linear correlation occurs between the columns of the matrix in the Gaussian elimination process, these linear correlation columns must be further adjusted in descending order, and the order adjustment is performed.
  • the subsequent sorting pattern is 0 2 , and according to the corresponding relationship and the sorting pattern 0 2 , the hard-sequenced sequence 0 2 ( 0!(C)) 0 is obtained.
  • Gaussian elimination consists of two steps. First, the front K m column of the joint generation matrix O Gc ⁇ ) is eliminated into a unit matrix, and the Gaussian-eliminated matrix G gauss is obtained , and then the joint generation matrix O ⁇ Gc ⁇ ) is linear. The related columns are sorted in descending order, and the matrix 0 2 is obtained.
  • the matrix 0 2 can be presented in the form of a permutation pattern. For example, when the first column in the current K m column is linearly related to the second column, the second column is interchanged with the K m +1 column with higher reliability, and then the descending sorting adjustment is performed, and the sorted adjusted sorting pattern is sorted. It is 0 2 and can be a matrix of 1 row and 3K columns.
  • S305 The coded words of the sorted statistical decoding are obtained according to the preceding sequence of the hard decision sequence 0 2 ( OJCQ ) and the matrix G gauss after the Gaussian elimination, and then the reverse order is rearranged to obtain the decoded result and the hard decision sequence after sorting is selected. 2 (( ⁇ (C))) The first column is multiplied with the Gaussian-destroyed matrix G gauss to obtain the codeword for sorting statistical decoding.
  • FIG. 4 is a schematic flowchart diagram of Embodiment 3 of a decoding processing method according to an embodiment of the present invention. As shown in FIG. 4, on the basis of the embodiment shown in FIG. 1 of the present invention, after obtaining the decoding processing result, step S403 is further included.
  • S401 Acquire a Turbo code generation matrix G tob . And cyclic redundancy check, CRC generator matrix G crc combined generator matrix G ⁇ m, and acquires the number of Turbo code decoder likelihood ratio sequence output;
  • S402 Perform CRC-assisted Turbo code iterative sorting statistical decoding by using a joint generation matrix G ⁇ m and a log likelihood ratio sequence to obtain a decoding processing result.
  • the codeword of the decoding processing result needs to be determined before the decoding result can be output.
  • the above-mentioned steps S401 and S402 are the same as the steps S101 and S102 in the embodiment shown in FIG. 1.
  • the specific implementation process of the step S402 is the same as that of the embodiment shown in FIG.
  • the coded result of the decoded processing result necessarily conforms to the CRC check, that is, in the decoding scheme, the CRC can no longer be used as the judgment codeword is correct.
  • the criterion, in the actual system, can not determine whether the code block can be received.
  • the final output decoding result is selected according to the discriminating manner of the false alarm and the miss alarm in the binary detection event.
  • the false alarm probability is: Under the condition that the Turbo iteration has no correct output, the CRC-assisted Turbo code iterative sorting statistically decodes the probability that all the frames that output the correct codeword are judged to be incorrect.
  • the probability of missed alarm is: Turbo iteration without Turbo iteration, CRC-assisted Turbo code iterative sorting Statistical decoding is determined as the correct codeword probability in all output error frames. In the communication system, the missed alarm is not allowed, and only a small probability of false alarm can be tolerated. Therefore, the code word of the decoding processing result can be judged according to the false alarm, and the final decoding result is output.
  • the decision method of the fixed threshold is used to judge the codeword outputted by the CRC-assisted Turbo code iterative sorting statistical decoding, and whether it needs to be retransmitted. Comparing the codeword in the decoded output result with the Euclidean distance of the information sequence received by the Turbo code decoder and the preset decision threshold, when decoding the output word in the output result and the Euclidean distance d of the information sequence, Default decision gate When the time limit is passed, the decision is passed, and the decoding result is output; if the Euclidean distance between the decoding processing result and the information sequence received by the Turbo code decoder is greater than the preset decision threshold, the decision is not passed, and the bit flipping decoding is performed.
  • the selection of the default decision threshold can be implemented by simulation statistics. For example, the simulation ensures that the number of error frames is at least 1000 and the total number of frames is at least 10,000 to meet the statistical requirements. For a certain code length and different signal-to-noise ratio, it is determined that the codeword in the decoding processing result and the information sequence received by the Turbo code decoder in the frame number of the erroneous decoding under the condition that the Turbo iterative decoding is incorrect The minimum of the Euclidean distance. On this basis, there are other ways to use this method. For example, by dividing the above Euclidean distance by the minimum of the sum of the absolute values of the input log likelihood ratio sequence, determine any value less than the minimum value.
  • the Euclidean distance is the true distance between two points in the m-dimensional space, and other selection manners obtained by the deformation of the method are not enumerated here.
  • the selection of the threshold of the pre-determined threshold is also obtained by an empirical method, and the embodiment of the present invention is not particularly limited herein.
  • the decoding processing method provided by the embodiment of the present invention can effectively verify the codeword in the decoding processing result by outputting the codeword in the decoding processing result, and output the correct codeword.
  • FIG. 5 is a schematic flowchart of Embodiment 4 of a decoding processing method according to an embodiment of the present invention.
  • the bit flipping decoding provided by the embodiment of the present invention includes:
  • S501 Flip the first provoke 1 bit symbol of the hard decision sequence 0 2 ((VC)) by bit traversal by at least one bit to obtain a hard-sequence sequence of bit flip.
  • the first K m bit symbols of the descending sorted hard decision sequence oo ⁇ c)) may be inverted by at least one bit by bit traversal.
  • Bit symbol flipping means that the bit changes from 1 to 0 and changes from 0 to 1.
  • one bit can be flipped in bits, that is, each bit symbol is flipped. It is also possible to flip the bit by two bits, that is, to flip every two bit symbols, and finally obtain a hard sequence of bit flipping.
  • the first K reordered for encoding m bits are likely to change after a 0-1 or 1-0, to change every time, and after the coding sequences need Gaussian Elimination System
  • the form of the Turbo code generation matrix is multiplied, including the KX3K submultiple addition operation.
  • the change of the i-th coded bit is only related to the element of the i-th row of the generator matrix, and the coded output codeword can be directly obtained by bit flipping: if the i-th row and the j-th column of the generated matrix are 0, Then the jth bit of the output codeword is unchanged; otherwise, the jth bit of the output codeword needs to be XORed with 1 to calculate an inverse encoding up to 3K XOR operation, which reduces the computational complex Miscellaneous.
  • This step differs from step S305 in the above embodiment of FIG. 3 only in that the pre-column sequence of the hard-sequence sequence after bit flip and the Gaussian-erased matrix G gauss are encoded to obtain at least one-order order statistically decoded codeword.
  • This embodiment of the present invention will not be described again.
  • S503 Determine a decoding processing result after the bit is inverted, and output a decoding result.
  • the decision is passed, and the decoding result is output; when the bit is inverted, the decoding processing result is obtained.
  • the codeword in the codeword and the information sequence received by the Turbo decoder are greater than the preset decision threshold, and then the codeword in the decoding processing result after the bit flip is determined to be an error codeword, requesting retransmission of the information sequence.
  • the number of bits of the bit symbol traversed by bit traversal may be determined according to requirements, or the bit symbol may be first traversed by bit by one bit, if the bit symbol is traversed by bit, the decoding result code word of 1 bit is inverted.
  • the bit symbol can be traversed by bit traversal by 2 bits. If the traversal flips 2 bits and the decision is not passed, it can be extended to 3 or 4 bits. The higher the number of bits traversed by flipping, the better the performance of decoding, but the higher the number of bits, the larger the amount of calculation, so you can choose the appropriate number of flips.
  • the decoding processing method by performing bit flipping on the hard decision sequence, the erroneous bit code whose decision is not passed can be corrected, and the decoding accuracy and the decoding gain are improved.
  • the inventor performed the system simulation using the above technical solution. It can be seen from the simulation results that the base has an additional 2 dB gain compared to the existing Max-Log-MAP iterative decoding scheme.
  • FIG. 6 is a schematic diagram 1 of a decoding performance curve of a decoding processing method according to an embodiment of the present invention; in a communication system, usually 5 3 ⁇ 4 ⁇ .
  • the relationship with the frame error rate is one of its main performance indicators.
  • E b represents the energy of the unit bit data signal, N.
  • the simulation parameters are defined.
  • Simulation parameter f indicates row
  • the legend in Fig. 6 represents the way of 0SD-assisted Turbo iterative decoding in the form of 0SD(s, f).
  • the Turbo code standard iterative decoding algorithm uses the Max-Log-MAP (MLM) algorithm.
  • the information sequence length K in Fig. 6 is 40.
  • the gain of the CRC-assisted Turbo code iterative sorting statistical decoding is considerable.
  • the scheme of sorting statistical decoding processing after the last iteration is more efficient than the Max-Log-MAP iterative decoding scheme.
  • An additional 2dB gain is added, which is about 1.5dB coding gain more than the iterative sorting statistical decoding scheme without CRC auxiliary inverse coding.
  • a sorting statistical decoding is performed after each iteration decoding.
  • the processed scheme has about 3.75 dB more gain than the traditional Max-Log-MAP iterative decoding scheme, and about 2.95 dB coding gain over the CRC-free iterative sorting statistical decoding scheme. It can be seen that the decoding of CRC-assisted Turbo code iterative sorting statistical decoding has very good decoding performance.
  • FIG. 7 is a schematic diagram 2 of a decoding performance curve of a decoding processing method according to an embodiment of the present invention
  • FIG. 8 is a schematic diagram 3 of a decoding performance curve of a decoding processing method according to an embodiment of the present invention
  • FIG. 9 is a decoding processing method according to an embodiment of the present invention
  • FIG. 10 is a schematic diagram 5 of a decoding performance curve of a decoding processing method according to an embodiment of the present invention.
  • VOIP Voice over Internet Protocol
  • the length of the information sequence K is 96, 128, 200, 352.
  • the simulation results are shown in Figure 7-10.
  • Frame error rate le-3 Iterative decoding can achieve a gain of up to about 0.7dB; 128-yard length can achieve a gain of about 0.5dB; 200-yard length can achieve a coding gain of about 0.3dB; 352-codelength can achieve a coding gain of about 0.13dB.
  • FIG. 11 is a schematic diagram 6 of a decoding performance curve of a decoding processing method according to an embodiment of the present invention.
  • a performance curve diagram of a CRC-assisted Turbo code iterative sorting statistical decoding using a preset decision threshold is preset.
  • the decision threshold is 47.
  • Genie-aided is the decoded result of the theoretical decoding obtained by comparing the original source sequence with the decoding result. It can be seen from Figure 11 that the actual decoding performance obtained by the preset decision threshold is lower in the SNR area than the theoretical decoding performance. There is a small loss in the domain, but there is still a large gain compared to the Turbo code iterative sorting statistical decoding without CRC assistance.
  • FIG. 12 is a schematic structural diagram of Embodiment 1 of a decoder according to an embodiment of the present invention.
  • the decoder 60 provided by the embodiment of the present invention includes a receiving module 601 and a decoding module 602.
  • the receiving module 601 is configured to acquire a Turbo code generation matrix G tob .
  • the joint generation matrix G c with the cyclic redundancy check CRC generation matrix Gere. m, and to obtain a logarithmic likelihood ratio sequence output from the Turbo Code decoder;
  • joint coding module 602 is used to preclude the use of the generator matrix G e. m and the log likelihood ratio sequence are subjected to CRC-assisted Turbo code iterative sorting statistical decoding to obtain a decoding processing result.
  • the decoder of this embodiment may be used to implement the technical solution of the method embodiment shown in FIG. 1.
  • the implementation principle and technical effects are similar, and details are not described herein again.
  • the receiving module 601 is specifically configured to obtain a log likelihood ratio sequence output by the component decoder of the turbo code decoder after iterative decoding of the first inner iteration number; or
  • the log likelihood ratio of each iteration output is accumulated to obtain the accumulated log likelihood ratio sequence.
  • the decoder of this embodiment can be used to implement the technical solution of the method embodiment of FIG. 1.
  • the principle and the technical effect are similar, and details are not described herein again.
  • the foregoing decoding module 602 is specifically configured to:
  • Obtaining a reliability sequence by taking an absolute value of the log likelihood ratio value in the log likelihood ratio sequence; sorting a log likelihood ratio absolute value in the reliability sequence, and obtaining, according to the correspondence relationship, Sorted joint generation matrix O ⁇ Gc ⁇ ) and hard decision sequence OC);
  • Gaussian elimination is performed on the sorted joint generation matrix O ⁇ Gc ⁇ , and the Gaussian-eliminated matrix G gauss and the matrix 0 2 are obtained , and are sorted according to the correspondence and the matrix 0 2 .
  • the decoder of this embodiment can be used to implement the technical solution of the method embodiment of FIG. 3, and the implementation principle and technical effects are similar, and details are not described herein again.
  • the foregoing decoding module 602 is further specifically configured to:
  • the decoding process and the Euclidean distance of the information sequence received by the Turbo code decoder are less than a preset decision threshold, the decision is passed, and the decoding result is output;
  • the decoder of this embodiment can be used to implement the technical solution of the method embodiment of FIG. 4, and the principle and the technical effect are similar, and details are not described herein again.
  • the foregoing decoding module 602 is specifically configured to:
  • the decoder of this embodiment can be used to implement the technical solution of the method embodiment of FIG. 5.
  • the principle and the technical effect are similar, and details are not described herein again.
  • the foregoing decoding module 602 is further specifically configured to:
  • the decoder of this embodiment can be used to implement the technical solution of the foregoing method embodiments.
  • the principle and the technical effects are similar, and details are not described herein again.
  • the above decoder can be applied to a base station, user equipment, or other entity that needs to perform a decoding action.
  • FIG. 13 is a schematic structural diagram of Embodiment 2 of a decoder according to an embodiment of the present invention.
  • the decoder 70 provided by the embodiment of the present invention includes a receiver 701 and a processor 702.
  • the receiver 701 is configured to acquire a Turbo code generation matrix G turb .
  • the generator matrix G erc combined with a cyclic redundancy check CRC generator matrix G ⁇ m, and acquires the number of Turbo code decoder likelihood ratio sequence output; processor 702 to preclude the use of the combined generator matrix G ⁇ m And the log likelihood ratio sequence, performing CRC-assisted Turbo code iterative sorting statistical decoding to obtain a decoding processing result.
  • the decoder of this embodiment can be used to implement the technical solution of the method embodiment shown in FIG. 1.
  • the implementation principle and technical effects are similar, and details are not described herein again.
  • the receiver 701 is specifically configured to obtain a log likelihood ratio sequence output by the component decoder of the turbo code decoder after iterative decoding by the first inner iteration number; or
  • the log likelihood ratio of each iteration output is accumulated to obtain the accumulated log likelihood ratio sequence.
  • the decoder of this embodiment can be used to implement the technical solution of the foregoing method embodiments.
  • the principle and the technical effects are similar, and details are not described herein again.
  • processor 702 is specifically configured to:
  • Obtaining a reliability sequence by taking an absolute value of the log likelihood ratio value in the log likelihood ratio sequence; sorting a log likelihood ratio absolute value in the reliability sequence, and obtaining, according to the correspondence relationship, Sorted joint generation matrix O ⁇ Gc ⁇ ) and hard decision sequence OC);
  • Gaussian elimination is performed on the sorted joint generation matrix O ⁇ Gc ⁇ , and the Gaussian-eliminated matrix G gauss and the matrix 0 2 are obtained , and are sorted according to the correspondence and the matrix 0 2 .
  • the decoder of this embodiment can be used to implement the technical solution of the method embodiment of FIG. 3, and the principle and the technical effect are similar, and details are not described herein again.
  • processor 702 is further configured to:
  • the decoding process and the Euclidean distance of the information sequence received by the Turbo code decoder are less than a preset decision threshold, the decision is passed, and the decoding result is output;
  • the decoder of this embodiment can be used to implement the technical solution of the method embodiment of FIG. 4, and the principle and the technical effect are similar, and details are not described herein again.
  • processor 702 is specifically configured to:
  • the decoder of this embodiment can be used to implement the technical solution of the method embodiment of FIG. 5.
  • the principle and the technical effect are similar, and details are not described herein again.
  • processor 702 is further configured to:
  • the decoder of this embodiment can be used to implement the technical solution of the foregoing method embodiments.
  • the principle and the technical effects are similar, and details are not described herein again.
  • the above decoder can be applied to a base station, user equipment, or other entity that needs to perform a decoding action.
  • the embodiment of the invention further provides a processor for acquiring a Turbo code generation matrix G tob .
  • the generator matrix G crc combined with a cyclic redundancy check CRC generator matrix G ⁇ m, and acquires logarithmic likelihood ratio sequence output from the Turbo Code decoder; United preclude the use of the generator matrix G c. m and the log likelihood ratio sequence are subjected to CRC-assisted Turbo code iterative sorting statistical decoding to obtain a decoding processing result.
  • the processor may be present in a decoder, a user equipment, a base station, or any other entity that needs to perform a decoding action for decoding a Turbo code.
  • the processor in the embodiment of the present invention may be an integrated circuit chip having signal processing capability.
  • each step of the above method may be completed by an integrated logic circuit of hardware in a processor or an instruction in a form of software.
  • the above processor may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component.
  • the processor may be a microprocessor or the above processor or any conventional processor, decoder or the like.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented as a hardware processor, or may be performed by a combination of hardware and software modules in the processor.
  • the software module can be located in random access memory, flash memory, read only memory, programmable read only memory or Wipe the programmable memory, registers, etc. in the mature storage medium of the field.
  • the storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the steps of the foregoing method.
  • the embodiment of the invention further provides a chip for performing decoding processing, and the chip may include the above processor.
  • the aforementioned program can be stored in a computer readable storage medium.
  • the steps of the foregoing method embodiments are performed; and the foregoing storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (ROM), and a random access memory (RAM, Random Access).
  • Various media that can store program code such as Memory), disk, or optical disk.
  • the disclosed systems, devices, and methods may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, i.e., may be located in one place, or may be distributed over multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • Error Detection And Correction (AREA)

Abstract

Selon certains modes de réalisation, la présente invention concerne un procédé de traitement de décodage et un décodeur. Le procédé comprend les étapes suivantes : obtention d'une matrice de génération composite Gcom composée d'une matrice de génération de turbo codes Gturbo et d'une matrice de génération d'un contrôle de redondance cyclique (CRC) Gcrc ; obtention d'une séquence de taux de probabilités logarithmiques produite par un décodeur de turbo codes ; et utilisation de la matrice de génération composite Gcom et de la séquence de taux de probabilités logarithmiques pour effectuer un décodage itératif de turbo codes par statistiques ordonnées assisté par CRC pour obtenir le résultat du traitement de décodage. Le procédé et le dispositif de décodage de turbo codes selon les modes de réalisation de la présente invention peuvent augmenter la performance du décodage.
PCT/CN2012/084675 2012-11-15 2012-11-15 Procédé de traitement de décodage et décodeur WO2014075267A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP12888467.3A EP2838204B1 (fr) 2012-11-15 2012-11-15 Procédé de traitement de décodage et décodeur
PCT/CN2012/084675 WO2014075267A1 (fr) 2012-11-15 2012-11-15 Procédé de traitement de décodage et décodeur
CN201280028136.2A CN104025459B (zh) 2012-11-15 2012-11-15 译码处理方法及译码器
US14/488,168 US9214958B2 (en) 2012-11-15 2014-09-16 Method and decoder for processing decoding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2012/084675 WO2014075267A1 (fr) 2012-11-15 2012-11-15 Procédé de traitement de décodage et décodeur

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/488,168 Continuation US9214958B2 (en) 2012-11-15 2014-09-16 Method and decoder for processing decoding

Publications (1)

Publication Number Publication Date
WO2014075267A1 true WO2014075267A1 (fr) 2014-05-22

Family

ID=50730493

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/084675 WO2014075267A1 (fr) 2012-11-15 2012-11-15 Procédé de traitement de décodage et décodeur

Country Status (4)

Country Link
US (1) US9214958B2 (fr)
EP (1) EP2838204B1 (fr)
CN (1) CN104025459B (fr)
WO (1) WO2014075267A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111600681A (zh) * 2020-05-15 2020-08-28 北京邮电大学 基于fpga硬件加速的下行链路比特级处理方法

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10205470B2 (en) 2014-02-14 2019-02-12 Samsung Electronics Co., Ltd System and methods for low complexity list decoding of turbo codes and convolutional codes
WO2015122751A1 (fr) * 2014-02-17 2015-08-20 연세대학교 원주산학협력단 Procédé de détermination d'une séquence de basculement et procédé de détermination d'un modèle d'erreur permettant de détecter une erreur sur la base d'une valeur de décision souple, et dispositif afférent
US20160266972A1 (en) * 2015-03-10 2016-09-15 Kabushiki Kaisha Toshiba Memory controller, storage device and decoding method
CN108933603B (zh) * 2018-02-28 2022-02-22 和芯星通科技(北京)有限公司 一种实现校验节点处理的方法及装置
CN109981112B (zh) * 2018-09-26 2022-11-18 东南大学 一种部分循环冗余校验辅助的排序统计译码方法
WO2020151835A1 (fr) * 2019-01-25 2020-07-30 Huawei Technologies Co., Ltd. Propagation de croyances combinée (bp) et décodage de statistiques ordonnées (osd) pour codes concaténés
WO2021107697A1 (fr) 2019-11-27 2021-06-03 Samsung Electronics Co., Ltd. Décodeur intelligent
CN110995278B (zh) * 2019-12-16 2024-01-12 山东希尔信息技术有限公司 一种改进极性码串行消除列表比特翻转译码方法及系统
CN112929036A (zh) * 2021-02-01 2021-06-08 山东科技大学 一种基于对数似然比的置信度传播动态翻转译码方法
CN113300718B (zh) * 2021-05-20 2024-04-09 南京大学 编码方法、译码方法、编码装置和译码装置
CN113285722B (zh) * 2021-05-21 2022-07-22 西南大学 一种短极化码的多偏差分段冗余校验辅助统计译码方法
US11722151B2 (en) * 2021-08-09 2023-08-08 Micron Technology, Inc. Bit flipping decoder based on soft information
CN113872609B (zh) * 2021-09-30 2024-03-26 东南大学 一种部分循环冗余校验辅助的自适应置信传播译码方法
CN118318397A (zh) * 2021-11-30 2024-07-09 三星电子株式会社 用于在通信和广播系统中解码数据的方法和设备
US11777522B1 (en) 2022-03-28 2023-10-03 Micron Technology, Inc. Bit flipping decoder with dynamic bit flipping criteria
CN115347982B (zh) * 2022-08-12 2024-07-23 中国电信股份有限公司 译码方法及装置、存储介质及电子设备
CN115665795A (zh) * 2022-09-20 2023-01-31 北京邮电大学 一种译码方法及装置
CN115714632B (zh) * 2022-11-04 2024-07-19 重庆邮电大学 一种基于高斯列消的极化码码长盲识别方法
US12081239B2 (en) 2022-12-12 2024-09-03 Microsoft Technology Licensing, Llc Multiuser decoding using iterative decoders

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101867379A (zh) * 2010-06-24 2010-10-20 东南大学 一种循环冗余校验辅助的卷积码译码方法
CN102111162A (zh) * 2009-12-28 2011-06-29 重庆重邮信科通信技术有限公司 Turbo 分量译码方法、分量译码器、支路计算器及Turbo 译码器
CN102356632A (zh) * 2009-03-15 2012-02-15 Lg电子株式会社 发送/接收系统和广播信号处理方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5499030A (en) 1994-03-18 1996-03-12 The United States Of America As Represented By The Secretary Of The Air Force Expert system constant false alarm rate (CFAR) processor
WO2002054951A2 (fr) 2001-01-12 2002-07-18 The Government Of The United States Of America As Represented By The Secretary, Department Of Health And Human Services Decodage d'algorithme pour reponses neuronales
US7519898B2 (en) * 2004-03-25 2009-04-14 Krishna Rama Narayanan Iterative decoding of linear block codes by adapting the parity check matrix
US9191256B2 (en) * 2012-12-03 2015-11-17 Digital PowerRadio, LLC Systems and methods for advanced iterative decoding and channel estimation of concatenated coding systems

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102356632A (zh) * 2009-03-15 2012-02-15 Lg电子株式会社 发送/接收系统和广播信号处理方法
CN102111162A (zh) * 2009-12-28 2011-06-29 重庆重邮信科通信技术有限公司 Turbo 分量译码方法、分量译码器、支路计算器及Turbo 译码器
CN101867379A (zh) * 2010-06-24 2010-10-20 东南大学 一种循环冗余校验辅助的卷积码译码方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2838204A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111600681A (zh) * 2020-05-15 2020-08-28 北京邮电大学 基于fpga硬件加速的下行链路比特级处理方法
CN111600681B (zh) * 2020-05-15 2022-07-01 北京邮电大学 基于fpga硬件加速的下行链路比特级处理方法

Also Published As

Publication number Publication date
US9214958B2 (en) 2015-12-15
CN104025459A (zh) 2014-09-03
EP2838204B1 (fr) 2017-04-19
EP2838204A4 (fr) 2015-08-19
US20150006992A1 (en) 2015-01-01
EP2838204A1 (fr) 2015-02-18
CN104025459B (zh) 2017-05-24

Similar Documents

Publication Publication Date Title
WO2014075267A1 (fr) Procédé de traitement de décodage et décodeur
JP3610329B2 (ja) 大最小距離を用いたターボ符号化方法及びそれを実現するシステム
US20090249165A1 (en) Event Cleanup Processing For Improving The Performance Of Sequence-Based Decoders
US7454684B2 (en) Apparatus and method for turbo decoder termination
US8650451B2 (en) Stochastic stream decoding of binary LDPC codes
JP2006115145A (ja) 復号装置及び復号方法
EP2418796B1 (fr) Indicateurs de fiabilité de niveau bit à partir de bits survivants dans les décodeurs Viterbi
Wang et al. An improved concatenation scheme of polar codes with Reed–Solomon codes
Ramabadran et al. Blind recognition of LDPC code parameters over erroneous channel conditions
CN102064917A (zh) 一种ldpc编码调制系统的解调译码方法
US9407293B2 (en) Wyner ziv coding
US7925964B2 (en) High-throughput memory-efficient BI-SOVA decoder architecture
US11750219B2 (en) Decoding method, decoder, and decoding apparatus
KR20110082311A (ko) 통신 시스템에서 복호된 데이터의 신뢰성을 판단하는 장치 및 방법
CN110798283A (zh) 用错误校正进行的信号处理
US20220337269A1 (en) Block code encoding and decoding methods, and apparatus therefor
JP4444755B2 (ja) 連接符号システムおよび連接符号処理方法、復号装置
Cho et al. Reduced complexity Chase-Pyndiah decoding algorithm for turbo product codes
Mao et al. Serially concatenated scheme of polar codes and the improved belief propagation decoding algorithm
CN111970008B (zh) 一种涡轮码解码器及软输入软输出方法、设备和存储介质
Li et al. An efficient decoding algorithm for concatenated RS-convolutional codes
Greeshma et al. Fpga implementatıon of turbo product codes for error correctıon
TW201817172A (zh) 用於通訊系統中迴旋碼解碼裝置的解碼方法及相關的判斷模組
Xu et al. Novel Construction and Decoding of Polar Product Codes with SPC Codes
Li et al. Outer Codes

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12888467

Country of ref document: EP

Kind code of ref document: A1

REEP Request for entry into the european phase

Ref document number: 2012888467

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2012888467

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE