WO2014068937A1 - 半導体モジュール - Google Patents

半導体モジュール Download PDF

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Publication number
WO2014068937A1
WO2014068937A1 PCT/JP2013/006342 JP2013006342W WO2014068937A1 WO 2014068937 A1 WO2014068937 A1 WO 2014068937A1 JP 2013006342 W JP2013006342 W JP 2013006342W WO 2014068937 A1 WO2014068937 A1 WO 2014068937A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor module
bare chip
joint surface
solder
wiring pattern
Prior art date
Application number
PCT/JP2013/006342
Other languages
English (en)
French (fr)
Inventor
崇 須永
昇 金子
修 三好
Original Assignee
日本精工株式会社
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Filing date
Publication date
Application filed by 日本精工株式会社 filed Critical 日本精工株式会社
Priority to EP13851001.1A priority Critical patent/EP2916348B1/en
Priority to JP2014526016A priority patent/JP5807721B2/ja
Priority to CN201380003701.4A priority patent/CN103918066B/zh
Priority to US14/435,690 priority patent/US9397030B2/en
Publication of WO2014068937A1 publication Critical patent/WO2014068937A1/ja

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    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
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    • H01L23/49551Cross section geometry characterised by bent parts
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B62LAND VEHICLES FOR TRAVELLING OTHERWISE THAN ON RAILS
    • B62DMOTOR VEHICLES; TRAILERS
    • B62D5/00Power-assisted or power-driven steering
    • B62D5/04Power-assisted or power-driven steering electrical, e.g. using an electric servo-motor connected to, or forming part of, the steering gear
    • B62D5/0403Power-assisted or power-driven steering electrical, e.g. using an electric servo-motor connected to, or forming part of, the steering gear characterised by constructional features, e.g. common housing for motor and gear box
    • B62D5/0406Power-assisted or power-driven steering electrical, e.g. using an electric servo-motor connected to, or forming part of, the steering gear characterised by constructional features, e.g. common housing for motor and gear box including housing for electronic control unit
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Definitions

  • the present invention relates to a semiconductor module such as a power module incorporated in an automobile electrical device.
  • a motor driving unit is provided in a housing that houses an electric motor related to steering of an automobile, and the electronic device is mounted on the motor driving unit.
  • This electronic device is incorporated as a power module in the motor drive unit.
  • the power module is equipped with power elements such as FET (Field Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor) suitable for controlling electric devices driven by a relatively large current such as an electric power steering device. It is configured as a so-called semiconductor module.
  • This type of power module is also referred to as an in-vehicle module because it is mounted on a vehicle.
  • Patent Document 1 a wire is used for electrical wiring for joining a wiring pattern on a metal substrate and a bare chip transistor.
  • the lead component for electrically connecting the semiconductor element mounted on the metal substrate is made larger than the electrode on the semiconductor, and the reliability of the contact portion is ensured.
  • some contact points are used and the contact width is widened.
  • Patent Document 3 for example, there is a case where a rising bent portion is provided or a fuse shape (wave shape) is provided in the middle of the wiring in order to relieve stress of the connector wiring.
  • an object of the present invention is to provide a semiconductor module capable of realizing reduction in manufacturing tact and reduction in manufacturing cost and ensuring the reliability of the joint.
  • an aspect of the semiconductor module according to the present invention includes a metal substrate, an insulating layer formed on the substrate, a plurality of wiring patterns formed on the insulating layer, and the plurality of wiring patterns.
  • a bare chip transistor mounted on one of the wiring patterns via solder, and an electrode formed on the top surface of the bare chip transistor and the other wiring pattern among the plurality of wiring patterns are joined via solder.
  • the copper connector includes a flat plate portion, a first leg portion that is bent so as to fall from one end of the flat plate portion, and is joined to the electrode, and is bent so as to fall from the other end of the flat plate portion.
  • the first leg portion is provided with a narrow portion whose width becomes narrower from an end portion on the side opposite to the bonding surface with the electrode toward an end portion where the bonding surface is formed.
  • the present invention is characterized in that a stress relaxation portion having a shape that relieves stress acting on the joint surface is provided on the joint surface of the first leg with the electrode.
  • the copper connector can absorb the displacement in the vertical, horizontal, front and rear, and twist directions of the copper connector joint that occurs during heating or cooling because the thermal expansion coefficient and thermal contraction ratio are different from those of the substrate. It has a unique shape.
  • the copper connector comprised with a copper plate as a joining member of the electrode of a bare chip transistor, and the wiring pattern on a board
  • these joining can be performed by solder mounting operation. That is, the same equipment is used for the bonding of the bare chip transistor electrode and the wiring pattern on the substrate, and the solder mounting operation performed when mounting the bare chip transistor and other substrate mounting components on the wiring pattern on the substrate. Can be performed simultaneously in the same process. For this reason, the manufacturing tact of the semiconductor module can be shortened, and dedicated equipment for wire bonding is not required, and the manufacturing cost of the semiconductor module can be reduced.
  • the displacement in the vertical and horizontal directions can be absorbed.
  • the displacement in the front-rear direction and the twist direction can be absorbed.
  • the stress relaxation portion is provided on the joint surface of the first leg portion with the electrode, the stress generated in the joint portion can be relaxed. Therefore, when thermal expansion or thermal contraction occurs due to the reflow process or operating heat, the solder joint between the copper connector and the bare chip transistor electrode can be made difficult to peel, and the reliability of the joint can be ensured.
  • a notch is formed in the joint surface
  • the joint surface is formed of a thin plate
  • a chamfered portion is formed at a corner of the joint surface
  • a hole may be formed in the center of the joint surface.
  • a dumbbell-shaped dumbbell portion that relieves stress acting on the joint surface may be formed on each of the first leg portion and the second leg portion.
  • the bare chip transistor electrode and the wiring pattern on the substrate can be joined by a solder mounting operation using a copper connector formed of a copper plate. Bonding to the pattern can be performed simultaneously in the same process as the solder mounting operation performed when the bare chip transistor or other substrate mounting component is mounted on the wiring pattern on the substrate. For this reason, the manufacturing tact of the semiconductor module can be shortened, and dedicated equipment for wire bonding is not required, and the manufacturing cost of the semiconductor module can be reduced. Further, since the copper connector has a bridge shape and the narrow leg portion and the stress relaxation portion are provided on the first leg portion joined to the electrode of the bare chip transistor, the displacement in any direction can be absorbed. Therefore, the thermal deformation of the copper connector in the reflow process can be absorbed, and the reliability of the joint can be ensured. Furthermore, it is possible to prevent the copper connector from being damaged due to temperature changes during product use.
  • FIG. 1 is a diagram showing a basic structure of an electric power steering apparatus in which a semiconductor module according to the present invention is used.
  • the column shaft 2 of the steering handle 1 is connected to a tie rod 6 of a traveling wheel via a reduction gear 3, universal joints 4 ⁇ / b> A and 4 ⁇ / b> B, and a pinion rack mechanism 5.
  • the column shaft 2 is provided with a torque sensor 7 that detects the steering torque of the steering handle 1, and an electric motor 8 that assists the steering force of the steering handle 1 is connected to the column shaft 2 via the reduction gear 3.
  • a torque sensor 7 that detects the steering torque of the steering handle 1
  • an electric motor 8 that assists the steering force of the steering handle 1 is connected to the column shaft 2 via the reduction gear 3.
  • the controller 10 that controls the electric power steering apparatus is supplied with electric power from a battery (not shown), and also receives an ignition key signal IGN (see FIG. 2) via an ignition key (not shown).
  • the controller 10 calculates a steering assist command value serving as an assist (steering assist) command based on the steering torque Ts detected by the torque sensor 7 and the vehicle speed V detected by the vehicle speed sensor 9, and the calculated steering is performed.
  • the current supplied to the electric motor 8 is controlled based on the auxiliary command value.
  • the controller 10 is mainly composed of a microcomputer, and the mechanism and configuration of the control device are as shown in FIG.
  • the steering torque Ts detected by the torque sensor 7 and the vehicle speed V detected by the vehicle speed sensor 9 are input to the control arithmetic unit 11 as a control arithmetic unit, and the current command value calculated by the control arithmetic unit 11 is used as the gate drive circuit 12.
  • the gate drive signal formed by the gate drive circuit 12 based on the current command value or the like is input to a motor drive unit 13 having a FET bridge configuration, and the motor drive unit 13 passes through an emergency stop interrupting device 14 for three phases.
  • An electric motor 8 composed of a brushless motor is driven.
  • Each phase current of the three-phase brushless motor is detected by the current detection circuit 15, and the detected three-phase motor currents ia to ic are input to the control arithmetic unit 11 as feedback currents.
  • a rotation sensor 16 such as a hall sensor is attached to the three-phase brushless motor, and a rotation signal RT from the rotation sensor 16 is input to the rotor position detection circuit 17, and the detected rotation position ⁇ is a control arithmetic unit. 11 is input.
  • the ignition signal IGN from the ignition key is input to the ignition voltage monitor unit 18 and the power supply circuit unit 19, and the power supply voltage Vdd is input from the power supply circuit unit 19 to the control arithmetic unit 11 and a reset signal for stopping the apparatus.
  • RS is input to the control arithmetic unit 11.
  • blocking apparatus 14 is comprised by the relay contacts 141 and 142 which interrupt
  • the circuit configuration of the motor drive unit 13 will be described.
  • the source electrode S of the FETTr1 and the drain electrode D of the FETTr2 are connected in series to constitute a c-phase arm of a three-phase motor, and a current is output through the c-phase output line 91c.
  • the FETTr3 and Tr4 are configured such that the source electrode S of the FETTr3 and the drain electrode D of the FETTr4 are connected in series to form an a-phase arm of a three-phase motor, and a current is output from the a-phase output line 91a.
  • the FETTr5 and Tr6 are configured such that the source electrode S of the FETTr5 and the drain electrode D of the FETTr6 are connected in series to form a b-phase arm of a three-phase motor, and a current is output from the b-phase output line 91b.
  • the controller 10 includes a case 20, a semiconductor module 30 as a power module including the motor driving unit 13, and heat dissipation. Sheet 39, control circuit board 40 including control arithmetic device 11 and gate drive circuit 12, power and signal connector 50, three-phase output connector 60, and cover 70.
  • the case 20 is formed in a substantially rectangular shape, and is provided on the flat-plate-shaped semiconductor module mounting portion 21 for mounting the semiconductor module 30 and the longitudinal end portion of the semiconductor module mounting portion 21.
  • the semiconductor module mounting portion 21 is formed with a plurality of screw holes 21a into which mounting screws 38 for mounting the semiconductor module 30 are screwed.
  • a plurality of mounting posts 24 for mounting the control circuit board 40 are erected on the semiconductor module mounting portion 21 and the power and signal connector mounting portion 22, and the control circuit board 40 is mounted on each mounting post 24.
  • a screw hole 24a into which a mounting screw 41 for mounting is screwed is formed.
  • the three-phase output connector mounting portion 23 is formed with a plurality of screw holes 23a into which mounting screws 61 for attaching the three-phase output connector 60 are screwed.
  • the semiconductor module 30 has the circuit configuration of the motor drive unit 13 described above. As shown in FIG. 4, the substrate 31 has six FETs Tr1 to Tr6, a positive terminal 81a connected to the power supply line 81, and A negative terminal 82a joined to the ground line 82 is mounted. Also, the substrate 31 has an a-phase output terminal 92a joined to the a-phase output line 91a, a b-phase output terminal 92b joined to the b-phase output line 91b, and a c-phase output joined to the c-phase output line 91c. A three-phase output unit 90 including a terminal 92c is mounted. In addition, other board mounting components 37 including a capacitor are mounted on the board 31. Further, the substrate 31 of the semiconductor module 30 is provided with a plurality of through holes 31a through which mounting screws 38 for mounting the semiconductor module 30 are inserted.
  • Each of the FETs Tr1 to Tr6 is composed of a bare chip FET (bare chip transistor) 35.
  • a source electrode S and a gate electrode G are provided on the bare chip FET 35, and a drain (not shown) is provided on the bottom surface of the bare chip FET 35. It has an electrode.
  • the semiconductor module 30 includes a metal substrate 31, and an insulating layer 32 is formed on the substrate 31.
  • the substrate 31 is made of a metal such as aluminum.
  • a plurality of wiring patterns 33a to 33d are formed on the insulating layer 32.
  • Each of the wiring patterns 33a to 33d is made of a metal such as copper or aluminum, or an alloy containing this metal.
  • a bare chip FET 35 constituting each of the FETs Tr1 to Tr6 is mounted on one wiring pattern 33a among the plurality of wiring patterns 33a to 33d via solder 34a.
  • the drain electrode formed on the lower surface of the bare chip FET 35 is joined to the wiring pattern 33a via the solder 34a.
  • the source electrode S of the bare chip FET 35 and the other wiring pattern 33b among the plurality of wiring patterns 33a to 33d are joined by the source electrode copper connector 36a via the solders 34e and 34b, respectively.
  • the source electrode copper connector 36a is formed by punching and bending a copper plate.
  • the source electrode copper connector 36a includes a flat plate portion 36aa, a connection portion 36ab that is bent and extended so as to fall from one end of the flat plate portion 36aa, and is joined to the source electrode S of the bare chip FET 35 via the solder 34e.
  • a connecting portion 36ac is provided which is bent and extended so as to fall from the other end of 36aa and is joined to the wiring pattern 33b via the solder 34b.
  • the gate electrode G of the bare chip FET 35 and the other wiring pattern 33c among the plurality of wiring patterns 33a to 33d are joined by the gate electrode copper connector 36b via solders 34f and 34c, respectively.
  • the gate electrode copper connector 36b is formed by punching and bending a copper plate.
  • the copper connector 36b for the gate electrode includes a flat plate portion 36ba, a connection portion 36bb which is bent and extended so as to fall from one end of the flat plate portion 36ba, and is joined to the gate electrode G of the bare chip FET 35 via the solder 34f.
  • another board mounting component 37 such as a capacitor is mounted on another wiring pattern 33d among the plurality of wiring patterns 33a to 33d formed on the insulating layer 32 via the solder 34d. .
  • the source electrode copper connector 36a has a bridge shape with a flat plate portion 36aa, a connection portion 36ab (first leg portion), and a connection portion 36ac (second leg portion). It has become. More specifically, in the source electrode copper connector 36a, one end of the connecting portion 36ab is connected to one end of the flat plate portion 36aa in the left-right direction (X-axis direction in FIG. 7) via the first bent portion 36ad. The other end of the connecting portion 36ab is formed with an outward joint surface 36af via the second bent portion 36ae. The lower surface of the bonding surface 36af is bonded to the source electrode S of the bare chip FET 35 via the solder 34e.
  • the connecting portion 36ab has a narrow portion 36ag in the vicinity of the joint surface 36af.
  • the narrow portion 36ag has a tapered shape in which the width becomes narrower from the first bent portion 36ad toward the second bent portion 36ae.
  • One end of the connecting portion 36ac is connected to the other end portion in the left-right direction of the flat plate portion 36aa via the third bent portion 36ah, and the other end of the connecting portion 36ac is directed outward via the fourth bent portion 36ai.
  • a joint surface 36aj is formed. The lower surface of the bonding surface 36aj is bonded to the wiring pattern 33b via the solder 34b.
  • the joint surface 36af is provided with a stress relaxation portion 36ak having a shape for relaxing the stress acting on the joint surface 36af.
  • 8 to 11 are diagrams showing examples of the shape of the stress relaxation portion 36ak.
  • the symbol P is a source PAD.
  • the stress relaxation part 36ak shown in FIG. 8 is provided with a slit (cut) in the joint surface 36af.
  • the said slit can divide the front-end
  • the stress relaxation part 36ak As another example of the stress relaxation part 36ak, as shown in FIG. 9, for example, there is one in which the thickness of the joint surface 36af is made thin. Further, as the stress relaxation part 36ak, as shown in FIG. 10, there is one in which a chamfered part is provided at a corner of the tip of the joint surface 36af. Here, the chamfered portion may be a large circle or a C chamfer instead of the R chamfer shown in FIG. Furthermore, as the stress relaxation portion 36ak, there is one in which a hole is provided in the center of the joint surface 36af as shown in FIG.
  • the shape of the source electrode copper connector 36a can be any shape as long as it is a bridge shape capable of joining the source electrode S and the wiring pattern 33b. Further, the shape of the stress relaxation portion 36ak can be any shape as long as it can be joined to the source electrode S. However, since reflow bonding, which will be described later, is performed at the time of solder bonding and the semiconductor module 30 is operated, the heat is generated due to heat generation, so that the thermal stress can be relieved. The same applies to the gate electrode copper connector 36b. As shown in FIG. 3, the semiconductor module 30 configured as described above is attached to the semiconductor module mounting portion 21 of the case 20 by a plurality of mounting screws 38. The substrate 31 of the semiconductor module 30 is formed with a plurality of through holes 31a through which the mounting screws 38 are inserted.
  • the control circuit board 40 constitutes a control circuit including the control arithmetic device 11 and the gate drive circuit 12 by mounting a plurality of electronic components on the board. After the semiconductor module 30 is mounted on the semiconductor module mounting portion 21, the control circuit board 40 has a plurality of standing uprights on the semiconductor module mounting portion 21 and the power and signal connector mounting portion 22 from above the semiconductor module 30. A plurality of mounting screws 41 are mounted on the mounting post 24.
  • the control circuit board 40 has a plurality of through holes 40a through which the mounting screws 41 are inserted.
  • the power and signal connector 50 is used to input a DC power source from a battery (not shown) to the semiconductor module 30 and various signals including signals from the torque sensor 12 and the vehicle speed sensor 9 to the control circuit board 40. Used.
  • the power and signal connector 50 is attached to the power and signal connector mounting portion 22 provided on the semiconductor module mounting portion 21 with a plurality of mounting screws 51.
  • the three-phase output connector 60 is used to output current from the a-phase output terminal 92a, the b-phase output terminal 92b, and the c-phase output terminal 92c.
  • the three-phase output connector 60 is attached to the three-phase output connector mounting portion 23 provided at the end in the width direction of the semiconductor module mounting portion 21 by a plurality of mounting screws 61.
  • the three-phase output connector 60 is formed with a plurality of through holes 60a through which the mounting screws 61 are inserted. Further, the cover 70 covers the case 20 to which the semiconductor module 30, the control circuit board 40, the power and signal connector 50, and the three-phase output connector 60 are attached from above the control circuit board 40. It is attached to cover.
  • FIG. 12A an insulating layer 32 is formed on one main surface of a metal substrate 31 (insulating layer forming step).
  • insulating layer forming step a plurality of wiring patterns 33a to 33d are formed on the insulating layer 32 (wiring pattern forming step).
  • solder paste solders 34a to 34d is applied on the plurality of wiring patterns 33a to 33d, respectively (solder paste applying step). Then, as shown in FIG.
  • one bare chip FET 35 is mounted on the solder paste (solder 33a) applied on one wiring pattern 33a among the plurality of wiring patterns 33a to 33d (bare chip).
  • another board mounting component 37 is mounted on the solder paste (solder 34d) applied on the other wiring pattern 33d.
  • Other bare chip FETs 35 are also mounted on the same or separate wiring pattern as the wiring pattern 33a.
  • solder paste (solder 34e, 34f) is applied on the source electrode S and the gate electrode D formed on the upper surface of the bare chip FET 35 (solder paste applying step).
  • solder paste (solder 34e) applied on the source electrode S of the bare chip FET 35 and the wiring pattern 33a other than the wiring pattern 33a on which the bare chip FET 35 is mounted among the plurality of wiring patterns 33a to 33d.
  • the source electrode copper connector 36a is mounted on the solder paste (solder 34b) applied on the other wiring pattern 33b (source electrode copper connector mounting step).
  • the semiconductor module intermediate assembly is configured.
  • the semiconductor module intermediate assembly constituted by the above steps is put in a reflow furnace (not shown), and the solder 34a between one wiring pattern 33a and the bare chip FET 35 among the plurality of wiring patterns 33a to 33d. Bonding, wiring pattern 33d and other board mounting component 37 via solder 34d, source electrode S formed on the upper surface of bare chip FET 35 and source electrode copper connector 36a via solder 34e
  • the other wiring pattern 33b of the plurality of wiring patterns 33a to 33d is joined to the source electrode copper connector 36a via the solder 34b, the gate electrode G formed on the upper surface of the bare chip FET 35 and the gate electrode copper connector 36b.
  • the semiconductor module 30 is completed.
  • the source electrode copper connector 36a is used to join the source electrode S of the bare chip FET 35 and the wiring pattern 33b on the substrate 31, and the gate electrode G of the bare chip FET 35 and another wiring pattern 33c on the substrate 31 are joined.
  • the copper connector 36b for the gate electrode, these junctions can be performed by solder mounting work. Therefore, the junction between the source electrode S of the bare chip FET 35 and the wiring pattern 33b on the substrate 31 and the gate electrode G of the bare chip FET 35 and the substrate 31 are performed.
  • the other wiring pattern 33c can be joined at the same time in the same process as the solder mounting operation performed when the bare chip FET 35 and other board mounting components 37 are mounted on the wiring patterns 33a and 33d on the board 31. it can. For this reason, the manufacturing tact of the semiconductor module 30 can be shortened, and dedicated equipment for wire bonding is not required, and the manufacturing cost of the semiconductor module 30 can be reduced.
  • the substrate 31 of the semiconductor module 30 aluminum is used for the substrate 31 of the semiconductor module 30, and a copper material is used for the copper connector 36a for the source electrode and the copper connector 36b for the gate electrode.
  • the linear expansion coefficient of aluminum is 23.6 ⁇ 10 ⁇ 6 / ° C.
  • the linear expansion coefficient of copper material is 16.8 ⁇ 10 ⁇ 6 / ° C.
  • the linear expansion coefficient of silicon of the bare chip FET 35 is 2.5 ⁇ . 10 ⁇ 6 / ° C. That is, the substrate 31 is more easily deformed with respect to temperature changes than the copper connectors 36a and 36b.
  • the copper connectors 36a and 36b are formed in a bridge shape, a narrow portion 36ag is provided in the vicinity of the bonding surface 36af with the electrode of the bare chip FET 35, and stress is applied to the bonding surface 36af with the electrode of the bare chip FET 35.
  • a relaxation part 36ak is provided.
  • the copper connectors 36a and 36b can be easily bent. Further, since the narrow portion 36ag is provided in the vicinity of the joint surface 36af, the solder joint between the copper connectors 36a and 36b and the bare chip FET 35 is difficult to peel off when the copper connectors 36a and 36b are bent with the narrow portion 36ag as a base point. Furthermore, the stress in the twisting direction can be relaxed by providing the stress relaxation part 36ak. In particular, when the stress relaxation shape of the copper connectors 36a and 36b is the slit shape shown in FIG. Even easier to follow. Moreover, since the so-called duplex system can be configured by using two contacts, electrical reliability is improved.
  • the tip R shape shown in FIG. 10 has an effect of releasing stress concentration at the corner when subjected to twisting. Furthermore, even in the case of the hole shape shown in FIG. Further, since the solder flows to the upper surface of the joint surface 36af due to the seepage wetting phenomenon and spreads radially, it is difficult for the solder to be peeled off even if it is twisted. Further, the shape of the source electrode copper connector 36a provided with the first dumbbell portion 36al and the second dumbbell portion 36am for relaxing the stress acting on the joint surface 36af and the joint surface 36aj will be described.
  • both or one of the first dumbbell part 36al and the second dumbbell part 36am may be further provided in addition to the stress relaxation part 36ak and the narrow part 36ag, but instead of the stress relaxation part 36ak or the narrow part 36ag. It may be provided. Moreover, you may provide both or one of the 1st dumbbell part 36al and the 2nd dumbbell part 36am, without providing the stress relaxation part 36ak and the narrow part 36ag.
  • the source electrode copper connector 36a has a bridge shape with a flat plate portion 36aa, a connection portion 36ab (first leg portion), and a connection portion 36ac (second leg portion). . More specifically, in the source electrode copper connector 36a, one end of the connection portion 36ab is connected to one end portion in the left-right direction (X-axis direction in FIG. 13) of the flat plate portion 36aa via the first bent portion 36ad. An outward joint surface 36af is formed at the other end of the connecting portion 36ab via the second bent portion 36ae. The lower surface of the bonding surface 36af is bonded to the source electrode of the bare chip FET 35 via the solder 34e.
  • a narrow first dumbbell portion 36al is formed in the vicinity of the joint surface 36af of the connection portion 36ab. More specifically, for example, semicircular arc-shaped notches are provided on both sides in the width direction of the connection portion 36ab so as to face each other, and the first dumbbell portion 36al having a dumbbell shape is formed in the connection portion 36ab. Is formed. One end of the connecting portion 36ac is connected to the other end portion in the left-right direction of the flat plate portion 36aa via the third bent portion 36ah, and the other end of the connecting portion 36ac is directed outward via the fourth bent portion 36ai. A joint surface 36aj is formed. The lower surface of the bonding surface 36aj is bonded to the wiring pattern 33b via the solder 34b.
  • the connecting portion 36ac is formed with a narrow second dumbbell portion 36am near the center. More specifically, for example, semicircular cutouts are provided on both sides in the width direction of the connection portion 36ac so that a second dumbbell portion 36am having a dumbbell shape is formed in the connection portion 36ac. Is formed.
  • the source electrode copper connector 36a With the narrow first dumbbell portion 36al and second dumbbell portion 36am, the source electrode copper connector 36a is easily twisted and easily absorbs displacement.
  • the source electrode copper connector 36a can further absorb deformation in the vertical direction and the horizontal direction by stress relaxation due to the bridge shape.
  • the connecting portion 36ab and the connecting portion 36ac are provided with a bending portion 36an and a bending portion 36ao that relieve stress acting on the joining surface 36af and the joining surface 36aj, instead of the first dumbbell portion 36al and the second dumbbell portion 36am. (See FIG. 14).
  • the shape of the source electrode copper connector 36a provided with the bending portion 36an and the bending portion 36ao will be described below.
  • both or one of the bending portion 36an and the bending portion 36ao may be further provided in addition to the stress relaxation portion 36ak and the narrow portion 36ag, but may be provided instead of the stress relaxation portion 36ak or the narrow portion 36ag. .
  • the source electrode copper connector 36a shown in FIG. 14 has the same basic configuration as the source electrode copper connector 36a shown in FIG. 13, but the shapes of the connecting portion 36ab and the connecting portion 36ac are different, and the source shown in FIG.
  • the connecting portion 36ab and the connecting portion 36ac of the electrode copper connector 36a are provided with a bending portion 36an and a bending portion 36ao which are formed to be bent in a substantially “7” shape.
  • the connecting portion 36ab is connected to one end of the flat plate portion 36aa in the left-right direction (X-axis direction in FIG. 7) and has a wide portion having the same width as the flat plate portion 36aa, and the width direction of the flat plate portion 36aa among the wide portions.
  • the connecting portion 36ab is curved in a generally “7” shape as a whole, and constitutes a curved portion 36an.
  • the connecting portion 36ac is substantially the same as the connecting portion 36ab.
  • the connecting portion 36ac is connected to the other end of the flat plate portion 36aa in the left-right direction (X-axis direction in FIG. 7) and has a wide portion having the same width as the flat plate portion 36aa.
  • the flat plate portion 36aa is composed of an oblique portion extending in an oblique direction from the other end portion in the width direction (Y-axis direction in FIG. 7) toward the center portion in the width direction of the joint surface 36aj.
  • the oblique portion is narrower than the wide portion, and has substantially the same width over the entire length from the wide portion to the joint surface 36aj.
  • the connecting portion 36ac is curved in a substantially “7” shape as a whole, and constitutes a curved portion 36ao. Since the curved portion 36an and the curved portion 36ao perform the same operation as the first dumbbell portion 36al and the second dumbbell portion 36am, the source electrode copper connector 36a of FIG. 14 is easily twisted and easily absorbs displacement. Further, the source electrode copper connector 36a of FIG. 14 can further absorb deformation in the vertical direction and the horizontal direction by stress relaxation due to the bridge shape.
  • the semiconductor module 30 according to the present embodiment is suitable even when the copper connectors 36a and 36b are thermally deformed in the reflow process or when the substrate 31 is expanded or contracted during the electric power steering (EPS) operation. Since the displacement can be absorbed, it is possible to prevent peeling of the solder joint between the copper connectors 36a and 36b and the bare chip FET 35, and to ensure the reliability of electrical connection. Further, the copper connectors 36a and 36b themselves can be prevented from being damaged.
  • EPS electric power steering
  • the bare chip FET 35 is used in the semiconductor module 30, other bare chip transistors such as the bare chip IGBT may be used instead of the bare chip FET 35.
  • the copper connector is used to connect the electrode formed on the top surface of the bare chip transistor and the wiring pattern other than the wiring pattern to which the bare chip transistor is joined among the plurality of wiring patterns. What is necessary is just to join via solder.
  • the bonding of the bare chip transistor electrode and the wiring pattern on the substrate is simultaneously performed in the same process as the solder mounting operation performed when the bare chip transistor or other substrate mounting component is mounted on the wiring pattern on the substrate. be able to.
  • the emitter electrode and the gate electrode formed on the bare chip IGBT are respectively joined to the wiring pattern on the substrate via solder using a copper connector.
  • the emitter of the bare chip IGBT is used.
  • the bonding of the electrode and the wiring pattern on the substrate and the bonding of the gate electrode of the bare chip IGBT and another wiring pattern on the substrate are performed when the bare chip IGBT or other substrate mounting component is mounted on the wiring pattern on the substrate. It can be performed simultaneously in the same process as the solder mounting operation.
  • the copper connector for the gate electrode is a first source electrode copper connector (180 ° in FIG. 4) that is 180 ° straight with respect to the gate electrode copper connector. Tr2 and Tr4) and a second source electrode copper connector (see Tr1, Tr3, and Tr5 in FIG. 4) that is 90 ° perpendicular to the gate electrode copper connector.
  • a first source electrode copper connector 180 ° in FIG. 4
  • Tr2 and Tr4 and a second source electrode copper connector (see Tr1, Tr3, and Tr5 in FIG. 4) that is 90 ° perpendicular to the gate electrode copper connector.
  • one type of copper connector for a gate electrode, and one type of copper connector for a source electrode selected from two types of copper connectors for a first source electrode and a copper connector for a second source electrode Use in combination.
  • the arrangement of the first source electrode copper connector relative to the gate electrode copper connector is preferably 95 to 265 °, and preferably 160 to 200. More preferably, the angle is more preferably 175 to 185 °, and most preferably 180 °.
  • the arrangement of the second source electrode copper connector relative to the gate electrode copper connector is preferably 5 to 175 °, and preferably 70 to 120. More preferably, it is 85 ° to 95 °, and most preferably 90 °.
  • this semiconductor module like the semiconductor module 30 described above, a degree of freedom is provided in the arrangement of the bare chip transistors mounted on the substrate, the degree of freedom in designing the wiring on the substrate is increased, and the semiconductor module on the substrate is increased.
  • the layout can be made compact. Furthermore, it is possible to easily make the length of the path of each phase of the three-phase motor on the substrate the same. As a result, the phase characteristics of the three-phase motor, particularly the impedance characteristics of each phase, can be easily matched, and ripple accuracy such as torque and speed can be improved.

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Abstract

 製造タクトの短縮と製造コストの削減とを実現すると共に、接合部の信頼性を確保することができる半導体モジュールを提供する。半導体モジュール(30)は、金属製の基板(31)と、基板(31)の上に形成された絶縁層(32)と、絶縁層(32)上に形成された複数の配線パターン(33a~33d)と、配線パターン(33a)上に半田(34a)を介して実装されるベアチップトランジスタ(35)と、ベアチップトランジスタ(35)の電極(S,G)上と配線パターン(33b,33c)上とを半田(34b,34c)を介して接合する銅コネクタ(36a,36b)とを備える。銅コネクタ(36a,36b)はブリッジ形状であり、電極(S,G)との接合面(36af)近傍に幅狭部(36ag)を設けると共に、電極(S,G)との接合面(36af)に応力緩和部(36ak)を設ける。

Description

半導体モジュール
 本発明は、自動車用電気機器に組み込まれるパワーモジュール等の半導体モジュールに関する。
 昨今、自動車等の車両における種々の電気機器の制御に電子装置が導入されてきた。電子装置が組み込まれた電気機器の一例として電動パワーステアリング装置では、自動車の操舵に係る電動モータが収容される筐体にモータ駆動部が設けられ、このモータ駆動部に電子装置が搭載される。この電子装置は、パワーモジュールとして、モータ駆動部に組み込まれる。
 パワーモジュールは、電動パワーステアリング装置のような比較的大きな電流で駆動される電気機器の制御に適した、例えば、FET(Field Effect Transistor)、IGBT(Insulated Gate Bipolar Transistor)等のパワー素子を搭載したいわゆる半導体モジュールとして構成される。この種のパワーモジュールは、車両に搭載されることから車載モジュール(In-vehicle Module)とも呼ばれる。
 従来、この種の半導体モジュールとして、例えば、特許文献1に記載の技術がある。この技術は、金属基板上の配線パターンとベアチップトランジスタとを接合する電気的配線にワイヤを使用したものである。
 また、例えば特許文献2に記載の技術のように、金属基板上に実装される半導体素子を電気的に接続するリード部品を、半導体上の電極よりも大きくすると共に、接触部の信頼性の確保のために複数の接点としたり、接点幅を広くしたりするものもある。
 さらに、例えば特許文献3に記載の技術のように、コネクタ配線の応力緩和を行うために、立ち上がり曲げ部を設けたり、配線途中にヒューズ形状(波形状)を設けたりするものもある。
JP2004-335725A JP2007-95984A JP2000-124398A
 しかしながら、上記特許文献1に記載の技術にあっては、ワイヤを使用した電気的配線を採用しているため、当該電気的配線をワイヤボンディング装置により実装することが必要となる。すなわち、その他の電子部品の半田実装とは異なり、製造工程を別で行う必要があり、製造タクトが長くなる。また、ワイヤボンディングの専用設備が必要となるため、製造コストが高くなる。
 また、上記特許文献2に記載の技術にあっては、大型の接点としているため、接合面が大きくなりすぎるために、捩れや熱収縮に弱くなる。そのため、接合部の信頼性を確保することが難しい。さらに、上記特許文献3に記載の技術にあっては、配線途中にヒューズ形状を設けているが、ヒューズ形状は成形が困難であり実用性に乏しい。
 そこで、本発明は、製造タクトの短縮と製造コストの削減とを実現すると共に、接合部の信頼性を確保することができる半導体モジュールを提供することを課題としている。
 上記課題を解決するために、本発明に係る半導体モジュールの一態様は以下の通りである。すなわち、本発明に係る半導体モジュールの一態様は、金属製の基板と、該基板の上に形成された絶縁層と、該絶縁層上に形成された複数の配線パターンと、該複数の配線パターンのうち一つの配線パターン上に半田を介して実装されるベアチップトランジスタと、該ベアチップトランジスタの上面に形成された電極上と前記複数の配線パターンのうち他の配線パターン上とを半田を介して接合する、銅板で構成される銅コネクタとを備えている。前記銅コネクタは、平板部と、該平板部の一端から立ち下がるように折り曲げられ前記電極上に接合される第1の脚部と、前記平板部の他端から立ち下がるように折り曲げられ前記他の配線パターン上に接合される第2の脚部とを有してブリッジ形状をなす。更に、前記第1の脚部に、前記電極との接合面とは反対側の端部から前記接合面が形成された端部へ向けて幅が狭くなる幅狭部を設ける。また、前記第1の脚部の前記電極との接合面に、当該接合面に作用する応力を緩和する形状を有する応力緩和部を設けることを特徴としている。
 すなわち、前記銅コネクタは、熱膨張率及び熱収縮率が前記基板とは異なることにより、加熱時もしくは冷却時に生じる銅コネクタ接合部の上下方向、左右方向、前後方向及び捻り方向の変位を吸収可能な形状を有することを特徴としている。このように、ベアチップトランジスタの電極と基板上の配線パターンとの接合部材として、銅板で構成される銅コネクタを用いる形態であるため、これらの接合を半田実装作業で行える。すなわち、ベアチップトランジスタの電極と基板上の配線パターンとの接合と、ベアチップトランジスタやその他の基板実装部品を基板上の配線パターン上に実装する際に行われる半田実装作業とを同一の設備、更には、同一の工程で同時に行うことができる。このため、半導体モジュールの製造タクトを短くすることができると共に、ワイヤボンディングの専用設備が不要になり、半導体モジュールの製造コストを安価にすることができる。
 さらに、銅コネクタをブリッジ形状とすることで、上下左右方向の変位が吸収可能となる。また、銅コネクタのベアチップトランジスタの電極と接合する第1の脚部に幅狭部を設けることで、前後方向及び捻り方向の変位が吸収可能となる。さらにまた、第1の脚部の上記電極との接合面に応力緩和部を設けるので、接合部に生じる応力を緩和することができる。したがって、リフロー工程や作動熱により熱膨張や熱収縮が発生した場合に、銅コネクタとベアチップトランジスタの電極との半田接合を剥がれ難くすることができ、接合部の信頼性を確保することができる。
 また、上記半導体モジュールにおいて、前記応力緩和部として、前記接合面に切り欠き部を形成したり、前記接合面を薄板で形成したり、前記接合面の角部に面取り部を形成したり、前記接合面の中央に孔を形成したりしてもよい。このように、切り欠き部を形成することで、接合部を2つにすることができると共に、各々の接合部の幅をさらに狭くすることができるため、捻りを受けても追従しやすくなる。また、接点が2つになることで所謂2重系を構成できるので、電気的信頼性が向上する。
 また、応力緩和部として薄板形状を採用した場合、板厚が薄いために捩れやすく、変位吸収しやすい。さらに、応力緩和部として先端R形状を採用した場合、捻りを受けたときの角部への応力集中を逃がす効果がある。さらにまた、応力緩和部として孔を形成した場合、半田が浸透ぬれ現象により接合面の上面に流れて放射状に広がるので、捻りを受けても半田が剥がれ難い。
 また、上記半導体モジュールにおいて、前記第1の脚部と前記第2の脚部にそれぞれ、前記接合面に作用する応力を緩和するダンベル形状のダンベル部を形成してもよい。
 本発明の半導体モジュールでは、ベアチップトランジスタの電極と基板上の配線パターンとの接合を、銅板で構成される銅コネクタを用いることにより、半田実装作業で行えるので、ベアチップトランジスタの電極と基板上の配線パターンとの接合を、ベアチップトランジスタやその他の基板実装部品を基板上の配線パターン上に実装する際に行われる半田実装作業と同一の工程で同時に行うことができる。このため、半導体モジュールの製造タクトを短くすることができると共に、ワイヤボンディングの専用設備が不要になり、半導体モジュールの製造コストを安価にすることができる。
 また、銅コネクタをブリッジ形状とすると共に、ベアチップトランジスタの電極と接合する第1の脚部に幅狭部と応力緩和部とを設けるので、あらゆる方向の変位が吸収可能となる。そのため、リフロー工程での銅コネクタの熱変形を吸収し、接合部の信頼性を確保することができる。さらに、製品使用時における温度変化による銅コネクタの破損を防止することができる。
本発明に係る半導体モジュールが用いられる電動パワーステアリング装置の基本構造を示す図である。 コントローラの制御系を示すブロック図である 半導体モジュールを含むコントローラの分解斜視図である。 半導体モジュールの平面図である。 ベアチップFETの概略平面図である。 ベアチップFETの電極と基板上の配線パターンとの接合状態を説明するための模式図である。 銅コネクタの形状を示す斜視図である。 応力緩和部の形状を示す図である。 応力緩和部の形状の別の例を示す図である。 応力緩和部の形状の別の例を示す図である。 応力緩和部の形状の別の例を示す図である。 半導体モジュールの製造方法を説明する図である。 第1の脚部と第2の脚部に形成したダンベル部の例を示す図である。 第1の脚部と第2の脚部に形成した湾曲部の例を示す図である。
 以下、本発明の実施の形態を図面に基づいて説明する。
 図1は、本発明に係る半導体モジュールが用いられる電動パワーステアリング装置の基本構造を示す図である。図1の電動パワーステアリング装置において、操向ハンドル1のコラム軸2は、減速ギア3、ユニバーサルジョイント4A及び4B、ピニオンラック機構5を経て走行車輪のタイロッド6に連結されている。コラム軸2には、操向ハンドル1の操舵トルクを検出するトルクセンサ7が設けられており、操向ハンドル1の操舵力を補助する電動モータ8が減速ギア3を介してコラム軸2に連結されている。
 電動パワーステアリング装置を制御するコントローラ10には、バッテリー(図示せず)から電力が供給されるとともに、イグニションキー(図示せず)を経てイグニションキー信号IGN(図2参照)が入力される。コントローラ10は、トルクセンサ7で検出された操舵トルクTsと車速センサ9で検出された車速Vとに基づいて、アシスト(操舵補助)指令となる操舵補助指令値の演算を行い、演算された操舵補助指令値に基づいて電動モータ8に供給する電流を制御する。コントローラ10は、主としてマイクロコンピュータで構成されるが、その制御装置の機構及び構成を示すと図2に示すようになる。
 トルクセンサ7で検出された操舵トルクTs及び車速センサ9で検出された車速Vは制御演算部としての制御演算装置11に入力され、制御演算装置11で演算された電流指令値をゲート駆動回路12に入力する。電流指令値等に基づいてゲート駆動回路12で形成されたゲート駆動信号は、FETのブリッジ構成で成るモータ駆動部13に入力され、モータ駆動部13は非常停止用の遮断装置14を経て3相ブラシレスモータで構成される電動モータ8を駆動する。3相ブラシレスモータの各相電流は電流検出回路15で検出され、検出された3相のモータ電流ia~icは制御演算装置11にフィードバック電流として入力される。また、3相ブラシレスモータには、ホールセンサ等の回転センサ16が取り付けられており、回転センサ16からの回転信号RTがロータ位置検出回路17に入力され、検出された回転位置θが制御演算装置11に入力される。
 また、イグニションキーからのイグニション信号IGNはイグニション電圧モニタ部18及び電源回路部19に入力され、電源回路部19から電源電圧Vddが制御演算装置11に入力されるとともに、装置停止用となるリセット信号RSが制御演算装置11に入力される。さらに、遮断装置14は、2相を遮断するリレー接点141及び142で構成されている。
 また、モータ駆動部13の回路構成について説明すると、電源ライン81に対し、直列に接続されたFETTr1及びTr2、FETTr3及びTr4、及びFETTr5及びTr6が直列に接続されている。そして、電源ライン81に対して、並列に接続されたFETTr1及びTr3、FETTr5及びTr2、及びFETTr4及びTr6が接地ライン82に接続されている。これにより、インバータを構成する。
 ここで、FETTr1及びTr2は、FETTr1のソース電極SとFETTr2のドレイン電極Dとが直列に接続され、3相モータのc相アームを構成し、c相出力ライン91cにて電流が出力される。また、FETTr3及びTr4は、FETTr3のソース電極SとFETTr4のドレイン電極Dとが直列に接続され、3相モータのa相アームを構成し、a相出力ライン91aにて電流が出力される。更に、FETTr5及びTr6は、FETTr5のソース電極SとFETTr6のドレイン電極Dとが直列に接続され、3相モータのb相アームを構成し、b相出力ライン91bにて電流が出力される。
 図3は、図1に示す電動パワーステアリング装置の半導体モジュールを含むコントローラ10の分解斜視図であり、コントローラ10は、ケース20と、モータ駆動部13を含むパワーモジュールとしての半導体モジュール30と、放熱用シート39と、制御演算装置11及びゲート駆動回路12を含む制御回路基板40と、電力及び信号用コネクタ50と、3相出力用コネクタ60と、カバー70とを備えている。
 ここで、ケース20は、略矩形状に形成され、半導体モジュール30を載置するための平板状の半導体モジュール載置部21と、半導体モジュール載置部21の長手方向端部に設けられた、電力及び信号用コネクタ50を実装するための電力及び信号用コネクタ実装部22と、半導体モジュール載置部21の幅方向端部に設けられた、3相出力用コネクタ60を実装するための3相出力用コネクタ実装部23とを備えている。
 そして、半導体モジュール載置部21には、半導体モジュール30を取り付けるための取付けねじ38がねじ込まれる複数のねじ孔21aが形成されている。また、半導体モジュール載置部21及び電力及び信号用コネクタ実装部22には、制御回路基板40を取り付けるための複数の取付けポスト24が立設され、各取付けポスト24には、制御回路基板40を取り付けるための取付けねじ41がねじ込まれるねじ孔24aが形成されている。更に、3相出力用コネクタ実装部23には、3相出力用コネクタ60を取り付けるための取付けねじ61がねじ込まれる複数のねじ孔23aが形成されている。
 また、半導体モジュール30は、前述したモータ駆動部13の回路構成を有し、図4に示すように、基板31に、6個のFETTr1~Tr6、電源ライン81に接続された正極端子81a、及び接地ライン82に接合された負極端子82aが実装されている。また、基板31には、a相出力ライン91aに接合されたa相出力端子92a、b相出力ライン91bに接合されたb相出力端子92b、及びc相出力ライン91cに接合されたc相出力端子92cを含む3相出力部90が実装されている。また、基板31上には、コンデンサを含むその他の基板実装部品37が実装されている。更に、半導体モジュール30の基板31には、半導体モジュール30を取り付けるための取付けねじ38が挿通する複数の貫通孔31aが設けられている。
 ここで、この半導体モジュール30において、6個のFETTr1~Tr6の基板31上への実装について説明する。各FETTr1~Tr6は、ベアチップFET(ベアチップトランジスタ)35で構成され、図5に示すように、ベアチップFET35上にソース電極Sとゲート電極Gとを備え、また、ベアチップFET35の下面には図示しないドレイン電極を備えている。半導体モジュール30は、図6に示すように、金属製の基板31を備え、基板31の上には、絶縁層32が形成されている。基板31は、アルミニウムなどの金属製である。また、この絶縁層32上には、複数の配線パターン33a~33dが形成されている。各配線パターン33a~33dは、銅やアルミニウムなどの金属、又はこの金属を含む合金で構成される。
 そして、複数の配線パターン33a~33dのうち一つの配線パターン33a上には半田34aを介して各FETTr1~Tr6を構成するベアチップFET35が実装されている。ベアチップFET35の下面に形成されたドレイン電極が半田34aを介して配線パターン33aに接合される。そして、ベアチップFET35のソース電極S上と複数の配線パターン33a~33dのうち他の配線パターン33b上とがソース電極用銅コネクタ36aでそれぞれ半田34e,34bを介して接合される。
 ソース電極用銅コネクタ36aは、銅板を打抜き及び曲げ加工することによって形成される。ソース電極用銅コネクタ36aは、平板部36aaと、平板部36aaの一端から立ち下がるように折り曲げられて延び、半田34eを介してベアチップFET35のソース電極Sに接合される接続部36abと、平板部36aaの他端から立ち下がるように折り曲げられて延び、半田34bを介して配線パターン33bに接合される接続部36acとを備えている。
 また、ベアチップFET35のゲート電極G上と複数の配線パターン33a~33dのうち更に他の配線パターン33c上とがゲート電極用銅コネクタ36bでそれぞれ半田34f,34cを介して接合される。
 ゲート電極用銅コネクタ36bは、銅板を打抜き及び曲げ加工することによって形成される。ゲート電極用銅コネクタ36bは、平板部36baと、平板部36baの一端から立ち下がるように折り曲げられて延び、半田34fを介してベアチップFET35のゲート電極Gに接合される接続部36bbと、平板部36baの他端から立ち下がるように折り曲げられて延び、半田34cを介して配線パターン33cに接合される接続部36bcとを備えている。
 また、絶縁層32上に形成された複数の配線パターン33a~33dのうち更にもう一つ他の配線パターン33d上には、半田34dを介してコンデンサなどの他の基板実装部品37が実装される。
 次に、ソース電極用銅コネクタ36aの形状について説明する。
 ソース電極用銅コネクタ36aは、図7に斜視図を示すように、平板部36aaと、接続部36ab(第1の脚部)と、接続部36ac(第2の脚部)とでブリッジ形状となっている。より具体的には、ソース電極用銅コネクタ36aは、平板部36aaの左右方向(図7のX軸方向)一端部に、第1屈曲部36adを介して接続部36abの一端が接続されており、接続部36abの他端は、第2屈曲部36aeを介して外向きの接合面36afが形成されている。この接合面36afの下面が半田34eを介してベアチップFET35のソース電極Sに接合される。
 また、接続部36abは、接合面36af近傍に幅狭部36agを有する。幅狭部36agは、第1屈曲部36adから第2屈曲部36aeに向けて幅が狭くなるテーパ形状となっている。平板部36aaの左右方向他端部には、第3屈曲部36ahを介して接続部36acの一端が接続されており、接続部36acの他端は、第4屈曲部36aiを介して外向きの接合面36ajが形成されている。この接合面36ajの下面が半田34bを介して配線パターン33bに接合される。
 さらに、接合面36afには、当該接合面36afに作用する応力を緩和する形状を有する応力緩和部36akを設ける。図8~図11は、応力緩和部36akの形状の例を示す図である。図8、図9及び図11において、符号PはソースPADである。図8に示す応力緩和部36akは、接合面36afにスリット(切り込み)を設けたものである。なお、当該スリットは、接合面36afの先端部を2つの面に分けられるものであれば、その形状や大きさは適宜選択可能である。
 応力緩和部36akの別の例としては、例えば図9に示すように、接合面36afの板厚を薄くするものもある。また、応力緩和部36akとしては、図10に示すように、接合面36af先端の角に面取り部を設けるものもある。ここで、面取り部は、図10に示すR面取りに代えて、大きな円でもよく、またC面取りでもよい。さらに、応力緩和部36akとしては、図11に示すように、接合面36afの中央に孔を設けるものもある。
 なお、ソース電極用銅コネクタ36aの形状は、ソース電極Sと配線パターン33bとを接合できるブリッジ形状であれば任意の形状をとることができる。また、応力緩和部36akの形状についても、ソース電極Sと接合できる形状であれば任意の形状をとることができる。但し、半田接合の際に後に述べるリフロー接合を行い、また、半導体モジュール30が稼働した際に発熱により高温になることから、熱応力を緩和できる形状とする。ゲート電極用銅コネクタ36bについても同様である。このように構成された半導体モジュール30は、図3に示すように、ケース20の半導体モジュール載置部21上に複数の取付けねじ38により取り付けられる。半導体モジュール30の基板31には、取付けねじ38が挿通する複数の貫通孔31aが形成されている。
 なお、半導体モジュール30を半導体モジュール載置部21上に取り付けるに際しては、放熱用シート39を半導体モジュール載置部21上に取付け、その放熱用シート39の上から半導体モジュール30を取り付ける。この放熱用シート39により、半導体モジュール30で発生した熱が放熱用シート39を介してケース20に放熱される。また、制御回路基板40は、基板上に複数の電子部品を実装して制御演算装置11及びゲート駆動回路12を含む制御回路を構成するものである。制御回路基板40は、半導体モジュール30を半導体モジュール載置部21上に取り付けた後、半導体モジュール30の上方から半導体モジュール載置部21及び電力及び信号用コネクタ実装部22に立設された複数の取付けポスト24上に複数の取付けねじ41により取り付けられる。制御回路基板40には、取付けねじ41が挿通する複数の貫通孔40aが形成されている。
 また、電力及び信号用コネクタ50は、バッテリー(図示せず)からの直流電源を半導体モジュール30に、トルクセンサ12や車速センサ9からの信号を含む各種信号を制御回路基板40に入力するために用いられる。電力及び信号用コネクタ50は、半導体モジュール載置部21に設けられた電力及び信号用コネクタ実装部22に複数の取付けねじ51により取り付けられる。
 そして、3相出力用コネクタ60は、a相出力端子92a、b相出力端子92b、及びc相出力端子92cからの電流を出力するために用いられる。3相出用コネクタ60は、半導体モジュール載置部21の幅方向端部に設けられた3相出力用コネクタ実装部23に複数の取付けねじ61により取り付けられる。3相出力コネクタ60には、取付けねじ61が挿通する複数の貫通孔60aが形成されている。更に、カバー70は、半導体モジュール30、制御回路基板40、電力及び信号用コネクタ50、及び3相出力用コネクタ60が取り付けられたケース20に対し、制御回路基板40の上方から当該制御回路基板40を覆うように取り付けられる。
 次に、半導体モジュール30の製造方法について図12を参照して説明する。半導体モジュール30の製造に際し、先ず、図12(a)に示すように、金属製の基板31の一方の主面上に絶縁層32を形成する(絶縁層形成工程)。次いで、絶縁層32上に複数の配線パターン33a~33dを形成する(配線パターン形成工程)。その後、図12(b)に示すように、複数の配線パターン33a~33d上にそれぞれ半田ペースト(半田34a~34d)を塗布する(半田ペースト塗布工程)。そして、図12(c)に示すように、複数の配線パターン33a~33dのうち一つの配線パターン33a上に塗布された半田ペースト(半田33a)上にベアチップFET35の一つを搭載するとともに(ベアチップFET搭載工程)、他の配線パターン33d上に塗布された半田ペースト(半田34d)上にその他の基板実装部品37を搭載する。その他のベアチップFET35についても、配線パターン33aと同一あるいは別個の配線パターン上に搭載する。
 次いで、図12(d)に示すように、ベアチップFET35の上面に形成されたソース電極S及びゲート電極D上に半田ペースト(半田34e,34f)を塗布する(半田ペースト塗布工程)。その後、図12(e)に示すように、ベアチップFET35のソース電極S上に塗布された半田ペースト(半田34e)上及び複数の配線パターン33a~33dのうちベアチップFET35が搭載された配線パターン33a以外の他の配線パターン33b上に塗布された半田ペースト(半田34b)上に、ソース電極用銅コネクタ36aを搭載する(ソース電極用銅コネクタ搭載工程)。
 また、ベアチップFET35のゲート電極G上に塗布された半田ペースト(半田34f)上、及び複数の配線パターン33a~33dのうちベアチップFET35が搭載された配線パターン33a及びソース電極用銅コネクタ36aが搭載された配線パターン33b以外の更に他の配線パターン33c上に塗布された半田ペースト(半田34c)上に、ゲート電極用銅コネクタ36bを搭載する(ゲート電極用銅コネクタ搭載工程)。これにより、半導体モジュール中間組立体が構成される。
 そして、以上の工程により構成された半導体モジュール中間組立体をリフロー炉(図示せず)に入れて、複数の配線パターン33a~33dのうち一つの配線パターン33aとベアチップFET35との半田34aを介しての接合、配線パターン33dとその他の基板実装部品37との半田34dを介しての接合、ベアチップFET35の上面に形成されたソース電極Sとソース電極用銅コネクタ36aとの半田34eを介しての接合、複数の配線パターン33a~33dのうち他の配線パターン33bとソース電極用銅コネクタ36aとの半田34bを介しての接合、ベアチップFET35の上面に形成されたゲート電極Gとゲート電極用銅コネクタ36bとの半田34fを介しての接合、及び複数の配線パターン33a~33dのうち更に他の配線パターン33cとゲート電極用銅コネクタ36bとの半田34cを介しての接合を一括して行う(接合工程)。これにより、半導体モジュール30は完成する。
 ここで、ベアチップFET35のソース電極Sと基板31上の配線パターン33bとの接合にソース電極用銅コネクタ36aを用い、ベアチップFET35のゲート電極Gと基板31上の別の配線パターン33cとの接合にゲート電極用銅コネクタ36bを用いることにより、これらの接合を半田実装作業により行えるので、ベアチップFET35のソース電極Sと基板31上の配線パターン33bとの接合及びベアチップFET35のゲート電極Gと基板31上の別の配線パターン33cとの接合を、ベアチップFET35やその他の基板実装部品37を基板31上の配線パターン33a,33d上に実装する際に行われる半田実装作業と同一の工程で同時に行うことができる。このため、半導体モジュール30の製造タクトを短くすることができるとともに、ワイヤボンディングの専用設備が不要になり、半導体モジュール30の製造コストを安価にすることができる。
 ところで、半導体モジュール30の基板31にはアルミニウムが用いられており、ソース電極用銅コネクタ36a及びゲート電極用銅コネクタ36bには銅材が用いられている。アルミニウムの線膨張係数は23.6×10-6/℃であり、銅材の線膨張係数は16.8×10-6/℃であり、ベアチップFET35のシリコンの線膨張係数は2.5×10-6/℃である。すなわち、基板31の方が、銅コネクタ36a及び36bよりも温度変化に対して変形しやすい。
 そのため、リフロー工程や、電動パワーステアリング(EPS)作動中の発熱により高温となると、基板31及びベアチップFET35と銅コネクタ36a,36bとの膨張率の違いにより、銅コネクタ36a,36bに応力がかかる。このとき、銅コネクタ36a,36bがこの応力を緩和できない構造となっていると、ベアチップFET35との半田接合が剥がれてしまうおそれがある。
 これに対して、本実施形態では、銅コネクタ36a及び36bをブリッジ形状とし、ベアチップFET35の電極との接合面36af付近に幅狭部36agを設けると共に、ベアチップFET35の電極との接合面36afに応力緩和部36akを設ける。このように、銅コネクタ36a,36bをブリッジ形状とすることで、上下左右方向(図7のZ軸方向,X軸方向)の変位が吸収可能となる。また、幅狭部36agを設けることで、曲げの基点を細くすることができ、前後方向(図7のY軸方向)及び捻り方向の変位が吸収可能となる。
 すなわち、熱膨張、熱収縮により基板31や銅コネクタ36a,36bに変形が生じた場合であっても、銅コネクタ36a,36bを曲がりやすくすることができる。また、幅狭部36agを接合面36af近傍に設けるので、銅コネクタ36a,36bが幅狭部36agを基点に曲がったときの、銅コネクタ36a,36bとベアチップFET35との半田接合が剥がれにくい。
 さらに、応力緩和部36akを設けることで、捻り方向への応力を緩和することができる。特に、銅コネクタ36a,36bの応力緩和形状を、図8に示すスリット形状とした場合、ベアチップFET35との接点が2つになると共に、各々の接合部の幅がさらに狭くなるため、捻りを受けても追従しやすくなる。また、接点が2つになることで所謂2重系を構成できるので、電気的信頼性が向上する。
 また、図9に示す薄板形状とした場合、板厚が薄いために捩れやすく、変位吸収しやすい。図10に示す先端R形状とした場合、捻りを受けたときの角部への応力集中を逃がす効果がある。さらに、図11に示す孔形状とした場合にも、捩りを受けても追従しやすくなる。また、半田が浸透ぬれ現象により接合面36afの上面に流れて放射状に広がるので、捻りを受けても半田が剥がれ難い。
 またさらに、接合面36af及び接合面36ajに作用する応力を緩和する第1ダンベル部36al及び第2ダンベル部36amを設けたソース電極用銅コネクタ36aの形状について説明する。なお、第1ダンベル部36al及び第2ダンベル部36amの両方又は一方を、応力緩和部36ak及び幅狭部36agに加えて更に設けてもよいが、応力緩和部36ak又は幅狭部36agに代えて設けてもよい。また、応力緩和部36ak及び幅狭部36agを設けることなく、第1ダンベル部36al及び第2ダンベル部36amの両方又は一方を設けてもよい。
 図13に示すように、ソース電極用銅コネクタ36aは、平板部36aaと、接続部36ab(第1の脚部)と、接続部36ac(第2の脚部)とでブリッジ形状となっている。より具体的には、ソース電極用銅コネクタ36aは、平板部36aaの左右方向(図13のX軸方向)の一端部に、第1屈曲部36adを介して接続部36abの一端が接続されており、接続部36abの他端には、第2屈曲部36aeを介して外向きの接合面36afが形成されている。この接合面36afの下面が半田34eを介してベアチップFET35のソース電極に接合される。
 接続部36abの接合面36af近傍には、幅狭な第1ダンベル部36alが形成されている。詳述すると、接続部36abの幅方向両側部に、例えば半円弧状の切り欠きが対向して設けられていて、この切り欠きにより、接続部36abにはダンベル形状をなす第1ダンベル部36alが形成されている。
 平板部36aaの左右方向他端部には、第3屈曲部36ahを介して接続部36acの一端が接続されており、接続部36acの他端は、第4屈曲部36aiを介して外向きの接合面36ajが形成されている。この接合面36ajの下面が半田34bを介して配線パターン33bに接合される。
 接続部36acには、そのほぼ中央付近に、幅狭な第2ダンベル部36amが形成されている。詳述すると、接続部36acの幅方向両側部に、例えば半円弧状の切り欠きが対向して設けられていて、この切り欠きにより、接続部36acにはダンベル形状をなす第2ダンベル部36amが形成されている。
 この幅狭な第1ダンベル部36al及び第2ダンベル部36amにより、ソース電極用銅コネクタ36aは、捩れやすく、変位吸収しやすい。第1ダンベル部36al及び第2ダンベル部36amによる応力緩和の効果としては、第1ダンベル部36al及び第2ダンベル部36amが伸び縮みするだけでなく、第1ダンベル部36al及び第2ダンベル部36amの曲部が折れる方向にも変形できるので、板バネの効果が得られる。かつ、ソース電極用銅コネクタ36aは、ブリッジ形状による応力緩和によって上下方向、左右方向への変形吸収が更に可能となる。
 なお、接続部36ab及び接続部36acには、第1ダンベル部36al及び第2ダンベル部36amの代わりに、接合面36af及び接合面36ajに作用する応力を緩和する湾曲部36an及び湾曲部36aoを設けてもよい(図14を参照)。湾曲部36an及び湾曲部36aoを設けたソース電極用銅コネクタ36aの形状について、以下に説明する。ただし、湾曲部36an及び湾曲部36aoの両方または一方を、応力緩和部36ak及び幅狭部36agに加えて更に設けてもよいが、応力緩和部36ak又は幅狭部36agに代えて設けてもよい。また、応力緩和部36ak及び幅狭部36agを設けることなく、湾曲部36an及び湾曲部36aoの両方又は一方を設けてもよい。
 図14に示すソース電極用銅コネクタ36aは、図13に示すソース電極用銅コネクタ36aと基本構成は同様であるが、接続部36ab及び接続部36acの形状が異なっており、図14に示すソース電極用銅コネクタ36aの接続部36ab及び接続部36acには、略“7”の字状に湾曲して形成された湾曲部36an及び湾曲部36aoが設けられている。
 詳述すると、接続部36abは、平板部36aaの左右方向(図7のX軸方向)一端部に接続され平板部36aaと同幅の幅広部と、この幅広部のうち平板部36aaの幅方向(図7のY軸方向)一端部から、平板部36aaの幅方向中央部に位置する接合面36afに向かって斜め方向に延びる斜め部とで構成されている。また、この斜め部は、幅広部よりも幅狭で、前記幅広部から接合面36afまでの全長にわたって略同幅である。これにより接続部36abは、全体として略“7”の字状に湾曲しており、湾曲部36anを構成している。
 一方、接続部36acも接続部36abとほぼ同様であり、平板部36aaの左右方向(図7のX軸方向)他端部に接続され平板部36aaと同幅の幅広部と、この幅広部のうち平板部36aaの幅方向(図7のY軸方向)他端部から、接合面36ajの幅方向中央部に向かって斜め方向に延びる斜め部とで構成されている。また、この斜め部は、幅広部よりも幅狭で、前記幅広部から接合面36ajまでの全長にわたって略同幅である。これにより接続部36acは、全体として略“7”の字状に湾曲しており、湾曲部36aoを構成している。
 これら湾曲部36an及び湾曲部36aoにより、第1ダンベル部36al及び第2ダンベル部36amと同様の作用が奏されるため、図14のソース電極用銅コネクタ36aは、捩れやすく、変位吸収しやすい。かつ、図14のソース電極用銅コネクタ36aは、ブリッジ形状による応力緩和によって上下方向、左右方向への変形吸収が更に可能となる。
 以上のように、本実施形態の半導体モジュール30は、銅コネクタ36a及び36bがリフロー工程で熱変形する場合や、電動パワーステアリング(EPS)作動中に基板31が膨張又は収縮する場合でも、適切に変位吸収することができるので、銅コネクタ36a及び36bとベアチップFET35との半田接合の剥がれを防止することができ、電気的接続の信頼性を確保することができる。また、銅コネクタ36a,36b自身の破損も防止することができる。
 以上、本発明の実施形態について説明してきたが、本発明はこれに限定されずに種々の変更、改良を行うことができる。
 例えば、半導体モジュール30においてベアチップFET35を用いているが、ベアチップFET35に限らず、ベアチップIGBTなどの他のベアチップトランジスタを用いてもよい。そして、その他のベアチップトランジスタを用いる場合には、銅コネクタにより、ベアチップトランジスタの上面に形成された電極上と複数の配線パターンのうちベアチップトランジスタが接合された配線パターン以外の他の配線パターン上とを半田を介して接合すればよい。これにより、ベアチップトランジスタの電極と基板上の配線パターンとの接合を、ベアチップトランジスタやその他の基板実装部品を基板上の配線パターン上に実装する際に行われる半田実装作業と同一の工程で同時に行うことができる。
 そして、ベアチップトランジスタとしてベアチップIGBTを用いる場合、ベアチップIGBT上に形成されたエミッタ電極及びゲート電極を、それぞれ、銅コネクタを用いて基板上の配線パターンに半田を介して接合することが好ましい。このように、ベアチップIGBTを用い、ベアチップIGBT上に形成されたエミッタ電極及びゲート電極を、それぞれ、銅コネクタを用いて基板上の配線パターンに半田を介して接合する場合には、ベアチップIGBTのエミッタ電極と基板上の配線パターンとの接合及びベアチップIGBTのゲート電極と基板上の別の配線パターンとの接合を、ベアチップIGBTやその他の基板実装部品を基板上の配線パターン上に実装する際に行われる半田実装作業と同一の工程で同時に行うことができる。
 更に、半導体モジュール30において、ゲート電極用銅コネクタは1種類であり、ソース電極用銅コネクタは、ゲート電極用銅コネクタに対して180°ストレート配置とする第1ソース電極用銅コネクタ(図4のTr2及びTr4を参照)と、ゲート電極用銅コネクタに対して90°直角配置とする第2ソース電極用銅コネクタ(図4のTr1、Tr3、及びTr5を参照)との2種類であり、1つのベアチップFETにおいて、1種類のゲート電極用銅コネクタと、2種類の第1ソース電極用銅コネクタ及び第2ソース電極用銅コネクタのうちから選択されたいずれか一方のソース電極用銅コネクタとを組み合わせて使用するとよい。
 なお、ゲート電極用銅コネクタに対する第1ソース電極用銅コネクタの配置(ゲート電極用銅コネクタと第1ソース電極用銅コネクタのなす角度)は、95~265°とすることが好ましく、160~200°とすることがより好ましく、175~185°とすることがさらに好ましく、180°とすることが最も好ましい。
 また、ゲート電極用銅コネクタに対する第2ソース電極用銅コネクタの配置(ゲート電極用銅コネクタと第2ソース電極用銅コネクタのなす角度)は、5~175°とすることが好ましく、70~120°とすることがより好ましく、85~95°とすることがさらに好ましく、90°とすることが最も好ましい。
 この半導体モジュールによれば、前述の半導体モジュール30と同様に、基板上に実装されるベアチップトランジスタの配置に自由度が生まれ、基板上の配線の設計の自由度が増大し、基板上における半導体モジュールのレイアウトをコンパクトにすることができる。さらに、基板上における3相モータの各相の径路の長さを同一にすることを容易に行うことができる。これにより、3相モータの各相特性、特に各相のインピーダンス特性を容易に一致させることができ、トルクや速度等のリップル精度を向上することが可能になる。
 1…操向ハンドル、2…コラム軸、3…減速ギア、4A,4B…ユニバーサルジョイント、5…ピニオンラック機構、6…タイロッド、7…トルクセンサ、8…電動モータ、9…車速センサ、10…コントローラ、11…制御演算装置、12…ゲート駆動回路、13…モータ駆動部、14…非常停止用の遮断装置、15…電流検出回路、16…回転センサ、17…ロータ位置検出回路、18…IGN電圧モニタ部、19…電源回路部、20…ケース、21…半導体モジュール載置部、21a…ねじ孔、22…電力及び信号用コネクタ実装部、23…3相出力用コネクタ実装部、23a…ねじ孔、24…取付けポスト、24a…ねじ孔、30…半導体モジュール、31…基板、31a…貫通孔、32…絶縁層、33a~33d…配線パターン、34a~34d…半田、35…ベアチップFET(ベアチップトランジスタ)、36a…ソース電極用銅コネクタ、36aa…平板部、36ab…接続部(第1の脚部)、36ac…接続部(第2の脚部)、36ad…第1屈曲部、36ae…第2屈曲部、36af…接合面、36ag…幅狭部、36ah…第3屈曲部、36ai…第4屈曲部、36aj…接合面、36ak…応力緩和部、36al…第1ダンベル部、36am…第2ダンベル部、36b…ゲート電極用銅コネクタ、36ba…平板部、36bb…接続部、36bc…接続部、37…基板実装部品、38…取付けねじ、39…放熱用シート、40…制御回路基板、40a…貫通孔、41…取付けねじ、50…電力及び信号用コネクタ、51…取付けねじ、60…3相出力用コネクタ、60a…貫通孔、61…取付けねじ、70…カバー、81…電源ライン、81a…正極端子、82…接地ライン、82a…負極端子、90…3相出力部、91a…a相出力ライン、91b…b相出力ライン、91c…c相出力ライン、G…ゲート電極(電極)、S…ソース電極(電極)

Claims (6)

  1.  金属製の基板と、該基板の上に形成された絶縁層と、該絶縁層上に形成された複数の配線パターンと、該複数の配線パターンのうち一つの配線パターン上に半田を介して実装されるベアチップトランジスタと、該ベアチップトランジスタの上面に形成された電極上と前記複数の配線パターンのうち他の配線パターン上とを半田を介して接合する、銅板で構成される銅コネクタとを備え、
     前記銅コネクタは、平板部と、該平板部の一端から立ち下がるように折り曲げられ前記電極上に接合される第1の脚部と、前記平板部の他端から立ち下がるように折り曲げられ前記他の配線パターン上に接合される第2の脚部とを有してブリッジ形状をなし、
     前記第1の脚部の前記電極との接合面近傍に、前記第1の脚部の他の部分と比較して幅の狭い幅狭部を設けると共に、前記第1の脚部の前記電極との接合面に、当該接合面に作用する応力を緩和する形状を有する応力緩和部を設けることを特徴とする半導体モジュール。
  2.  前記応力緩和部として、前記接合面に切り欠き部を形成したことを特徴とする請求項1に記載の半導体モジュール。
  3.  前記応力緩和部として、前記接合面を薄板で形成したことを特徴とする請求項1又は2に記載の半導体モジュール。
  4.  前記応力緩和部として、前記接合面の角部に面取り部を形成したことを特徴とする請求項1~3の何れか1項に記載の半導体モジュール。
  5.  前記応力緩和部として、前記接合面の中央に孔を形成したことを特徴とする請求項1~4の何れか1項に記載の半導体モジュール。
  6.  前記第1の脚部と前記第2の脚部にそれぞれ、前記接合面に作用する応力を緩和するダンベル形状のダンベル部を形成したことを特徴とする請求項1~5の何れか1項に記載の半導体モジュール。
PCT/JP2013/006342 2012-11-05 2013-10-25 半導体モジュール WO2014068937A1 (ja)

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