WO2014067522A1

WO2014067522A1 - Power factor correction circuit

Info

Publication number: WO2014067522A1
Application number: PCT/DK2013/050311
Authority: WO
Inventors: Peter Jensen; Hans Christian Holm; Jens Ulrik Jaeger
Original assignee: Danfoss Power Electronics A/S
Priority date: 2012-10-29
Filing date: 2013-10-01
Publication date: 2014-05-08

Abstract

A power factor correction circuit including a boost converter and a controller is described. The boost converter comprises a semiconductor switch including a MOSFET and an IGBT connected in parallel. In a normal mode of operation, the controller is configured to provide signals for driving the semiconductor switch to both the MOSFET and the IGBT. In a low noise mode of operation, the controller is configured to provide said signals for driving the semiconductor switch to the IGBT, such that the MOSFET is effectively disabled.

Description

POWER FACTOR CORRECTION CIRCUIT

FIELD OF THE INVENTION

The present invention relates to a power factor correction circuit. In particular, the invention relates to a switch used as part of a power factor correction circuit.

BACKGROUND OF THE INVENTION

Power factor correction is a well-known method for shaping voltage and current waveforms such that the apparent power deliver to a load (such as a motor) is well matched to the actual power delivered to the load. Amongst other advantages, the use of power factor correction increases the efficiency of operation of a load, thereby reducing the power that needs to be drawn from a power supply.

Figure 1 is a block diagram of a system, indicated generally by the reference numeral 1, incorporating a simple power factor correction arrangement. The system 1 comprises an AC power supply 2, a rectifier 4, a power factor correction (PFC) circuit 6 and a load 8.

Figure 2 shows an exemplary implementation of the PFC 6. The PFC 6 comprises an inductor 10, a switch 12, a diode 14 and a capacitor 16. The PFC 6 also includes a power factor controller 18. The inductor 10 has a first terminal for coupling to a first output of the rectifier 4 and a second terminal coupled to a first terminal of the switch 12 and the anode of the diode 14. The switch 12 has a second terminal for coupled to a second output of the rectifier 4. The capacitor 16 has a first terminal coupled to the cathode of the diode 14 and to a first output of the PFC 6. The capacitor 16 also has a second terminal coupled to the second terminal of the switch 12 and to a second output of the PFC 6. The power factor controller 18 provides switching instructions for the switch 12, as described further below.

The PFC 6 is based on a boost converter. As is well known in the art, if the switch 12 is switched at a sufficiently high frequency, then the voltage across the two outputs of the PFC circuit 6 will be higher than the voltage across the two inputs of the PFC circuit. This is due to the reluctance of the inductor 10 to changes in voltage. The PFC controller 18 can therefore be used to control the switching of the switch 12 in order to provide a desired voltage at the output of the PFC circuit 6 (and hence provide a desired voltage to the load 8) .

A problem with switch-based PFC circuits, such as that shown in Figure 2, is the inevitable generation of noise in the form of electromagnetic interference (EMI) due to the high frequency switching required. A variety of mechanisms exist for reducing EMI, such as providing a filter. Many such methods require additional circuits, which require additional cost and additional circuit space. The present invention seeks to address at least some of the problems outlined above.

SUMMARY OF THE INVENTION

The present invention provides a power factor correction circuit

comprising a boost converter and a controller, wherein the boost converter comprises a semiconductor switch including a MOSFET and an IGBT connected in parallel, wherein : in a first mode of operation, the controller is configured to provide signals for driving the semiconductor switch to both the MOSFET and the IGBT; and in a second (low noise) mode of operation, the controller is configured to provide said signals for driving the semiconductor switch to the IGBT, such that the MOSFET is effectively disabled.

The present invention also provides a method for driving a semiconductor switch of a power factor correction circuit, wherein the power factor correction circuit comprises a boost converter and a controller and the boost converter comprises a semiconductor switch including a MOSFET and an IGBT connected in parallel, the method comprising : providing signals for driving the semiconductor switch to both the MOSFET and the IGBT in a first mode of operation; and providing signals for driving the semiconductor switch to the IGBT in a second (low noise) mode of operation, such that the MOSFET is effectively disabled. The steps of providing signals for driving the semiconductor switch may include providing a MOSFET enable signal indicative of the mode of operation.

Thus, the controller can be used to adjust the function of the PFC in order to switch from a high efficiency, high noise mode (which might, in some circumstances, be considered to be a normal mode) to a low efficiency, low noise mode. The advantage of deliberately providing a low-efficiency mode is that in some uses of a PFC, the generation of EMI noise may be a more important consideration that the efficiency of the switch. Thus, the invention enables efficiency and EMI noise performance to be traded off against one another. The controller may be implemented as a software module or in some other way, such as a programmable memory module or as a hardware module that may be replaced if the functionality is required to be changed. In this way, the invention can enable in-field EMI issues to be addressed by changing the mode of operation, perhaps requiring just a simple software change. The controller may comprise a first output for providing the signals for driving the semiconductor switch and a second output for providing an enable signal for said MOSFET. Thus, the enable signal may be in an enabled state in the first mode and a disabled state in the second mode. The power factor correction circuit may further comprise a MOSFET enabling switch, wherein the second output of the controller controls the state of the MOSFET enabling switch.

In one form of the invention a gate driver is provided, wherein the gate driver receives the signals for driving the semiconductor switch and the enable signal for said MOSFET, wherein the gate driver is configured to provide driving signals for the MOSFET and the IGBT accordingly.

In an alternative form of the invention, the controller may comprise a first output for providing the signals for driving the MOSFET and a second output for providing the signals for driving the IGBT.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described in further detail with reference to the following schematic drawings, in which :

Figure 1 is a block diagram of a power factor correction circuit;

Figure 2 shows a boost converter that may be used in the power factor correction circuit of Figure 1;

Figure 3 shows a power factor correction circuit in accordance with an aspect of the present invention;

Figure 4 shows a gate drive arrangement in accordance with an aspect of the present invention;

Figure 5 shows a gate drive arrangement in accordance with an aspect of the present invention; and Figure 6 shows a gate drive arrangement in accordance with a further aspect of the present invention .

DETAILED DESCRIPTION OF THE INVENTION

Figure 3 shows a PFC circuit, indicated generally by the reference numeral 6' that may be used in the power factor arrangement 1 instead of the PFC circuit 6 described above.

The PFC circuit 6' includes the inductor 10, diode 14 and capacitor 16 described above. The PFC circuit 6' additionally includes a switch 22 (instead of the switch 12 described above) and a PFC controller 28

(instead of the PFC controller 18). As shown in Figure 3, the switch 22 comprises two inputs, each coupled to an output of the PFC controller. The switch 22 comprises a MOSFET 24 and an IGBT 26 connected in parallel. Such an arrangement enables a switch to take advantage of the benefits of a MOSFET (high efficiency caused by low switching and conducting losses) and the benefits of an IGBT (low cost). Providing an IGBT in parallel with the MOSFET is well known.

The inventors have realised that by providing different control signals to the MOSFET 24 and the IGBT 26, the EMI performance of the PFC circuit 6' can be changed . In a first mode of operation, the switch 22 is driven with the MOSFET and IGBT operating in parallel. In a second mode of operation, the MOSFET is disabled. Thus, in the second mode of

operation, only the IGBT is used to provide the switching function of the switch 22.

In this way, the PFC circuit 20 enables different switch configurations to be selected. In the first mode (with the MOSFET 24 and the IGBT 26 operated in parallel), the switch 22 (and hence the PFC circuit 6') operates in a high efficiency, high noise mode. In the second mode (with the MOSFET 24 disabled), the switch 20 (and hence the PFC circuit 6') operates in a low efficiency, low noise mode. The advantage of

deliberately providing a low-efficiency switch in the second mode is that in some PFC implementations, the generation of EMI noise is a more important consideration that the efficiency of the switch itself.

If the PFC controller 28 is sufficiently flexible, then the PFC circuit 6' enables a user to select between the two modes of operation, even after the hardware for the PFC controller 28 has been installed. The PFC controller 28 might be implemented using a software module, or using a programmable module that can be readily re-programmed. Thus, the switch configuration (and hence the mode of operation) can be adjusted in situ. Moreover, the PFC circuit 6' can be provided with the same hardware elements as the PFC circuit 6. As no additional hardware elements are required, there is no additional circuit footprint.

The PFC controller 18 of the prior art PFC controller 6 typically drives the switch 12 using the output of a pulse width modulated (PWM) converter. With the MOSFET 24 and the IGBT 26 connected in parallel, both can be driven by the some PWM signal. However, the switch arrangement 20 of the present invention requires that the MOSFET 24 and the IGBT 26 can have different control inputs. Figures 4 to 6 show three different control mechanisms that could be used to implement the circuit of Figure 3. The skilled person will be aware of many alternative configurations that could be provided.

Figure 4 shows a gate drive arrangement, indicated generally by the reference numeral 40, in accordance with an aspect of the present invention. The gate drive arrangement 40 forms part of the PFC

controller 28 described above. The gate drive arrangement 40 comprises a PWM generator 42, a gate driver 44 and a switch 46. The gate driver 44 has a first output that provides a gate drive signal to the MOSFET 24 via the switch 46 (so that the gate drive signal only reaches the MOSFET when the switch is closed). The gate drive has a second output that provides a gate drive signal to the IGBT 26.

The PWM generator 42 generates PWM signals for the switch arrangement 22 in accordance with a PFC control algorithm. That control algorithm does not form part of the present invention and is not described further here. In addition to the PWM output for driving the switch arrangement, a control output is provided by the PWM generator 42. The control output indicates whether the switch arrangement is being operated in the first mode (such that the MOSFET 24 and the IGBT 26 are both being driven by the PWM signals) or in the second mode (such that only the IGBT 26 is driven). The control input is used to close the switch 46 in the first mode and to open that switch in the second mode.

Figure 5 shows a gate drive arrangement, indicated generally by the reference numeral 50, in accordance with an aspect of the present invention. The gate drive arrangement 50 forms part of the PFC

controller 28 described above and has many similarities with the gate drive arrangement 40. The gate drive arrangement 50 comprises a PWM generator 52 and a gate driver 54. The PWM generator 52 provides the same outputs as the PWM generator 52 described above, with the exception that the control signal provided to the switch 46 in the gate drive arrangement 40 is provided to a second input to the gate driver 54.

The gate driver 54 has a first output providing a gate drive signal to the MOSFET 24 and a second output that provides a gate drive signal to the IGBT 26. Thus, the gate driver 54 implements the function of the switch 46 described above. Figure 6 shows a gate drive arrangement, indicated generally by the reference numeral 60, in accordance with an aspect of the present invention. The gate drive arrangement 60 forms part of the PFC controller 28 and has many similarities with the gate drive arrangements 40 and 50. The gate drive arrangement 60 comprises a PWM generator 62 and a gate driver 64. The PWM generator 62 provides two separate PWM outputs: one for the MOSFET 24, the other for the IGBT 26. Thus, the PWM generator 62 implements the function of the switch 46 described above.

The embodiments of the invention described above are provided by way of example only. The skilled person will be aware of many modifications, changes and substitutions that could be made without departing from the scope of the present invention. The claims of the present invention are intended to cover all such modifications, changes and substitutions as fall within the spirit and scope of the invention.

Claims

CLAIMS:

1. A power factor correction circuit comprising a boost converter and a controller, wherein the boost converter comprises a semiconductor switch including a MOSFET and an IGBT connected in parallel, wherein:

in a first mode of operation, the controller is configured to provide signals for driving the semiconductor switch to both the MOSFET and the IGBT; and

in a second mode of operation, the controller is configured to provide said signals for driving the semiconductor switch to the IGBT, such that the MOSFET is effectively disabled.

2. A power factor correction circuit as claimed in claim 1, wherein the controller comprises a first output for providing the signals for driving the semiconductor switch and a second output for providing an enable signal for said MOSFET.

3. A power factor correction circuit as claimed in claim 2, further comprising a MOSFET enabling switch, wherein the second output of the controller controls the state of the MOSFET enabling switch.

4. A power factor correction circuit as claimed in claim 2, further comprising a gate driver, wherein the gate driver receives the signals for driving the semiconductor switch and the enable signal for said MOSFET, wherein the gate driver is configured to provide driving signals for the MOSFET and the IGBT accordingly.

5. A power factor correction circuit as claimed in claim 1, wherein the controller comprises a first output for providing the signals for driving the MOSFET and a second output for providing the signals for driving the IGBT.

6. A method for driving a semiconductor switch of a power factor correction circuit, wherein the power factor correction circuit comprises a boost converter and a controller and the boost converter comprises a semiconductor switch including a MOSFET and an IGBT connected in parallel, the method comprising :

providing signals for driving the semiconductor switch to both the MOSFET and the IGBT in a first mode of operation; and

providing signals for driving the semiconductor switch to the IGBT in a second mode of operation, such that the MOSFET is effectively disabled.

7. A method as claimed in claim 6, wherein the steps of providing signals for driving the semiconductor switch include providing a MOSFET enable signal indicative of the mode of operation.