JP2009050080A - Snubber circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a snubber circuit which can downsize power conversion equipment and reduce its cost by constituting it of minimum parts. <P>SOLUTION: This snubber circuit is equipped with a transistor, where an emitter terminal and a collector terminal are connected in reverse parallel with a snubber diode, and a base resistor, which regulates the base current of the transistor, being interposed between the base terminal of this transistor and one terminal of a switching element, to which one terminal of a snubber resistor is connected, and the transistor has an accumulation time that is longer than the discharge time of a snubber capacitor and shorter than the application time of voltage pulses applied to it at a usual operation time of the switching element. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a snubber circuit, and more particularly to a snubber circuit optimal for suppressing a surge voltage applied to a switching element used in a switching power supply or the like or a semiconductor element such as a diode.

2. Description of the Related Art Conventionally, there is a DC converter (DC-DC converter) that switches an input DC voltage using a semiconductor switching element, converts the DC voltage into a different DC voltage, and outputs it. As a type of this DC-DC converter, an insulated DC-DC converter in which a primary side (power supply side) and a secondary side (load side) are insulated by a transformer is known (for example, see Patent Document 1). reference).
FIG. 8 shows an example of an insulated DC-DC converter configured using MOSFETs as semiconductor switching elements. This isolated DC-DC converter (hereinafter referred to as a DC-DC converter) has a source of one MOSFET (Q1 or Q3) and a drain of the other MOSFET (Q2 or Q4) of two MOSFETs connected. Two sets of series circuits are connected in parallel to constitute the inverter 1.
The on / off control unit 3 turns on the MOSFETs (Q1, Q4) while turning off the MOSFETs (Q2, Q3) (first state), and a state in which the on and off are switched (second state). And a state (third state) in which all MOSFETs (Q1, Q2, Q3, Q4) are turned off. Then, the on / off control unit 3 switches the first to third states at high speed, and controls the high-frequency alternating current (rectangular wave) to be applied to the primary winding T1 of the transformer T. When controlled in this way, a voltage (alternating current) according to a rectangular wave applied to the primary winding T1 is generated in the secondary winding T2 of the transformer T. The frequency of this high-frequency alternating current is generally 10 kHz or more in order to reduce the size of the transformer T and prevent noise.

Connected to the secondary winding T2 is a diode bridge 4 composed of four diodes (D1, D2, D3, D4) for rectifying the alternating current generated in the secondary winding T2. Since the output of the diode bridge 4 is a pulsating current, a smoothing circuit 6 including a DC reactor L and a smoothing capacitor C is provided in series and in parallel with the load 5, and smoothed DC is supplied to the load 5.
Thus, the on / off control unit 3 switches the first to third states at a high speed and controls the ratio between the on period and the off period of the MOSFETs (Q1, Q2, Q3, Q4) to apply to the load 5. Adjust the DC voltage value.
Incidentally, even in a period (third state) in which all of the MOSFETs (Q1, Q2, Q3, Q4) are turned off, that is, in a period in which the voltage applied to the primary winding T1 of the transformer T is [0V] The DC converter releases the electromagnetic energy stored in the DC reactor L and continues to supply current to the load 5 (reflux period).
Since the reverse voltage is applied to the diodes D2 and D3 when the DC-DC converter shifts to the first state where the voltage is applied to the transformer T from the return period, the reverse current, that is, the reverse recovery current is very short. This is cut off after flowing. The source of reverse recovery current at this time is a transformer T. The leakage reactance Le of the transformer T exists in the current path of the transformer T. For this reason, a voltage (surge voltage) corresponding to the current change rate at the time of current interruption is generated in the leakage reactance Le. The surge voltage generated at this time is applied across the diodes D2 and D3. The diodes D2 and D3 may be damaged when the surge voltage level increases.

As a countermeasure against this, a power conversion device including a snubber circuit that protects the diode bridge 4 from a surge voltage is known (see, for example, Patent Document 1). As shown in FIG. 8, the snubber circuit disclosed in this Patent Document 1 includes a snubber capacitor Cs that stores charges generated by a surge voltage, absorbs the energy of the surge voltage, and relieves a surge of the surge voltage, and a switching element. The snubber diode Ds that prevents unnecessary discharge of the snubber capacitor Cs when no voltage is applied, the peak value of the current flowing through the snubber circuit, and the resonance between the snubber circuit Cs and the inductance on the circuit are suppressed. A snubber circuit 10 having a snubber resistor Rs is provided between the diode bridge 4 and the smoothing circuit 6.
In the DC-DC converter provided with the snubber circuit 10, the reverse recovery current of the diode D3 is a path of the secondary winding T2 of the transformer T → leakage reactance Le → diode D1 → diode D3 → secondary winding T2 of the transformer T. It flows in. At this time, the diode D3 cuts off the current flowing through this path, but the secondary winding T2 of the transformer T → leakage reactance Le → diode D1 → snubber diode Ds → snubber capacitor Cs → diode D4 → secondary winding of the transformer T Current continues to flow through the path of line T2. For this reason, the time change (current change rate) of the current flowing through the leakage reactance Le is suppressed, and the voltage applied to the diode D3 is lowered. At this time, the snubber capacitor Cs is charged and its voltage rises once, but is discharged through the snubber resistor Rs, so that it returns to the voltage before charging until the next charging cycle comes. In the snubber circuit 10, the loss consumed by the snubber resistor Rs decreases as the difference between the voltage output from the diode bridge 4 and the voltage applied to both ends of the load 5 decreases.

The operation on the diode D2 is the same.
Alternatively, a DC / DC converter including a snubber circuit to which the step-down chopper shown in FIG. 9 is applied is known (see, for example, Patent Document 2). In this DC / DC converter, the snubber resistor Rs in the DC-DC converter shown in FIG. 8 is replaced with a switching element (MOSFET) Q, a reactor Lf, and a diode Df.
In the step-down chopper, the current flowing through the reactor Lf increases when the MOSFET (Q) is turned on, and the current decreases when the MOSFET (Q) is turned off. Therefore, the voltage of the snubber capacitor Cs can be maintained within a predetermined range higher than that of the smoothing capacitor C by adjusting the ratio of the ON time and the OFF time of the MOSFET (Q). Specifically, the voltage of the snubber circuit can be maintained near the rectified voltage by turning on the semiconductor switching element Q in synchronization with the high-frequency alternating current applied to the primary winding T1 of the transformer T, and the snubber capacitor Cs Loss associated with discharge can be minimized.
Or the DC-DC converter which applied the snubber circuit by the diode with long storage time is known (for example, refer patent document 3). The snubber circuit applied to this DC-DC converter is longer than ½ of the period of the oscillating voltage generated in the winding of the transformer based on the leakage reactance and stray capacitance of the transformer, and is used for the rectifier circuit. A rectifier diode having an accumulation time shorter than the minimum off period of the switching element is used for the snubber circuit.
JP-A 61-106068 JP-A-1-177870 JP 2001-186759 A

However, the snubber circuit in the power conversion device described in Patent Document 1 described above has a problem that loss generated in the snubber resistor Rs increases when the difference voltage between the rectifier circuit and the output voltage is large.
For example, assume that the DC-DC converter shown in FIG. 8 has an input voltage (DC power supply 2) of 200V, a transformation ratio of the transformer T of 1: 1, and a rated voltage of the load 5 of 100V. . In this case, even if the leakage reactance Le does not exist in the transformer T, the snubber capacitor Cs is charged to 200 V, which is the peak of the output voltage Er of the diode bridge 4, and then the rated voltage Eo of the load during the return period. To about 100V. Further, during the application of the output voltage Er of the diode bridge 4, a difference voltage 100V between the output voltage Er and the rated voltage Eo is applied to both ends of the snubber resistor Rs.
Since this operation is repeated, energy larger than the energy held by the leakage reactance Le of the transformer T is lost from the snubber resistor Rs. In addition, since the leakage reactance Le and the snubber capacitor Cs actually cause series resonance, a voltage higher than the original applied voltage is added to the snubber resistor Rs, and there is a problem that the discharge loss becomes larger.
Of course, these problems can be improved to some extent by increasing the resistance value of the snubber resistor Rs. However, the increase in the resistance value of the snubber resistor Rs must remain at a level that does not cause overvoltage due to insufficient discharge of the snubber capacitor Cs under any operating condition of the DC-DC converter. There is concern that it will be limited.

On the other hand, the snubber circuit applied to the DC / DC converter described in Patent Document 2 has a problem that the step-down chopper circuit must have a large capacity, although it solves the above-described problems. That is, in this DC / DC converter, the current path when charging the snubber capacitor Cs is the secondary winding T2 of the transformer T → leakage reactance Le → diode D1 → snubber diode Ds → snubber capacitor Cs → transformer T. The next winding T2.
Therefore, the electromotive force Er in this circuit is the sum of the counter electromotive force ΔE generated in the leakage reactance Le and the electromotive force E2 of the secondary winding T2 as shown in FIG. For this reason, the voltage Ec at both ends of the snubber capacitor Cs becomes as shown in FIG. 10B, so that the snubber capacitor Cs receives energy not only from the leakage reactance Le but also from the transformer T. .
Although the back electromotive force ΔE generated in the leakage reactance Le can be adjusted by the capacitance of the snubber capacitor Cs, about 10% of the electromotive force E2 induced in the secondary winding T2 for the purpose of suppressing the back electromotive force ΔE. It is as follows.
Note that the current flowing through the secondary winding T2 of the transformer T and the leakage reactance Le is common, and the ratio of these voltages is equal to the ratio of power. Therefore, when the energy of the leakage reactance Le is converted into electric power, the step-down chopper circuit requires an extra power capacity of 10 to 20% of the apparatus capacity for this reason, regardless of the capacity of about several percent of the capacity of the DC / DC converter. Become.

In addition, this system exchanges control signals with a main control circuit (not shown) that controls switching of MOSFETs (Q1, Q2, Q3, Q4) as well as a drive / control circuit (not shown) that controls switching of MOSFET (Q). A transmission circuit for performing the above is required. For this reason, this method has hindered the downsizing and cost reduction of a power converter having a small capacity.
The snubber circuit of the invention has been made to solve the above-described circumstances, and the object of the snubber circuit is to configure the snubber circuit with the minimum number of parts, and to reduce the size and cost of the power converter. It is to provide a snubber circuit capable of performing the above.

In order to achieve the above-described object, the snubber circuit of the present invention is a snubber circuit that is connected in parallel with a switching element to be protected and suppresses a surge voltage generated at the time of switching, and the snubber circuit includes energy of the surge voltage. A snubber capacitor that absorbs the surge voltage and alleviates the surge voltage surge, and a snubber diode that is connected to one terminal of the snubber capacitor and prevents discharge of the snubber capacitor when no voltage is applied to the switching element; The snubber diode connected to the other terminal of the snubber diode is connected in series with a snubber resistor that suppresses the peak value of the current flowing through the snubber circuit and suppresses resonance between the snubber capacitor and the inductance on the circuit. Become
Further, the snubber circuit includes a transistor having an emitter terminal and a collector terminal connected in reverse parallel to the snubber diode, and a base terminal of the transistor and one end of the switching element to which one terminal of the snubber resistor is connected. And a base resistor that regulates the base current of the transistor,
The transistor has a storage time longer than a discharge time for discharging the charge stored in the snubber capacitor and shorter than a voltage pulse application time applied to both ends of the switching element during normal switching (normal operation). It is characterized by having.

The snubber circuit includes a MOSFET in which a source terminal and a drain terminal are connected in reverse parallel to the snubber diode instead of the transistor, and the switching element in which a gate terminal of the MOSFET and one terminal of the snubber resistor are connected. A gate resistor that adjusts the change time of the gate terminal voltage of the MOSFET, and the gate capacitance of the MOSFET is the snubber under the condition that the gate resistor is connected. The discharge time is longer than the discharge time for discharging the charge stored in the capacitor and shorter than the voltage pulse application time applied to both ends of the switching element during normal switching (normal operation). Yes.
Alternatively, the snubber circuit further includes a shunt diode that is connected in parallel with the snubber resistor and shunts a current flowing through the snubber resistor.
The snubber circuit further includes a discharging means connected in parallel with the snubber capacitor and discharging the electric charge stored in the snubber capacitor when the voltage of the snubber capacitor exceeds a predetermined voltage. . For example, a Zener diode is applied to this discharging means.

According to the snubber circuit of the first aspect of the present invention, the transistor having an accumulation time longer than the discharging time of the snubber capacitor is connected in antiparallel with the snubber diode, and the transistor is driven by the voltage drop generated in the snubber resistor. Therefore, even after the snubber capacitor Cs is charged, the transistor maintains a conductive state, and the energy stored in the snubber capacitor Cs can be regenerated in the main circuit.
The snubber circuit of the present invention uses a transistor having an accumulation time sufficiently shorter than the voltage pulse application time applied to the switching element during normal operation. Therefore, even if the switching element applied voltage is lost, the snubber capacitor Cs Unnecessary discharge can be prevented.
Alternatively, the snubber circuit according to claim 2 of the present invention connects a MOSFET having a gate capacitance having a discharge time longer than the discharge time of the snubber capacitor in antiparallel with the snubber diode and generates a voltage drop generated in the snubber resistor. Since the MOSFET is driven by this, even after the snubber capacitor Cs is charged, the MOSFET is kept in a conductive state, and the energy stored in the snubber capacitor Cs can be regenerated to the main circuit.
The snubber circuit of the present invention uses a MOSFET having a gate capacitance having a discharge time sufficiently shorter than the voltage pulse application time applied to both ends during normal operation, so that the voltage on the secondary side DC line is lost. Even so, unnecessary discharge of the snubber capacitor Cs can be prevented.

Further, since the snubber circuit according to claim 3 of the present invention is provided with the shunt diode in parallel with the snubber resistor, the voltage rise of the snubber circuit can be effectively suppressed.
In addition, the snubber circuit according to claim 4 of the present invention includes, for example, a Zener diode as a discharging means for discharging the charge stored in the snubber capacitor when the voltage of the snubber capacitor exceeds a predetermined voltage. It is possible to prevent the capacitor from becoming overvoltage.
As described above, the snubber circuit of the present invention can be configured with a minimum number of components, and has a great practical effect that the power conversion device can be reduced in size and cost.

  Hereinafter, a snubber circuit according to an embodiment of the present invention will be described with reference to the accompanying drawings. 1 to 7 illustrate a snubber circuit according to an embodiment of the present invention, and the snubber circuit of the present invention is not limited by these drawings.

FIG. 1 shows a snubber circuit according to Embodiment 1 of the present invention. In the figure, the same reference numerals as those in FIG. 1 denote the same parts, and the basic configuration is shown in FIGS. Since it is the same as the conventional one shown, its description is omitted. Incidentally, in the first embodiment, the snubber circuit of the present invention is applied to a DC-DC converter.
The snubber circuit according to the first embodiment is different from the conventional snubber circuit in that the anode terminal and the cathode terminal of the snubber diode Ds are respectively connected to the emitter terminal and the collector terminal of an NPN transistor Q (hereinafter simply referred to as transistor Q). Are connected in parallel with a point where a base resistor Rb for regulating the base current of the transistor Q is interposed between the base terminal of the transistor Q and the positive voltage line 7, and a snubber capacitor Cs. When the voltage of the snubber capacitor Cs exceeds a predetermined voltage, a zener diode Zd for discharging the charge stored in the snubber capacitor Cs is connected.
The transistor Q has an accumulation time Tstg that is longer than the discharge time of the snubber capacitor Cs and shorter than the voltage pulse application time applied to the switching element during normal operation of the DC-DC converter.
The operation of the snubber circuit of the present invention having such characteristics will be described in more detail with reference to FIG. This snubber circuit suppresses the surge voltage by absorbing energy generated in the leakage reactance Le existing in the transformer T by the snubber capacitor Cs.

First, an on / off control unit 3 that controls on / off of the MOSFETs (Q1 to Q4) switches these MOSFETs (Q1 to Q4) at high speed to give a high-frequency alternating current to the primary winding T1 of the transformer T. In the secondary winding T2 of the transformer T, high-frequency alternating current with the same frequency appears (FIG. 2 (a)).
At the moment when the voltage generated in the secondary winding T2 shifts from [0V] to a positive voltage, the snubber circuit 10 is supplied with a current from the positive voltage line 7 toward the negative voltage line 8 to charge the snubber capacitor Cs. Is flows (FIG. 2B). This current Is causes a voltage drop across the snubber resistor Rs. Then, the emitter potential of the transistor Q becomes lower than that of the positive voltage line 7. For this reason, the transistor Q becomes conductive when the base current Ib flows through the path of the positive voltage line 7 → the base resistor Rb → the emitter (FIG. 2C).
When the charging of the snubber capacitor Cs is completed, the current Is becomes [0A], and the base current Ib of the transistor Q also becomes [0A]. However, the transistor Q has a property of maintaining the conducting state during the accumulation time Tstg even when the base current Ib becomes [0A] (FIG. 2D). For this reason, current Is flows through the path of snubber capacitor Cs → transistor Q (collector → emitter) → snubber resistor Rs, and discharge is performed. Although some energy is lost by the snubber resistor Rs along with this discharge, the output voltage Er output from the diode bridge 4 is applied between the positive voltage line 7 and the negative voltage line 8. Most of the energy is regenerated in the main circuit.

Therefore, in the snubber circuit according to the first embodiment of the present invention, the accumulation time of the transistor Q needs to be longer than the time required for discharging the snubber capacitor Cs. On the other hand, by selecting a transistor Q having an accumulation time sufficiently shorter than the pulse width of the electromotive force E2 generated in the secondary winding T2 of the transformer T during normal operation, the positive voltage line 7 and the negative voltage line 8 are Unnecessary discharge when the output voltage Er is not applied therebetween can be prevented.
Moreover, as shown to Fig.3 (a), it may operate | move in the state which shortened the pulse width of the electromotive force E2 induced by the secondary winding T2 of the transformer T. FIG. This corresponds to, for example, so-called soft start in which the pulse width of the electromotive force E2 is gradually widened and the output voltage is slowly raised to the rated voltage in order to prevent an inrush current flowing through the smoothing capacitor C and the load 5 at the time of startup. Alternatively, the pulse width of the electromotive force E2 is similarly reduced when the output voltage is reduced in order to prevent a current from flowing when the load 5 is short-circuited.
At this time, the electromotive force E2 and the output voltage Er between the positive voltage line 7 and the negative voltage line 8 become [0V] before the accumulation time Tstg of the transistor Q elapses, and the charge of the snubber capacitor Cs is overdischarged. It will be in the state to obtain (FIG.3 (b)). However, the discharge current at this time causes a voltage drop across the snubber resistor Rs, thus providing a reverse bias to the transistor Q. Then, a negative base current flows through the transistor Q (FIG. 3C). Therefore, the transistor Q is turned off in a relatively short time to prevent the snubber capacitor Cs from being discharged (FIG. 3D).

The Zener diode Zd connected in parallel with the snubber capacitor Cs plays a role of clamping to a predetermined voltage so that the snubber capacitor Cs does not become an overvoltage. When the Zener diode Zd is turned on, the snubber resistor Rs, the transistor Q, and the Zener diode Zd cause a larger loss than usual. However, this state is limited to a short time by controlling the on / off time (pulse width control) of the on / off controller 3. Therefore, the loss that occurs does not affect the efficiency of the DC-DC converter, and it is not necessary to increase the size of the snubber circuit to cope with these heat generation.
Incidentally, if the state where the pulse width of the electromotive force E2 is shortened is extremely short, the Zener diode Zd is unnecessary.
Thus, the snubber circuit according to the first embodiment of the present invention sniffs the transistor Q having a storage time longer than the discharge time of the snubber capacitor Cs and shorter than the voltage pulse application time applied during normal operation of the DC-DC converter. The transistor Q is connected in antiparallel with the diode Ds, and the transistor Q is driven by a voltage drop generated in the snubber resistor Rs. Therefore, the transistor Q remains conductive during the accumulation time Tstg even after the snubber capacitor Cs is charged. The energy stored in the snubber capacitor Cs can be regenerated in the main circuit.

Further, since the transistor Q having an accumulation time Tstg that is sufficiently shorter than the voltage pulse application time applied during normal operation is used, even if the secondary side voltage Er is lost, unnecessary discharge of the snubber capacitor Cs can be prevented.
Furthermore, the snubber circuit according to the first embodiment of the present invention includes, for example, a Zener diode as a discharging means for discharging the charge stored in the snubber capacitor when the voltage of the snubber capacitor exceeds a predetermined voltage. Prevent overvoltage from being applied to the capacitor.
Although the NPN transistor is used in the first embodiment, it can be modified by using a PNP transistor as shown in FIG. This modified snubber circuit connects a snubber capacitor Cs, a snubber diode Ds, and a snubber resistor Rs in series from the positive voltage line 7 to the negative voltage line 8. Then, the anode terminal of the snubber diode Ds is connected to the collector terminal of the PNP transistor Q, and the cathode terminal and the emitter terminal so as to be in antiparallel with the snubber diode Ds. The base terminal of the PNP transistor Q is connected to the negative voltage line 8 via a base resistor Rb that limits the current flowing through the base.
Thus, the snubber circuit obtained by modifying the first embodiment of the present invention configured using the PNP transistor can obtain the same operation and effect as the snubber circuit configured using the NPN transistor described above.

Next, a snubber circuit according to a second embodiment of the present invention will be described with reference to FIG. This embodiment differs from the first embodiment described above in that a shunt diode Dp is provided in parallel with the snubber resistor Rs. The shunt diode Dp plays a role of suppressing a voltage increase across the snubber resistor Rs that occurs when the snubber capacitor Cs is charged.
Incidentally, the reverse bias voltage of the transistor Q corresponds to the forward voltage generated in the shunt diode Dp. Therefore, the value of the base resistor Rb is made smaller than that of the first embodiment, and a base current necessary for the operation of the transistor Q is ensured.
Thus, since the snubber circuit according to the second embodiment of the present invention includes the shunt diode Dp in parallel with the snubber resistor Rs, it is possible to suppress the voltage increase of the snubber circuit.

Next, a snubber circuit according to a third embodiment of the present invention will be described with reference to FIG. This embodiment differs from the first and second embodiments described above in that an n-channel MOSFET (Q5) is used instead of the transistor Q. That is, the anode terminal of the snubber diode Ds is connected to the source terminal of the n-channel MOSFET (Q5), the cathode terminal, and the drain terminal so as to be in antiparallel with the snubber diode Ds. The gate terminal of the n-channel MOSFET (Q5) is connected to the positive voltage line 7 via a gate resistor Rg that adjusts the time change of the voltage applied to the gate terminal.
In this case, instead of the accumulation time Tstg of the transistor Q described in the first embodiment, the time required for discharging the gate capacitance of the MOSFET (Q5) is ensured as the discharging time of the snubber capacitor Cs. Therefore, the same operation and effect as Example 1 can be obtained also in Example 3.
Thus, the snubber circuit according to the third embodiment of the present invention includes a gate capacitance having a discharge time longer than the discharge time of the snubber capacitor Cs and shorter than the voltage pulse application time applied during normal operation of the DC-DC converter. Since the MOSFET (Q5) is connected in antiparallel with the snubber capacitor Cs and the MOSFET (Q5) is driven by the voltage drop generated in the snubber resistor Rs, the MOSFET (Q5) is charged even after the snubber capacitor Cs is charged. ) Can maintain the conduction state and regenerate the energy stored in the snubber capacitor Cs to the main circuit.

Moreover, since the snubber circuit of the present invention uses the MOSFET (Q5) having a gate capacitance having a discharge time sufficiently shorter than the voltage pulse application time applied during normal operation, the secondary voltage Er is lost. In addition, unnecessary discharge of the snubber capacitor Cs can be prevented.
Although the n-channel MOSFET is used in the third embodiment, it can be modified by using a p-channel MOSFET as shown in FIG. This snubber circuit connects a snubber capacitor Cs, a snubber diode Ds, and a snubber resistor Rs in series from the positive voltage line 7 to the negative voltage line 8. Then, the anode terminal of the snubber diode Ds is connected to the source terminal of the MOSFET (Q6), the cathode terminal and the drain terminal so as to be in antiparallel with the snubber diode Ds. The gate terminal of the MOSFET (Q6) is connected to the negative voltage line 8 via a gate resistor Rg that limits the gate voltage applied to the gate terminal.
Thus, the snubber circuit obtained by modifying the third embodiment of the present invention configured using the p-channel MOSFET can lead to the above-described operation and effect even if the n-channel MOSFET is used.

  The snubber circuit of the present invention is not limited to the above-described embodiment, and various modifications may be made without departing from the gist of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The schematic circuit diagram which shows a structure when the snubber circuit which concerns on Example 1 of this invention is applied to a DC-DC converter. The figure which shows the waveform of the voltage in the normal operation of the DC-DC converter shown in FIG. 1, and an electric current. The figure which shows the waveform of the voltage and electric current at the time of starting or overload of the DC-DC converter shown in FIG. The circuit diagram which shows the modification of the snubber circuit shown in FIG. The circuit diagram which shows the structure of the snubber circuit which concerns on Example 2 of this invention. The circuit diagram which shows the structure of the snubber circuit which concerns on Example 3 of this invention. The circuit diagram which shows the modification of the snubber circuit shown in FIG. The schematic circuit diagram which shows an example which applied the conventional snubber circuit to the DC-DC converter. The schematic circuit diagram which shows an example which applied the conventional snubber circuit to the pressure | voltage fall chopper. FIG. 10 is a diagram showing voltage and current waveforms during normal operation of the step-down chopper shown in FIG. 9.

Explanation of symbols

Cs Snubber capacitor Ds Snubber diode Q Transistor Rb Base resistor Rg Gate resistor Rs Snubber resistor T Transformer Zd Zener diode 1 Inverter 2 DC power supply 3 On-off control unit 4 Diode bridge 5 Load 6 Smoothing circuit 7 Positive voltage line 8 Negative voltage Line 10 snubber circuit

Claims (4)

A snubber circuit that is connected in parallel with a switching element to be protected and suppresses a surge voltage generated during switching,
The snubber circuit includes a snubber capacitor that absorbs the energy of the surge voltage and relaxes the surge voltage surge;
A snubber diode connected to one terminal of the snubber capacitor to prevent discharge of the snubber capacitor when no voltage is applied to the switching element;
Connected in series with a snubber resistor connected to the other terminal of this snubber diode to suppress the peak value of the current flowing in the snubber circuit,
Further, the snubber circuit includes a transistor having an emitter terminal and a collector terminal connected in reverse parallel to the snubber diode;
A base resistor that is interposed between the base terminal of the transistor and one end of the switching element to which one terminal of the snubber resistor is connected, and regulates the base current of the transistor;
The transistor has an accumulation time longer than a discharge time for discharging the charge stored in the snubber capacitor and shorter than a voltage pulse application time applied to both ends of the switching element during normal switching. Snubber circuit to do. The snubber circuit includes a MOSFET in which a source terminal and a drain terminal are connected in reverse parallel to the snubber diode instead of the transistor;
Instead of the base resistor, interposed between the gate terminal of the MOSFET and one end of the switching element to which one terminal of the snubber resistor is connected, the change time of the gate terminal voltage of the MOSFET is reduced. A gate resistor to be adjusted,
The gate capacitance of the MOSFET has a discharge time longer than a discharge time for discharging the electric charge stored in the snubber capacitor and shorter than a voltage pulse application time applied to both ends of the switching element during normal switching. The snubber circuit according to claim 1.   The snubber circuit according to claim 1, further comprising a shunt diode that is connected in parallel with the snubber resistor and shunts a current flowing through the snubber resistor.   The snubber circuit is further connected to the snubber capacitor in parallel, and further includes a discharging means for discharging the charge stored in the snubber capacitor when the voltage of the snubber capacitor exceeds a predetermined voltage. The snubber circuit in any one of Claims 1-3.

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