WO2014065524A1 - 3d semiconductor device having cache memory array in which chapter data can be saved and method for operating same - Google Patents

Abstract

Provided are 3D semiconductor devices having a cache memory array. The cache memory array can be configured to save at least page-unit data. Writing and/or reading actions using the cache memory array can be performed to effectively reduce data disturbance of a main memory array while enabling increased speed of action.

Description

Three-dimensional semiconductor device having a cache memory array that can store chapter data and its operation method

The present invention relates to a three-dimensional semiconductor device having a two-dimensional cache memory array provided between a three-dimensional main memory array and a one-dimensional page buffer.

Various three-dimensional memory devices have been proposed, including memory cells that are three-dimensionally arranged and rewritable. For example, three-dimensional flash memory devices and three-dimensional cross-point memory devices have been studied to overcome technical limitations in two-dimensional memory devices. The 3D memory devices may include a plurality of horizontal electrodes (eg, word lines of a 3D vertical channel NAND flash device) sequentially stacked on a substrate. In order to avoid complexity in the connection structure, a plurality of the horizontal electrodes located at the same height are electrically connected to each other. As a result of this connection structure, three-dimensional memory devices are vulnerable to program and read disturb problems.

Some embodiments of the present invention provide three-dimensional memory devices capable of suppressing write and / or read disturb and methods of operation thereof.

Some embodiments of the present invention provide three-dimensional memory devices and methods of operating the same that can speed up write and / or read operations.

Some embodiments of the present invention provide three-dimensional memory devices and methods of operating the same that can reduce energy consumption.

Three-dimensional semiconductor devices according to embodiments of the present invention include a cache memory array configured to store more than one page of data (eg, two-dimensional chapter data). The cache memory array is provided between a main memory array including three-dimensionally arranged memory cells and a peripheral circuit area (eg, a bitline decoder or page buffer). The use of the cache memory array is a technical challenge in data exchange (e.g., write / read disturbance or unnecessary energy consumption) caused by the dimensional difference between the three-dimensional main memory array and the one-dimensional page buffer. Makes it possible to solve the problem. In addition, when the cache memory array is implemented using memory elements having a faster operating speed than the main memory array, read and write operations to the main memory array are compared to when the cache memory array is not used. It can dramatically improve the speed of.

The use of the cache memory array can effectively reduce write and / or read disturb and energy consumption in three-dimensional memory devices, as well as speed up write and / or read operations.

1 is a schematic perspective view showing a typical three-dimensional memory device.

2 is a diagram illustrating two other structures of the main memory array.

3 is a schematic perspective view illustrating an example of three-dimensional memory devices according to example embodiments.

4 is a table exemplarily illustrating layout structures of three-dimensional memory devices according to example embodiments.

5 through 7 are perspective views illustrating other examples of three-dimensional memory devices according to example embodiments.

8 to 12 are perspective views schematically showing one side of main and cache memory arrays according to embodiments of the present invention.

FIG. 13 is a diagram exemplarily illustrating a hierarchical structure of a main memory array.

14 is a diagram illustrating an aspect of a data transmission process performed through bit lines.

FIG. 15 is a diagram illustrating some of operations performed in a 3D memory device according to example embodiments.

16 and 17 are diagrams exemplarily illustrating a method of performing operations of a 3D memory device according to example embodiments.

18 and 19 are diagrams illustrating an example of a read operation of a 3D memory device according to example embodiments.

20 and 21 are diagrams illustrating an example of a write operation of a 3D memory device according to example embodiments.

22 and 23 are diagrams illustrating other operations of a 3D memory device according to exemplary embodiments of the present invention, respectively.

24 to 29 are diagrams exemplarily illustrating data processing methods performed through modified operating methods or a combination thereof.

30 to 32 are tables for exemplarily describing some of technical features of operating steps of a 3D memory device according to example embodiments.

33 is a circuit diagram exemplarily illustrating a cache cell array including unit cache memories.

34 and 35 schematically and exemplarily illustrate some of the possible structures of the unit cache memory.

36 is a diagram illustrating memory elements that may be used as cache cells by way of example.

37 is a diagram illustrating some of the possible structures of the main memory array.

38 is a table for describing an aspect of an operation of a 3D memory device according to example embodiments.

39 to 43 are diagrams for describing an operation of a semiconductor device according to example embodiments.

44 to 46 are views for explaining modified embodiments of the present invention.

47 to 53 are diagrams for describing an operation of a semiconductor device according to example embodiments of the present inventive concepts.

54 to 57 are diagrams for describing an operation of a semiconductor device according to other modified embodiments of the inventive concept.

58 is a diagram illustrating an example of CM-CM copying.

59 and 60 are perspective views illustrating a semiconductor device in accordance with some embodiments of the present invention.

61 to 65 are diagrams illustrating semiconductor devices according to example embodiments of the inventive concepts.

66 is a diagram illustrating a semiconductor device and a part of an operation thereof according to some example embodiments of the inventive concepts.

FIG. 67 is a diagram schematically illustrating paths of a 3D memory device and an operating current according to still other embodiments of the inventive concept.

68 is a schematic perspective view illustrating a semiconductor memory device in accordance with some embodiments of the present invention.

69 through 72 are circuit diagrams illustrating some examples of three-dimensional semiconductor memory devices in accordance with some embodiments of the inventive concept.

73 and 74 are schematic plan views illustrating semiconductor chips in accordance with some embodiments of the present invention.

75 and 76 are block diagrams and perspective views illustratively showing embodiments of the present invention that include distributed partial cache memory arrays, respectively.

77 is a graph comparing embodiments of the present invention and operating methods according to the related art in terms of the number of disturbances.

78 and 79 are graphs comparing time required between read and write operations according to the embodiments of the present invention and the prior art.

80 is a schematic diagram illustrating an electronic product including a memory device according to the present invention.

The objects, other objects, features and advantages of the present invention will be readily understood through the following embodiments related to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art.

In the present specification, when it is mentioned that a film (or layer) is on another film (or layer) or substrate, it may be formed directly on another film (or layer) or substrate or a third film between them. (Or layers) may be interposed. In addition, the size and thickness of the components of the drawings may be exaggerated for clarity. In addition, in various embodiments of the present disclosure, terms such as first, second, and third may be used to describe various regions, films (or layers), and the like, but these regions and films may be used by such terms. It should not be limited. These terms may only be used to distinguish any given region or film (or layer) from other regions or films (or layers). Therefore, the film quality referred to as the first film quality in one embodiment may be referred to as the second film quality in other embodiments. Each embodiment described and illustrated herein also includes its complementary embodiment. The expression 'and / or' is used herein to include at least one of the components listed before and after. Portions denoted by like reference numerals denote like elements throughout the specification.

The contents disclosed in Korean Patent Nos. 10-2012-0129303, 10-2012-0123938, and 10-2012-0119179 are included as part of this application.

The technical terms referred to herein may be used as the following meanings. A bit line is a signal transmission line used to transmit information (ie, an electrical signal) stored in a memory cell to a peripheral circuit (for example, a sensing circuit, a decoder, or a page buffer) or to transmit external data to a memory cell. it means. The word line refers to a line configured to transmit a signal used to select some of a plurality of memory cells connected to one bit line.

The memory cell may refer to an area including a material or a thin film structure capable of charge storage and a material or a thin film structure (eg, PCM, MTJ, resistive memory element) exhibiting variable resistance characteristics. However, the present invention is not limited to a specific type of memory cell, and based on the characteristics of the memory cell used, embodiments of the present invention can be further subdivided and diversified.

Adjacent memory cells may be provided in the form of localized patterns spatially separated from each other or as a structure including at least a portion connected to each other.

The wiring or the wire may refer to a conductive pattern formed of a material having a low specific resistance. For example, they may be metals or high concentrations of semiconductor materials (but not limited to these), but organics, carbon nanostructures (such as nanotubes or graphene), or molybdenum sulfides may lead to the wiring or wires. It may be used to implement.

According to some embodiments, the data exchange with the peripheral circuit may be in the form of an optical signal. In this case, the wiring or the bit line may be provided in the form of an optical waveguide, and the peripheral circuit may include a multiplexer such as a star coupler.

Although, in the figures, 'F' is used to indicate that the element is in an electrically floating state, this is merely a notation for brevity of description and can prevent the element from generating a current path through it. That voltage may be applied.

1 is a schematic perspective view showing a typical three-dimensional memory device. Referring to FIG. 1, a typical three-dimensional memory device includes a main memory array MMA and a bit line structure BLS provided on a substrate SUB. The main memory array MMA may include three-dimensionally arranged memory cells and internal lines connecting the memory cells.

For example, as shown in FIG. 2, the main memory array MMA may be provided in an A-type or B-type structure. In the case of the A-type, the main memory array MMA is (1) vertical lines VL arranged on the substrate SUB (i.e. two-dimensionally) forming a multi-line and multi-row structure, ( 2) a plurality of horizontal lines HL crossing the vertical lines VL while forming a multi-layer and multi-row structure, and (3) a three-dimensional arrangement of the vertical and horizontal lines VL and HL. It may include main memory cells (hereinafter, referred to as memory cells) MC provided at intersections. In the case of the B-type, the main memory array MMA includes (1) first horizontal lines HLx forming a multilayer and multi-row structure, and (2) second horizontal lines forming a multi-layer and multi-line structure ( HLy), and (3) the memory cells MC provided at their intersections. The vertical lines VL or the horizontal lines HL, HLx, and HLy may be electrically connected to a peripheral circuit via the bit line structure BLS.

According to embodiments of the present invention, a three-dimensional memory device is provided between the main memory array (MMA) and the bit lines (BL) as shown in Figure 3 and two-dimensionally arranged cache memory cells (hereinafter referred to as It may further include a cache memory array (CMA) including a cache cell (CC). The cache memory array CMA may be provided as part of a cell array region. This means that the cache memory array CMA is provided between, for example, the main memory array MMA and a circuit (for example, a bit line decoder and a sensing circuit) constituting a peripheral area. In addition, this means that the cache memory array CMA is disposed in a peripheral circuit area and is separated from a storage space (for example, a one-dimensional page buffer) that stores data transferred from or to the bit lines. Means.

The relative arrangement between the cache memory array CMA, the main memory array MMA, and the bit line structure BLS may be variously modified from those shown in FIG. 3. 4 is a table showing some examples of these various modifications, and FIGS. 5-7 are schematic perspective views illustratively showing these various modifications.

Referring to FIG. 4, according to the first basic structure, as shown in FIG. 5 or as type A in FIG. 3, the cache memory array CMA includes the main memory array MMA and the bit line structure BLS. It can be placed in between. According to a second basic structure, as shown as type B in FIG. 5, the main memory array MMA may be disposed between the cache memory array CMA and the bitline structure BLS. According to a third basic structure, as shown as type C in FIG. 5, the bitline structure BLS may be disposed between the main memory array MMA and the cache memory array CMA. According to a fourth basic structure, as shown as type D in FIG. 5, the cache memory array CMA and the main memory array MMA are disposed adjacent to and parallel to each other on a substrate, and the bitline structure ( BLS) may be provided on top of them.

The first basic structure is variously modified by the presence of additional structures, such as selection structure (SLS) or environmental structure (EVS) (described in more detail below), as shown as type AS and type AE of FIG. 6. Can be. For example, when the 3D memory device further includes the selection structure SLS, the first basic structure may be modified to one of the first to fourth modified structures of FIG. 4. In addition, as in the fifth to eighth modified structures of FIG. 4, the first basic structure may include the cache memory array CMA and the main memory array MMA on the bit line structure BLS in turn. It may be deformed to have a stacked structure (ie, an inverted structure of the first to fourth modified structures).

The selection structure SLS may be, for example, (1) selecting one or some of internal lines (eg, VL, HL, HLx, or HLy) constituting the main memory array MMA (2); ) May be configured to enable selection of one or some of the conductive lines constituting the cache memory array (CMA). In some embodiments, the selection structure SLS may be interpreted as part of the cache memory array CMA. Technical features related to the selection structure SLS will be described in more detail later with reference to FIGS. 30 to 35 and 39 to 67.

Even if a three-dimensional memory device further comprises the environmental structure EVS, the first basic structure may be modified in a similar manner as in the variants provided with the selection structure SLS. The environment structure EVS may be configured to enhance the effectiveness of the pairing, which will be described in more detail later with reference to FIG. 38. Similarly, each of the second to fourth basic structures may also be variously modified, such as modified structures for the first basic structure.

Each of the main and cache memory arrays (MMA, CMA) may be composed of a plurality of parts, operating separately or independently from each other, as shown in type AF and AP of FIG. 6 and type DF and DP of FIG. 7. Can be. Each portion of the cache memory array CMA is formed to have a fully corresponding structure, as in the corresponding respective portion of the main memory array MMA, type AF of FIG. 6 and type DF of FIG. AP and may be formed to have a partial correspondence structure, as in type DF of FIG. 7. The full or partial corresponding structures will be described in more detail below.

The bit line structure BLS is a memory cell of the cache memory array CMA connected to or connected to the internal lines (eg, VL or HL) of the main memory array MMA, as shown in FIG. 3. The plurality of bit lines BL may be configured to be electrically connected to the plurality of bit lines BL. The bit line structure BLS may be configured to intersect or be commonly connected to portions of the main and cache memory arrays MMA and CMA. For example, the bitline structure BLS is provided on top of portions of the main memory array MMA, as shown in type AF and AP in FIG. 6 and type DF and DP in FIG. It may be provided under the main memory array (MMA) as shown in the type DI.

Meanwhile, the first to fourth basic structures are classified by the above-described arrangement or arrangement order between the main memory array MMA, the cache memory array CMA, and the bit line structure BLS, and the substrate The relative arrangement with respect to (SUB) can vary or be freely modified. For example, the first basic structure may be embodied as inverted forms, as shown in the first and fifth modified structures of FIG. 4, or as 90 degrees rotated clockwise or counterclockwise, although not shown. May be The second to third basic structures and variations thereof may also be implemented with the above-mentioned variety or freedom in relative arrangement with respect to the substrate SUB.

8 to 12 are schematic perspective views exemplarily showing positions of the main and cache memory arrays MMA and CMA and directions of inner lines thereof. For example, each of the structures of FIGS. 8 and 9 may be implemented to implement embodiments in which the main memory array (MMA) is provided in the form of vertical-channel and vertical-gate NAND flash memories. Can be used. Similarly, but not limited to, each of the structures of FIGS. 8-12 may be used to implement embodiments in which the main memory array (MMA) is provided in the form of a three-dimensional crosspoint resistive memory.

8 to 12, each of the word lines WL is illustrated in the form of a flat plate, but may be provided in a one-dimensional structure including a plurality of lines, such as a multi-layer or multi-column structure. When each of the word lines WL is provided in a flat form, two-dimensionally arranged ones of the memory cells MC may be commonly connected to each of the word lines WL. This may cause read / write disturbances to be described later. Even when each of the word lines WL includes a plurality of lines that are spatially separated but electrically connected, the disturbance problem may occur in the same manner.

In the cache memory array CMA, a plurality of cache lines CWL connecting the cache cells CC may be provided. In some embodiments, the cache lines CWL may be electrically separated from each other, and disposed to cross the bit lines BL.

FIG. 13 is a diagram exemplarily illustrating a hierarchy structure of the main memory array MMA of the 3D memory device to which the present invention can be applied. Referring to FIG. 13, the main memory array MMA may include at least one block, and the block may include one or a plurality of (eg, r) chapters. Each may include a plurality of (eg q) pages, and each of the pages may include a plurality of (eg p) cells. The concepts of chapters, pages, and cells described herein are equally applicable to describing the hierarchical structure of the cache memory array (CMA).

The block may be a unit of cells or data size (eg, maximum) in which an operation may be performed independently. For example, according to some embodiments of the invention applicable to NAND flash memory, a block can be used as a unit of data that can be erased at one time. However, the concept of the block need not be limited to the definition based on this method of operation. For example, the block may be a collection of three-dimensionally arranged memory cells, and such memory cells may be provided in a localized area or in a distributed form in several areas.

The chapter may refer to data or cells included in one plane of the main memory array (MMA) or the block. In other words, the chapter is composed of data or cells arranged two-dimensionally on a predetermined plane. Here, the plane may mean a plane in at least one of the data-layer structural side or the side of the physical arrangement of the cells, the direction of the plane of the bit lines (BL) and the word lines (WL) Selection may be made based on the arrangement and method of operation performed using them. For example, in the case of the vertical-channel NAND flash memory of FIG. 8 (where coplanar wordlines are electrically connected and used as a common gate electrode of two-dimensionally arranged memory cells), one chapter (the common The two-dimensionally arranged memory cells (controlled by a gate electrode) or data stored therein.

The page refers to a data size or a maximum size that can be read at one time through the bit line structure BLS. As described above, since each bit line is electrically connected to a plurality of internal lines constituting the main memory array MMA, two-dimensional data constituting the chapter or three-dimensional data constituting the block It may be difficult to input or output at one time through the bit line structure BLS. Accordingly, as shown in FIG. 14, two-dimensional data constituting one chapter or three-dimensional data constituting one block is divided into groups of one-dimensional data, and then the bit lines ( Are sequentially input or output through BL). The page may correspond to each of the one-dimensional data groups.

In order to provide a better understanding of the chapter and page concepts, one chapter of the main memory array (MMA) and the pages constituting it are exemplarily illustrated in FIGS. 8 to 12.

In the main memory array MMA, the memory cells are each of intersection points between the vertical lines VL and the horizontal lines HL or between the first and second horizontal lines HLx and HLy. Means the information storage space provided in. In embodiments of the present invention, the cell may be configured to store single or multi bits.

As described above, the memory cells constituting the block may be provided in a distributed form in various areas. Similarly, memory cells constituting one chapter or one page may also be provided in a distributed form in various areas. For example, each block, chapter, and / or page may be divided into a plurality of sections configured to operate independently, based on a method of pair / hole division or left / right division. For brevity of description, the description of possible embodiments of the present invention that can be applied to such separate sections will be minimized, but the method of section separation can be variously modified in view of the efficiency of read or write operations. have. Thus, known techniques based on such section separation (eg, applied to two-dimensional memory semiconductors) can be used or applied to implement the technical idea of the present invention, and such use or application is an embodiment of the present invention. Included as part of the

FIG. 15 is a diagram illustrating some of operations performed in a 3D memory device according to example embodiments. Referring to FIG. 15, operations of a 3D memory device according to some embodiments of the present invention may include MM-CM copy (S [RM]), CM-MM copy (S [WM]), and CM write (S [WC]. ]), And CM read (S [RC]). The steps of the MM-CM copy (S [RM]) and the CM-MM copy (S [WM]) are performed between the main memory array MMA and the cache memory array CMA as shown in FIG. And the steps of the CM write (S [WC]) and the CM read (S [RC]) are data performed between the cache memory array CMA and the peripheral area as shown in FIG. Transmission processes.

According to some embodiments, the MM-CM copy (S [RM]) and CM-MM copy (S [WM]) are performed in chapter units, and the CM write (S [WC]) and CM read (S) are performed. Steps of [RC]) may be performed sequentially or randomly in units of pages. However, embodiments of the present invention are not limited thereto, and as described with reference to FIGS. 25 to 30, each of these steps may be variously modified in units and methods of data processing.

The MM-CM copy (S [RM]), CM-MM copy (S [WM]), CM write (S [WC]), CM read (S [RC]), and CM-CM copy (S [CC] ]) Steps may be performed in combination as appropriate. For example, these steps may include (1) a read operation for reading information stored in the main memory array (MMA) into a peripheral circuit (eg, a page buffer or sensing circuit) and (2) an external device provided through the peripheral circuit. And a write operation for storing data in the main memory array MMA.

According to some embodiments, the read operation may include the MM-CM copy (S [RM]) and the CM read (S [RC]) steps as illustrated in FIGS. 18 and 19, wherein the write operation is performed. 20 and 21 may include the steps of the CM write (S [WC]) and the CM-MM copy (S [WM]). For simplicity of explanation, below, read and write operations for data in one chapter will be described by way of example. That is, the plurality of chapter data can be processed by repeating the operation described below.

As illustrated in FIGS. 16 and 18, the MM-CM copy S [RM] refers to a process of copying data stored in the main memory array MMA to the cache memory array CMA. The MM-CM copy S [RM] may be performed to copy chapter-based data into the cache memory array CMA at a time, as shown in the left side of FIG. 19. According to modified embodiments, the MM-CM copy S [RM] may comprise a plurality of substeps, each of which is implemented to copy data of two pages or more (eg, 24, 26, or 28).

As shown in FIGS. 17 and 18, the CM read S [RC] uses the bit line structure BLS to transmit data of the cache memory array CMA to peripheral circuits (eg, sensing circuits or the like). Page buffer). The CM read S [RC] may include a plurality of cache page read steps, each of which may be implemented to transmit data in units of pages to the peripheral circuit. According to modified embodiments, the CM read S [RC] may comprise a plurality of substeps, each of which is implemented to transmit data of a size smaller than a page. For example, each of the substeps of the CM read S [RC] may be implemented to process one or more cell data.

As illustrated in FIGS. 17 and 20, the CM write S [WC] refers to a process of writing external data into the cache memory array CMA using the bit line structure BLS. The CM write S [WC] may comprise a plurality of cache page write steps, each of which is implemented to write page-by-page data to the cache memory array CMA, as shown on the left side of FIG. 21. Can be. According to modified embodiments, the CM write S [WC] may comprise a plurality of substeps, each of which is implemented to transmit data of a size smaller than a page. For example, each of the substeps of the CM write S [WC] may be implemented to process bit, byte, or more cell data.

As illustrated in FIGS. 16 and 20, the CM-MM copy S [WM] refers to a process of copying data stored in the cache memory array CMA to the main memory array MMA. The CM-MM copy S [WM] is configured to copy chapter-based data stored in the cache memory array CMA to predetermined chapters of the main memory array MMA at one time, as shown in the right side of FIG. 21. Can be implemented. According to modified embodiments, the CM-MM copy S [WM] may comprise a plurality of substeps, each of which is implemented to copy data in units of two pages or more (eg, , See FIG. 24).

In some embodiments, data is read from the cache memory array (CMA) or read from the cache memory array (CMA) in a random access manner or based on one of cache algorithms applied to L1, L2, or L3 cache memory. Can be recorded. For example, the CM read (S [RC]) and the CM write (S [WC]) may be implemented to process data in bit, byte, word, or page units. In some embodiments, the cache memory array CMA may be used as any one of L1, L2 or L3 caches and may be configured to implement the functionality of a DRAM or SRAM currently used. According to some embodiments, the peripheral circuit may be configured to implement the random access scheme or a cache algorithm for the L1, L2, or L3 cache. For example, the peripheral circuit may further include a driving or decoding circuit used in DRAM, SRAM or NOR flash memory devices.

The step of CM-CM copy S [CC] is a data transfer process performed between two different portions P1 and P2 of the cache memory array CMA. The CM-CM copy (S [CC]) may be combined with at least one of the other steps illustrated in FIG. 15 to implement the random access or cache algorithm described above. Two different portions of the cache memory array CMA may be configured to share the bitline structure BLS, and the step of CM-CM copy S [CC] may comprise the shared bitline structure BLS. It can be performed using. According to some embodiments, as illustrated in FIG. 22, data is directly copied from one of the two parts P1 and P2 to another without copying or migrating data to the peripheral area. Or to migrate. However, according to modified embodiments, the CM-CM copy S [CC] may be sequentially performed using the peripheral area (eg, page buffer). For example, as shown in FIG. 29, the CM-CM copy S [CC] is performed in the two parts P1 and P2 respectively and sequentially, the CM read S [RC] and the It can be implemented through a combination of CM writes (S [WC]).

15 and 23, according to modified embodiments of the present invention, each of the write and read operations may include an MM direct write (S [WMd]) that does not use the cache memory array CMA, and It can be implemented in a manner including the step of MM direct read (S [RMd]).

The MM direct write (S [WMd]) refers to a process of directly writing external data provided through the peripheral circuit to the main memory array MMA. For example, the MM direct write S [WMd] may be a data transfer process performed without an interruption step of storing data in the cache memory array CMA. According to some embodiments, the MM direct write (S [WMd]), as shown in FIG. 23, is implemented to write the data in page units directly to a predetermined chapter of the main memory array MMA, as shown in FIG. 23. A plurality of lower direct write steps may be included. According to modified embodiments, each of the lower direct write steps may be implemented to process one or more cell data. Alternatively, the MM direct write (S [WMd]) may be implemented to process chapter or more data, as in the erasing step of the flash memory.

The MM direct read S [RMd] refers to a process of transferring data of the main memory array MMA to the peripheral circuit without an interruption step of storing data in the cache memory array CMA. The MM direct read (S [RMd]) may include a plurality of lower direct read steps, each of which is implemented to transmit page-by-page data to the peripheral circuit, as shown in FIG. Each of the direct read steps may be implemented to process one or more cell data.

According to some embodiments of the present disclosure, as illustrated in FIG. 15, an operation of the 3D memory device may initialize (eg, initialize) all or part of the cache memory array CMA or the cache cells CC. CM initialization (S [IN]) step may be further included. If the cache cell CC is non-volatile (eg, as in a magnetic tunnel junction), its data change may be due to external factors (eg, external or electrical transmitted from the main memory array MMA). Signals as well as dependencies on internal factors (e.g., the data state of the cache cell CC itself). In this case, it may be necessary to eliminate the nonuniformity in the cache memory array CMA related to the internal factor through the CM initialization (S [IN]) step. In other words, when the cache cells CC are not initialized, some of the data stored in the cache cells CC may not be changed. In this case, for example, the CM write (S [ WC]) and during the MM-CM copy S [RM]) only some of the data from the external or the main memory array MMA may be written to the cache cells CC. That is, an error may occur.

Nevertheless, if the data change of the cache cell CC has a small or negligible dependency on the internal factor, in some embodiments, the CM initialization (S [IN]) step may be omitted. More specifically, this omission is determined by the data storage principle of the cache cells CC or the type of electrical signal including the information stored in the memory cells MC, the determination of which is illustrated in the examples below. Based on the knowledge level of one skilled in the art. For example, when the cache cell CC is implemented through a memory element having a short retention characteristic (ie, volatile), the CM initialization (S [IN]) step may be omitted. The CM initialization S [IN] may be performed in units of chapters or smaller data (pages).

Each of the above-described steps may be changed in various ways, and each of the read and write operations may be performed in various combinations. For example, as shown in FIGS. 24 and 25, the MM-CM copy (S [RM]), the CM-MM copy (S [WM]), the CM write (S [WC]), and the The CM read (S [RC]) may be performed by transmitting data in units smaller than chapters. In addition, as illustrated in FIGS. 26 and 27, chapter data stored in the cache memory array CMA may be different from data transmitted from the main memory array MMA through the MM-CM copy S [RM]. It may be the sum of data transmitted from the peripheral area through the CM write (S [WC]). In this case, the MM-CM copy (S [RM]) may be performed in units of data or chapters of chapters or less as shown in FIGS. 26 and 27, and the CM write (S [WC]) is performed in FIG. 27. It may be performed in an overwrite manner as shown in FIG. In addition, as shown in FIG. 28, the chapter data stored in the cache memory array CMA is different from that of the main memory array MMA obtained through the steps of the MM-CM copy S [RM]. It can be the sum of two chapter data. Here, various modifications in the data processing method have been described, but embodiments of the present invention are not limited thereto, and may be variously modified based on the additional technical descriptions and known techniques provided below.

30 and 31 are tables for exemplarily describing some of technical features of operating steps of a 3D memory device according to example embodiments.

As shown in FIG. 30, the CM write (S [WC]) and the CM read (S [RC]) take a current path through the bit line BL, the cache cell CC, and the select line SL. It may be performed in units of pages. In this case, since it is not necessary to form a current path connected to the memory cells MC, the problem of disturbance to the main memory array MMA can be prevented.

In contrast, the MM-CM copy (S [RM]) and the CM-MM copy (S [WM]) share a current path through the bit line BL, the cache cell CC, and the memory cell MC. It can be performed in units of chapters. In this case, a disturbance phenomenon may appear, but since each of them is one chapter data transmission process, the problem of repetitive disturbance can be prevented.

In order to implement the change in the current path, the cache memory array CMA may include the bit line BL as the select line SL and the internal wiring of the main memory array MMA as illustrated in FIG. 31. , VL or HL) may include a selector or switch that can be selectively connected to any one. The selector may be provided as part of the selection structure SLS described with reference to FIG. 6.

31 exemplarily shows a direction in which a signal is transmitted in each step. For example, since the CM write S [WC] is a process of writing data transmitted from the peripheral area to the cache cell CC, data is transferred from the bit line BL to the cache cell CC. Is transmitted in a direction towards. In contrast, in the case of the MM-CM copy S [RM], since the data is transferred from the memory cell MC to the cache cell CC, the signal direction in the CM write S [WC]. Can be antiparallel to (On the other hand, the direction of the signal mentioned herein may vary depending on the structure and operating principle of the memory or cache cells, and may differ from the direction of the current.)

According to embodiments of the present invention, the selector may be configured to implement such a change in signal direction. 32 shows an example of a direction of a write current according to the type of the cache cell CC and a possible type of the selector for implementing the same.

33 is a circuit diagram exemplarily illustrating a cache cell array (CMA) including unit cache memories, and FIGS. 34 and 35 schematically and exemplarily illustrate some of the possible structures of the unit cache memory.

Referring to FIG. 33, the cache memory array CMA may include unit cache memories CMU arranged in two dimensions. Each of the internal wires (eg, VL or HL) of the main memory array MMA is connected to a corresponding one or second of the first lines L1 through a corresponding one of the unit cache memories CMU. May be connected to the corresponding one of the lines L2. The first lines L1 are arranged to cross the second lines L2, and the internal lines VL or HL cross both the first and second lines L1 and L2. It may have a long axis to shout. For example, the first and second lines L1 and L2 and the internal lines VL or HL may be substantially perpendicular to each other.

Each of the unit cache memories CMU may include at least one cache cell CC for data storage and at least one selector ST for changing the aforementioned signal transmission path or current path. The operation of the cache cell CC and the selector ST may be controlled by the cache line CWL, which may be one of the first or second lines L1 and L2. 33-35 illustrate embodiments in which the cache line CWL is implemented using the second line L2, the cache line CWL is similarly similar. It may be implemented using the first line L1.)

According to some embodiments, the first line L1 is used as the bit line structure BLS or the bit lines BL, and the second line L2 is described with reference to FIGS. 30 and 31. It can be used as a wiring for implementing a change of the current path. However, according to other embodiments, these functions of the first and second lines L1 and L2 may be interchanged. These two types of embodiments will be more clearly understood from the comparison of FIGS. 39 and 47 which will be described below.

The structure of the cache line CWL may be varied according to the structure and / or principle of operation of the cache cell CC and the selector ST, as shown in FIG. 34. For example, the cache line CWL may include one or more lines SL, GL, and CL used to control the selector ST and / or the cache cell CC.

More specifically, the selector ST is a two-terminal switching element (for example, provided between the selection source line SL and the cache cell CC, as in types A and B of FIGS. 34 and 35, for example). Diodes), but as in types C and D of FIGS. 34 and 35, a three-terminal switching element (e.g., further comprising a control line or a gate line GL in addition to the selection source line SL) , Transistors). In addition, the cache cell CC, as in types A and C of FIGS. 34 and 35, is a two-terminal memory element provided between the first line L1 and the selector ST (for example, Variable resistance memory element) but may be a three-terminal memory element (e.g., a memory element of a transistor structure) controlled by the cache control line CL, as in types B and D of FIGS. 34 and 35 have. In other words, the cache line CWL may include the selection source line SL, the gate line GL, and the like according to the type, structure, and / or operating principle of the cache cell CC and the selector ST. It may be configured to include at least one of the cache control line (CL).

Although not limited thereto, the unit cache memory CMU or the cache cell CC may be implemented using one of the memory elements illustrated in FIG. 36. For example, the unit cache memory (CMU) is DRAM, SRAM, FRAM, NAND FLASH, MRAM, STT-MRAM, PCRAM, NRAM, RRAM, CBRAM, SEM, T-RAM, Z-RAM, Polymer, Molecular, Racetrack It may include one selected from the group consisting of memory elements known as, Holographic, Probe and the like. Alternatively, the unit cache memory (CMU) is at least one of the known memory elements (e.g., at least one of the memory elements, disclosed in the documents constituting the International Technology Roadmap for Semiconductor (ITRS) and its reference list). ) May be included.

In some embodiments, the cache cells CC may be memory cells based on a data storage principle different from that of the memory cells MC. For example, the main memory array (MMA) may be implemented in the form of a three-dimensional NAND flash memory, PCRAM, CBRAM, or ReRAM, the cache memory array (CMA) is SRAM, PCRAM, STT-MRAM, CBRAM, The T-RAM, the ReRAM, or the Z-RAM may be implemented using other than the memory cells MC. However, in other embodiments, the cache and memory cells CC and MC may be memory cells of the same kind or memory cells based on the same or similar operating principle.

In some embodiments, each of the cache cells CC may be configured to have a faster write and / or read speed than each of the memory cells MC. For example, when the memory cells MC are charge storage elements as in a flash memory device, the cache cells CC may include memory elements (eg, PCMs) having variable resistance characteristics shown in FIG. 36. , MTJ, Z-RAM, CBRAM, ReRAM materials, etc.).

In some embodiments, the main memory array MMA is comprised of nonvolatile memory elements, and the cache memory array CMA is a volatile or nonvolatile memory having a faster operating speed than the memory cell MC. It may consist of elements. For example, when the memory cells MC are charge storage elements as in a flash memory device, the cache cells CC may be implemented in the form of SRAM, T-RAM, or Z-RAM.

However, the cache and memory cells CC and MC need not be combined in the manner illustrated above. For example, based on consideration of other technical issues such as manufacturing process, manufacturing cost, data retention characteristics, mating characteristics (described below), and ease of current path formation, the implementation scheme described above is mitigated or changed. Can be. Alternatively, a type of memory element for the cache memory array CMA may include a principle of operation of the memory cells MC and characteristics of an electrical signal for operation (for example, unidirectional or bidirectional, voltage application or current application). , Amount of current, speed, etc.) or various technical requirements for the cache memory array (CMA) itself (eg, operability as RAM or buffer memory). For example, in relation to the CM-MM copy (S [WM]) step, the MM-CM is configured such that the characteristic of the read signal of the cache cell CC corresponds to the characteristic of the write signal of the memory cell MC. In relation to the copying S [RM] step, the cache cell CC and the memory cell C are arranged such that the characteristics of the read signal of the memory cell MC correspond to the characteristics of the write signal of the cache cell CC. It may be necessary to design MC). In addition, the cache and memory cells CC and MC may be combined to maximize the technical effects of the disturbance reduction and the read / write time reduction described below with reference to FIGS. 77 to 79.

Although not limited thereto, the main memory array MMA may be configured to include one of the array structures illustrated in FIG. 37. For example, as in type A of FIG. 37, the main memory array MMA uses the internal line VL / HL as a channel region (eg, as in a cell string of NAND flash memory). ) May be provided in a structure including a plurality of memory cells MC connected in series.

Alternatively, as in types B, C, and D of FIG. 37, the main memory array MMA may be provided in a structure including a plurality of memory cells MC connected in parallel to the internal line VL / HL. have. In this case, according to some embodiments, each of the memory cells MC may be configured to include a rectifying element (eg, a diode) as in type D. Alternatively, as in type B, the internal line VL / HL may be a semiconductor material whose potential is controlled by a conductive line, and the electrical connection between the memory cells MC and the cache cell CC may be Can be controlled by conductive lines. For example, as will be described again with reference to FIG. 66, the conductive line and the inner line VL / HL may form a structure of a MOS capacitor or a vertical path control structure VPCS.

Meanwhile, the MM-CM copy S [RM] may be a process of writing data read from the memory cells MC to the cache cell CC. In other words, in the MM-CM copy S [RM], a read operation of the memory cell MC is performed in pairs with a write operation of the cache cell CC. The CM-MM copy S [WM] may be a process of writing data read from the cache cell CC to the memory cell MC. In other words, in the CM-MM copy S [WM], a write operation of the memory cell MC may be performed in pairs with a read operation of the cache cell CC. This is because, in order for the CM-MM copy (S [WM]) and the MM-CM copy (S [RM]) to be performed effectively, the paired operations are characterized by electrical or operational characteristics (e.g., For example, it is necessary to harmonize with each other in the amount of current and operating time).

According to some embodiments of the present invention, as shown in type A-E of FIG. 6, the semiconductor device may further include an environmental structure (EVS) configured to enhance the effectiveness of this pairing. For example, the environmental structure EVS may be configured to adjust an electrical resistance of a path connecting the memory cell MC and the cache cell CC. Alternatively, the environmental structure EVS is further configured to mitigate inconsistencies in electrical characteristics therebetween, which may occur during a data exchange or copy operation between the memory cell MC and the cache cell CC. May include memory elements. For example, the data exchange or copy operation may include a data transfer process configured to directly or indirectly pass through the additional memory element provided in the environment structure EVS.

The environmental structure EVS may be configured to bring about a change in an operating environment (eg, temperature) of the cache cell CC. The environmental structure EVS may be configured to operate locally or selectively, for which it may comprise a plurality of environmental control elements and conductive lines for electrically controlling them. In addition, when the bit lines are provided in the form of an optical waveguide, the environmental structure EVS may include photoelectric conversion elements for converting an electrical signal into an optical signal or vice versa.

6 illustrates an example in which the environmental structure EVS is interposed between the main memory array MMA and the wiring structure UWS, but embodiments of the present invention are limited thereto. no. For example, the location of the environmental structure EVS may be variously modified as described with reference to FIGS. 4 to 7.

39 to 43 are diagrams for describing an operation of a semiconductor device according to example embodiments. In this embodiment, the main memory array (MMA) is configured to have a structure of vertical channel three-dimensional NAND flash (e.g., BiCS or TCAT) as in type A of FIG. 37, and the cache memory array (CMA) May be configured to include cache cells CC that are two-dimensionally arranged on the main memory array MMA. Here, an embodiment in which the cache cells CC are high speed resistive memory elements (eg, STT-MTJ) operating using bidirectional current will be described by way of example.

The cache cells CC may be interposed between the bit line BL and the main memory array MMA, and the vertical line VL may be a semiconductor pattern perpendicular to an upper surface of the substrate SUB. And a charge storage layer (eg, ONO), which functions as the memory cells MC, may be interposed between the vertical line VL and the horizontal line HL. The semiconductor pattern of the vertical line VL may include, for example, n-type impurity regions used as source and drain electrodes, and a vertical or intrinsic vertical channel region interposed therebetween. In example embodiments, the n-type impurity regions may be replaced with a metal-containing film that may form a rectifying device together with the vertical channel region.

The horizontal lines HL or the word lines WL may include metal or doped silicon. A plurality of gate lines GL may cross the bit lines BL between the cache cells CC and the main memory array MMA. Each of the gate lines GL may be used as a gate electrode of a transistor (ie, the selector T) using the semiconductor pattern of the vertical line VL as a channel region, and the selection source line SL And an electrical path between the cache cell and the cache cell CC.

By virtue of the presence of the selector T, the vertical channel region is electrically connected for the CM write (S [WC]) and the CM read (S [RC]), as shown in FIGS. 39, 40, and 43. It is not used as a path. Accordingly, the problem of read and write disturbances that may be applied to the main memory array MMA can be reduced.

During the CM write S [WC], as shown in FIGS. 39 and 40, either one of the cache lines CWL or the selection source lines SL and the plurality of bit lines BL. Operating voltages can be applied. In this case, input data may be transferred to the cache cells CC through the bit lines BL (eg, from a page buffer of a peripheral circuit). For example, depending on the data to be input, a voltage (for example, V1 or Vlow) applied to a part of the bit lines BL may be different from a voltage (eg, V2 or Vhigh) applied to another part. . In this case, as shown, if a voltage substantially equal to any of the bit line voltages is applied to one of the selected source lines SL, the write current for the cache cell CC is connected to it. And may be selectively formed by a potential difference between the bit line BL and the selection source line SL. In the drawings of this application, including FIG. 39, a question mark ("?") Indicates that a current path via it may be selectively formed by the data stored in the memory element it points to, or an associated data write operation may optionally be performed. That means you can.

During the CM-MM copy S [WM], as shown in FIGS. 39 and 41, a bit line voltage V_BL is applied to the bit lines BL, and any of the word lines WL is applied. The program voltage Vpgm is applied to one (hereinafter, selected word line). In this case, the current path from the bit line BL to the cell string may be selectively generated depending on data stored in each of the cache cells CC. For example, when the cache cell CC is in an on state, the corresponding channel region may have a potential substantially equal to that of the bit line (ie, V_BL) (eg, 0V). In this case, when the voltage (ie, Vpgm) applied to the selected word line is high, a program through F-N tunneling occurs. On the other hand, when the cache cell CC is in an off state, the corresponding channel region is electrically isolated, and thus has a potential increased by voltages applied to the word lines WL. As a result, the potential difference with the program voltage can be reduced. That is, program prevention through self-boosting technology may be enabled.

During the MM-CM copy S [RM], as shown in FIGS. 39 and 42, a plurality of bit lines BL and one of the word lines WL (hereinafter, selected word lines) may be used. Operating voltages are applied. In this case, as illustrated in FIG. 39, a current path through each of the cache cells CC may be selectively generated depending on each of the data stored in the two-dimensional memory cells MC controlled by the selection word line. have. When such a current path is generated, the data of the corresponding cache cell CC may be changed (for example, in a high resistance state or an off state). In some embodiments, prior to the MM-CM copy S [RM], the CM initialization S [IN] may be performed to turn on the cache cells CC.

During the CM read S [RC], as shown in FIGS. 39 and 43, different operating voltages V1 and V2 are applied to any one of the cache lines CWL or the selected source lines SL. One and one may be applied to the bit lines BL, respectively. In this case, according to the applied voltage condition, a current in the direction shown in FIG. 39 or the opposite direction may be selectively generated depending on the data stored in the cache cell CC. The sense amplifiers in the peripheral region may be configured to detect variations in the electrical state (eg, potential) of the bit lines caused by the generation of such current paths. As illustrated in FIG. 43, the CM read S [RC] may be performed in page units (or less).

The read and write operations described above may be performed selectively and / or randomly on a portion (eg, page or less) of the cache memory array (CMA). Further, such selective read and write operations to the cache memory array CMA may be performed independently without access to the main memory array MMA. This means that the cache memory array CMA can be used as L1, L2, or L3 cache. Access to the main memory array (MMA) may be performed at a time when it is determined that long-term storage of data stored in the cache memory array (CMA) is necessary. That is, the main memory array MMA may be used as storage, for example.

Meanwhile, when self-boosting using the cache cell CC in the CM-MM copy S [WM], the need for string select lines SSL, which is required in the prior art, may be reduced. . For example, if the off resistance of the cache cell CC is sufficiently large, the CM-MM copy S [WM] may be effectively performed even when the string select lines SSL are not present. Nevertheless, this does not necessarily require the removal of the string select lines SSL.

According to some embodiments, as illustrated in FIG. 44, the string select line SSL may be used as the gate line GL of the selector ST. In this embodiment, the semiconductor pattern constituting the vertical line VL is used as an active pattern of the selector ST, and a current path between the bit line BL and the cache cell CC is connected to the gate line. GL) or the string select line SSL. In some embodiments, the bit line BL may be formed using a process of patterning the string select line SSL, and may be formed of a conductive material capable of forming the semiconductor pattern and the rectifying device. . In other embodiments, a conductive thin film (eg, n + polysilicon) capable of implementing the rectifying device may be further provided between the bit line BL and the semiconductor pattern VL. In example embodiments, the bit line BL may be formed to cross the gate line GL.

As illustrated in FIG. 45, the main memory array MMA may be programmed (for example, in page units) through the MM direct write operation S [WMd]. For example, if the cache cells CC do not have a sufficiently high resistance even when in the off state, it may be difficult to implement the above-described self-boosting technique. In this case, the MM direct write (S [WMd]) step may be performed. The erase operation on the main memory array MMA may be equally performed based on known conventional techniques.

The CM initialization S [IN] may be implemented using one of three methods as shown in FIG. For example, the CM initialization S [IN] may be performed using a current path through the selector ST without access (ie, disturbing) to the main memory array MMA, or the common source line. It may be implemented using a current path through the CSL and the main memory array MMA. When the CM initialization S [IN] is performed using a current passing through the selector ST, the CM initialization S [IN] may be performed in units of chapters. In this case, a large current may be discharged through the selection source line SL or the bit line BL. In some embodiments, the select source line SL or the bit line BL may be formed to a sufficiently thick thickness to enable such a large current discharge.

As shown in FIG. 46, when the selection source line SL is provided on the selector ST, the selection source line SL has a thick thickness (e.g., 100 nm-5 um). 46, the CM write (S [WC]) and the CM-MM copy (S [WM) even when the selection source line SL is provided on top of the selector ST. ]), The MM-CM copy (S [RM]), and the CM read (S [RC]) may be effectively performed. However, embodiments of the present invention are not limited to those illustrated in FIG. 46. In example embodiments, the bit line BL may be formed to cross the gate line GL. In addition, the structure of the selector ST or the illustrated voltage conditions may be changed in various ways according to the type and operation method of the cache cells CC.

47 to 52 are diagrams for describing an operation of a semiconductor device according to example embodiments of the present inventive concepts. According to this embodiment, the main memory array MMA is configured to include variable resistance memory elements connected in parallel to the internal line VL as in type D of FIG. 37, wherein the cache memory array CMA is It may be configured to include cache cells (CC) two-dimensionally arranged above or below the main memory array (MMA). Here, an embodiment in which the cache cells CC are memory elements having bidirectional current characteristics will be described as an example. For example, the cache cells CC may be provided in the form of FBM or Z-RAM described with reference to FIG. 36. When the cache cells CC have a unidirectional current characteristic, the cache memory array CMA may be implemented in an easier or simplified structure than the bidirectional current. For example, since the unidirectional current characteristic can be implemented through a two-terminal switching element (eg a diode), compared to the case where a three-terminal switching element (eg a transistor) is used to realize the bidirectional current characteristic. It can have a simplified structure. Therefore, the description of the embodiments in which the cache cells CC have a unidirectional current characteristic will be omitted.

The internal line VL may be connected to a connection node positioned between the cache cell CC and the selector ST constituting the unit cache memory CMU. (The inner line may be any one of the horizontal lines HL, HLx, and HLy, but for the sake of brevity, the description of these embodiments will be omitted.) Each of the bit lines BL may be It may be connected to the internal line VL via the cache cell CC, and the operation of the cache cell CC may be controlled by the cache control line CL crossing the bit lines BL. . The selection source line SL may be connected to the internal line VL via the selector ST, and the operation of the selector ST may be performed through the gate line GL across the bit lines BL. Can be controlled by

47 to 52 exemplarily illustrate that various operations or generation of a current path for the three-dimensional memory device described with reference to FIGS. 15 to 29 may be implemented through such a configuration or structure. For example, as in the previous embodiments, due to the presence of the selector ST, the CM write (S [WC]), the CM read, as shown in FIGS. 48, 51, and 52 (S [RC]), and it is possible to create a current path that does not cause disturbance to the main memory array MMA during the CM initialization S [IN]. Further, the CM-MM copy (S [WM]) and the MM-CM copy (S [RM]) may have a difference in the direction of transmission of the signal, but are shown in chapter units as shown in FIGS. 49 and 50. (Ie two dimensional).

Embodiments of the present invention are not limited to the voltage condition, circuit structure, or wiring structure shown in FIGS. 47 to 52. For example, FIG. 53 shows that the gate lines GL are connected to each other and may be used as a common gate electrode of adjacent ones of the cache cells CC. In addition, the current direction is not limited to that illustrated in FIG. 47, and may be variously modified according to a developer's needs. In addition, the structure and connection of the cache cells CC implements the operations described with reference to FIGS. 15 to 29 based on one of the conventional cell array structures used in DRAM, FRAM, NOR flash, and the like. It can be modified to.

54 is a diagram for describing an operation of a semiconductor device according to an embodiment of the present disclosure. According to this embodiment, similar to the embodiment described with reference to FIG. 47, the main memory array MMA is configured to have a structure of type D of FIG. 37, and the cache memory array CMA is illustrated in FIGS. It may be configured to have a structure of type D of FIG. However, in this embodiment, the internal structure of the cache memory array CMA may be modified from the structure of FIG. 47. For example, as shown in FIG. 54, each of the bit lines BL may be connected to the internal line VL via the selector ST, and the operation of the selector ST may be performed by the bit line. It may be controlled by the gate line GL across the field BL. The selection source line SL may be connected to the internal line VL via the cache cell CC, and the operation of the cache cell CC may be a cache control line crossing the bit lines BL. Can be controlled by (CL). Despite this difference in the internal structure of the cache memory array CMA, similar to the embodiment of FIG. 47, the operations described with reference to FIGS. 15 to 29 are effectively implemented through the structure according to this embodiment. 54 shows that it can be done.

55 is a diagram for describing an operation of a semiconductor device according to another modified embodiment of the present invention. According to these embodiments, the main memory array MMA may be configured to have a type D structure of FIG. 37, and the cache memory array CMA may be configured to have a type C structure of FIGS. 34 and 35. have. That is, the cache memory array CMA uses a two-terminal memory element (for example, a variable resistance memory element) provided between the bit line BL and the internal line VL as the cache cell CC. It can be configured to. The selection source line SL may be connected to the internal line VL through the selector ST. FIG. 55 shows that the operations described with reference to FIGS. 15 to 29 can be effectively implemented even when the cache cell CC is provided in the form of a two-terminal memory element.

56 is a diagram for describing an operation of a semiconductor device according to another modified embodiment of the present invention. According to these embodiments, the main memory array MMA may be configured to have a type A structure of FIG. 37, and the cache memory array CMA may be configured to have a type D structure of FIGS. 34 and 35. have. The internal structure of the cache memory array CMA may be configured substantially the same as that of FIG. 54. That is, the cache memory array CMA may include a three-terminal memory element (eg, FBM or Z-RAM) provided between the selection source line SL and the internal line VL. It can be configured to use as. However, the internal structure of the cache memory array CMA may be modified to be substantially the same as that of FIG. 55. 56 illustrates that the operations described with reference to FIGS. 15 through 29 are effective even when the cache cell CC is provided in the form of a two-terminal memory element and the main memory array MMA is provided as a structure of a NAND string. It can be implemented.

57 is a diagram for describing an operation of a semiconductor device according to another modified embodiment of the present invention. According to these embodiments, the main memory array MMA may be configured to have a type D structure of FIG. 37, and the cache memory array CMA may be configured to have a type B structure of FIGS. 34 and 35. have. That is, the cache memory array CMA may include a three-terminal memory element (eg, FBM or Z-RAM) provided between the selection source line SL and the internal line VL. And a two-terminal switching element (for example, a diode) provided between the bit line BL and the internal line VL as the selector ST. Even when using the two-terminal switching element as the selector ST, FIG. 57 shows that the operations described with reference to FIGS. 15 to 29 can be effectively implemented.

58 is a diagram illustrating an example of an implementation of the CM-CM copy (S [CC]) step. As illustrated in FIG. 58, the CM-CM copy S [CC] may be effectively performed in embodiments in which the unit cache memory CMU is provided in the structure of type D of FIG. 34. For example, at two different portions P1 and P2 of the cache memory array CMA, a predetermined potential difference (eg, Vcc-GND) is formed between the selection source lines SL and the cache line. Different operating voltages Vread and Vwrite may be applied to the signals CL.

59 and 60 are perspective views illustrating a semiconductor device in accordance with some embodiments of the present invention. 59 and 60, the main memory array MMA is configured to have a structure of vertical channel three-dimensional NAND flash (eg, BiCS or TCAT) as in type A of FIG. 37, and the cache memory array ( The CMA may be configured to include cache cells CC that are two-dimensionally arranged on the main memory array MMA. The cache cells CC may be high speed resistive memory elements (eg, STT-MTJ) that operate using bidirectional current. The bit lines BL may be provided on the cache cells CC as shown in FIG. 59 or between the cache cells CC and the main memory array MMA as shown in FIG. 60. . In other words, FIG. 60 may illustrate an example of the 3D semiconductor device according to the exemplary embodiment described with reference to FIG. 44. In the embodiment of FIG. 60, since the selection source line SL is provided on the cache cells CC, the selection source line SL may be formed in a thick plate shape and a low resistivity material. This enables the above-mentioned large current discharge.

61 to 65 are diagrams illustrating semiconductor devices according to example embodiments of the inventive concepts. According to these embodiments, the cache memory array CMA is configured to include cache cells CC arranged two-dimensionally below the main memory array MMA, and the cache cells CC are illustrated in FIG. 36. It may be configured to include the Z-RAM or FBM described with reference. The apparatus shown in FIG. 61 may be one of examples implementing the embodiment described with reference to FIG. 47, and FIGS. 62 to 65 may be examples implementing the embodiments described with reference to FIGS. 54 and 56. have. The selector ST or the cache cells CC may be implemented in the form of a planar transistor using an SOI substrate including an buried oxide film BOX as shown in FIG. 61 or a vertical channel surround gate transistor as shown in FIG. It can be implemented in the form of or by a combination of these two transistor structures as shown in FIG.

On the other hand, the type and arrangement of the selector ST is not limited to the MOS transistor as shown, and may be variously modified to have a structure corresponding to electrical characteristics required for the cache cells CC. In addition, in some embodiments, the selector ST may itself be configured to function as the cache cell CC, in which case the technical features in the embodiments to be described with reference to FIG. 72 are described. Can be implemented.

66 is a diagram illustrating a semiconductor device and a part of an operation thereof according to example embodiments of the inventive concepts. According to this embodiment, each of the vertical lines may constitute a vertical path control structure (VPCS). Technical features related to the vertical path control structure (VPCS) are disclosed in PCT Publication No. WO 2010/018888 (2010.02.18) and US Application No. 13 / 059,059, the contents of which are fully incorporated as part of the present invention. . The use of the vertical path control structure VPCS is parasitic between three-dimensionally arranged memory cells MC, even when no rectifying element (eg, diode) is placed in each of the memory cells MC. It is possible to cut off the current path.

More specifically, when one of the bit lines BL and one of the gate lines GL are selected, one of the cache cells CC may be uniquely selected, but the vertical line VL may be metallic. When formed of a material, even if one of the cache cells CC is uniquely selected, the hidden parasitic paths may not be completely blocked. However, the vertical path control structure VPCS is connected to each of the cache cells CC and is disposed to face the semiconductor pattern used as the vertical line VL and the semiconductor pattern to control the potential of the semiconductor pattern. It can be configured to include a control electrode. In this case, generation of the above-described hidden parasitic current path may be blocked. In other words, when the vertical path control structure VPCS is used to connect with the cache memory array CMA, a parasitic current path therein without using a rectifying element in the main memory array MMA. You can block the creation of sneak paths. Since the rectifying element is omitted, a structure of the main memory array MMA and a method of manufacturing the same may be simplified, and a description of a matching or combination between the cache cells CC and the memory cells MC may be provided. Requirements can be relaxed.

FIG. 67 is a diagram schematically illustrating paths of a 3D memory device and an operating current according to some embodiments of the present disclosure. According to some embodiments, the memory cells MC may be configured to have a unidirectional current characteristic by including a rectifying element. In this case, the currents used for the CM-MM copy (S [WM]), the MM-CM copy (S [RM]), and the CM read (S [RC]) are as shown in FIG. It may have the same direction. On the other hand, the cache cells CC may be configured to have bidirectional current characteristics. In this case, the current path through the memory cells MC is difficult to use for initialization of the cache cells CC. However, as shown in FIG. 67, by forming a separate current path DL, this difficulty of initialization may be solved. In some embodiments, the separate current path DL may be implemented using one of the word lines WL.

On the other hand, when the cache cells CC do not have a bidirectional current characteristic or (ie, volatile) memory element having a short retention characteristic, it may not be necessary to form the separate current path. In addition, such a separate current path may be adaptively implemented based on the types of the cache cells CC and the memory cells MC and their combined characteristics, as shown in FIG. 67. It is not limited to. For example, gate electrodes of the switching transistors connected to the separate current path DL and the bit line BL may be independently controlled, unlike illustrated.

68 is a schematic perspective view illustrating a semiconductor memory device in accordance with some embodiments of the present invention. For example, the apparatus of FIG. 68 may include a plurality of blocks as shown, each of which may be provided in the form of the first basic structure of FIG. The blocks are connected in parallel to the bitline structure BLS connected to a bitline decoder and / or a sense amplifier BLD / SA, each main memory array MMA being an independent wordline decoder WLD. ) Can be connected.

According to modified embodiments of the present invention, the main memory array MMA may be configured to include two-dimensionally arranged memory cells MC. In this case, the cache memory array CMA may be provided between the main memory array MMA and a peripheral circuit in order to reduce disturbance and increase speed of the main memory array MMA.

69 and 70 are circuit diagrams showing some examples of three-dimensional semiconductor memory devices in which the main memory array MMA has the structure of type B of FIG. 2. Referring to FIG. 69, the cache lines CWL may be substantially parallel to the second horizontal lines HLy, and the bit lines BL may cross the cache lines CWL. Referring to FIG. 70, the bit lines BL may be substantially parallel to the second horizontal lines HLy, and the cache lines CWL may cross the bit lines BL. Large dotted lines represent each chapter, and small dotted lines represent each page.

71 and 72 are schematic circuit diagrams illustrating some of the modified embodiments of the present invention. As shown in FIGS. 71 and 72, in each of the cache memory arrays CMA, the cache cells CC may be provided in a multi-layer or multi-column structure. For example, as shown in FIG. 71, the cache cells CC may be three-dimensionally arranged, and at least two cache cells CC may be connected in series to each of the first horizontal lines HLx. . This means that the cache memory array CMA may include at least two chapters, and the cache memory array CMA may have a three-dimensional block structure. Alternatively, as shown in FIG. 72, at least two cache cells CC may be connected to each of the first horizontal lines HLx in parallel. This means that the cache memory array CMA has a two-dimensional block structure, but the cache memory array CMA may be configured to store at least two chapters.

As shown in FIG. 71 or 72, when a plurality of the cache cells CC are connected in series or in parallel to each of the first horizontal lines HLx, they may implement different functions or higher operating speeds. Can be used for For example, one of them may be used to perform the CM-MM copy or the MM-CM copy, and the other may temporarily change chapter data to be written to that chapter or another chapter during the CM-MM copy or the MM-CM copy. Can be used for storage. That is, the cache memory array CMA may be configured to hold a plurality of chapter data.

Alternatively, when the memory cells MC are memory elements capable of implementing a multilevel cell MLC, the plurality of cache cells CC connected to each of the first horizontal lines HLx may be the memory cells MC. Can be used to implement this multilevel characteristic.

According to other modified embodiments, each of the cache cells CC may be a memory element capable of implementing a multilevel characteristic, in which case the technical features described with reference to FIG. 71 or 72 (eg, , Various functions or improved operating speeds) may be implemented using such multi-level cache cells CC.

The technical features in the circuitry illustrated in FIGS. 71 and 72 may be implemented in physical terms by forming the cache memory array CMA as a single layer or a multi-layer structure. In addition, each of the structures shown in FIG. 4 may also be configured to implement the technical features or technical effects described with reference to FIGS. 71 and 72. Similarly, the cache memory array CMA of FIGS. 71 and 72 is shown to be parallel to the yz plane, but may be configured to be parallel to the xz or xy plane.

FIG. 73 illustrates an example of a memory semiconductor chip including the main memory array MMA and the cache memory array CMA. FIG. 74 illustrates the main memory array MMA and the cache memory array CMA. An example of a processor (eg, CPU or AP) is shown. That is, the semiconductor device according to example embodiments of the inventive concept may be configured to have structural features illustrated in FIGS. 73 and 74. According to some embodiments, in the processor chip of FIG. 74, the main and cache memory arrays MMA and CMA may be portions of one chip formed in a monolithic manner, each of which is L1 and L2. It can be used as caches or as L2 and L3 caches. 73 and 74 further comprise circuits (eg, a controller) configured to adaptively perform a cache algorithm or each of the steps of FIGS. 15-29 with respect to the cache memory array (CMA). can do.

As described above, the chapter is composed of data or cells arranged two-dimensionally on a predetermined plane. However, the plane may mean a plane in terms of data-hierarchical structure. This means that one chapter of the cache memory array CMA is not a concept limited to a particular one of the blocks. For example, as shown in FIG. 75, the cache memory array CMA may be configured as partial cache memory arrays PCMA distributed in each of a plurality of blocks.

According to some embodiments, the number of cache cells CC constituting each of the partial cache memory arrays PCMA (hereinafter, cache density) is determined by the main memory array MMA (eg, connected thereto). The number of memory cells MC (hereinafter, referred to as a storage density) constituting any one chapter of any one block may be substantially the same. According to other embodiments, the cache density may be greater than the reservoir density. For example, as in the embodiments described with reference to FIGS. 71 and 72, the cache density may be twice the reservoir density. According to still other embodiments, the cache density may be less than the reservoir density. For example, each of the partial cache memory arrays PCMA may be configured to store page data. For example, as shown in FIG. 76, the semiconductor device may include a plurality of main memory blocks having a VG-NAND structure and a plurality of partial cache memory arrays PCMA connected to each of the main memory blocks. have. The partial cache memory arrays PCMA may be controlled by the cache lines CWL across the bit lines BL, and the respective data storage size may be, for example, a page.

Although there are differences in levels that can be easily modified by those skilled in the art, the operating methods of the vertical channel NAND flash memory described with reference to FIGS. 39 to 46 are substantially the same for the example of the VG-NAND structure of FIG. 76. Can be. Therefore, for the sake of brevity of description, detailed description of these operating methods will be omitted. On the other hand, embodiments including the distributed partial cache memory arrays (PCMA) are not limited to the example of FIG. 76 (provided as an example for a better understanding of the present invention), based on the foregoing descriptions. It can be variously modified.

When the cache density is smaller than the storage density, each of the cache cells CC may be implemented using a memory element having a unit area larger than that of each of the memory cells MC. For example, the cache cells CC may be memory elements having a large area (such as SRAM or racetrack memory, etc.), and the memory cells MC may occupy a small amount (such as crosspoint memory or flash memory, etc.). May be memory elements having an area.

According to some modified embodiments, the main memory array MMA and the cache memory array CMA are each implemented on different chips and then electrically connected to each other (eg, through silicon through vias). Can be. For example, when the difference between the cache density and the storage density is large, as in the example of FIG. 76, since the size of the cache cells CC can be increased as described above, the difficulty in such an electrical connection is Can be mitigated.

According to some embodiments of the present disclosure, the cache memory array CMA may be disposed on the substrate SUB or above or below the main memory array MMA (eg, in a single integrated manner). ) May be an internal structure of the integrated chip. In this case, the cache memory array CMA may be distinguished from an external memory chip connected by using silicon-through vias or bonding wires having a size of several to several tens of micrometers. For example, the internal lines VL or HL connected to the cache cells CC may have a width of several nm to several tens of nm. Thus, except for the case where the cache density is smaller than the reservoir density, the above-described relationship between the cache density and the reservoir density is difficult to obtain from the silicon-through vias or bonding wires.

In addition, when viewed from the side of the plan view, the cache cells CC may include connection lines (for example, vertical lines VL) constituting the main memory array MMA in a cell array region. Can be electrically connected to the In other words, the cache cells CC may be electrically connected to the memory cells MC without passing through a peripheral circuit (such as a page buffer, a bit line decoder, or a sensing circuit). As such, in terms of the data path length from an external device (e.g., a CPU), the cache memory array CMA is internal to the peripheral circuit in that the cache memory array CMA is longer than the peripheral circuit. The internal lines VL or HL may be lines provided inside the semiconductor chip. In contrast, the silicon-via vias or bonding wires are used as interconnects connecting the I / O terminals of the stacked chips, which corresponds to the outer structure for the peripheral circuit of each of the stacked chips.

In addition, as exemplarily shown in FIGS. 2, 8 to 12, and 60 to 63, the inner lines VL or HL are formed so as not to completely penetrate the substrate SUB, and the length of the inner lines VL or HL may not be completely penetrated. May be smaller than the overall thickness of the substrate SUB or a chip including the same.

Nevertheless, semiconductor chips according to embodiments of the present invention should not be implemented without the application of silicon-through vias or wafer bonding techniques. For example, semiconductor chips including the cache memory array (CMA) according to embodiments of the present invention may be provided as part of a multi-chip package using the silicon-through vias.

[effect]

According to some embodiments of the present invention, the CM read (S [RC]), the CM write (S [WC]) and the CM initialization (S [IN]) are electrically connected to the main memory array (MMA). Can be performed without access. Accordingly, data stored in the memory cells MC are not disturbed by these steps. In addition, the CM-MM copy (S [WM]) and the MM-CM copy (S [RM]) access chapter-by-chapter once, without repetitive page-by-page access to the main memory array (MMA). It can be performed through. Accordingly, unnecessary access (ie, data disturbance) to the main memory array MMA may be reduced. As a result, the number of disturbance operations occurring during normal read and write operations for one block of the main memory array MMA is substantially equal to the number r of chapters constituting each block, as shown in FIG. May be the same. For the same reason, energy consumption in access to the main memory array MMA can be reduced.

In contrast, in the case of a conventional read and write operation performed without or without the cache memory array CMA, in order to process data of one chapter, the main memory array (at least as many as the number of pages constituting the chapter) is processed. Iterative approach to MMA) is required. In other words, in the prior art, the number of disturbance operations may be substantially equal to the product of the number r of chapters constituting each block and the number q of pages constituting each chapter, as shown in FIG. 77. Can be. However, these numbers are provided for a better understanding of the present invention, and in practice can be varied by additional operations (e.g., verify operations) to improve data reliability.

When each of the cache cells CC has a faster writing and / or reading speed than each of the memory cells MC, a time required to read or write the entire chapter data (hereinafter, chapter reading time and chapter writing time). ) Can be reduced compared to the prior art which does not use the cache memory array (CMA).

For example, in a conventional technique performed without the cache memory array CMA, the chapter read time may include a time T0 for reading page data from the memory cells MC once and the number of pages of each chapter ( q) (~ qx T0). In contrast, in the reading method of FIGS. 18 and 19, the chapter reading time may include: a) a time T0 ′ for reading chapter data once from the memory cells MC and b) page data for the cache cells ( CC) is equal to the sum of the time T1 spent reading from the product of the number of pages q of each chapter (ie, T0 '+ qx T1). Here, T0 'and T0 may be approximately equal, and thus, the chapter read time may be approximately T0 + q x T1.

In addition, compared with the reading method of FIGS. 18 and 19, the writing method of FIGS. 20 and 21 may have the same mathematical logic as that of the chapter read time, although there is a difference in operation order. Accordingly, the chapter writing time may be given as approximately T2 + qx T3 for the writing method of FIGS. 20 and 21, and qx T2 for the prior art (where T2 represents chapter data for the memory cells MC). Is a time required to write once, and T3 is a time required to write page data to the cache cells CC once).

Therefore, if the read rate T1 or write rate T3 for the cache cells CC is sufficiently smaller than those T0 and T2 of the memory cells MC, as shown in Figs. 78 and 79, respectively, the chapter reads Time and chapter writing time can be significantly reduced compared to the prior art. For example, Table 1 below shows an RRAM in which the memory cells MC have a read and write speed of approximately 25us and 200us, and the cache cells CC have a read and write speed of approximately 10ns and 10ns. Or, in case of STT-MRAM, it shows the time required for read and write operation for one chapter including 16 pages.

TABLE 1

Referring to Table 1, when the cache memory array (CMA) is included, the read and write times (25.16us and 200.16us) for one chapter are calculated as one read and write times (T0 (25.00) for the memory cell. us), little difference from T2 (200.00us)). Accordingly, when including the cache memory array (CMA), the read and write time for the chapter data can be as fast as the number of pages constituting one chapter (approximately 16 times in the case of Table 1) compared to the other case. have.

[Applications]

As illustrated in FIG. 80, an electronic product 1000 according to some embodiments of the present disclosure may include a memory device 1001 and an electronic component 1002 that operates independently or independently of the memory device 1001. Can be. The electronics 1000 may include electronic components (such as memory modules, SSDs, processors, controllers, or memory cards), personal electronic products (such as mobile devices, wearable devices, image recording / storage devices, laptops, or computers), And complex systems (such as data centers, server systems, clouding systems, medical devices, military devices, automobiles, ships, or broadcast equipment, etc.). The memory device 1001 may be provided in a form including at least one of the semiconductor devices according to the embodiments of the present invention described above. When the electronic product 1000 is provided in the form of an electronic component, the electronic component 1002 may be provided in the form of a capacitor, a resistor, a coil, a semiconductor chip (eg, a controller), and / or a wiring board. In the case of a personal electronic product, the electronic component 1002 may include an antenna, a display, a control device, user information input means (for example, a touch panel) and / or a power source, and, in the case of a system, The electronic component 1002 may include an input / output means, a housing and / or a power supply unit.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

Embodiments of the present invention can be used to implement a semiconductor device having a three-dimensional memory cell array.

Claims (12)

1. A main memory array comprising memory cells three-dimensionally arranged to store block data;

   A cache memory array including cache cells that are two-dimensionally arranged to store chapter data;

   A bitline structure including bitlines arranged one-dimensionally to transmit page data; And

   And a bitline decoder coupled to the cache memory array through the bitline structure.
2. The method according to claim 1,

   And the cache cells are implemented using memory elements different from the memory cells.
3. The method according to claim 1,

   And the cache cells are implemented using memory elements having a faster operating speed than the memory cells.
4. The method according to claim 1,

   And the cache memory array includes a plurality of cache lines that control the cache memory cells while crossing the bit lines.
5. The method according to claim 1,

   The main memory array includes a plurality of vertical lines arranged two-dimensionally to connect the memory cells,

   Each of the cache cells is connected to a corresponding one of the vertical lines.
6. The method according to claim 5,

   The memory cells are memory elements comprising a charge storage layer,

   And the cache cells are memory elements having a variable resistance characteristic.
7. The method according to claim 1,

   The main memory array comprising a plurality of blocks, each configured to store block data,

   The cache memory array includes a plurality of partial cache memory arrays provided corresponding to each of the blocks.
8. The method according to claim 7,

   Each of the partial cache memory arrays is configured to store one page or less of data.
9. The method according to claim 7,

   Each of the partial cache memory arrays is configured to store two pages or more data.
10. In the method of operating the semiconductor device of claim 1,

    The data exchange between the cache memory array and the bit line decoder is performed in units of one page or less,

    And exchanging data between the cache memory array and the main memory array in units of at least two pages.
11. The method according to claim 10,

    The write operation to the main memory array is

    At least once performing a cache write for writing external data input through the bit line decoder to the cache memory array in units of one page or less; And

    And performing a cache-main copy, which writes data stored in the cache memory array to the main memory array in units of at least two pages.
12. The method according to claim 10,

    The read operation on the main memory array is

    Performing a main-cache copy for writing data stored in the main memory array in the cache memory array in units of at least two pages; And

    And performing at least one cache read for transmitting the data written in the cache memory array to the bit line decoder in units of one page or less.

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