KR20120125217A - Memory Devices Having A Cache Memory Array, In Which Chapter Data Can Be Stored, And Methods Of Operating The Same - Google Patents

Abstract

PURPOSE: A memory device and an operation method thereof are provided to improve operation of 3D memory devices by including memory cells for enabling rewriting and to reduce the disturbance of reading and/or writing in the 3D memory devices. CONSTITUTION: A main memory array comprises memory cells. The memory cells are arranged in three dimensions. A cache memory array comprises memory cells(MC) arranged in two dimensions. A bit-line decoder(BLD) is connected to the cache memory array through a bit-line structure. The cache memory array is placed between a main memory array and the bit-line structure.

Description

Memory Devices Having A Cache Memory Array, In Which Chapter Data Can Be Stored, And Methods Of Operating The Same}

The present invention relates to a memory device capable of processing chapter data.

Various three-dimensional memory devices have been proposed, including memory cells that are three-dimensionally arranged and rewritable. For example, three-dimensional flash memory devices and three-dimensional cross-point memory devices such as BiCS, P-BiCS, TCAT, VGNAND and VSAT are actively studied.

The 3D memory devices may include a plurality of horizontal electrodes (eg, word lines of a 3D NAND flash device) that are sequentially stacked on a substrate. In order to avoid complexity in the connection structure, a plurality of the horizontal electrodes located at the same height are electrically connected to each other. As a result of this parallel connection scheme, three-dimensional memory devices are vulnerable to program and read disturb problems.

Some embodiments of the present invention provide three-dimensional memory devices capable of suppressing write and / or read disturb and methods of operation thereof.

Some embodiments of the present invention provide three-dimensional memory devices and methods of operating the same that can speed up write and / or read operations.

Three-dimensional semiconductor devices according to embodiments of the present invention include a cache memory array configured to store data of pages or more (eg, chapter data).

The use of the cache memory array can effectively reduce write and / or read disturb in three-dimensional memory devices, as well as speed up write and / or read operations.

1 is a schematic cross-sectional view showing a cell array structure of three-dimensional memory devices.
2 and 3 are perspective views illustrating two different structures of the main memory array of the three-dimensional memory device to which the present invention can be applied.
4 is a table illustratively showing some of the possible embodiments of a cell array structure of a three-dimensional memory device, to which the present invention may be applied.
5 through 8 are cross-sectional views schematically illustrating cell array structures in accordance with some of the embodiments listed in FIG. 4.
9 and 10 are schematic views showing examples of the structures shown in FIGS. 5 and 8.
FIG. 11 is a diagram illustrating a hierarchical structure of a main memory array of a 3D memory device to which the present invention can be applied.
12 is a view provided to schematically explain one aspect of the operation according to the embodiments of the present invention.
FIG. 13 is a diagram exemplarily illustrating operations performed in a 3D memory device according to some embodiments of the inventive concept.
14 and 15 are flowcharts and schematic diagrams schematically illustrating an example of a read operation according to some embodiments of the present invention, respectively.
16 and 17 are flowcharts and schematic diagrams schematically illustrating an example of a write operation according to some embodiments of the present invention, respectively.
18 is a schematic diagram schematically showing an example of a read or write operation according to other embodiments of the present invention.
19 is a graph comparing embodiments of the present invention and operating methods according to the related art in terms of the number of disturbances.
20 and 21 are graphs comparing the time required between read and write operations according to the embodiments of the present invention and the prior art.
22 through 28 are diagrams exemplarily showing some of the memory elements that can be used for the cache memory array.
29 is a perspective view illustrating a semiconductor device according to an embodiment of the present invention.
30 to 40 are diagrams for describing an operation of the semiconductor device of FIG. 29.
41 and 42 are a perspective view and a plan view showing a semiconductor device according to another embodiment of the present invention.
43 to 48 are diagrams for describing an operation of a semiconductor device according to example embodiments of the present inventive concepts.
49 is a diagram illustrating a semiconductor device and a part of an operation thereof according to example embodiments of the inventive concepts.
50 and 51 are tables exemplarily illustrating paths of electrical signals for implementing some operations of a 3D memory device according to some embodiments of the inventive concept.
52 to 54 are views illustrating some operations of a 3D memory device according to some embodiments of the present invention.
55 is a circuit diagram schematically illustrating a cache array structure of a 3D memory device according to another embodiment of the present invention.
56 is a diagram schematically illustrating paths of a 3D memory device and an operating current according to some embodiments of the present invention.
57 and 58 exemplarily illustrate embodiments of the present invention applied to an aspect or a two-dimensional memory device of some embodiments of the present invention.
59 is a schematic diagram illustrating an electronic product including a memory device according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more readily apparent from the following description of preferred embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the present specification, when it is mentioned that a film (or layer) is on another film (or layer) or substrate, it may be formed directly on another film (or layer) or substrate or a third film between them. In addition, the size and thickness of the components of the drawings are exaggerated for clarity. Also, in various embodiments herein, the terms first, second, third, etc. are used to describe various regions, films (or layers), etc., but these regions, films are defined by these terms. It should not be. These terms are only used to distinguish any given region or film (or layer) from other regions or films (or layers). Therefore, the film quality referred to as the first film quality in one embodiment may be referred to as the second film quality in other embodiments. Each embodiment described and illustrated herein also includes its complementary embodiment. The expression 'and / or' is used herein to mean at least one of the components listed before and after. Like numbers refer to like elements throughout the specification.

The technical terms referred to herein may be used as the following meanings. The bit line refers to a wiring used to transmit information (ie, an electrical signal) stored in the memory cell to the sensing circuit or a conductive line used to transmit external data to the memory cell. The word line refers to a conductive line used to select some of a plurality of memory cells connected to one bit line.

The memory cell may mean a region including a material or a thin film structure capable of charge storage and a material or a thin film structure (eg, PCM, MTJ,) exhibiting variable resistance characteristics. However, the present invention is not limited to a particular type of memory cell. For example, depending on the nature of the memory cell used, embodiments of the invention may be subdivided and diversified.

Adjacent memory cells may be provided in the form of localized patterns spatially separated from each other or as a structure including at least a portion connected to each other.

The wiring or the wire may refer to a conductive pattern formed of a material having a low specific resistance. For example, they may be metals or high concentrations of semiconductor materials (but not limited to these). Organic materials or carbon nanostructures such as nanotubes or graphene may be used to implement the wirings or wires.

1 shows a general cell array structure of three-dimensional memory devices, including a main memory array MMA, a wiring structure UWS, and an external horizontal structure EHL provided on a substrate SUB. The main memory array MMA may include three-dimensionally arranged memory cells and cell wires connecting the memory cells.

For example, as shown in FIG. 2, the main memory array MMA includes (1) vertical lines arranged on the substrate SUB while forming (i.e., two-dimensionally) a multi-line and multi-row structure. VL), (2) a plurality of horizontal lines HL crossing the vertical lines VL while forming a multi-layer and multi-row structure, and (3) of the vertical and horizontal lines VL, HL, 3 It may include memory cells MC provided at intersections, which are arranged dimensionally. Alternatively, as shown in FIG. 3, the main memory array MMA includes (1) first horizontal lines HLx forming a multilayer and multi-row structure, and (2) second horizontal lines forming a multi-layer and glad structure. And HLy, and (3) the memory cells MC provided at their intersections.

Each of the vertical and horizontal lines VL and HL may be electrically connected to a peripheral circuit via each or both of the wiring structure UWS and the external horizontal structure EHL. For example, the wiring structure UWS may be used as the bit lines BL, and the external horizontal structure EHL may be used as the (global) word lines WL. However, the connection structure may be variously modified according to the type of memory device, and embodiments of the present invention are not limited to one specific connection structure.

According to embodiments of the present invention, the 3D memory device may include a cache memory array CMA as shown in FIGS. 4 to 10. The cache memory array CMA may be located on a cell array region. This means that the cache memory array CMA is, for example, at least with peripheral circuits (eg, bit line decoders BLD and sensing circuits SA) connected to at least the main memory array MMA and bit lines. It means placed between. In addition, this means that the cache memory array CMA is a storage space that is disposed in a peripheral circuit area and is distinct from a storage space (for example, a page buffer) that stores data transferred from or to the bit lines. .

According to some embodiments, as shown in FIG. 5 or 9, the cache memory array CMA may be located between the main memory array MMA and the bit line structure BLS. According to other embodiments, the bit line structure BLS may be located between the main memory array MMA and the cache memory array CMA. have. (Hereinafter, this structure will be referred to as a second basic structure.) In addition, the three-dimensional memory device may include at least one selection structure (SLS), according to the position of the selection structure (SLS), Each of the first and second basic structures may be variously modified as shown in FIG. 4. For example, the first basic structure illustrated in FIG. 5 may include the selection structure SLS positioned between the cache memory array CMA and the main memory array MMA, as illustrated in FIGS. 8 and 10. It may be modified to include.

The selection structure SLS may include, for example, (1) connection lines constituting the main memory array MMA (for example, the vertical or horizontal lines VL or HL or the first or first). Two horizontal lines HLx or HLy) or (2) one or some of the conductive lines constituting the cache memory array CMA. Technical features related to the selection structure SLS will be described in more detail later with reference to FIGS. 21 through 32.

On the other hand, the bit line structure (BLS), as shown in Figure 5 to 7 in order, the upper wiring structure (UWS), the lower wiring structure (LWS) disposed on the upper, lower or side surfaces of the main memory array (MMA) Or an external horizontal structure (EHL). The first basic structure is classified by the above-described arrangement or arrangement order between the main memory array MMA, the cache memory array CMA, and the bit line structure BLS, and the substrate SUB. The relative arrangement with respect to means that it can be varied or freely modified. For example, the first basic structure may be embodied as inverted forms as shown in FIGS. 5 and 6, or may be embodied as rotated 90 degrees clockwise or counterclockwise as illustrated in FIG. 7. Each of the structures classified in FIG. 4 may also be implemented with the above-described variety or freedom in relative arrangement with respect to the substrate SUB.

The bit line structure BLS may include a plurality of bit lines electrically connecting the connection lines constituting the main memory array MMA. For example, when the main memory array MMA is provided as the structure of FIG. 2, as shown in FIGS. 9 and 10, each of the bit lines is electrically connected to each of the columns of the vertical lines VL. Can be connected. Although not shown, when the main memory array MMA is provided as the structure of FIG. 3, each of the bit lines may correspond to a corresponding one of the columns or layers of the first or second horizontal lines HLx or HLy. Can be electrically connected.

FIG. 11 is a diagram exemplarily illustrating a hierarchy structure of a main memory array of a 3D memory device to which the present invention can be applied. Referring to FIG. 11, the main memory array MMA may include at least one block, and the block may include a plurality of (eg, r) chapters, each of which may include: A plurality of (eg, q) pages may be included, and each of the pages may include a plurality of (eg, p) cells.

The block may be a unit of data (eg, a maximum) of data or cells in which an operation may be performed independently. For example, according to some embodiments of the invention applicable to NAND flash memory, a block can be used as a unit of data that can be erased at one time.

The chapter may refer to data or cells included in one plane of the main memory array (MMA) or the block. In other words, the chapter is composed of data or cells arranged two-dimensionally on a predetermined plane. Here, a plane means a plane in terms of a data-layer structural aspect or a physical arrangement of cells, and the direction of the plane is based on the arrangement of the bitlines and the wordlines and the manner of operation performed using them. Can be selected. For example, in the case of a vertical-channel three-dimensional NAND flash memory known as a BiCS structure (coplanar word lines are electrically connected and used as a common gate electrode of two-dimensionally arranged memory cells), one chapter is described. May be composed of the two-dimensionally arranged memory cells (controlled by the common gate electrode) or data stored therein.

The page refers to a data unit that can be read out at one time through the bit line structure BLS (or UWS, LWS, EHL). As described above, since each bit line is electrically connected to a plurality of connection lines constituting the main memory array MMA, two-dimensional data constituting the chapter or three-dimensional data constituting the block It is difficult to input or output at one time through the bit line structure BLS. Accordingly, as shown in FIG. 12, two-dimensional data constituting one chapter or three-dimensional data constituting one block is divided into groups of one-dimensional data, and then, through the bit lines. Input or output sequentially. The page may correspond to one group of the one-dimensional data.

The cell refers to an information storage space provided at each intersection between the vertical lines VL and the internal horizontal lines IHL or between the first and second horizontal lines HLx and HLy. In embodiments of the present invention, the cell may be configured to store single or multi bits.

The cache memory array CMA may also be configured to have the above-described hierarchical structure including chapters, pages, and cells. In addition, according to some embodiments, the cache memory array CMA may include at least two chapters, and in this case, the cache memory array CMA may also have a block structure. The main memory array MMA and the cache memory array CMA may be configured to include at least two blocks. This means that the cache memory array CMA includes memory cells configured to store at least two pages of data (hereinafter, cache cells CC).

According to another embodiment of the present invention, a three-dimensional semiconductor device may include a chapter or a page divided into a plurality of sections (for example, based on a pair / hole division or a left / right division). It can be configured to operate each of the sections independently. Although, for the sake of brevity of description, the description of possible embodiments of the present invention that can be applied to such separate sections will be minimized, the method of section separation may be variously modified in view of the efficiency of read or write operations. Can be. Thus, known techniques based on such section separation (eg, applied to two-dimensional memory semiconductors) can be used or applied to implement the technical idea of the present invention, and such use or application is an embodiment of the present invention. Included as part of the

According to some embodiments of the present invention, as shown in FIG. 13, the operation of the 3D memory device may transfer information stored in the main memory array MMA to a peripheral circuit (for example, a page buffer or a sensing circuit). The read operation may include a read operation and a write operation of storing external data provided through the peripheral circuit in the main memory array MMA. According to some embodiments, the read operation includes MM-CM copy (S [RM]) and CM read (S [RC]) steps, and the write operation includes CM write ([S [WC]]) and It may include the steps of CM-MM copy (S [WM]). For simplicity of explanation, below, read and write operations for data in one chapter will be described by way of example. That is, the plurality of chapter data can be processed by repeating the operation described below.

As illustrated in FIG. 14, the MM-CM copy S [RM] refers to a process of copying data stored in the main memory array MMA to the cache memory array CMA. The MM-CM copy S [RM] may be performed to copy chapter-based data into the cache memory array CMA at a time, as shown in the left side of FIG. 15. According to modified embodiments, the MM-CM copy S [RM] may include a plurality of substeps, each of which is implemented to copy data of two pages or more.

As shown in FIG. 14, the CM read S [RC] uses the bit line structure BLS to store data of the cache memory array CMA in a peripheral circuit (eg, a sensing circuit or a page buffer). Means the process of transmission. The CM read (S [RC]) may include a plurality of cache page read steps, each of which is implemented to transmit page unit data to the peripheral circuit, as shown on the right side of FIG. 15. According to modified embodiments, the CM read S [RC] may comprise a plurality of substeps, each of which is implemented to transmit data of a size smaller than a page. For example, each of the substeps of the CM read S [RC] may be implemented to process one or more cell data.

As illustrated in FIG. 16, the CM write ([S [WC]]) refers to a process of writing external data to the cache memory array CMA using the bit line structure BLS. The CM write ([S [WC]]), as shown on the left side of FIG. 17, each performs a plurality of cache page write steps, each of which is performed to write page-by-page data to the cache memory array CMA. It may include. According to modified embodiments, the CM write ([S [WC]]) may comprise a plurality of substeps, each of which is implemented to transmit data of a size smaller than a page. For example, each of the substeps of the CM write ([S [WC]]) may be implemented to process bit, byte or more cell data.

In some embodiments, data may be read from or written to the cache memory array CMA in a random access manner. For example, the CM read (S [RC]) and the CM write ([S [WC]]) may be implemented to process bit, byte, or more cell data, as described above. In this case, the cache memory array CMA may be used as any one of those generally called L3, L2 or L1 cache memory. For example, the cache memory array (CMA) may be configured to implement the functionality of the currently used DRAM. According to some embodiments, the peripheral circuit may be configured to enable implementation of such a random access scheme. For example, the peripheral circuit may include a circuit used in DRAM, SRAM or NOR flash memory devices.

The CM-MM copy S [WM] refers to a process of copying data stored in the cache memory array CMA to the main memory array MMA. The CM-MM copy S [WM] is configured to copy chapter-based data stored in the cache memory array CMA to predetermined chapters of the main memory array MMA at one time, as shown in the right side of FIG. 17. Can be implemented. According to modified embodiments, the CM-MM copy S [WM] may include a plurality of substeps, each of which is implemented to copy data in units of two pages or more.

According to modified embodiments of the present invention, the write operation and the read operation may be performed by MM direct write (S [WMd]) and MM direct read (S [RMd]) not using the cache memory array (CMA). It can be done in a manner.

The MM direct write (S [WMd]) refers to a process of directly writing external data provided through the peripheral circuit to the main memory array MMA. For example, the MM direct write S [WMd] may be a data transfer process performed without an interruption step of storing data in the cache memory array CMA. According to some embodiments, the MM direct write (S [WMd]), as shown in FIG. 18, is implemented such that each writes data in page units directly into a predetermined chapter of the main memory array MMA. Although the method may include a plurality of lower direct write steps, each of the lower direct write steps may be implemented to process one or more cell data. Alternatively, the MM direct write (S [WMd]) may be implemented to process chapter or more data. One such example of the MM direct write (S [WMd]) may be an erase step of a flash memory that directly changes block data at once.

The MM direct read S [RMd] refers to a process of transferring data of the main memory array MMA to the peripheral circuit without an interruption step of storing data in the cache memory array CMA. The MM direct read (S [RMd]) may include a plurality of lower direct read steps, each of which may be implemented to transmit page-by-page data to the peripheral circuit, as shown in FIG. Each of the direct read steps may be implemented to process one or more cell data.

According to other modified embodiments of the present invention, the read operation is in addition to the MM-CM copy (S [RM]) and CM read (S [RC]) steps of FIGS. 14 and 15, FIG. 18. The method may further include reading the MM direct reading (S [RMd]). Further, the write operation may be performed in addition to the CM write ([S [WC]]) and the CM-MM copy (S [WM]) steps of FIGS. 16 and 17, and the MM direct write (S [ WMd]) may be further included.

According to some embodiments of the present disclosure, as illustrated in FIG. 13, an operation of the 3D memory device may initialize (eg, initialize) all or part of the cache memory array CMA or the cache cells CC. CM initialization ([S [IN]]) step may be further included. For example, the data change of the cache cell CC is not only an external factor (for example, an external or electrical signal transmitted from the memory cell array MMA) but also an internal factor (for example, the cache cell ( CC) together with its own data state), the CM initialization ([S [IN]]) step eliminates the inhomogeneity associated with the internal factors within the cache memory array (CMA). It may be necessary. In other words, when the cache cells CC are not initialized, some of the data stored in the cache cells CC may not be changed. In this case, for example, the CM write ([S [WC]]) and only some of the data from the memory cell array MMA externally or during the MM-CM copy S [RM] may be written to the cache cells CC (ie with errors). Can be.

Nevertheless, if the data change of the cache cell CC has a small or negligible dependency on the internal factor, in some embodiments, the CM initialization ([S [IN]]) step may be omitted. More specifically, this omission is determined by the data storage principle of the cache cells CC or the type of electrical signal including the information stored in the memory cells MC, the determination of which is illustrated in the examples below. Based on the knowledge level of one skilled in the art.

As described above, the cache memory array CMA is configured to include a plurality of the cache cells CC capable of storing data of at least two pages. For example, the cache memory array CMA may be configured to store data corresponding to one chapter of the main memory array MMA.

According to some embodiments of the present invention, the cache cells CC may be memory cells based on a data storage principle different from that of the memory cells MC. However, according to other embodiments, the cache cells CC and the memory cells MC may be memory cells of the same type or memory cells based on the same or similar operating principle.

According to some embodiments of the present disclosure, each of the cache cells CC may be configured to have a faster write and / or read speed than each of the memory cells MC. For example, if the memory cells MC are charge storage elements (such as a film or floating gate rich in charge trap sites), the cache cells CC (such as PCM, MTJ, ReRAM materials, etc.), FIG. 22. As shown in FIG. 2, the film may be configured to include a material or a film structure exhibiting variable resistance characteristics. However, the embodiments of the present invention are not limited thereto. For example, based on consideration of other technical characteristics such as manufacturing process, data retention characteristics and ease of current path formation, such conditions may be relaxed or changed.

In some embodiments, each of the cache cell CC and the memory cell MC is, for example, DRAM, FRAM, NAND FLASH, MRAM, STT-MRAM, PCRAM, NRAM, RRAM, CBRAM, SEM, T -May be selected from a group of memory elements known as RAM, Z-RAM, Polymer, Molecular, Racetrack, Holographic, Probe and the like.

According to embodiments of the present invention, the CM-MM copy (S [WM]) and CM read (S [RC]) steps may comprise conductive lines (eg, the vertical) of the main memory array (MMA). It is embodied so that lines VL or the horizontal lines IHL do not experience a substantial change in the applied voltage. This means that data stored in the memory cells MC may not be disturbed by voltages applied for the CM-MM copy S [WM] and CM read S [RC] steps. Disturbance to the memory cells MC includes applying a voltage to the conductive lines of the main memory array MMA, the MM-CM copy (S [RM]) and the CM write ([S [ WC]]) takes place during that time. As a result, the number of disturbance operations occurring during normal read and write operations for one block may be substantially equal to the number r of chapters constituting each block, as shown in FIG. 19.

In contrast, in the case of the conventional read and write operations that do not use the cache memory array (CMA), in order to process data of one chapter, the main memory array (MMA) of the main memory array (MMA) is used for the number or time of pages constituting the chapter. There is a need for applying an operating voltage to the conductive lines. In other words, in the prior art, the number of disturbance operations may be substantially equal to the product of the number r of chapters constituting each block and the number q of pages constituting each chapter, as shown in FIG. 19. Can be. However, these numbers are provided for a better understanding of the present invention, and in practice may be varied by additional operations for improving data reliability.

On the other hand, as described above, when each of the cache cells (CC) is configured to have a faster write and / or read speed than each of the memory cells (MC), the time required to read or write the entire chapter data (hereinafter referred to as , Chapter read time and chapter write time) can be reduced compared to the prior art which does not use the cache memory array (CMA).

For example, in the related art, the chapter read time is a product of a time T0 for reading once from the memory cells MC and the number of pages q of each chapter (~ q x T0). In contrast, in the reading method of FIGS. 14 and 15, the chapter reading time may include: a) a time T0 ′ for reading chapter data once from the memory cells MC and b) page data for the cache cells ( It is equal to the sum of the time T1 spent reading from CC) and the product of the number of pages q of each chapter (i.e., T0 + qx T1). Here, T0 'and T0 may be substantially the same, and in this case, the chapter read time may be approximately T0 + q x T1.

In addition, compared with the reading methods of FIGS. 14 and 15, the writing methods of FIGS. 16 and 17 may have the same mathematical logic as in the chapter reading time, although there is a difference in operation order. Accordingly, the chapter writing time may be given as approximately T2 + q x T3 for the writing method of FIGS. 16 and 17 and q x T2 for the prior art. (T2 is a time required to write chapter data to the memory cells MC once, and T3 is a time required to write page data to the cache cells CC once.)

Therefore, if the read rate T1 or write rate T3 for the cache cells CC is sufficiently smaller than those T0 and T2 of the memory cells MC, as shown in Figs. 20 and 21, respectively, the chapter reads Time and chapter writing time can be significantly reduced compared to the prior art. For example, in the table below, the memory cells MC are flash memory cells having read and write speeds of approximately 25us and 200us, and the cache cells CC have read and write speeds of approximately 10ns and 10ns. In case of STT-MRAM, it shows the time required for read and write operation for one chapter including 16 pages.

[Table 1]

Referring to Table 1, when the cache memory array CMA is included, a read and write time for one chapter is hardly different from a single read and write operation for the memory cell. Accordingly, when including the cache memory array (CMA), the read and write time for chapter data can be approximately 16 times faster (that is, the number of pages constituting one chapter) than otherwise.

In embodiments of the present invention, the cache memory array CMA or the cache cell CC may include at least one of known memory elements (e.g., an International Technology Roadmap for Semiconductor (ITRS) and a list of references thereof). And at least one of the memory elements, as disclosed in the constituent documents. 22-28 exemplarily illustrate some of such memory elements, which are provided for a better understanding of the present invention. The type of memory element for the cache memory array CMA may include a principle of operation of the memory cells MC, characteristics of an electrical signal for operation (for example, unidirectional or bidirectional, voltage application or current application, and current). Amount, speed, etc.) or various technical requirements for the cache memory array (CMA) itself (e.g., operability as RAM or buffer memory), and the like. Those skilled in the art will be able to find the case of an optimized or preferred combination of the cache memory array (CMA) and the memory memory array (MMA) based on the content discussed herein, and so below, these possible combinations for the sake of brevity of description. Some of these will be described by way of example. However, the technical idea of the present invention is not limited to these examples.

29 is a perspective view illustrating a semiconductor device according to an embodiment of the present invention, and FIGS. 30 to 40 are diagrams for describing an operation of the semiconductor device of FIG. 29. More specifically, referring to FIG. 29, the main memory array MMA is configured to have a structure (eg, BiCS or TCAT) of a vertical channel 3D NAND flash, and the cache memory array CMA is configured as the main memory array. It may be configured to include the cache cells (CC) two-dimensionally arranged on the memory array (MMA). Here, an embodiment in which the cache cells CC are implemented using a high-speed resistive memory element (eg, STT-MTJ) operating using bidirectional current will be described.

The cache cells CC may be interposed between the bit line BL and the vertical line VL, and the vertical line VL is a semiconductor pattern perpendicular to the upper surface of the substrate SUB (ie, silicon). And a charge storage layer (eg, ONO). The semiconductor pattern of the vertical line VL may include n-type impurity regions used as source and drain electrodes, and a vertical or intrinsic vertical channel region interposed therebetween.

The horizontal lines IHL may include metal or doped silicon. According to some embodiments, as shown in FIG. 29, a plurality of cache lines CWL or DL may be interposed between the cache cells CC and the horizontal lines IHL. Each of the cache lines CWL may connect the n-type impurity regions used as the drain electrode while crossing the bit lines. The cache lines CWL may be formed of a material (for example, a p-type semiconductor) constituting the n-type impurity regions and a rectifying device.

Due to the presence of the cache lines CWL, the vertical channel region is the CM for the CM read S [RC] as shown in FIGS. 32 and 33, as shown in FIGS. 34 and 35. It may not be used as an electrical path for writing ([S [WC]]) and for the CM initialization ([S [IN]]) as shown in FIG. This makes it possible to reduce the problem of read and write disturbances applied to the main memory array (MMA).

During the MM-CM copy S [RM], as shown in FIG. 31, an operating voltage is applied to any one of the plurality of bit lines 1 and the horizontal lines IHL (hereinafter, selected word line). do. In this case, the current path of FIG. 30 may be selectively generated depending on data stored in two-dimensional memory cells () controlled by the selection word line. When the current path of FIG. 30 is generated, data of the corresponding cache cell CC may be changed (for example, in a high resistance state or an off state).

During the CM read S [RC], different operating voltages V1 and V2 are applied to one of the bit lines BL and the cache lines CWL, respectively, as shown in FIG. 33. Can be. In this case, depending on the applied voltage condition, the current path shown in FIG. 32 or in the opposite direction may be selectively generated depending on the data stored in the cache cell CC. In some embodiments, the sense amplifier can be configured to detect a change in bit line potential caused by the generation of such a current path. As shown, the CM read (S [RC]) may be performed in units of pages (or less).

During the CM write ([S [WC]]), as shown in FIG. 35, operating voltages may be applied to any one of the plurality of bit lines BL and the cache lines CWL. In this case, input data may be transferred through the bit lines BL. For example, the voltage (eg, V1) applied to a part of the bit lines BL may be different from the voltages (eg, V2) applied to another part of the bit lines BL. In addition, a voltage substantially equal to any one of the bit line voltages may be applied to any one of the cache lines CWL. In other words, the write current for the cache cell CC may be selectively generated by the potential difference between the bit line BL and the cache line CWL to which it is connected. As illustrated in FIG. 35, the CM write ([S [WC]]) may be performed in page units (or less).

During the CM-MM copy S [WM], as shown in FIG. 37, a bit line voltage V_BL is applied to the bit lines BL, and any one of the horizontal lines IHL (hereinafter, referred to as “B”) is applied to the bit lines BL. , A program voltage is applied to the selected word line. In this case, the current path of FIG. 36 may be selectively generated depending on data stored in each of the cache cells CC constituting the cache memory array CMA. For example, when the cache cell CC is in an on state, the corresponding channel region may have a potential substantially equal to that of the bit line (eg, 0V). In this case, when the voltage applied to the selected word line is high, programming through F-N tunneling is possible. On the other hand, when the cache cell CC is in an off state, the corresponding channel region is electrically isolated, and has a potential raised by voltages applied to the horizontal lines IHL, and thus a potential difference from the program voltage. Can be reduced. That is, program prevention through self-boosting technology may be enabled.

On the other hand, when the self-boosting using the cache cell (CC), although shown in the drawing, the need for the string select lines SSL in the prior art can be reduced. For example, even when the string select lines SSL are applied with substantially the same voltage as the word lines A adjacent thereto, the above-described operations may be effectively performed. However, this may not necessarily require the removal of the string select lines SSL.

In addition, if the cache cells CC do not have a sufficiently high resistance even when in the off state, it may be difficult to implement the above self-boosting. In this case, as illustrated in FIG. 38, the main memory array may be programmed (for example, in page units) through the MM direct write operation S [WMd].

39 and 40 exemplarily show two possible methods for the CM initialization ([S [IN]]). In the case of FIG. 39, the CM initialization ([S [IN]]) may be performed without disturbing the main memory array in units of chapters. However, as shown in FIG. 40, the CM initialization ([S [IN]]) may be performed in units of chapters or pages by using a current path through the channel region.

41 and 42 are perspective and plan views illustrating a semiconductor device according to another embodiment of the present invention, and FIGS. 43 to 47 are views for explaining an operation of the semiconductor device according to another embodiment of the present invention. More specifically, according to this embodiment, the cache memory array CMA may be configured to include cache cells CC that are two-dimensionally arranged below the main memory array MMA. Here, an embodiment in which the memory cells MC are memory elements having bidirectional current characteristics will be described as an example. Since implementing a unidirectional current path is easier than in the case of bidirectional current, embodiments using memory elements using unidirectional current as the main memory array CMA will be described briefly below.

According to these embodiments, the cache cells () shown in FIGS. 41 to 47 may be configured to include the zero-capacitor RAM described with reference to FIGS. 25 and 26. Between the cache line SWL or DL and each of the cache cells 1, by a second gate line GL2, to generate a current path that does not cause disturbance to the main memory array MMA. A controlled selector (ST) may be provided. The vertical line () may be connected to a node between the selector (ST) and the cache cell (CC). The cache cells CC may be connected to the first gate line GL1 that crosses the bit lines.

41 and 42 exemplarily illustrate that a current path for various operations described above may be generated in a unit cell of the cache memory array CMA, but embodiments of the present invention are not limited thereto. . For example, although FIG. 41 shows a planar transistor using an SOI substrate including an buried oxide film, this planar transistor can be replaced with a vertical channel transistor as shown in FIG.

43 to 47 may be circuit diagrams corresponding to the semiconductor devices illustrated in FIGS. 41 and 42. 43 exemplarily shows that the CM write ([S [WC]]) can be implemented using the illustrated circuit structure. 44 exemplarily shows that the CM-MM copy S [WM] can be implemented using the circuit structure shown. 45 exemplarily shows that the MM-CM copy (S [RM]) can be implemented using the circuit structure shown. 46 exemplarily shows that the CM read S [RC] can be implemented using the circuit structure shown. 48 exemplarily shows that the CM initialization S [IN] can be implemented using the illustrated circuit structure. FIG. 48 shows that the second gate lines A may be connected to each other to be used as a common gate electrode of adjacent ones of the cache cells A. FIG. However, embodiments of the present invention are not limited thereto.

49 is a diagram illustrating a semiconductor device and a part of an operation thereof according to example embodiments of the inventive concepts. According to this embodiment, each of the vertical lines may be configured to include a vertical path control structure (VPCS). Technical features related to the vertical path control structure (VPCS) are disclosed in PCT Publication No. WO 2010/018888 (2010.02.18) and US Application No. 13 / 059,059, the contents of which are fully incorporated as part of the present invention. . The use of the vertical path control structure VPCS allows parasitic currents between the three-dimensionally arranged memory cells MC, even when no rectifying element (eg, diode) is placed in each of the memory cells. Makes it possible to block a sneak path. For example, when one of the bit lines BL and one of the gate lines GL are selected, one of the cache cells CC may be uniquely selected. However, when the vertical line is formed of a metallic material, even if one of the cache cells CC is uniquely selected, the hidden parasitic paths may not be completely blocked.

When using the vertical path control structure (VPCS), the vertical line () may be configured to include a semiconductor pattern connected to each of the cache cells (CC) and a vertical control electrode for controlling the potential of the semiconductor pattern. In this case, generation of the above-described hidden parasitic current path may be blocked. In other words, when the vertical path control structure VPCS is used to connect to the cache memory array, the parasitic current path may be blocked without using a rectifying element. Thus, the semiconductor device can be manufactured more easily. In addition, a more relaxed condition may be required for the combination between the cache cells and the memory cells.

50 and 51 are tables exemplarily illustrating paths of electrical signals for implementing some operations of a 3D memory device according to some embodiments of the inventive concept.

52 to 54 are views illustrating some operations of a 3D memory device according to some embodiments of the present invention.

55 is a circuit diagram schematically illustrating a cache array structure of a 3D memory device according to another embodiment of the present invention.

56 is a diagram schematically illustrating paths of a 3D memory device and an operating current according to some embodiments of the present invention.

57 and 58 exemplarily illustrate embodiments of the present invention applied to an aspect or a two-dimensional memory device of some embodiments of the present invention.

According to some embodiments of the present invention, the cache memory array CMA is a structure integrated on top of the substrate SUB or on top or bottom of the main memory array MMA in a monolithic manner. Can be. In this case, the cache memory array (CMA) can be distinguished from structures formed using techniques such as silicon-through vias or wafer bonding. For example, in the case of the cache memory array CMA according to this embodiment, the number of the cache cells CC constituting it is equal to the number of memory cells MC of any one chapter located below it. Or at least greater than 1/4. In addition, in terms of a plan view, the cache cells CC may be connected to the main memory array MMA in a cell array region (eg, within a boundary of the cache memory array CMA). Can be electrically connected to the However, reference to the monolithic approach described above does not mean that memory devices according to embodiments of the present invention exclude the application of silicon-through vias or wafer bonding techniques. For example, memory devices may be provided as a multi-chip package structure including a plurality of chips, wherein at least one of the chips is configured to include the cache memory array (CMA) formed in a monolithic manner. Can be.

[Applications]

As illustrated in FIG. 59, an electronic product 1000 according to some embodiments of the present disclosure may include a memory device 1001 and an electronic component 1002 that operates organically or independently from the memory device 1001. Can be. The electronics 1000 may include electronic components (such as memory modules, SSDs, memory cards), personal electronics (such as mobile phones, laptops, computers), and systems (such as data centers, server systems, and clouding systems). It may be provided in the form. The memory device 1001 may be provided in a form including at least one of the memory devices according to the above-described embodiments of the present invention. When the electronic product 1000 is provided in the form of an electronic component, the electronic component 1002 may be provided in the form of a capacitor, a resistor, a coil, a semiconductor chip (eg, a controller), and a wiring board. In the case of a personal product, the electronic component 1002 may include an antenna, a display, a control device, a user information input means (for example, a touch panel), a power supply, and the like. In the case of a system, the electronic component 1002 ) May include an input / output means, a housing, a power supply, and the like.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

Claims (1)

A main memory array including three-dimensionally arranged memory cells;
A cache memory array including two-dimensionally arranged memory cells; And
And a bitline decoder coupled to the cache memory array through a bitline structure.

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