KR20140101705A - Three-Dimensional Semiconductor Devices Having A Cache Memory Array, In Which Chapter Data Can Be Stored, And Methods Of Operating The Same - Google Patents

Abstract

Provided are three-dimensional semiconductor devices having a cache memory array. The cache memory array may be configured to save at least page-unit data. Writing and/or reading actions using the cache memory array can be performed to effectively reduce data disturbance against a main memory array, and enables increased speed of action.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-dimensional semiconductor device having a cache memory array in which chapter data can be stored, and a method of operating the same.

The present invention relates to a three-dimensional semiconductor device having a two-dimensional cache memory array provided between a three-dimensional main memory array and a one-dimensional page buffer.

A variety of three-dimensional memory devices have been proposed, including three-dimensionally arranged rewritable memory cells. For example, three-dimensional flash memory devices and three-dimensional cross-point memory devices are being studied to overcome the technical limitations in two-dimensional memory devices. The three-dimensional memory devices may include a plurality of horizontal electrodes (e.g., word lines of a 3D vertical channel NAND flash device) stacked in turn on a substrate. In order to avoid the complexity in the connection structure, a plurality of the same horizontal electrodes are electrically connected to each other. As a result of this connection structure, three-dimensional memory devices are vulnerable to program and read disturb problems.

Some embodiments of the present invention provide three-dimensional memory devices and methods of operation that can suppress write and / or read disturbances.

Some embodiments of the present invention provide three-dimensional memory devices and methods of operation that can improve the speed of write and / or read operations.

Some embodiments of the present invention provide three-dimensional memory devices and methods of operation that can reduce energy consumption.

The three-dimensional semiconductor devices according to the embodiments of the present invention include a cache memory array configured to store data (for example, two-dimensional chapter data) over a page. The cache memory array is provided between a main memory array including three-dimensionally arranged memory cells and a peripheral circuit area (for example, a bit line decoder or page buffer). The use of the cache memory arrays has the technical difficulties (e.g., write / read disturbance or unnecessary energy consumption) in the data exchange caused by the dimensional difference between the three-dimensional main memory array and the one- . In addition, when the cache memory array is implemented using memory elements having a faster operating speed than the main memory array, the read and write operations to the main memory array Can be remarkably improved.

The use of the cache memory array can effectively reduce write and / or read disturbances and energy consumption in three-dimensional memory devices, as well as improve the speed of write and / or read operations.

Figure 1 is a schematic perspective view showing a typical three-dimensional memory device.
2 is a diagram showing two other structures of a main memory array.
3 is a schematic perspective view illustrating an example of three-dimensional memory devices according to embodiments of the present invention.
FIG. 4 is a table illustrating an exemplary arrangement of three-dimensional memory devices according to embodiments of the present invention.
5-7 are perspective views illustrating other examples of three-dimensional memory devices according to embodiments of the present invention.
8 to 12 are perspective views schematically showing one side of main and cache memory arrays according to embodiments of the present invention.
13 is a diagram exemplarily showing a hierarchical structure of a main memory array.
14 is a diagram illustrating an aspect of a data transfer process performed through bit lines.
15 is a diagram showing a part of operations performed in a three-dimensional memory device according to embodiments of the present invention.
Figures 16 and 17 are illustrations of how the operations of a three-dimensional memory device according to embodiments of the present invention may be performed.
FIGS. 18 and 19 are views showing an example of a read operation of the three-dimensional memory device according to the embodiments of the present invention.
20 and 21 are views showing an example of a write operation of the three-dimensional memory device according to the embodiments of the present invention.
Figures 22 and 23 are illustrations of other operations of a three-dimensional memory device, in accordance with embodiments of the present invention, respectively.
FIGS. 24-29 are illustrations of data processing methods performed through modified operating methods or combinations thereof.
Figures 30-32 are tables for illustrating some of the technical features of operating steps of a three-dimensional memory device according to embodiments of the present invention.
33 is a circuit diagram exemplarily showing a cache cell array including unit cache memories.
Figures 34 and 35 are diagrams that schematically and illustratively show some of the possible structures of a unit cache memory.
Figure 36 is an exemplary illustration of memory elements that may be used as cache cells.
37 is an exemplary illustration of a portion of possible structures of a main memory array.
38 is a table for explaining one aspect of the operation of the three-dimensional memory device according to the embodiments of the present invention.
FIGS. 39 to 43 are views for explaining the operation of the semiconductor device according to an embodiment of the present invention.
44 to 46 are views for explaining modified embodiments of the present invention.
47 to 53 are views for explaining the operation of the semiconductor device according to another embodiment of the present invention.
54 to 57 are views for explaining the operation of the semiconductor device according to another modified embodiment of the present invention.
58 is a diagram showing an example of CM-CM copying.
59 and 60 are perspective views showing a semiconductor device according to some embodiments of the present invention.
61 to 65 are views showing a semiconductor device according to another embodiment of the present invention.
FIG. 66 is a view exemplarily showing a semiconductor device and a part of its operation in accordance with still another embodiment of the present invention. FIG.
67 is a diagram schematically illustrating paths of three-dimensional memory devices and operating currents according to further embodiments of the present invention.
68 is a schematic perspective view showing a semiconductor memory device according to some embodiments of the present invention.
69 to 72 are circuit diagrams showing some examples of three-dimensional semiconductor memory devices according to some embodiments of the present invention.
73 and 74 are schematic plan views illustrating, by way of example, semiconductor chips according to some embodiments of the present invention.
Figures 75 and 76 are block and perspective views, respectively, illustrating, illustratively, embodiments of the present invention including distributed partial cache memory arrays, respectively.
77 is a graph comparing the embodiments of the present invention and the operation methods according to the prior art in terms of the number of disturbance times.
Figures 78 and 79 are graphs comparing the time required between embodiments of the present invention and read and write operations according to the prior art.
80 is a schematic diagram showing an electronic product including a memory device according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The objects, other objects, features and advantages of the present invention will become more readily apparent from the following detailed description taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In this specification, when it is mentioned that a film (or layer) is on another film (or layer) or substrate, it may be formed directly on another film (or layer) or substrate, or a third film (Or layer) may be interposed. In addition, the size, thickness, etc. of the constituent elements of the drawings may be exaggerated for clarity. It should also be understood that although the terms first, second, third, etc. may be used in various embodiments herein to describe various regions, films (or layers), etc., It should not be limited. These terms may only be used to distinguish any given region or film (or layer) from another region or film (or layer). Thus, the membrane referred to as the first membrane in one embodiment may be referred to as the second membrane in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Like numbers refer to like elements throughout the specification.

Korean Patent No. 10-2012-0129303, 10-2012-0123938, and 10-2012-0119179 are incorporated herein by reference.

The technical terms referred to herein may be used with the following meanings. The bit line may be used to transfer information stored in a memory cell (i.e., an electrical signal) to a peripheral circuit (e.g., a sensing circuit, a decoder, a page buffer, or the like), or a signal transmission line used to transfer external data to a memory cell it means. A word line means a line configured to transmit a signal used to select some of a plurality of memory cells connected to one bit line.

A memory cell may refer to a region containing a material or thin film structure capable of charge storage, a material exhibiting variable resistance characteristics, or a thin film structure (e.g., PCM, MTJ, resistive memory element). However, the present invention is not limited to a particular type of memory cell, and based on the characteristics of the memory cell being used, embodiments of the present invention may be further subdivided and diversified.

Adjacent memory cells may be provided in the form of spatially separated localized patterns or as a structure comprising at least a portion connected to each other.

The wiring or wire may mean a conductive pattern formed of a material having a low resistivity. For example, they may be (but are not limited to) metal or semiconductor materials of high concentration, but may be organic materials, carbon nanostructures (such as nanotubes or graphene), or molybdenum sulfides, It can also be used to implement.

According to some embodiments, the exchange of data with the peripheral circuit may be in the form of an optical signal. In this case, the wiring or the bit line is provided in the form of an optical waveguide, and the peripheral circuit may include a multiplexer such as a star coupler.

Although, in the figures, 'F' is used to indicate that the element is electrically floating, it is only a notation for the sake of clarity of description, and the element can be prevented from generating a current path through it A voltage may be applied.

Figure 1 is a schematic perspective view showing a typical three-dimensional memory device. Referring to FIG. 1, a typical three-dimensional memory device includes a main memory array (MMA) and a bit line structure (BLS) provided on a substrate SUB. The main memory array (MMA) may include three-dimensionally arranged memory cells and internal lines connecting the memory cells.

For example, as shown in FIG. 2, the main memory array (MMA) may be provided in an A-type or B-type structure. In the case of the A-type, the main memory array MMA includes (1) vertical lines VL arranged on the substrate SUB while forming a positive and a multi-layer structure (i.e., two- (2) a plurality of horizontal lines (HL) traversing the vertical lines (VL) while forming a multi-layered and multi-row structure, and (3) (Hereinafter referred to as " memory cells ") MC provided at intersections. In the case of the B-type, the main memory array MMA includes (1) first horizontal lines HLx forming a multi-layered and multi-row structure, (2) second horizontal lines HLy, and (3) the memory cells MC provided at their intersections. The vertical lines VL or the horizontal lines HL, HLx and HLy may be electrically connected to peripheral circuits via the bit line structure BLS.

According to embodiments of the present invention, a three-dimensional memory device is provided between the main memory array (MMA) and the bit lines (BL) as shown in FIG. 3, and two-dimensionally arranged cache memory cells , Cache cells (CC)). The cache memory array < RTI ID = 0.0 > (CMA) < / RTI > The cache memory array (CMA) may be provided as part of the cell array area. This means that the cache memory array (CMA) is provided, for example, between the main memory array (MMA) and a circuit (for example, a bit line decoder and a sensing circuit) constituting a peripheral region. Also, the cache memory array (CMA) has a storage space (for example, one-dimensional page buffer) which is disposed in a peripheral circuit area and stores data to be transmitted from or to the bit lines .

The relative arrangement between the cache memory array (CMA), the main memory array (MMA) and the bit line structure (BLS) can be variously modified from that shown in FIG. Fig. 4 is a table showing some examples of these various modifications, and Fig. 5 to Fig. 7 are schematic perspective views exemplarily showing such various modifications.

Referring to FIG. 4, according to a first basic structure, the cache memory array (CMA) includes a main memory array (MMA) and a bit line structure (BLS) As shown in FIG. According to a second basic structure, the main memory array (MMA) may be arranged between the cache memory array (CMA) and the bit line structure (BLS), as shown as type B in Fig. According to a third basic structure, the bit line structure (BLS) may be disposed between the main memory array (MMA) and the cache memory array (CMA), as shown as type C in Fig. According to a fourth basic structure, the cache memory array (CMA) and the main memory array (MMA) are arranged adjacent to and in parallel with each other on a substrate, as shown as type D in Fig. 5, BLS) may be provided on top of them.

The first basic structure may be variously modified by the presence of additional structures, such as selective structures (SLS) or environmental structures (EVS) (as will be described in more detail below), as shown as type AS and type AE of FIG. . For example, when the three-dimensional memory device further includes the selection structure (SLS), the first basic structure may be modified to one of the first through fourth modified structures of FIG. In addition, as in the fifth to eighth modified structures of FIG. 4, the first basic structure is formed such that the cache memory array (CMA) and the main memory array (MMA) are sequentially arranged on the bit line structure (I.e., the inverted structure of the first to fourth deformable structures).

The selection structure SLS may include, for example, (1) selecting one or a portion of internal lines (e.g., VL, HL, HLx, or HLy) constituting the main memory array MMA ) May be configured to enable selection of one or a portion of the conductive lines constituting the cache memory array (CMA). In some embodiments, the selection structure (SLS) may be interpreted as part of the cache memory array (CMA). The technical features associated with the Selective Structure (SLS) will be described in more detail below with reference to Figures 30-35 and 39-67.

Even when the three-dimensional memory device further includes the environmental structure (EVS), the first basic structure may be modified in a similar manner as in the variants provided with the selection structure (SLS). The environmental structure EVS may then be configured to enhance the effectiveness of the mating, which will be described in more detail with reference to FIG. Similarly, each of the second to fourth basic structures may be variously modified, such as the modified structures for the first basic structure.

Each of the main and cache memory arrays (MMA, CMA) is comprised of a plurality of portions that operate separately or independently from one another, as shown in Type AF and AP of FIG. 6 and Types DF and DP of FIG. . Each portion of the cache memory array (CMA) is configured to have a fully counterpart structure, such as in the respective respective portions of the main memory array (MMA), type AF in FIG. 6 and type DF in FIG. 7, AP and the type DF of Fig. 7, as shown in Fig. The fully or partially corresponding structures will be described in more detail below.

The bit line structure BLS is connected to the memory cells CMA of the cache memory array CMA connected to or to the internal lines (e.g., VL or HL) of the main memory array MMA, And a plurality of bit lines BL electrically connected to the bit line BL. The bit line structure BLS may be configured to traverse or to be connected to portions of the main and cache memory arrays (MMA, CMA). For example, the bit line structure (BLS) may be provided on top of portions of the main memory array (MMA), as shown in Type AF and AP of Figure 6 and types DF and DP of Figure 7, May be provided under the main memory array (MMA) as shown in type DI of FIG.

Meanwhile, the first to fourth basic structures are classified according to the above-described arrangement or arrangement order between the main memory array (MMA), the cache memory array (CMA) and the bit line structure (BLS) (SUB) can be varied or freely modified. For example, the first basic structure may be implemented as inverted shapes, as in the first and fifth modified structures of FIG. 4, or may be implemented as a clock or counterclockwise rotation of 90 degrees . The second to third basic structures and their variations may also be implemented with the above-described variety or freedom in relative arrangement to the substrate SUB.

FIGS. 8-12 are schematic perspective views illustratively showing the locations of the main and cache memory arrays (MMA, CMA) and their internal lines. For example, each of the structures of FIGS. 8 and 9 may be used to implement embodiments in which the main memory array (MMA) is provided in the form of vertical-channel and vertical-gate NAND flash memory Can be used. Similarly, although not exclusively, each of the structures of FIGS. 8-12 may be used to implement embodiments in which the main memory array (MMA) is provided in the form of a three-dimensional cross-point resistive memory.

To avoid complexity in the figures, in Figures 8-12, each of the word lines WL is shown in a planar form, but may also be provided in a one-dimensional structure including a plurality of lines, such as a multi-layer or multi-row structure. When each of the word lines WL is provided in the form of a flat plate, two-dimensionally arranged ones of the memory cells MC may be commonly connected to each of the word lines WL. This can cause read / write disturbances as described below. Even when each of the word lines WL includes a plurality of spatially separated but electrically connected lines, the disturbance problem may occur equally.

In the cache memory array (CMA), a plurality of cache lines (CWL) connecting the cache cells (CC) may be provided. In some embodiments, the cache lines (CWL) are electrically isolated from each other and may be arranged to traverse the bit lines (BL).

Figure 13 is an exemplary diagram illustrating the hierarchical structure of the main memory array (MMA) of a three-dimensional memory device to which the present invention may be applied. 13, the main memory array (MMA) may include at least one block, which may include one or more (e.g., r) chapters, and the chapters Each may include a plurality (e.g., q) of pages, each of which may comprise a plurality (e.g., p) of cells. The concepts of chapters, pages, and cells described herein may equally be applied to describe the hierarchical structure of the cache memory array (CMA).

The block may be a data size (e.g., maximum) or a unit of cells over which an operation may be performed independently. For example, according to some embodiments of the present invention applicable to NAND flash memory, a block may be used as a unit of data that can be erased at one time. However, the concept of the block need not be limited to the definition based on this operation method. For example, the block may be a set of three-dimensionally arranged memory cells, and such memory cells may be provided in a localized region or distributed in various regions.

The chapter may refer to data or cells included in the main memory array (MMA) or one plane constituting the block. In other words, the chapter consists of data or cells arranged two-dimensionally on a predetermined plane. Here, the plane may mean a plane in at least one of the data-hierarchical aspects or the sides of the physical arrangement of the cells, and the direction of the plane may be the direction of the bit lines BL and the word lines WL Arrangement and operation method to be performed using them. For example, in the case of the vertical-channel NAND flash memory of FIG. 8 (where the word lines forming the coplanar are electrically connected and used as the common gate electrode of two-dimensionally arranged memory cells), one chapter Dimensionally arranged memory cells (controlled by a gate electrode) or data stored therein.

The page refers to a data size or its maximum size that can be read at a time through the bit line structure (BLS). As described above, since each bit line is electrically connected to a plurality of internal lines constituting the main memory array (MMA), the two-dimensional data constituting the chapter or the three-dimensional data constituting the block It may be difficult to input or output at once through the bit line structure (BLS). Accordingly, as shown in Fig. 14, the two-dimensional data constituting one chapter or the three-dimensional data constituting one block are divided into groups of one-dimensional data, and then the bit lines BL). The page may correspond to each of the one-dimensional data groups.

To provide a better understanding of the chapter and page concepts, a chapter of the main memory array (MMA) and the pages that make up it are illustrated by way of example in FIGS. 8-12.

In the main memory array (MMA), the memory cells are arranged at intersections between the vertical lines (VL) and the horizontal lines (HL) or between the first and second horizontal lines (HLx and HLy) Quot; information storage space " In embodiments of the present invention, the cell may be configured to store single or multi-bits.

As described above, the memory cells constituting the block may be provided in a distributed form in various regions. Similarly, memory cells constituting one chapter or one page may also be provided in a distributed form in various areas. For example, each of the blocks, chapters, and / or pages may be divided into a plurality of sections configured to operate independently, based on a method of pair / hole partitioning or left / right partitioning. For the sake of brevity of description, the description of possible embodiments of the present invention that may be applied to such a separate section will be minimized, but the method of section separation can be variously modified in view of the efficiency of the read or write operation have. Therefore, known techniques (e.g., applied to two-dimensional memory semiconductors) based on such section separation can be used or applied to implement the technical idea of the present invention, and such use or application can be applied to embodiments of the present invention Lt; / RTI >

15 is a diagram showing a part of operations performed in a three-dimensional memory device according to embodiments of the present invention. Referring to Figure 15, the operation of the three-dimensional memory device according to some embodiments of the present invention includes the MM-CM copy S [RM], CM-MM copy S [WM] ]), And CM reading (S [RC]). The steps of the MM-CM copy (S [RM]) and the CM-MM copy (S [WM]) are performed between the main memory array (MMA) and the cache memory array (CMA) The steps of the CM write (S [WC]) and the CM read (S [RC]) are data transfer processes between the cache memory array (CMA) and the peripheral area Transmission processes.

According to some embodiments, the MM-CM copy (S [RM]) and CM-MM copy (S [WM]) are performed chapters, [RC]) may be performed sequentially or randomly on a page basis. However, the embodiments of the present invention are not limited thereto, and as will be described with reference to FIGS. 25 to 30, each of these steps may be variously modified in units of data processing and the like.

CM copy (S [RM]), CM-MM copy (S [WM]), CM write (S [WC]), CM read ]) May be performed in an appropriate combination. For example, these steps may include (1) a read operation that reads information stored in the main memory array (MMA) into a peripheral circuit (e.g., a page buffer or a sensing circuit) and (2) And to perform a write operation to store data in the main memory array (MMA).

According to some embodiments, the read operation includes the MM-CM copy (S [RM]) and the CM read (S [RC]) steps as shown in Figures 18 and 19, The CM write (S [WC]) and the CM-MM copy (S [WM]) as shown in Figures 20 and 21. For the sake of simplicity of explanation, the read and write operations for one chapter unit of data will be exemplarily described below. That is, a plurality of chapter data can be processed by repeating the operation described below.

As shown in FIGS. 16 and 18, the MM-CM copy (S [RM]) refers to a process of copying data stored in the main memory array (MMA) to the cache memory array (CMA). The MM-CM copy (S [RM]) may be implemented to copy chapter-based data to the cache memory array (CMA) at a time, as shown on the left side of FIG. According to a variant embodiment, the MM-CM copy (S [RM]) may comprise a plurality of sub-steps, each of which is carried out to copy two pages of data or more , Fig. 24, Fig. 26, or Fig. 28).

As shown in FIGS. 17 and 18, the CM read (S [RC]) uses the bit line structure (BLS) to transfer the data of the cache memory array (CMA) to a peripheral circuit Page buffer). The CM read (S [RC]) may include a plurality of cache page reading steps, each of which is implemented to transmit page-by-page data to the peripheral circuit, as shown on the right side of FIG. According to alternative embodiments, the CM read (S [RC]) may comprise a plurality of sub-steps, each of which is implemented to transmit data of a size smaller than the page. For example, each of the lower steps of the CM read (S [RC]) may be implemented to process one or more cell data.

As shown in FIGS. 17 and 20, the CM write (S [WC]) refers to a process of writing external data to the cache memory array (CMA) using the bit line structure (BLS). The CM write (S [WC]) includes a plurality of cache page writing steps, each of which is performed to write page-by-page data to the cache memory array (CMA), as shown on the left side of Fig. . According to a variant embodiment, the CM write (S [WC]) may comprise a plurality of sub-steps, each of which is carried out to transmit data of a size smaller than the page. For example, each of the lower steps of the CM write S [WC] may be implemented to process bits, bytes, or more of the cell data.

As shown in FIGS. 16 and 20, the CM-MM copy (S [WM]) refers to a process of copying data stored in the cache memory array (CMA) to the main memory array (MMA). The CM-MM copy (S [WM]) copies the data of the chapter unit stored in the cache memory array (CMA) to a predetermined chapter of the main memory array (MMA) at once as shown on the right side of FIG. . According to a variant embodiment, the CM-MM copy (S [WM]) may comprise a plurality of sub-steps, each of which is carried out to copy data of two pages or more , See Fig. 24).

In some embodiments, the data may be read from the cache memory array (CMA) or read from the cache memory array (CMA) in a random access manner or based on one of the cache algorithms applied to the L1, L2 or L3 cache memory. Lt; / RTI > For example, the CM read (S [RC]) and CM write (S [WC]) may be implemented to process bit, byte, word, or page data. In some embodiments, the cache memory array (CMA) may be used as any of the L1, L2, or L3 caches and may be configured to implement the functions of the DRAM or SRAM currently used. According to some embodiments, the peripheral circuitry may be configured to implement the random access method or a cache algorithm for the L1, L2 or L3 cache. For example, the peripheral circuitry may further include a driving or decoding circuit used in DRAM, ESRAM or NOR flash memory devices.

The step of CM-CM copy (S [CC]) is a data transfer process performed between two different parts (P1, P2) of the cache memory array (CMA). The CM-CM copy (S [CC]) may be combined with at least one of the other steps illustrated in FIG. 15 to implement the random access or cache algorithm described above. Wherein two different portions of the cache memory array (CMA) may be configured to share the bit line structure (BLS), wherein the step of CM-CM copy (S [CC] . ≪ / RTI > According to some embodiments, as shown in FIG. 22, without copying or migration of data to the peripheral area, copying data directly from one of the two parts P1 and P2 to another Or to migrate. However, according to modified embodiments, the CM-CM copy (S [CC]) may be implemented sequentially using the peripheral area (e.g., a page buffer). For example, as shown in FIG. 29, the CM-CM copy (S [CC]) includes the CM read (S [RC]) performed in each of the two parts P1 and P2, CM write (S [WC]).

15 and 23, according to the modified embodiments of the present invention, each of the writing and reading operations are MM direct writing (S [WMd]) which does not use the cache memory array (CMA) And direct MM reading (S [RMd]).

The MM direct write (S [WMd]) means a process of directly writing external data provided through the peripheral circuit to the main memory array (MMA). For example, the MM direct write (S [WMd]) may be a data transfer process performed without an interruption step of storing data in the cache memory array (CMA). According to some embodiments, the MM direct write (S [WMd]) is implemented to write page-by-page data directly to a predetermined chapter of the main memory array (MMA), as shown in Figure 23 , And a plurality of sub-direct write steps. According to alternative embodiments, each of the lower direct write steps may be implemented to process one or more cell data. Alternatively, the MM direct write (S [WMd]) may be implemented to process the chapter or more data, as in the erase step of the flash memory.

The direct MM read (S [RMd]) means a process of transmitting data of the main memory array (MMA) to the peripheral circuit without an interruption step of storing data in the cache memory array (CMA). The MM direct read (S [RMd]) may comprise a plurality of lower direct read steps, each of which is implemented to transfer page-by-page data to the peripheral circuit, as shown in Figure 23, Each of the direct reading steps may be implemented to process one or more cell data.

According to some embodiments of the present invention, as shown in FIG. 15, operation of the three-dimensional memory device may be performed by initializing all or a portion of the cache memory array (CMA) or the cache cells (e.g., (S [IN]) step to create a specific data state. If the cache cell CC is nonvolatile (e.g., as in a magnetic tunnel junction), its data modification may be performed by an external factor (e.g., external or electrical Signal) as well as internal factors (e.g., the data state of the cache cell CC itself). In this case, it may be necessary to eliminate the non-uniformity in the cache memory array (CMA) associated with the internal factor through the CM initialization (S [IN]) step. In other words, when the cache cells CC are not initialized, some of the data stored in the cache cells CC may not be able to be changed. In this case, the CM write S [ Only a portion of the data from the main memory array (MMA) or outside the MM-CM copy (S [RM]) and the MM-CM copy (S [RM]) may be written to the cache cells (CC). That is, an error may occur.

Nevertheless, in some embodiments, the CM initialization (S [IN]) step may be omitted if the data change of the cache cell CC has a small or negligible dependency on the internal factor. More specifically, this omission is determined by what type of electrical signal contains the data storage principle of the cache cells (CC) or the information stored in the memory cells (MC), and this determination can be made, for example, Based on the knowledge of those skilled in the art. For example, if the cache cell CC is implemented with a memory element having a short retention characteristic (i.e., volatile), the CM initialization (S [IN]) step may be omitted. The CM initialization (S [IN]) may be performed in units of chapters or smaller data (pages).

Each of the above-described steps may be variously changed, and each of the read and write operations may be implemented in various combinations. For example, as shown in FIGS. 24 and 25, the MM-CM copy S [RM], the CM-MM copy S [WM], the CM write S [WC] The CM reading (S [RC]) can be performed by transmitting data in units smaller than chapters. 26 and 27, the chapter data stored in the cache memory array (CMA) is divided into data transferred from the main memory array (MMA) through the MM-CM copy (S [RM] May be the sum of data transmitted from the peripheral area through the CM write (S [WC]). In this case, the MM-CM copy (S [RM]) may be performed in units of chapter data or chapter data as shown in FIGS. 26 and 27, and the CM write (S [WC] May be performed in an overwriting manner as shown in FIG. 28, the chapter data stored in the cache memory array (CMA) is stored in the main memory array (MMA), which is obtained through the steps of the MM-CM copy (S [RM] It can be the sum of two chapter data. Here, various modifications in the data processing method are described, but the embodiments of the present invention are not limited thereto, and can be modified in various ways based on the additional technical explanations and known techniques provided below.

FIGS. 30 and 31 are tables for illustrating some of the technical features of operation steps of a three-dimensional memory device according to embodiments of the present invention.

30, the CM write (S [WC]) and the CM read (S [RC]) have a current path via the bit line BL, the cache cell CC and the select line SL Can be performed on a page-by-page basis. In this case, the problem of disturbance to the main memory array (MMA) can be prevented because the formation of the current path connected to the memory cells MC is not necessary.

Alternatively, the MM-CM copy (S [RM]) and the CM-MM copy (S [WM]) may include a current path via the bit line (BL), the cache cell (CC) Can be performed on a chapter-by-chapter basis. In this case, the disturbance phenomenon may appear, but since each of them is a data transmission process of one chapter unit, the problem of repetitive disturbance can be prevented.

31, the bit line BL is connected to the select line SL and the internal wirings (e, g) of the main memory array MMA, for example, , VL, or HL), which may include a selector or switch. The selector may be provided as part of the selection structure (SLS) described with reference to FIG.

FIG. 31 exemplarily shows directions in which signals are transmitted in each step. For example, since the CM write (S [WC]) is a process of writing data transferred from the peripheral region to the cache cell (CC), data is transferred from the bit line (BL) As shown in Fig. In the case of the MM-CM copy (S [RM]), since the data is transferred from the memory cell MC to the cache cell CC, the signal direction in the CM write S [WC] As shown in FIG. (Meanwhile, the direction of the signal mentioned here may be changed according to the structure and the operating principle of the memory or the cache cells, and may be different from the direction of the current.)

According to embodiments of the present invention, the selector can be configured to implement such a change in signal direction. FIG. 32 shows an example of the direction of the write current according to the type of the cache cell CC and a possible type of the selector to implement the write current.

FIG. 33 is a circuit diagram exemplarily showing a cache cell array (CMA) including unit cache memories, and FIGS. 34 and 35 are views schematically and exemplarily showing a part of possible structures of the unit cache memory.

Referring to FIG. 33, the cache memory array (CMA) may include two-dimensionally arranged unit cache memories (CMU). Each of the internal wirings (eg, VL or HL) of the main memory array MMA is connected to a corresponding one of the first lines L1 through a corresponding one of the unit cache memories CMU, May be coupled to a corresponding one of the lines L2. The first lines L1 are arranged to traverse the second lines L2 and the internal lines VL or HL are arranged to cross both the first and second lines L1 and L2 You can have a long axis to bend. For example, the first and second lines L1 and L2 and the internal wires VL or HL may be substantially perpendicular to each other.

Each of the unit cache memories (CMU) may include at least one cache cell (CC) for storing data and at least one selector (ST) for changing the above-mentioned signal transmission path or current path. The operation of the cache cell CC and the selector ST may be controlled by a cache line CWL, which may be one of the first or second lines L1 and L2. (For brevity's sake, FIGS. 33-35 illustrate embodiments in which the cache line CWL is implemented using the second line L2, but the cache line CWL may be implemented in a similar manner And may be implemented using the first line L1.

According to some embodiments, the first line (L1) is used as the bit line structure (BLS) or the bit lines (BL), and the second line (L2) is described with reference to Figures 30 and 31 Can be used as a wiring for realizing the change of the current path. However, according to other embodiments, these functions of the first and second lines L1 and L2 may be interchanged. These two types of embodiments may be more clearly understood from the comparison of Figures 39 and 47, which will be described below.

The structure of the cache line CWL may be varied according to the structure and / or operation principle of the cache cell CC and the selector ST, as shown in FIG. For example, the cache line CWL may include one or more lines SL, GL, CL used to control the selector ST and / or the cache cell CC.

More specifically, the selector ST is a two-terminal switching element provided between the selection source line SL and the cache cell CC, for example, as shown in the types A and B of FIGS. 34 and 35 , A diode). However, as in the types C and D of FIGS. 34 and 35, a three-terminal switching device (for example, a three-terminal switching device) including a control line or a gate line GL in addition to the above- , Transistors). The cache cell CC also includes a two terminal memory element provided between the first line L1 and the selector ST as in the types A and C of FIGS. 34 and 35 (for example, Variable memory element), but may be a three-terminal memory element (e.g., a memory element of a transistor structure) controlled by a cache control line CL, as in types B and D of Figures 34 and 35 have. In other words, the cache line CWL may be connected to the selection source line SL, the gate line GL, and / or the source line SL according to the type, structure, and / or operation principle of the cache cell CC and the selector ST, And the cache control line (CL).

The unit cache memory (CMU) or the cache cell (CC) may be implemented using one of the memory elements illustrated by way of example in FIG. For example, the unit cache memory (CMU) may be a DRAM, SRAM, FRAM, NAND FLASH, MRAM, STT-MRAM, PCRAM, NRAM, RRAM, CBRAM, SEM, T-RAM, Z-RAM, , Holographic, and Probe, and the like. Alternatively, the unit cache memory (CMU) may comprise at least one of the memory elements described in documents comprising at least one of the known memory elements (e.g., ITRS (International Technology Roadmap for Semiconductor) and its reference list) ).

In some embodiments, the cache cells CC may be memory cells based on a different data storage principle than the memory cells MC. For example, the main memory array MMA may be implemented in the form of a three-dimensional NAND flash memory, a PCRAM, a CBRAM, or a ReRAM, and the cache memory array CMA may include SRAM, PCRAM, STT- T-RAM, ReRAM, or Z-RAM, which are different from the memory cells MC. However, in other embodiments, the cache and memory cells CC, MC may be memory cells of the same type or memory cells based on the same or similar operating principle.

In some embodiments, each of the cache cells CC may be configured to have a faster write and / or read rate than each of the memory cells MC. For example, when the memory cells MC are charge storage elements as in a flash memory device, the cache cells CC may include memory elements (e.g., PCMs) , MTJ, Z-RAM, CBRAM, ReRAM materials, etc.).

In some embodiments, the main memory array (MMA) is comprised of non-volatile memory elements, and the cache memory array (CMA) is a volatile or nonvolatile memory having a faster operating speed than the memory cells Elements. For example, if the memory cells MC are charge storage elements as in a flash memory device, the cache cells CC may be implemented in the form of SRAM, T-RAM, or Z-RAM.

However, the cache and memory cells CC, MC need not be combined in the manner illustrated above. Based on consideration of other technical issues, such as, for example, manufacturing process, manufacturing cost, data retention characteristics, mismatching characteristics (to be described below) and ease of current path formation, the above described implementation may be mitigated or altered . Alternatively, the type of the memory element for the cache memory array (CMA) may be determined according to the operation principle of the memory cells MC, characteristics of the electrical signal for operation (for example, unidirectional or bidirectional, , The amount of current, the speed, etc.), or various technical requirements for the cache memory array (CMA) itself (e.g., operational capability as a RAM or buffer memory). For example, in relation to the CM-MM copy (S [WM]) step, the MM-CM may be configured so that the characteristic of the read signal of the cache cell CC matches the characteristic of the write signal of the memory cell MC The memory cell MC and the memory cell MC are connected in such a manner that the characteristic of the read signal of the memory cell MC matches the characteristic of the write signal of the cache cell CC, MC) may be needed. In addition, the cache and memory cells CC, MC can be combined to maximize the technical effect of disturbance reduction and read / write time reduction, which will be described below with reference to Figures 77-79.

The main memory array (MMA) may be configured to include one of the array structures illustrated by way of example in FIG. 37, although it is not limited thereto. For example, as in Type A of FIG. 37, the main memory array MMA may be configured to use the internal line VL / HL as a channel region (e.g., as in a cell string of a NAND flash memory) ) May be provided in a structure including a plurality of memory cells MC connected in series.

Alternatively, as in types B, C, and D of FIG. 37, the main memory array MMA may be provided with a structure including a plurality of memory cells MC connected in parallel to the internal line VL / HL have. In this case, according to some embodiments, each of the memory cells MC may be configured to include a rectifying device (e.g., a diode) as in Type D. Alternatively, as in Type B, the internal line (VL / HL) may be a semiconductor material whose potential is controlled by a conductive line, and the electrical connection between the memory cells MC and the cache cell (CC) Can be controlled by a conductive line. For example, as will be described again with reference to FIG. 66, the conductive line and the internal line VL / HL may form a structure of a MOS capacitor or a vertical path control structure (VPCS).

Meanwhile, the MM-CM copy S [RM] may be a process of writing data read from the memory cells MC into the cache cell CC. In other words, in the MM-CM copy (S [RM]), the read operation of the memory cell MC is performed in a pair with the write operation of the cache cell CC. The CM-MM copy (S [WM]) may be a process of writing data read from the cache cell (CC) to the memory cell (MC). In other words, in the CM-MM copy (S [WM]), the write operation of the memory cell MC may be performed in a pair with the read operation of the cache cell CC. This means that in order for the CM-MM copy (S [WM]) and the MM-CM copy (S [RM]) to be validly performed, the paired operations must have electrical or operational characteristics , The amount of current and the operating time).

According to some embodiments of the present invention, the semiconductor device may further include an environmental structure (EVS) configured to enhance the effectiveness of such mating, as shown in Type A-E of Fig. For example, the environmental structure EVS may be configured to adjust an electrical resistance of a path connecting the memory cell MC and the cache cell CC. Alternatively, the environmental structure (EVS) may be an additional structure that is configured to mitigate discrepancies in electrical characteristics between them, which may occur during a data exchange or copy operation between the memory cell MC and the cache cell Memory elements. For example, the data exchange or copy operation may include a data transfer process configured to directly or indirectly pass the additional memory element provided in the environmental structure (EVS).

The environmental structure EVS may be configured to bring about a change in the operating environment (e.g., temperature) of the cache cell CC. The environmental structure (EVS) may be configured to operate locally or selectively, and may include a plurality of environmental control elements and conductive lines for electrically controlling them. In addition, when the bit lines are provided in the form of optical waveguides, the environmental structure (EVS) may include photoelectric conversion elements that convert electrical signals to optical signals or vice versa.

Meanwhile, in the type AE of FIG. 6, the environmental structure EVS is interposed between the main memory array MMA and the wiring structure UWS, but the embodiments of the present invention are not limited thereto no. For example, the location of the environmental structure (EVS) may be modified in various ways, as described with reference to Figs. 4-7.

FIGS. 39 to 43 are views for explaining the operation of the semiconductor device according to an embodiment of the present invention. In this embodiment, the main memory array (MMA) is configured to have a structure (e.g., BiCS or TCAT) of vertical channel three-dimensional NAND flash as in Type A of FIG. 37, and the cache memory array (CMA) May be configured to include cache cells (CC) arranged two-dimensionally on the main memory array (MMA). Herein, an embodiment will be described in which the cache cells CC are high-speed resistive memory elements (e.g., STT-MTJ) that operate using bidirectional currents.

The cache cells CC may be interposed between the bit lines BL and the main memory array MMA and the vertical lines VL may be formed in a semiconductor pattern perpendicular to the upper surface of the substrate SUB, Silicon), and a charge storage film (e.g., ONO) functioning as the memory cells MC may be interposed between the vertical line VL and the horizontal line HL. The semiconductor pattern of the vertical line (VL) may include, for example, n-type impurity regions used as source and drain electrodes and a vertical channel region of intervening embedded or intrinsic channel regions. According to some embodiments, the n-type impurity regions may be replaced with a metal-containing film capable of forming a rectifying element together with the vertical channel region.

The horizontal lines HL or the word lines WL may comprise metal or doped silicon. A plurality of gate lines GL may traverse the bit lines BL between the cache cells CC and the main memory array MMA. Each of the gate lines GL may be used as a gate electrode of a transistor (i.e., the selector T) using the semiconductor pattern of the vertical line VL as a channel region, And the cache cell (CC).

Due to the presence of the selector T, the vertical channel region is electrically coupled to the CM write (S [WC]) and the CM read (S [RC]), as shown in Figures 39, It is not used as a path. Thus, the problem of read and write disturbances that can be applied to the main memory array (MMA) can be reduced.

During the CM write (S [WC]), as shown in FIGS. 39 and 40, either one of the cache lines CWL or the selection source lines SL and the plurality of bit lines BL Operating voltages can be applied. In this case, input data may be transferred to the cache cells (CC) via the bit lines (BL) (for example, from a page buffer of a peripheral circuit). For example, depending on the data to be input, a voltage (e.g., V1 or V _low ) applied to a part of the bit lines BL is different from a voltage (e.g., V2 or V _high ) applied to another part . In this case, as shown, when a voltage substantially equal to any one of the bit line voltages is applied to any of the selection source lines SL, the write current for the cache cell CC , And a potential difference between the bit line (BL) and the selection source line (SL). 39, a question mark ("?") Indicates that a current path through it may be selectively formed by data stored in the memory element to which it is pointed, or a related data write operation may be selectively performed .

During the CM-MM copy (S [WM]), a bit line voltage (V_BL) is applied to the bit lines BL as shown in FIGS. 39 and 41, And a program voltage Vpgm is applied to one (hereinafter, selected word line). In this case, the current path from the bit line BL to the cell string may be selectively generated depending on the data stored in each of the cache cells CC. For example, when the cache cell CC is on, the corresponding channel region may have substantially the same potential (i.e., V_BL) (for example, 0V) as the bit line. In this case, when the voltage applied to the selected word line (i.e., Vpgm) is high, a program through F-en tunneling occurs. On the other hand, when the cache cell CC is off, the corresponding channel region is electrically isolated and has an increased potential due to the voltages applied to the word lines WL. As a result, the potential difference with the program voltage can be reduced. That is, it is possible to prevent the program through the self-boosting technique.

During the MM-CM copy (S [RM]), one of a plurality of bit lines BL and one of the word lines WL (hereinafter referred to as a selected word line) Operating voltages are applied. In this case, as shown in FIG. 39, the current path through each of the cache cells CC may be selectively generated depending on each of the data stored in the two-dimensional memory cells MC controlled by the selected word line have. When such a current path is generated, the data of the corresponding cache cell CC can be changed (for example, to a high resistance state or an OFF state). In some embodiments, prior to the MM-CM copy (S [RM]), the CM initialization (S [IN]) may be performed to turn on the cache cells (CC).

During the CM reading (S [RC]), different operating voltages (V1, V2) are applied to either the cache lines (CWL) or the selection source lines (SL) And the bit lines BL, respectively. In this case, depending on the applied voltage condition, the current in the direction shown in Fig. 39 or the opposite direction can be selectively generated depending on the data stored in the cache cell CC. The sense amplifiers in the peripheral region can be configured to sense variations in the electrical state (e.g., potential) of the bit lines caused by the generation of such current paths. As shown in FIG. 43, the CM reading (S [RC]) may be performed page by page (or less).

The read and write operations described above may be performed selectively and / or randomly for a portion (e.g., page or less) of the cache memory array (CMA). Also, such selective read and write operations to the cache memory array (CMA) may be performed independently without access to the main memory array (MMA). This means that the cache memory array (CMA) can be used as an L1, L2, or L3 cache. The access to the main memory array (MMA) may be performed when it is determined that long-term storage of data stored in the cache memory array (CMA) is required. That is, the main memory array (MMA) can be used as storage, for example.

On the other hand, when performing self-boosting using the cache cell CC in the CM-MM copy (S [WM]), the need for string selection lines SSL required in the prior art can be reduced . For example, if the off-resistance of the cache cell CC is sufficiently large, the CM-MM copy (S [WM]) can be effectively performed even when there is no string selection lines SSL. Nevertheless, this does not necessarily require the removal of the string selection lines (SSL).

According to some embodiments, as shown in FIG. 44, the string selection line SSL can be used as the gate line GL of the selector ST. In this embodiment, the semiconductor pattern constituting the vertical line VL is used as the active pattern of the selector ST, and the current path between the bit line BL and the cache cell CC is the gate line GL) or the string selection line (SSL). In some embodiments, the bit line BL may be formed using a process of patterning the string selection line SSL, and may be formed of a conductive material capable of forming the rectification element with the semiconductor pattern . In other embodiments, a conductive thin film (e.g., n + polysilicon) capable of implementing the rectifying element may further be provided between the bit line BL and the semiconductor pattern VL. According to some embodiments, the bit line BL may be formed to traverse the gate line GL

On the other hand, as shown in FIG. 45, the main memory array (MMA) can be programmed (for example, on a page basis) by way of the MM direct write (S [WMd]). For example, if the cache cells CC do not have a sufficiently high resistance value even when the cache cells CC are off, it may be difficult to implement the self-boosting technique described above. In this case, the MM direct write (S [WMd]) step may be performed. The erase operation for the main memory array (MMA) may be performed identically based on known conventional techniques.

The CM initialization (S [IN]) may be implemented using one of the three methods as shown in FIG. For example, the CM initialization (S [IN]) may be performed using a current path via the selector (ST) without access (i.e., disturbance) to the main memory array (MMA) (CSL) and the main memory array (MMA). If the CM initialization (S [IN]) is carried out using the current via the selector ST, it may be performed on a chapter-by-chapter basis. In this case, a large current can be discharged through the selection source line SL or the bit line BL. According to some embodiments, in order to enable such a large current discharge, the selection source line SL or the bit line BL may be formed to have a sufficiently thick thickness.

46, when the selection source line SL is provided on the upper portion of the selector ST, the selection source line SL is formed to have a large thickness (for example, 100 nm-5 um). The CM write (S [WC]), the CM-MM copy (S [WM]), and the CM write ), The MM-CM copy (S [RM]), and the CM read (S [RC]). However, the embodiments of the present invention are not limited to those illustrated in Fig. According to some embodiments, the bit line BL may be formed to traverse the gate line GL. In addition, the structure of the selector ST or the illustrated voltage conditions may be more variously changed depending on the type of the cache cells CC and the operating method.

47 to 52 are views for explaining the operation of the semiconductor device according to another embodiment of the present invention. According to this embodiment, the main memory array (MMA) is configured to include variable resistive memory elements connected in parallel to the internal line (VL) as in Type D of Figure 37, the cache memory array (CMA) And cache cells (CC) arranged two-dimensionally above or below the main memory array (MMA). Herein, an embodiment in which the cache cells CC are memory elements having bi-directional current characteristics will be exemplarily described. For example, the cache cells CC may be provided in the form of FBM or Z-RAM as described with reference to FIG. When the cache cells CC have a unidirectional current characteristic, the cache memory array (CMA) can be implemented easily or in a simplified structure as compared with the case of bi-directional current. For example, since the unidirectional current characteristic can be realized through a two-terminal switching element (for example, a diode), compared with the case of using a three-terminal switching element (for example, a transistor) It can have a simplified structure. Therefore, description of the embodiments in which the cache cells CC have a unidirectional current characteristic is omitted.

The internal line VL may be connected to a connection node located between the cache cell CC and the selector ST constituting the unit cache memory CMU. (The internal line may be any one of the horizontal lines HL, HLx, and HLy, but a description of these embodiments is omitted for the sake of simplicity of explanation.) Each of the bit lines BL Can be connected to the internal line (VL) via a cache cell (CC) and the operation of the cache cell (CC) can be controlled by a cache control line (CL) across the bit lines (BL) . The selection source line SL may be connected to the internal line VL via the selector ST and the operation of the selector ST may be connected to the gate line GL crossing the bit lines BL ). ≪ / RTI >

Figs. 47-52 illustrate illustratively that the various operations of the three-dimensional memory device described with reference to Figs. 15-29, or the generation of a current path for them, can be implemented through such a structure or structure. 48, 51 and 52, the CM write (S [WC]), the CM read (S [WC]), and the CM read It is possible to generate a current path that does not cause disturbance to the main memory array (MMA) during the initialization (S [RC]) and the CM initialization (S [IN]). In addition, although the CM-MM copy (S [WM]) and the MM-CM copy (S [RM]) may have a difference in the direction of signal transmission, (I.e., two-dimensionally).

The embodiments of the present invention are not limited to the voltage conditions, the circuit structure, or the wiring structure shown in Figs. 47 to 52. For example, FIG. 53 shows that the gate lines GL are connected to each other and can be used as common gate electrodes of adjacent ones of the cache cells CC. The current direction is not limited to that illustrated in FIG. 47, and may be variously modified according to the needs of the developer. In addition, the structure and connection of the cache cells CC may be implemented using any of the conventional cell array architectures used in DRAM, FRAM, NOR flash, etc. to implement the operations described with reference to Figures 15 to 29 .

54 is a view for explaining the operation of the semiconductor device according to the modified embodiment of the present invention. According to this embodiment, like the embodiment described with reference to FIG. 47, the main memory array (MMA) is configured to have the structure of type D of FIG. 37, and the cache memory array (CMA) May be configured to have the structure of type D of FIG. However, in this embodiment, the internal structure of the cache memory array (CMA) can be modified from the structure of FIG. For example, as shown in FIG. 54, each of the bit lines BL may be connected to the internal line VL via the selector ST, and the operation of the selector ST may be connected to the bit line Lt; RTI ID = 0.0 > BL. ≪ / RTI > The selection source line SL may be connected to the internal line VL via the cache cell CC and the operation of the cache cell CC may be connected to a cache control line CK crossing the bit lines BL. (CL) < / RTI > Despite this difference in the internal structure of the cache memory array (CMA), similar to the embodiment of Fig. 47, the operations described with reference to Figs. 15 to 29 are also effectively implemented through the structure according to this embodiment Lt; / RTI >

55 is a view for explaining the operation of the semiconductor device according to another modified embodiment of the present invention. According to these embodiments, the main memory array (MMA) is configured to have the structure of type D of FIG. 37 and the cache memory array (CMA) may be configured to have the structure of type C of FIGS. 34 and 35 have. That is, the cache memory array (CMA) uses a two-terminal memory element (for example, a variable resistance memory element) provided between the bit line BL and the internal line VL as the cache cell CC . The selection source line SL may be connected to the internal line VL through the selector ST. FIG. 55 shows that the operations described with reference to FIGS. 15 to 29 can be effectively implemented even when the cache cell CC is provided in the form of a two-terminal memory element.

56 is a view for explaining the operation of the semiconductor device according to still another modified embodiment of the present invention. According to these embodiments, the main memory array (MMA) is configured to have a structure of type A of FIG. 37 and the cache memory array (CMA) may be configured to have the structure of type D of FIGS. 34 and 35 have. The internal structure of the cache memory array (CMA) may be configured substantially the same as that of FIG. In other words, the cache memory array (CMA) can supply a three-terminal memory element (for example, FBM or Z-RAM) provided between the selection source line SL and the internal line VL to the cache cell CC, As shown in FIG. However, the internal structure of the cache memory array (CMA) may be modified to be substantially the same as that of FIG. 56 is a block diagram showing a case where the cache cell CC is provided in the form of a two-terminal memory element and the operations described with reference to FIGS. 15 to 29 are effective even when the main memory array MMA is provided as a structure of a NAND string Can be implemented.

57 is a view for explaining the operation of the semiconductor device according to still another modified embodiment of the present invention. According to these embodiments, the main memory array (MMA) is configured to have the structure of type D of Figure 37, and the cache memory array (CMA) may be configured to have the structure of type B of Figures 34 and 35 have. In other words, the cache memory array (CMA) can supply a three-terminal memory element (for example, FBM or Z-RAM) provided between the selection source line SL and the internal line VL to the cache cell CC, And a two-terminal switching element (for example, a diode) provided between the bit line BL and the internal line VL may be used as the selector ST. The operation described with reference to Figs. 15 to 29 can be effectively implemented even when a two-terminal switching element is used as the selector ST.

58 is a diagram showing an example of an implementation of the CM-CM copy (S [CC]) step. As shown in FIG. 58, the CM-CM copy (S [CC]) in embodiments in which the unit cache memory (CMU) is provided with the structure of type D of FIG. 34 can be performed effectively. For example, a predetermined potential difference (eg, Vcc-GND) is formed between the selection source lines SL in two different parts P1 and P2 of the cache memory array CMA, Different operating voltages V _read and V _write may be applied to the transistors CL.

59 and 60 are perspective views showing a semiconductor device according to some embodiments of the present invention. 59 and 60, the main memory array (MMA) is configured to have a structure of vertical channel three-dimensional NAND flash (for example BiCS or TCAT) as in type A of FIG. 37, and the cache memory array CMA) may be configured to include cache cells (CC) arranged two-dimensionally on the main memory array (MMA). Here, the cache cells CC may be high-speed resistive memory elements (e.g., STT-MTJ) that operate using bi-directional currents. The bit lines BL may be provided on the cache cells CC as shown in FIG. 59 or may be provided between the cache cells CC and the main memory array MMA as shown in FIG. 60 . In other words, Fig. 60 may be an example of a three-dimensional semiconductor device according to the embodiment described with reference to Fig. In the embodiment of FIG. 60, since the selection source line SL is provided on the cache cells CC, it can be formed in a thick-plate form and in a low resistivity material. This enables the above-described large current discharge.

61 to 65 are views showing a semiconductor device according to another embodiment of the present invention. According to these embodiments, the cache memory array (CMA) is configured to include cache cells (CC) arranged two-dimensionally under the main memory array (MMA), and the cache cells (CC) RAM or FBM as described with reference to FIG. The apparatus shown in Fig. 61 may be one of the examples implementing the embodiment described with reference to Fig. 47, and Figs. 62 to 65 may be examples of implementing the embodiments described with reference to Figs. 54 and 56 have. The selector ST or the cache cells CC may be implemented in the form of a planar transistor using an SOI substrate including a buried oxide film BOX as shown in FIG. 61, or a vertical channel surround gate transistor Or may be implemented through a combination of these two transistor structures as shown in FIG.

The types and arrangement of the selectors ST are not limited to the MOS transistors as shown in the drawings, but may be variously modified to have a structure corresponding to the electrical characteristics required for the cache cells CC. In addition, in some embodiments, the selector ST may be configured to function as the cache cell CC by itself, in which case the technical features in the embodiments to be described with reference to Figure 72 Can be implemented.

FIG. 66 is a view exemplarily showing a semiconductor device and a part of the operation thereof according to other embodiments of the present invention. FIG. According to this embodiment, each of the vertical lines may constitute a vertical path control structure (VPCS). Technical features relating to the vertical path control structure (VPCS) are disclosed in PCT Publication No. WO 2010/018888 (2010.02.18) and U.S. Application No. 13 / 059,059, the contents of which are fully incorporated as part of the present invention . The use of the vertical path control structure VPCS is advantageous in that even when rectifying elements (e.g., diodes) are not disposed in each of the memory cells MC, the parasitic capacitance between the memory cells MC arranged three- Thereby making it possible to shut off the sneak path.

More specifically, when one of the bit lines BL and one of the gate lines GL is selected, one of the cache cells CC can be selected uniquely, It is not possible to completely block hidden parasitic paths, even if one of the cache cells CC is uniquely selected. However, the vertical path control structure (VPCS) may include a semiconductor pattern connected to each of the cache cells CC and used as the vertical line VL, and a vertical line VL disposed to face the semiconductor pattern to control the potential of the semiconductor pattern. And may include a control electrode. In this case, the generation of the above-described hidden parasitic current path (sneak path) can be blocked. In other words, when the vertical path control structure (VPCS) is used for connection to the cache memory array (CMA), a parasitic current path (not shown) is used in the main memory array (MMA) sneak path can be prevented from being generated. The structure of the main memory array (MMA) and the method of manufacturing the main memory array MMA can be simplified, and the technical or functional relationship between the cache cells CC and the memory cells MC can be simplified. Requirements can be mitigated.

67 is a schematic diagram illustrating three-dimensional memory devices and paths of operating currents in accordance with some embodiments of the present invention. According to some embodiments, the memory cells MC may be configured to have a unidirectional current characteristic by including a rectifying element. In this case, the currents used for the CM-MM copy (S [WM]), the MM-CM copy (S [RM] It can have the same direction. On the other hand, the cache cells CC may be configured to have bi-directional current characteristics. In this case, the current path through the memory cells MC is hardly used for initializing the cache cells CC. However, by forming a separate current path DL as shown in Fig. 67, this initialization difficulty can be solved. In some embodiments, the separate current path DL may be implemented using one of the word lines WL.

On the other hand, if the cache cells CC do not have a bi-directional current characteristic or are short-retention characteristic (i.e., volatile) memory elements, it may not be necessary to form the separate current path. This separate current path can also be adaptively implemented based on the types of the cache cells CC and the memory cells MC and their combined characteristics, . For example, the separate current path DL and the gate electrodes of the switching transistors connected to the bit line BL can be controlled independently from those shown.

68 is a schematic perspective view showing a semiconductor memory device according to some embodiments of the present invention. For example, the apparatus of FIG. 68 may include a plurality of blocks as shown, each of which may be provided in the form of a first basic structure of FIG. The blocks are connected in parallel to the bit line structure BLS connected to a bit line decoder and / or a sense amplifier BLD / SA, and each of the main memory arrays MMA is connected to an independent word line decoder WLD .

According to the modified embodiments of the present invention, the main memory array (MMA) may be configured to include two-dimensionally arranged memory cells MC. In this case, the cache memory array (CMA) may be provided between the main memory array (MMA) and the peripheral circuit to implement disturbance reduction, speed increase, and the like for the main memory array (MMA).

Figs. 69 and 70 are circuit diagrams showing some examples of three-dimensional semiconductor memory devices in which the main memory array (MMA) thereof has the structure of type B of Fig. 69, the cache lines CWL may be substantially parallel to the second horizontal lines HLy, and the bit lines BL may cross the cache lines CWL. Referring to FIG. 70, the bit lines BL may be substantially parallel to the second horizontal lines HLy, and the cache lines CWL may cross the bit lines BL. A large dotted line represents each chapter, and a small dotted line represents each page.

71 and 72 are schematic circuit diagrams showing a part of modified embodiments of the present invention. 71 and 72, in each of the cache memory arrays (CMA), the cache cells CC may be provided in a multi-layered or multi-row structure. For example, as shown in FIG. 71, the cache cells CC may be three-dimensionally arranged, and at least two cache cells CC may be serially connected to each of the first horizontal lines HLx . This means that the cache memory array (CMA) can include chapters of at least two layers, and the cache memory array (CMA) can have a three-dimensional block structure. Alternatively, as shown in FIG. 72, at least two cache cells CC may be connected in parallel to each of the first horizontal lines HLx. This means that the cache memory array (CMA) has a two-dimensional block structure, but the cache memory array (CMA) can be configured to store at least two layers of chapters

As shown in FIG. 71 or 72, when a plurality of the cache cells CC are connected to each of the first horizontal lines HLx in series or in parallel, they may perform different functions or implement a higher operation speed Lt; / RTI > For example, one of them is used to perform the CM-MM copy or the MM-CM copy, and the other is used to temporarily store the chapter data to be written to the corresponding chapter or another chapter during the CM-MM copy or the MM- Lt; / RTI > That is, the cache memory array (CMA) can be configured to store a plurality of chapter data.

(MC) connected to each of the first horizontal lines (HLx) is connected to the memory cells MC (MC) connected to the first horizontal lines HLx when the memory cells MC are memory elements capable of implementing a multi-level cell ) ≪ / RTI > characteristics of the memory cell.

According to other modified embodiments, each of the cache cells CC may be a memory element capable of implementing multilevel features, in which case the technical features described with reference to Figure 71 or Figure 72 , Various functions or improved operating speed) can be implemented using these multi-level cache cells (CC).

The technical features in the circuit aspects shown in FIGS. 71 and 72 can be implemented by forming the cache memory array (CMA) as a single layer or a multilayer structure in terms of the physical aspects. In addition, each of the structures shown in Fig. 4 may also be configured to implement the technical features or technical effects described with reference to Figs. 71 and 72, too. Similarly, the cache memory arrays (CMA) of Figures 71 and 72 are shown as being parallel to the yz plane, but may be configured to be parallel to the xz or xy plane.

73 shows an example of a memory semiconductor chip including the main memory array (MMA) and the cache memory array (CMA), FIG. 74 shows an example of the main memory array (MMA) and the cache memory array (CMA) (E.g., a CPU or an AP). That is, the semiconductor device according to the embodiments of the present invention can be configured to have the structural characteristics exemplarily shown in Figs. 73 and 74. Fig. 74, the main and cache memory arrays (MMA, CMA) may be portions of a single chip formed in a single monolithic manner, each of which may be a combination of L1 and L2 May be used as caches or as L2 and L3 caches. The semiconductor chips of FIGS. 73 and 74 further include circuits (e.g., a controller) configured to adaptively perform the cache algorithm or the steps of FIGS. 15-29 for the cache memory array (CMA) can do.

As described above, the chapter consists of data or cells arranged two-dimensionally on a predetermined plane. However, the plane may refer to a plane in the data-hierarchical aspect. This means that a chapter of the cache memory array (CMA) is not limited to a specific one of the blocks. For example, as shown in FIG. 75, the cache memory array (CMA) may be composed of partial cache memory arrays (PCMA) distributed in each of a plurality of blocks.

According to some embodiments, the number of cache cells (CC) constituting each of the partial cache memory arrays (hereinafter referred to as " PCMA ") (hereinafter referred to as cache density) (Hereinafter referred to as storage density) of the memory cells MC constituting any one of the blocks of any one of the blocks. According to other embodiments, the cache density may be greater than the storage density. For example, as in the embodiments described with reference to Figures 71 and 72, the cache density may be twice the storage density. According to yet other embodiments, the cache density may be less than the storage density. For example, each of the partial cache memory arrays (PCMA) may be configured to store page data. 76, the semiconductor device may include a plurality of main memory blocks having a VG-NAND structure and a plurality of partial cache memory arrays (PCMA) connected to each of the main memory blocks. have. The partial cache memory arrays (PCMA) can be controlled by cache lines (CWL) across bit lines (BL), and their respective data storage sizes can be, for example, pages.

Although there is a difference at a level that is easily deformable by those skilled in the art, the operating methods of the vertical channel NAND flash memory described with reference to FIGS. 39 to 46 are substantially the same as the example of the VG-NAND structure of FIG. 76 . Thus, for brevity's sake, a detailed description of these operating methods is omitted. On the other hand, embodiments including the distributed partial cache memory arrays (PCMA) are not limited to the example of FIG. 76 (provided as an example for better understanding of the present invention), and based on the above description And can be variously modified.

When the cache density is smaller than the storage density, each of the cache cells CC may be implemented using a memory element having a larger unit area than each of the memory cells MC. For example, the cache cells CC may be memory elements having a large area (such as ESRAM or racetrack memory, etc.), and the memory cells MC may be small occupied (such as cross-point memory or flash memory) May be memory elements having an area.

According to some modified embodiments, the main memory array (MMA) and the cache memory array (CMA) are each implemented on different chips and then electrically connected (e.g., via silicon through vias) . For example, as in the example of FIG. 76, when the difference between the cache density and the storage density is large, it is possible to increase the size of the cache cells CC as described above, Can be mitigated.

According to some embodiments of the present invention, the cache memory array (CMA) may be implemented on top of the substrate SUB or above or below the main memory array (MMA) ) May be an internal structure of an integrated chip. In this case, the cache memory array (CMA) can be distinguished from an external memory chip connected using silicon-through vias or bonding wires having a size of several to several tens of micrometers. For example, the internal lines (VL or HL) connected to the cache cells (CC) may have a width of several to several tens of nanometers. Accordingly, the relationship between the above-described cache density and the storage density is difficult to obtain from the silicon-through vias or the bonding wires, except that the cache density is smaller than the storage density.

In addition, in view of the plan view, the cache cells CC are connected to the connection lines (for example, the vertical lines VL) constituting the main memory array MMA in the cell array region, As shown in FIG. In other words, the cache cells CC can be electrically connected to the memory cells MC without passing through peripheral circuits (such as page buffers, bit line decoders or sensing circuits, etc.). As such, the cache memory array (CMA) may be configured such that the cache memory array (CMA) is longer than the peripheral circuit in the data path length from an external device (e.g., CPU) Structure, and the internal lines (VL or HL) may be lines provided inside the semiconductor chip. Alternatively, the silicon-through vias or bonding wires correspond to the external structure for the peripheral circuit of each of the stacked chips, in that they are used as interconnects connecting the I / O terminals of the stacked chips.

Further, as exemplarily shown in Figs. 2, 8 to 12 and 60 to 63, the internal lines VL or HL are formed so as not to completely penetrate the substrate SUB, May be less than the overall thickness of the substrate (SUB) or the chip comprising it.

Nevertheless, semiconductor chips according to embodiments of the present invention need not be implemented without the application of silicon-through vias or wafer bonding techniques. For example, semiconductor chips including the cache memory array (CMA) according to embodiments of the present invention may be provided as part of a multi-chip package using the silicon-through vias.

[effect]

According to some embodiments of the present invention, the CM read (S [RC]), CM write (S [WC]) and CM initialization (S [IN] Can be performed without access. Thus, the data stored in the memory cells MC is not disturbed by these steps. In addition, the CM-MM copy (S [WM]) and the MM-CM copy (S [RM]) can be accessed once per chapter without repeated access to the main memory array (MMA) Lt; / RTI > Thus, unnecessary access to the main memory array (MMA) (i.e., data disturbance) can be reduced. As a result, the number of disturbance operations occurring during normal read and write operations for one block of the main memory array (MMA) is substantially equal to the number (r) of chapters constituting each block, Can be the same. For the same reason, it is possible to reduce the energy consumption occurring in access to the main memory array (MMA).

Alternatively, in the case of conventional read and write operations performed without or using the cache memory array (CMA), in order to process data of one chapter, at least the number of pages constituting the main memory array MMA) is required. In other words, in the case of the prior art, the number of times of the disturbance operation is substantially equal to the product of the number (r) of chapters constituting each block and the number (q) of pages constituting each chapter, . However, these numbers are provided for a better understanding of the present invention and, in practice, may be varied by additional operations (e.g., verify operations) to improve data reliability.

When each of the cache cells CC has a faster writing and / or reading speed than that of each of the memory cells MC, the time required for reading or writing the entire chapter data (hereinafter referred to as a chapter reading time and a chapter writing time May be reduced compared to the prior art that does not use the cache memory array (CMA).

For example, in the case of the conventional technique without the cache memory array (CMA), the chapter reading time is divided into a time T0 required for reading page data from the memory cells MC once and a number of pages q) (~ qx T0). 18 and 19, the chapter read time may include a) time (T0 ') required to read chapter data from the memory cells MC once and b) page data to the cache cells CC) is equal to the sum of the times T1 and q of each chapter (ie, T0 '+ qx T1). Here, T0 'and T0 can be approximately the same, and therefore, the chapter reading time can be approximately T0 + qxT1.

20 and 21, the same mathematical logic as in the chapter read time can be applied although there is a difference in the operation order. Accordingly, the chapter writing time is given by approximately T2 + qx T3 in the case of the writing method of FIGS. 20 and 21, and can be given by qx T2 in the prior art (where T2 is the chapter data in the memory cells MC) And T3 is the time required to write the page data once to the cache cells CC.

Therefore, if the read speed T1 or the write speed T3 for the cache cells CC is sufficiently smaller than those of the memory cells MC, respectively, as shown in FIGS. 78 and 79, The time and chapter writing time can be greatly reduced compared to the prior art. For example, Table 1 below shows that the memory cells MC are flash memory cells having read and write rates of approximately 25 us and 200 us, and the cache cells CC are RRAMs having read and write rates of approximately 10 ns and 10 ns, Or STT-MRAM, the time required for a read and write operation for a chapter including 16 pages is shown.

[Table 1]

Referring to Table 1, when the cache memory array (CMA) is included, the read and write times (25.16us, 200.16us) for one chapter are calculated based on one read and write times T0 us), T2 (200.00us). Accordingly, when the cache memory array (CMA) is included, the time for reading and writing the chapter data can be faster than the number of pages constituting one chapter (about 16 times in the case of Table 1) have.

[Applications]

80, an electronic product 1000 according to some embodiments of the present invention includes a memory device 1001 and an electronic component 1002 that operates independently or in dependence on the memory device 1001 . The electronic product 1000 may be an electronic component (such as a memory module, SSD, processor, controller, or memory card), a personal electronic device (such as a mobile device, a wearable device, an image recording / And in the form of complex systems (such as data centers, server systems, clouding systems, medical devices, military equipment, automobiles, ships, or broadcast equipment, etc.). The memory device 1001 may be provided in a form including at least one of the semiconductor devices according to the embodiments of the present invention described above. When the electronic product 1000 is provided in the form of an electronic component, the electronic component 1002 may be provided in the form of a capacitor, a resistor, a coil, a semiconductor chip (for example, a controller), and / In the case of a personal electronic device, the electronic component 1002 may include an antenna, a display, a control device, a user information input means (e.g., a touch panel) and / or a power source, The electronic component 1002 may include input / output means, a housing, and / or a power supply.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

Claims (3)

A main memory array including memory cells arranged three-dimensionally and storing block data, a cache memory array including cache cells arranged two-dimensionally and storing chapter data, And a bit line decoder coupled to the cache memory array via the bit line structure, the method comprising:
Wherein the data exchange between the cache memory array and the bit line decoder is performed in units of one page or less,
Wherein the data exchange between the cache memory array and the main memory array is performed in units of at least two pages. Claim 1:
The write operation to the main memory array
Performing at least one cache write in which the external data input via the bit line decoder is written to the cache memory array in units of one page or less; And
And performing a cache-main copy in which data stored in the cache memory array is written to the main memory array in units of at least two pages. Claim 1:
The read operation to the main memory array
Performing a main-cache copy in which data stored in the main memory array is written to the cache memory array in units of at least two pages; And
And performing at least one cache read to transfer the data written to the cache memory array to the bit line decoder in a unit of one page or less.

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