KR20120132671A - Memory Devices Having A Cache Memory Array, In Which Chapter Data Can Be Stored, And Methods Of Operating The Same - Google Patents

Abstract

PURPOSE: A memory device and an operation method thereof are provided to effectively reduce writing and/or reading disturbance in 3-dimensional memory devices and energy consumption. CONSTITUTION: Three main memory arrays(MMA) comprises memory cells which stores block data. A cache memory array(CMA) comprises cache cells which stores chapter data. The cache cells are formed by using different memory elements with the memory cells. A bit line structure comprises bit lines for transmitting page data. A bit line decoder is connected to the cache memory array through the bit line structure.

Description

Memory Devices Having A Cache Memory Array, In Which Chapter Data Can Be Stored, And Methods Of Operating The Same}

The present invention relates to a memory device capable of processing chapter data.

Various three-dimensional memory devices have been proposed, including memory cells that are three-dimensionally arranged and rewritable. For example, three-dimensional flash memory devices and three-dimensional cross-point memory devices such as BiCS, P-BiCS, TCAT, VGNAND and VSAT are actively studied.

The 3D memory devices may include a plurality of horizontal electrodes (eg, word lines of a 3D NAND flash device) that are sequentially stacked on a substrate. In order to avoid complexity in the connection structure, a plurality of the horizontal electrodes located at the same height are electrically connected to each other. As a result of this parallel connection scheme, three-dimensional memory devices are vulnerable to program and read disturb problems.

Some embodiments of the present invention provide three-dimensional memory devices capable of suppressing write and / or read disturb and methods of operation thereof.

Some embodiments of the present invention provide three-dimensional memory devices and methods of operating the same that can speed up write and / or read operations.

Three-dimensional semiconductor devices according to embodiments of the present invention include a cache memory array configured to store more than one page of data (eg, two-dimensional chapter data). The cache memory array is provided between a main memory array including three-dimensionally arranged memory cells and a peripheral circuit area (eg, a bitline decoder or page buffer). The use of the cache memory array is a technical challenge in data exchange (e.g., write / read disturbance or unnecessary energy consumption) caused by the dimensional difference between the three-dimensional main memory array and the one-dimensional page buffer. Makes it possible to solve the problem. In addition, when the cache memory array is implemented using memory elements having a faster operating speed than the main memory array, read and write operations to the main memory array are compared to when the cache memory array is not used. It can dramatically improve the speed of.

The use of the cache memory array can effectively reduce write and / or read disturb and energy consumption in three-dimensional memory devices, as well as speed up write and / or read operations.

1 is a schematic cross-sectional view showing a cell array structure of three-dimensional memory devices.
2 and 3 are perspective views illustrating two different structures of the main memory array of the three-dimensional memory device to which the present invention can be applied.
4 is a table illustratively showing some of the possible embodiments of a cell array structure of a three-dimensional memory device, to which the present invention may be applied.
5 through 8 are cross-sectional views schematically illustrating cell array structures in accordance with some of the embodiments listed in FIG. 4.
9 and 10 are schematic views showing examples of the structures shown in FIGS. 5 and 8.
FIG. 11 is a diagram illustrating a hierarchical structure of a main memory array of a 3D memory device to which the present invention can be applied.
12 is a view provided to schematically explain one aspect of the operation according to the embodiments of the present invention.
FIG. 13 is a diagram exemplarily illustrating operations performed in a 3D memory device according to some embodiments of the inventive concept.
14 and 15 are flowcharts and schematic diagrams schematically illustrating an example of a read operation according to some embodiments of the present invention, respectively.
16 and 17 are flowcharts and schematic diagrams schematically illustrating an example of a write operation according to some embodiments of the present invention, respectively.
18 is a schematic diagram schematically showing an example of a read or write operation according to other embodiments of the present invention.
19 is a graph comparing embodiments of the present invention and operating methods according to the related art in terms of the number of disturbances.
20 and 21 are graphs comparing the time required between read and write operations according to the embodiments of the present invention and the prior art.
22 through 28 are diagrams exemplarily showing some of the memory elements that can be used for the cache memory array.
29 is a perspective view illustrating a semiconductor device according to an embodiment of the present invention.
30 to 40 are diagrams for describing an operation of the semiconductor device of FIG. 29.
41 and 42 are a perspective view and a plan view showing a semiconductor device according to another embodiment of the present invention.
43 to 48 are diagrams for describing an operation of the semiconductor device of FIGS. 41 and 42.
49 is a diagram illustrating a semiconductor device and a part of an operation thereof according to example embodiments of the inventive concepts.
50 and 51 are tables exemplarily illustrating paths of electrical signals for implementing some operations of a 3D memory device according to some embodiments of the inventive concept.
52 to 54 are views illustrating some operations of a 3D memory device according to some embodiments of the present invention.
55 is a circuit diagram schematically illustrating a cache array structure of a 3D memory device according to another embodiment of the present invention.
56 is a diagram schematically illustrating paths of a 3D memory device and an operating current according to some embodiments of the present invention.
57 and 58 exemplarily illustrate embodiments of the present invention applied to an aspect or a two-dimensional memory device of some embodiments of the present invention.
59 and 60 are circuit diagrams illustrating three-dimensional semiconductor memory devices according to some embodiments of the inventive concept.
61 and 62 are schematic circuit diagrams illustrating some of the modified embodiments of the present invention.
63 through 67 are schematic perspective views illustrating exemplary structures of main and cache memory arrays.
68 and 69 are schematic diagrams illustratively showing semiconductor chips having main and cache memory arrays.
70 and 71 are block diagrams and perspective views illustratively showing embodiments of the present invention that include distributed partial cache memory arrays, respectively.
72 is a schematic diagram illustrating an electronic product including a memory device according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more readily apparent from the following description of preferred embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the present specification, when it is mentioned that a film (or layer) is on another film (or layer) or substrate, it may be formed directly on another film (or layer) or substrate or a third film between them. (Or layers) may be interposed. In addition, the size and thickness of the components of the drawings may be exaggerated for clarity. In addition, in various embodiments of the present specification, the terms first, second, third, etc. may be used to describe various regions, films (or layers), etc., but these regions, films, It should not be limited. These terms may only be used to distinguish any given region or film (or layer) from other regions or films (or layers). Therefore, the film quality referred to as the first film quality in one embodiment may be referred to as the second film quality in other embodiments. Each embodiment described and illustrated herein also includes its complementary embodiment. The expression 'and / or' is used herein to mean at least one of the components listed before and after. Like numbers refer to like elements throughout the specification.

The technical terms referred to herein may be used as the following meanings. A bit line is a signal transmission line used to transmit information (ie, an electrical signal) stored in a memory cell to a peripheral circuit (for example, a sensing circuit, a decoder, or a page buffer) or to transmit external data to a memory cell. it means. The word line refers to a line configured to transmit a signal used to select some of a plurality of memory cells connected to one bit line.

The memory cell may mean a region including a material or a thin film structure capable of charge storage and a material or a thin film structure (eg, PCM, MTJ,) exhibiting variable resistance characteristics. However, the present invention is not limited to a particular type of memory cell. For example, embodiments of the present invention may be subdivided and diversified based on the characteristics of the memory cell used.

Adjacent memory cells may be provided in the form of localized patterns spatially separated from each other or as a structure including at least a portion connected to each other.

The wiring or the wire may refer to a conductive pattern formed of a material having a low specific resistance. For example, they may be metals or high concentrations of semiconductor materials (but not limited to these), but organic materials or carbon nanostructures such as nanotubes or graphene may also be used to implement the interconnects or wires.

According to some embodiments, the data exchange with the peripheral circuit may be in the form of an optical signal. In this case, the wiring or the bit line may be provided in the form of an optical waveguide, and the peripheral circuit may include a multiplexer such as a star coupler.

Although, in the figure, 'F' is used to indicate that the element is in an electrically floating state, this is merely for the sake of brevity of description and can prevent the element from generating a current path through it. Voltage may be applied.

1 shows a general cell array structure of three-dimensional memory devices, including a main memory array MMA, a wiring structure UWS, and an external horizontal structure EHL provided on a substrate SUB. The main memory array MMA may include three-dimensionally arranged memory cells and cell wires connecting the memory cells.

For example, as shown in FIG. 2, the main memory array MMA includes (1) vertical lines arranged on the substrate SUB while forming (i.e., two-dimensionally) a multi-line and multi-row structure. VL), (2) a plurality of horizontal lines IHL across the vertical lines VL while forming a multi-layer and multi-row structure, and (3) of the vertical and horizontal lines VL, IHL, 3 It may include memory cells MC provided at intersections, which are arranged dimensionally. Alternatively, as shown in FIG. 3, the main memory array MMA includes (1) first horizontal lines HLx forming a multilayer and multi-row structure, and (2) second horizontal lines forming a multi-layer and glad structure. And HLy, and (3) the memory cells MC provided at their intersections.

The vertical and horizontal lines VL and HL may be electrically connected to a peripheral circuit via each or all of the wiring structure UWS and the external horizontal structure EHL, respectively. For example, in some embodiments employing the structure of FIG. 2, the wiring structure UWS is used as bit lines BL electrically connected to the vertical lines VL and the external horizontal structure EHL. ) May be used as (global) wordlines WL electrically connected to the horizontal lines IHL. However, the connection structure may be variously modified according to the type of memory device, and embodiments of the present invention are not limited to one specific connection structure.

According to embodiments of the present invention, the 3D memory device may include a cache memory array CMA as shown in FIGS. 4 to 10. The cache memory array CMA may be located on a cell array region. This means that the cache memory array CMA is, for example, at least with peripheral circuits (eg, bit line decoders BLD and sensing circuits SA) connected to at least the main memory array MMA and bit lines. It means placed between. In addition, this means that the cache memory array CMA is a storage space that is disposed in a peripheral circuit area and is distinct from a storage space (for example, a page buffer) that stores data transferred from or to the bit lines. .

According to some embodiments, as shown in FIG. 5 or 9, the cache memory array CMA may be located between the main memory array MMA and the bit line structure BLS. According to other embodiments, the main memory array MMA may be located between the bit line structure BLS and the cache memory array CMA. have. In some embodiments, the bit line structure BLS may be located between the main memory array MMA and the cache memory array CMA. Can be. (Hereinafter, such a structure will be referred to as a third basic structure.) In addition, the three-dimensional memory device may include at least one selection structure SLS, and according to the position of the selection structure SLS, The first basic structure may be variously modified as shown in FIG. 4. For example, the first basic structure illustrated in FIG. 5 may include the selection structure SLS positioned between the cache memory array CMA and the main memory array MMA, as illustrated in FIGS. 8 and 10. It may be modified to include. Similarly, each of the second and third basic structures may also be variously modified, such as modified structures for the first basic structure.

The selection structure SLS may include, for example, (1) connection lines constituting the main memory array MMA (for example, the vertical or horizontal lines VL or HL or the first or first). Two horizontal lines HLx or HLy) or (2) one or some of the conductive lines constituting the cache memory array CMA. Technical features related to the selection structure SLS will be described in more detail later with reference to FIGS. 22-67.

Meanwhile, the bit line structure BLS may be disposed on the upper, lower, or side surfaces of the main memory array MMA, as shown in FIGS. 5 through 7, and the upper wiring structure UWS and the lower wiring structure ( LWS) or an external horizontal structure (EHL). The first basic structure is classified by the above-described arrangement or arrangement order between the main memory array MMA, the cache memory array CMA, and the bit line structure BLS, and the substrate SUB. The relative arrangement with respect to means that it can be varied or freely modified. For example, the first basic structure may be embodied as inverted forms as shown in FIGS. 5 and 6, or may be embodied as rotated 90 degrees clockwise or counterclockwise as illustrated in FIG. 7. Each of the structures classified in FIG. 4 may also be implemented with the above-described variety or freedom in relative arrangement with respect to the substrate SUB.

The bit line structure BLS may include a plurality of bit lines electrically connected to the connection lines forming the main memory array MMA. For example, in some embodiments in which the main memory array MMA is provided as the structure of FIG. 2, as shown in FIGS. 9 and 10, each of the bit lines has columns of the vertical lines VL. It can be electrically connected to each. Although not shown, in some embodiments in which the main memory array MMA is provided as the structure of FIG. 3, each of the bit lines is one of columns or layers of the first or second horizontal lines HLx or HLy. It can be electrically connected to the corresponding one.

FIG. 11 is a diagram exemplarily illustrating a hierarchy structure of a main memory array of a 3D memory device to which the present invention can be applied. Referring to FIG. 11, the main memory array MMA may include at least one block, and the block may include one or a plurality of (eg, r) chapters. Each may include a plurality of (eg q) pages, and each of the pages may include a plurality of (eg p) cells.

The block may be a unit of cells or data size (eg, maximum) in which an operation may be performed independently. For example, according to some embodiments of the invention applicable to NAND flash memory, a block can be used as a unit of data that can be erased at one time.

The chapter may refer to data or cells included in one plane of the main memory array (MMA) or the block. In other words, the chapter is composed of data or cells arranged two-dimensionally on a predetermined plane. Here, a plane means a plane in terms of a data-layer structural aspect or a physical arrangement of cells, and the direction of the plane is based on the arrangement of the bitlines and the wordlines and the manner of operation performed using them. Can be selected. For example, in the case of a vertical-channel three-dimensional NAND flash memory known as a BiCS structure (coplanar word lines are electrically connected and used as a common gate electrode of two-dimensionally arranged memory cells), one chapter is described. May be composed of the two-dimensionally arranged memory cells (controlled by the common gate electrode) or data stored therein.

The page refers to a data size that can be read out at one time through the bit line structure BLS (or UWS, LWS, EHL). As described above, since each bit line is electrically connected to a plurality of connection lines constituting the main memory array MMA, two-dimensional data constituting the chapter or three-dimensional data constituting the block It may be difficult to input or output at one time through the bit line structure BLS. Accordingly, as shown in FIG. 12, two-dimensional data constituting one chapter or three-dimensional data constituting one block is divided into groups of one-dimensional data, and then, through the bit lines. Input or output sequentially. The page may correspond to each of the one-dimensional data groups.

The cell refers to an information storage space provided at each intersection between the vertical lines VL and the horizontal lines IHL or between the first and second horizontal lines HLx and HLy. In embodiments of the present invention, the cell may be configured to store single or multi bits.

The cache memory array CMA may also be configured to have the above-described hierarchical structure including chapters, pages, and cells. In addition, according to some embodiments, as shown in FIG. 61, the cache memory array CMA may include at least two chapters, in which case the cache memory array CMA may also have a block structure. Can have Although the cache memory array CMA is shown in FIG. 61 as being parallel to the yz plane, it is obvious that the cache memory array CMA may be configured to be parallel to the xz or xy plane. The main memory array MMA and the cache memory array CMA may be configured to include at least two blocks. This means that the cache memory array CMA includes memory cells configured to store at least two pages of data (hereinafter, cache cells CC).

According to another embodiment of the present invention, a three-dimensional semiconductor device may include a chapter or a page divided into a plurality of sections (for example, based on a pair / hole division or a left / right division). It can be configured to operate each of the sections independently. Although, for the sake of brevity of description, the description of possible embodiments of the present invention that can be applied to such separate sections will be minimized, the method of section separation may be variously modified in view of the efficiency of read or write operations. Can be. Thus, known techniques based on such section separation (eg, applied to two-dimensional memory semiconductors) can be used or applied to implement the technical idea of the present invention, and such use or application is an embodiment of the present invention. Included as part of the

According to some embodiments of the present invention, as shown in FIG. 13, the operation of the 3D memory device may transfer information stored in the main memory array MMA to a peripheral circuit (for example, a page buffer or a sensing circuit). The read operation may include a read operation and a write operation of storing external data provided through the peripheral circuit in the main memory array MMA. According to some embodiments, the read operation includes MM-CM copy (S [RM]) and CM read (S [RC]) steps, and the write operation includes CM write (S [WC]) and CM-. Steps of MM copy (S [WM]). For simplicity of explanation, below, read and write operations for data in one chapter will be described by way of example. That is, the plurality of chapter data can be processed by repeating the operation described below.

As illustrated in FIG. 14, the MM-CM copy S [RM] refers to a process of copying data stored in the main memory array MMA to the cache memory array CMA. The MM-CM copy S [RM] may be performed to copy chapter-based data into the cache memory array CMA at a time, as shown in the left side of FIG. 15. According to modified embodiments, the MM-CM copy S [RM] may include a plurality of substeps, each of which is implemented to copy data of two pages or more.

As shown in FIG. 14, the CM read S [RC] uses the bit line structure BLS to store data of the cache memory array CMA in a peripheral circuit (eg, a sensing circuit or a page buffer). Means the process of transmission. The CM read S [RC] may include a plurality of cache page read steps, each of which may be implemented to transmit data in units of pages to the peripheral circuit. According to modified embodiments, the CM read S [RC] may comprise a plurality of substeps, each of which is implemented to transmit data of a size smaller than a page. For example, each of the substeps of the CM read S [RC] may be implemented to process one or more cell data.

As illustrated in FIG. 16, the CM write S [WC] refers to a process of writing external data to the cache memory array CMA using the bit line structure BLS. The CM write (S [WC]) may comprise a plurality of cache page write steps, each of which is implemented to write page-by-page data to the cache memory array CMA, as shown on the left side of FIG. Can be. According to modified embodiments, the CM write S [WC] may comprise a plurality of substeps, each of which is implemented to transmit data of a size smaller than a page. For example, each of the substeps of the CM write S [WC] may be implemented to process bit, byte, or more cell data.

In some embodiments, data may be read from or written to the cache memory array CMA in a random access manner or based on known access schemes for an L1, L2 or L3 cache. Can be. For example, the CM read (S [RC]) and the CM write (S [WC]) may be implemented to process data in units of bits, bytes, words, or pages, as described above. In some embodiments, the cache memory array CMA may be used as any one of L1, L2 or L3 caches and may be configured to implement the functionality of a DRAM or SRAM currently used. According to some embodiments, the peripheral circuit may be configured to implement the random access method or the L1, L2, or L3 cache access method. For example, the peripheral circuit may further include a driving or decoding circuit used in DRAM, SRAM or NOR flash memory devices.

The CM-MM copy S [WM] refers to a process of copying data stored in the cache memory array CMA to the main memory array MMA. The CM-MM copy S [WM] is configured to copy chapter-based data stored in the cache memory array CMA to predetermined chapters of the main memory array MMA at one time, as shown in the right side of FIG. 17. Can be implemented. According to modified embodiments, the CM-MM copy S [WM] may include a plurality of substeps, each of which is implemented to copy data in units of two pages or more.

According to modified embodiments of the present invention, the write operation and the read operation may be performed by MM direct write (S [WMd]) and MM direct read (S [RMd]) not using the cache memory array (CMA). It can be done in a manner.

The MM direct write (S [WMd]) refers to a process of directly writing external data provided through the peripheral circuit to the main memory array MMA. For example, the MM direct write S [WMd] may be a data transfer process performed without an interruption step of storing data in the cache memory array CMA. According to some embodiments, the MM direct write (S [WMd]), as shown in FIG. 18, is implemented such that each writes data in page units directly into a predetermined chapter of the main memory array MMA. Although the method may include a plurality of lower direct write steps, each of the lower direct write steps may be implemented to process one or more cell data. Alternatively, the MM direct write (S [WMd]) may be implemented to process chapter or more data. One such example of the MM direct write (S [WMd]) may be an erase step of a flash memory that directly changes block data at once.

The MM direct read S [RMd] refers to a process of transferring data of the main memory array MMA to the peripheral circuit without an interruption step of storing data in the cache memory array CMA. The MM direct read (S [RMd]) may include a plurality of lower direct read steps, each of which is implemented to transmit page-by-page data to the peripheral circuit, as shown in FIG. Each of the direct read steps may be implemented to process one or more cell data.

According to other modified embodiments of the present invention, the read operation is in addition to the MM-CM copy (S [RM]) and CM read (S [RC]) steps of FIGS. 14 and 15, FIG. 18. The method may further include reading the MM direct reading (S [RMd]). Further, the write operation may be performed in addition to the CM write (S [WC]) and CM-MM copy (S [WM]) steps of FIGS. 16 and 17, and the MM direct write (S [WMd]) of FIG. The method may further include a step.

According to some embodiments of the present disclosure, as illustrated in FIG. 13, an operation of the 3D memory device may initialize (eg, initialize) all or part of the cache memory array CMA or the cache cells CC. CM initialization (S [IN]) step may be further included. For example, the data change of the cache cell CC is not only an external factor (for example, an external or electrical signal transmitted from the main memory array MMA) but also an internal factor (for example, the cache cell ( CC) together with its own data state), it may be necessary to resolve the inhomogeneity associated with the internal factors within the cache memory array CMA through the CM initialization (S [IN]) step. have. In other words, when the cache cells CC are not initialized, some of the data stored in the cache cells CC may not be changed. In this case, for example, the CM write (S [ WC]) and during the MM-CM copy S [RM]) only some of the data from the external or the main memory array MMA may be written to the cache cells CC. That is, an error may occur.

Nevertheless, if the data change of the cache cell CC has a small or negligible dependency on the internal factor, in some embodiments, the CM initialization (S [IN]) step may be omitted. More specifically, this omission is determined by the data storage principle of the cache cells CC or the type of electrical signal including the information stored in the memory cells MC, the determination of which is illustrated in the examples below. Based on the knowledge level of one skilled in the art. For example, when the cache cell CC is implemented through a memory element having a short retention characteristic (ie, volatile), the CM initialization (S [IN]) step may be omitted.

As described above, the cache memory array CMA is configured to include a plurality of the cache cells CC capable of storing data of at least two pages. For example, the cache memory array CMA may be configured to store data corresponding to one chapter of the main memory array MMA.

According to some embodiments of the present invention, the cache cells CC may be memory cells based on a data storage principle different from that of the memory cells MC. However, according to other embodiments, the cache cells CC and the memory cells MC may be memory cells of the same type or memory cells based on the same or similar operating principle.

According to some embodiments of the present disclosure, each of the cache cells CC may be configured to have a faster write and / or read speed than each of the memory cells MC. For example, if the memory cells MC are charge storage elements (such as a film or floating gate rich in charge trap sites), the cache cells CC may be (PCM, MTJ, Memory elements exhibiting variable resistance characteristics (such as ReRAM materials, etc.). However, the embodiments of the present invention are not limited thereto. For example, based on consideration of other technical characteristics such as manufacturing process, data retention characteristics, mating characteristics (described below) and ease of current path formation, such conditions may be relaxed or changed.

In some embodiments, each of the cache cell CC and the memory cell MC is, for example, DRAM, SRAM, FRAM, NAND FLASH, MRAM, STT-MRAM, PCRAM, NRAM, RRAM, CBRAM, SEM Can be selected from a group of memory elements known as T-RAM, Z-RAM, Polymer, Molecular, Racetrack, Holographic, and Probe. For example, the main memory array MMA may be implemented in the form of NAND flash memory, PCRAM, or RRAM, and the cache memory array CMA may be SRAM, STT-MRAM, CBRAM, T-RAM, or Z. It can be implemented in the form of RAM. In some embodiments, the main memory array MMA is comprised of nonvolatile memory elements, and the cache memory array CMA is a volatile or nonvolatile memory having a faster operating speed than the memory cell MC. It may consist of elements.

According to some embodiments of the present invention, the CM read (S [RC]), the CM write (S [WC]) and the CM initialization (S [IN]) are electrically connected to the main memory array (MMA). Can be performed without access. Accordingly, data stored in the memory cells MC are not disturbed by these steps. In addition, the CM-MM copy (S [WM]) and the MM-CM copy (S [RM]) access chapter-by-chapter, without repetitive page-by-page access to the main memory array (MMA). It can be performed through. Accordingly, unnecessary access (ie, data disturbance) to the main memory array MMA may be reduced. As a result, the number of disturbance operations occurring during normal read and write operations for one block of the main memory array MMA is substantially equal to the number r of chapters constituting each block, as shown in FIG. 19. May be the same. For the same reason, energy consumption in access to the main memory array MMA can be reduced.

In contrast, in the case of a conventional read and write operation performed without or without the cache memory array CMA, in order to process data of one chapter, the main memory array (at least as many as the number of pages constituting the chapter) may be used. Iterative approach to MMA) is required. In other words, in the prior art, the number of disturbance operations may be substantially equal to the product of the number r of chapters constituting each block and the number q of pages constituting each chapter, as shown in FIG. 19. Can be. However, these numbers are provided for a better understanding of the present invention, and in practice can be varied by additional operations (e.g., verify operations) to improve data reliability.

On the other hand, as described above, when each of the cache cells (CC) is configured to have a faster write and / or read speed than each of the memory cells (MC), the time required to read or write the entire chapter data (hereinafter referred to as , Chapter read time and chapter write time) can be reduced compared to the prior art which does not use the cache memory array (CMA).

For example, in a conventional technique performed without the cache memory array CMA, the chapter read time may include a time T0 for reading page data from the memory cells MC once and the number of pages of each chapter ( q) (~ qx T0). In contrast, in the reading method of FIGS. 14 and 15, the chapter reading time may include: a) a time T0 ′ for reading chapter data once from the memory cells MC and b) page data for the cache cells ( It is equal to the sum of the time T1 spent reading from CC) and the product of the number of pages q of each chapter (i.e., T0 + qx T1). Here, T0 'and T0 may be approximately the same, and in this case, the chapter read time may be approximately T0 + q x T1.

In addition, compared with the reading methods of FIGS. 14 and 15, the writing methods of FIGS. 16 and 17 may have the same mathematical logic as in the chapter reading time, although there is a difference in operation order. Accordingly, the chapter writing time may be given as approximately T2 + q x T3 for the writing method of FIGS. 16 and 17 and q x T2 for the prior art. (T2 is a time required to write chapter data to the memory cells MC once, and T3 is a time required to write page data to the cache cells CC once.)

Therefore, if the read rate T1 or write rate T3 for the cache cells CC is sufficiently smaller than those T0 and T2 of the memory cells MC, as shown in Figs. 20 and 21, respectively, the chapter reads Time and chapter writing time can be significantly reduced compared to the prior art. For example, in the table below, the memory cells MC are flash memory cells having read and write speeds of approximately 25us and 200us, and the cache cells CC have read and write speeds of approximately 10ns and 10ns. In case of STT-MRAM, it shows the time required for read and write operation for one chapter including 16 pages.

[Table 1]

Referring to Table 1, when the cache memory array (CMA) is included, the read and write times (25.16us and 200.16us) for one chapter are calculated as one read and write times (T0 (25.00) for the memory cell. us), little difference from T2 (200.00us)). Accordingly, when including the cache memory array (CMA), the read and write time for the chapter data can be as fast as the number of pages constituting one chapter (approximately 16 times in the case of Table 1) compared to the other case. have.

In embodiments of the present invention, the cache memory array CMA or the cache cell CC may include at least one of known memory elements (e.g., an International Technology Roadmap for Semiconductor (ITRS) and a list of references thereof). And at least one of the memory elements disclosed in the constituent documents, but may be configured to maximize the technical effects of the disturbance reduction and the read / write time reduction described above. 22-28 exemplarily illustrate some of such memory elements, which are provided for a better understanding of the present invention. The type of memory element for the cache memory array CMA may include a principle of operation of the memory cells MC, characteristics of an electrical signal for operation (for example, unidirectional or bidirectional, voltage application or current application, and current). Amount, speed, etc.) or various technical requirements for the cache memory array (CMA) itself (e.g., operability as RAM or buffer memory), and the like. For example, in relation to the CM-MM copy (S [WM]) step, the MM-CM is configured such that the characteristic of the read signal of the cache cell CC corresponds to the characteristic of the write signal of the memory cell MC. In relation to the copying S [RM] step, the cache cell CC and the memory cell C are arranged such that the characteristics of the read signal of the memory cell MC correspond to the characteristics of the write signal of the cache cell CC. It may be necessary to design MC). Those skilled in the art will be able to find the case of an optimized or preferred combination of the cache memory array (CMA) and the main memory array (MMA) on the basis of the content discussed herein, and so below, these possible combinations for the sake of brevity of description. Some of these will be described by way of example. However, the technical idea of the present invention is not limited to these examples.

29 is a perspective view illustrating a semiconductor device according to an embodiment of the present invention, and FIGS. 30 to 40 are diagrams for describing an operation of the semiconductor device of FIG. 29. More specifically, referring to FIG. 29, the main memory array MMA is configured to have a structure (eg, BiCS or TCAT) of a vertical channel 3D NAND flash, and the cache memory array CMA is configured as the main memory array. It may be configured to include the cache cells (CC) two-dimensionally arranged on the memory array (MMA). Here, an embodiment in which the cache cells CC are implemented using a high-speed resistive memory element (eg, STT-MTJ) operating using bidirectional current will be described.

The cache cells CC may be interposed between the bit line BL and the vertical line VL, and the vertical line VL is a semiconductor pattern perpendicular to the upper surface of the substrate SUB (ie, silicon). And a charge storage layer (eg, ONO). The semiconductor pattern of the vertical line VL may include, for example, n-type impurity regions used as source and drain electrodes, and a vertical or intrinsic vertical channel region interposed therebetween.

The horizontal lines IHL may include metal or doped silicon. According to some embodiments, as shown in FIG. 29, a plurality of cache lines CWL or DL may be interposed between the cache cells CC and the horizontal lines IHL. Each of the cache lines CWL may connect the n-type impurity regions used as the drain electrode while crossing the bit lines BL. In some embodiments, the cache lines CWL may be formed of a material (eg, a p-type semiconductor) constituting the rectifying device with the n-type impurity regions.

Due to the presence of the cache lines CWL, the vertical channel region is divided into the CM as shown in FIGS. 34 and 35 for the CM read S [RC] as shown in FIGS. 32 and 33. It may not be used as an electrical path for write (S [WC]) and for the CM initialization (S [IN]) as shown in FIG. This makes it possible to reduce the problem of read and write disturbances applied to the main memory array (MMA).

During the MM-CM copy S [RM], as shown in FIG. 31, an operating voltage is applied to any one of the plurality of bit lines BL and the horizontal lines IHL (hereinafter, selected word line). Is approved. In this case, as shown in FIG. 30, a current path via each of the cache cells CC may be selectively generated depending on each of the data stored in the two-dimensional memory cells MC controlled by the selection word line. have. When the current path of FIG. 30 is generated, data of the corresponding cache cell CC may be changed (for example, in a high resistance state or an off state). In some embodiments, the CM initialization S [IN] may be performed to bring the cache cells CC on before the MM-CM copy S [RM].

During the CM read S [RC], as shown in FIGS. 32 and 33, different operating voltages V1 and V2 are applied to any one of the cache lines CWL and the bit lines BL. Each can be applied to. In this case, depending on the applied voltage condition, the current path shown in FIG. 32 or in the opposite direction may be selectively generated depending on the data stored in the cache cell CC. In some embodiments, the sense amplifier can be configured to detect a change in the electrical state (eg, potential) of the bit line caused by the generation of such a current path. As shown, the CM read (S [RC]) may be performed in units of pages (or less).

During the CM write S [WC], as illustrated in FIGS. 34 and 35, operating voltages may be applied to one of the cache lines CWL and the plurality of bit lines BL. In this case, input data may be transferred to the cache cells CC through the bit lines BL (eg, from a page buffer of a peripheral circuit). For example, according to the data to be input, a voltage (for example, V1) applied to some of the bit lines BL may be different from voltages (e.g., V2) applied to other portions. In addition, a voltage substantially equal to any one of the bit line voltages may be applied to any one of the cache lines CWL. In other words, the write current for the cache cell CC may be selectively generated by the potential difference between the bit line BL and the cache line CWL to which it is connected. As illustrated in FIG. 35, the CM write S [WC] may be performed in page units (or less).

The read and write operations described above may be performed selectively and / or randomly on a portion (eg, page or less) of the cache memory array (CMA). Further, such selective read and write operations to the cache memory array CMA may be performed independently without access to the main memory array MMA. This means that the cache memory array CMA can be used as L1, L2, or L3 cache. Access to the main memory array (MMA) may be performed at a time when it is determined that long-term storage of data stored in the cache memory array (CMA) is necessary. That is, the main memory array MMA may be used as storage, for example.

During the CM-MM copy S [WM], as shown in FIGS. 36 and 37, a bit line voltage V_BL is applied to the bit lines BL, and any one of the horizontal lines IHL is applied. The program voltage is applied to one (hereinafter, selected word line). In this case, the current path of FIG. 36 may be selectively generated depending on data stored in each of the cache cells CC constituting the cache memory array CMA. For example, when the cache cell CC is in an on state, the corresponding channel region may have a potential substantially equal to that of the bit line (ie, V_BL) (eg, 0V). In this case, when the voltage applied to the selected word line is high, programming through F-N tunneling is possible. On the other hand, when the cache cell CC is in an off state, the corresponding channel region is electrically isolated, and has a potential raised by voltages applied to the horizontal lines IHL, and thus a potential difference from the program voltage. Can be reduced. That is, program prevention through self-boosting technology may be enabled.

On the other hand, when the self-boosting using the cache cell (CC), the need for the string select lines (SSL), which is required in the prior art can be reduced. For example, even when the string select lines SSL are applied with substantially the same voltage as the word lines WL adjacent thereto, the operations described above with reference to FIGS. 30 to 37 may be effectively performed. have. However, this may not necessarily require the removal of the string select lines SSL.

As illustrated in FIG. 38, the main memory array MMA may be programmed (for example, in page units) through the MM direct write operation S [WMd]. For example, if the cache cells CC do not have a sufficiently high resistance even when in the off state, it may be difficult to implement the above self-boosting. In this case, the MM direct write (S [WMd]) step may be performed. In the case of the erasing step, known conventional techniques can be equally applied.

39 and 40 exemplarily show two possible methods for the CM initialization (S [IN]). In the case of FIG. 39, the CM initialization S [IN] may be performed in units of chapters using currents passing through the cache lines CWL. In this case, disturbance of the main memory array MMA may be performed. Can be performed without. However, as shown in FIG. 40, the CM initialization (S [IN]) may be performed in chapters or pages by using a current path through the channel region.

41 and 42 are perspective and plan views illustrating a semiconductor device according to another embodiment of the present invention, and FIGS. 43 to 47 are views for explaining an operation of the semiconductor device according to another embodiment of the present invention. More specifically, according to this embodiment, the cache memory array CMA may be configured to include cache cells CC that are two-dimensionally arranged below the main memory array MMA. Here, an embodiment in which the memory cells MC are memory elements having bidirectional current characteristics will be described as an example. When the memory cells MC have a unidirectional current characteristic (for example, by use of a diode), the cache memory array CMA may be more easily implemented than the bidirectional current. Accordingly, some embodiments of the case where the memory cells MC have a unidirectional current characteristic will be briefly described below.

According to these embodiments, the cache cells CC illustrated in FIGS. 41 to 47 may be configured to include the zero-capacitor RAM described with reference to FIGS. 25 and 26. A selector ST controlled by the second gate line GL2 may be provided between the cache line SWL or DL and each of the cache cells CC. By the presence of the selector ST, it may be possible to create a current path that does not cause disturbance to the main memory array MMA. The vertical line VL may be connected to a node (eg, source / drain) between the selector ST and the cache cell CC. The cache cells CC may be connected to a first gate line GL1 that crosses the bit lines BL. On the other hand, the type and arrangement of the selector ST is not limited to the MOS transistor as shown, and may be variously modified to have a structure corresponding to electrical characteristics required for the cache cells CC. In addition, the selector ST may itself be configured to function as the cache cell CC, in which case the technical features in the embodiments to be described with reference to FIG. 62 may be implemented.

41 and 42 exemplarily illustrate that a current path for various operations described above may be generated in a unit cell of the cache memory array CMA, but embodiments of the present invention are not limited thereto. . For example, although FIG. 41 shows a planar transistor using an SOI substrate including an buried oxide film, this planar transistor can be replaced with a vertical channel transistor as shown in FIG.

43 to 47 may be circuit diagrams corresponding to the semiconductor devices illustrated in FIGS. 41 and 42. 43 to 47 show the CM write (S [WC]), the CM-MM copy (S [WM]), the MM-CM copy (S [RM]), and the CM read (S [RC], respectively. ]), And the CM initialization (S [IN]) can be implemented using the illustrated circuit structure. That is, embodiments of the present invention are not limited to the voltage condition, circuit structure, or wiring structure shown in FIGS. 43 to 47. For example, FIG. 48 shows that the second gate lines GL2 are connected to each other and may be used as a common gate electrode of adjacent ones of the cache cells CC. In addition, the structure and connection of the cache cells CC may be modified to implement the above-described operations based on one of the conventional cell array structures used in DRAM, FRAM, NOR flash, or the like.

49 is a diagram illustrating a semiconductor device and a part of an operation thereof according to example embodiments of the inventive concepts. According to this embodiment, each of the vertical lines may be configured to include a vertical path control structure (VPCS). Technical features related to the vertical path control structure (VPCS) are disclosed in PCT Publication No. WO 2010/018888 (2010.02.18) and US Application No. 13 / 059,059, the contents of which are fully incorporated as part of the present invention. . The use of the vertical path control structure VPCS is parasitic between three-dimensionally arranged memory cells MC, even when no rectifying element (eg, diode) is placed in each of the memory cells MC. Makes it possible to block the current path. For example, when one of the bit lines BL and one of the gate lines GL are selected, one of the cache cells CC may be uniquely selected. However, when the vertical line VL is formed of a metallic material, even if one of the cache cells CC is uniquely selected, the hidden parasitic paths may not be completely blocked.

When the vertical path control structure VPCS is used, the vertical line VL may be configured to include a semiconductor pattern connected to each of the cache cells CC and a vertical control electrode controlling a potential of the semiconductor pattern. . In this case, generation of the above-described hidden parasitic current path may be blocked. In other words, when the vertical path control structure VPCS is used to connect to the cache memory array CMA, a parasitic current path may be blocked without using a rectifying device. Thus, the semiconductor device can be manufactured more easily. In addition, a preferred combination (in kind) between the cache cells CC and the memory cells MC can be obtained under more relaxed conditions.

50 and 51 are tables exemplarily illustrating paths of electrical signals for implementing some operations of a 3D memory device according to some embodiments of the inventive concept.

52 to 54 schematically illustrate some operations of a 3D memory device according to some embodiments of the inventive concept.

55 is a circuit diagram schematically illustrating a cache array structure of a 3D memory device according to another embodiment of the present invention.

56 is a diagram schematically illustrating paths of a 3D memory device and an operating current according to some embodiments of the present invention. According to some embodiments, the memory cells MC may be configured to have a unidirectional current characteristic by including a rectifying element. In this case, the currents used for the CM-MM copy (S [WM]), the MM-CM copy (S [RM]), and the CM read (S [RC]) are as shown in FIG. It may have the same direction. On the other hand, the cache cells CC may be configured to have bidirectional current characteristics. In this case, the current path through the memory cells MC is difficult to use for initialization of the cache cells CC. However, as shown in FIG. 56, by forming a separate current path DL, this difficulty of initialization can be solved. In some embodiments, the separate current path DL may be implemented using one of the horizontal lines IHL.

On the other hand, when the cache cells CC do not have a bidirectional current characteristic or (ie, volatile) memory element having a short retention characteristic, it may not be necessary to form the separate current path. In addition, such a separate current path may be adaptively implemented based on the types of the cache cells CC and the memory cells MC and their combined characteristics, as shown in FIG. 56. It is not limited to.

FIG. 57 is a schematic perspective view illustrating a semiconductor memory device in accordance with some embodiments of the present invention, and FIG. 58 is a schematic circuit diagram of elements constituting a plane along the dotted line I-I of FIG. 57. For example, FIG. 57 may correspond to the first basic structure of FIG. 4. Meanwhile, according to modified embodiments of the present invention, the main memory array MMA may be configured to include two-dimensionally arranged memory cells MC. In this case, the cache memory array CMA may be provided between the main memory array MMA and a peripheral circuit in order to reduce disturbance and increase speed of the main memory array MMA.

59 and 60 are circuit diagrams showing some examples of three-dimensional semiconductor memory devices in which the main memory array MMA has the structure described with reference to FIG. 3. Referring to FIG. 59, the cache lines CWL may be substantially parallel to the second horizontal lines HLy, and the bit lines BL may cross the cache lines CWL. Referring to FIG. 60, the bit lines BL may be substantially parallel to the second horizontal lines HLy, and the cache lines CWL may cross the bit lines BL. Large dotted lines represent each chapter, and small dotted lines represent each page.

61 and 62 are schematic circuit diagrams illustrating some of the modified embodiments of the present invention. As illustrated in FIG. 61, the cache memory array CMA may be provided in a multilayer or multi-row structure. For example, the cache cells CC may be three-dimensionally arranged, and at least two cache cells CC may be connected in series to each of the first horizontal lines HLx. As shown in FIG. 62, at least two cache cells CC may be connected to each of the first horizontal lines HLx in parallel.

As shown in FIG. 61 or 62, when the plurality of cache cells CC are connected in series or in parallel to each of the first horizontal lines HLx, they may be configured to implement different functions or improved operating speeds. Can be used for For example, one of these may be used for the operation of the CM-MM copy or the MM-CM copy, and the other may be used to temporarily store chapter data to be written to another chapter during this operation. That is, the cache memory array CMA may be configured to hold a plurality of chapter data.

Alternatively, when the memory cells MC are memory elements capable of implementing a multilevel cell MLC, the plurality of cache cells CC connected to each of the first horizontal lines HLx may be the memory cells MC. Can be used to implement this multilevel characteristic. According to other modified embodiments, each of the cache cells CC may be a memory element capable of implementing a multilevel characteristic, in which case the technical features described with reference to FIG. 61 or 62 (eg, , Various functions or improved operating speeds) may be implemented using such multi-level cache cells CC.

Technical features in the circuitry illustrated in FIGS. 61 and 62 may be implemented in physical terms by forming the cache memory array CMA as a single layer or a multi-layer structure. In addition, each of the embodiments shown in FIG. 4 may also be configured to implement the technical features or technical effects described with reference to FIGS. 61 and 62.

63 to 67 are schematic perspective views exemplarily showing positions of the main and cache memory arrays MMA and CMA and directions of inner lines thereof. For example, FIG. 63 illustrates an example applied to embodiments in which the main memory array MMA is provided in the form of a vertical-channel NAND flash memory, and FIG. 64 illustrates an example applied to a vertical-gate NAND flash memory. 65 shows an example applied to a three-dimensional crosspoint resistive memory or a vertical-gate NAND flash memory, and FIGS. 66 and 67 show examples applied to a three-dimensional crosspoint resistive memory. In order to avoid complexity in the drawings, in FIGS. 63 to 67, the word lines WL are shown in the form of flat plates, but may be provided in a multi-layer and multi-row structure.

FIG. 68 illustrates an example of a memory semiconductor chip including the main memory array MMA and the cache memory array CMA, and FIG. 69 illustrates the main memory array MMA and the cache memory array CMA. An example of a multi-core processor (eg, CPU or AP) is shown. That is, embodiments of the present invention may be implemented as the semiconductor devices illustrated in FIGS. 68 and 69. According to some embodiments, in the processor chip of FIG. 69, the main and cache memory arrays MMA and CMA may be portions of one chip formed in a monolithic manner, each of which is L1 and L2. It can be used as caches or as L2 and L3 caches. The processor chip of FIG. 69 may further include circuits configured to perform a cache algorithm on the cache memory array CMA.

As described above, the chapter is composed of data or cells arranged two-dimensionally on a predetermined plane, where the plane may mean a plane in terms of data-hierarchical structure. This means that one chapter of the cache memory array CMA is not a concept limited to a particular one of the blocks. For example, as shown in FIG. 70, the cache memory array CMA may be configured as partial cache memory arrays PCMA distributed in each of a plurality of blocks.

According to some embodiments, as in the embodiments described with reference to FIGS. 9, 10, and 29, the number of the cache cells CC constituting each of the partial cache memory arrays PCMA (hereinafter, referred to as the embodiments) may be described. , Cache density) is substantially equal to the number of memory cells MC (hereinafter referred to as storage density), which constitutes any chapter of any block of the main memory array MMA (e.g., connected to it). can do. According to other embodiments, the cache density may be greater than the reservoir density. For example, as in the embodiments described with reference to FIGS. 61 and 62, the cache density may be twice the reservoir density.

According to still other embodiments, the cache density may be less than the reservoir density. For example, each of the partial cache memory arrays PCMA may be configured to store page data. For example, as illustrated in FIG. 71, the semiconductor device may include a plurality of blocks having a VG-NAND structure and a plurality of partial cache memory arrays PCMA connected to each of the blocks. The partial cache memory arrays PCMA may be controlled by the cache lines CWL across the bit lines BL, and the respective data storage size may be, for example, a page.

Although there are differences in the levels easily deformable by those skilled in the art, the operating methods for the vertical channel structure described with reference to FIGS. 29 to 40 may be substantially the same for the vertical gate structure of FIG. 71. Therefore, for the sake of brevity, the description of these operating methods will be omitted. Meanwhile, for a better understanding of embodiments including the distributed partial cache memory arrays (PCMA), an example of implementing the main memory array (MMA) in a VG-NAND structure is illustrated in FIG. 71 by way of example. It became. However, these embodiments are not limited to the VG-NAND structure and may be variously modified based on the above descriptions.

In addition, for embodiments based on FIG. 70, the cache density may be less than the reservoir density. Due to this density difference, each of the cache cells CC may be implemented using a memory element having a larger unit area than each of the memory cells MC. For example, the cache cells CC may be memory elements having a large area (such as SRAM or racetrack memory, etc.), and the memory cells MC may occupy a small amount (such as crosspoint memory or flash memory, etc.). It may be a flash memory having an area.

According to some embodiments of the present disclosure, the cache memory array CMA may be disposed on the substrate SUB or above or below the main memory array MMA (eg, in a single integrated manner). ) May be an internal structure of the integrated chip. In this case, the cache memory array CMA may be distinguished from an external memory chip connected by using silicon-through vias or bonding wires having a size of several to several tens of micrometers. For example, the relationship between the cache density and the storage density described above is difficult to obtain from the silicon-through vias or bonding wires.

In addition, when viewed from the side of the plan view, the cache cells CC may include connection lines (for example, vertical lines VL) constituting the main memory array MMA in a cell array region. Can be electrically connected to the In other words, the cache cells CC may be electrically connected to the memory cells MC without passing through a peripheral circuit such as a page buffer, a bit line decoder, or a sensing circuit. As such, in the data path length from an external device (for example, a CPU), the cache memory array CMA is closer to the main memory array MMA than the peripheral circuit. ) May be an internal structure for the peripheral circuit, and the vertical lines VL may be chip internal lines. On the other hand, the silicon-via vias or bonding wires are used as wirings connecting the I / O terminals of the stacked chips, which corresponds to the external structure for the peripheral circuit of each of the stacked chips.

2, 41, 63, 66 and 67, the vertical line VL is formed so as not to completely penetrate the substrate SUB, the length of which includes it. It may be less than the overall thickness of the chip.

Nevertheless, semiconductor chips according to embodiments of the present invention should not be implemented without the application of silicon-through vias or wafer bonding techniques. For example, semiconductor chips including the cache memory array (CMA) according to embodiments of the present invention may be provided as part of a multi-chip package using the silicon-through vias.

In the case of the MM-CM copy S [RM], a read operation of the memory cell MC is performed in pairs with a write operation of the cache cell CC, and the CM-MM copy S [WM] is performed. ), The write operation of the memory cell MC may be performed in pairs with the read operation of the cache cell CC. According to modified embodiments of the present invention, as shown in FIG. 72, the semiconductor device may further include an environmental layer (EVL) configured to enhance the effectiveness of such pairing.

For example, the environmental layer EVL may be configured to adjust an electrical resistance of a path connecting the memory cell MC and the cache cell CC. Alternatively, the environmental layer EVL may include additional memory elements configured to mitigate characteristic mismatches in data exchange or copying between the memory cell MC and the cache cell CC. Alternatively, the environmental layer EVL may be configured to bring about a change in an operating environment (eg, temperature) of the cache cell CC. The environmental layer EVL may be configured to operate locally or selectively, and may include a plurality of environmental control elements and conductive lines electrically controlling them for this purpose. In addition, when the bit lines are provided in the form of an optical waveguide, the environmental layer EVL may include photoelectric conversion elements for converting an electrical signal into an optical signal or vice versa.

72 illustrates an example in which the environmental layer EVL is interposed between the main memory array MMA and the wiring structure UWS, but embodiments of the present invention are not limited thereto. The variations in the arrangement of the cache memory array CMA shown in FIG.

[Applications]

As illustrated in FIG. 73, an electronic product 1000 according to some embodiments of the present disclosure may include a memory device 1001 and an electronic component 1002 that operates organically or independently of the memory device 1001. Can be. The electronics 1000 may include electronic components (such as memory modules, SSDs, processors, controllers, or memory cards), personal electronics (such as mobile devices, wearable devices, image recording devices, laptops, or computers), and ( Data centers, server systems, clouding systems, medical devices, military devices, automobiles, ships, or broadcast equipment). The memory device 1001 may be provided in a form including at least one of the semiconductor devices according to the embodiments of the present invention described above. When the electronic product 1000 is provided in the form of an electronic component, the electronic component 1002 may be provided in the form of a capacitor, a resistor, a coil, a semiconductor chip (for example, a controller), and / In the case of a personal electronic device, the electronic component 1002 may include an antenna, a display, a control device, a user information input means (e.g., a touch panel) and / or a power source, The electronic component 1002 may include input / output means, a housing, and / or a power supply.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

Claims (12)

A main memory array comprising memory cells three-dimensionally arranged to store block data;
A cache memory array including cache cells that are two-dimensionally arranged to store chapter data;
A bitline structure including bitlines arranged one-dimensionally to transmit page data; And
And a bitline decoder coupled to the cache memory array through the bitline structure. The method according to claim 1,
And the cache cells are implemented using memory elements different from the memory cells. The method according to claim 1,
And the cache cells are implemented using memory elements having a faster operating speed than the memory cells. The method according to claim 1,
And the cache memory array includes a plurality of cache lines that control the cache memory cells while crossing the bit lines. The method according to claim 1,
The main memory array includes a plurality of vertical lines arranged two-dimensionally to connect the memory cells,
Each of the cache cells is connected to a corresponding one of the vertical lines. The method according to claim 5,
The memory cells are memory elements comprising a charge storage layer,
And the cache cells are memory elements having a variable resistance characteristic. The method according to claim 1,
The main memory array comprising a plurality of blocks, each configured to store block data,
The cache memory array includes a plurality of partial cache memory arrays provided corresponding to each of the blocks. The method of claim 7,
Each of the partial cache memory arrays is configured to store one page or less of data. The method of claim 7,
Each of the partial cache memory arrays is configured to store two pages or more data. In the method of operating the semiconductor device of claim 1,
The data exchange between the cache memory array and the bit line decoder is performed in units of one page or less,
And exchanging data between the cache memory array and the main memory array in units of at least two pages. For 10 claimed,
The write operation to the main memory array is
At least once performing a cache write for writing external data input through the bit line decoder to the cache memory array in units of one page or less; And
And performing a cache-main copy, which writes data stored in the cache memory array to the main memory array in units of at least two pages. For 10 claimed,
The read operation on the main memory array is
Performing a main-cache copy for writing data stored in the main memory array in the cache memory array in units of at least two pages; And
And performing at least one cache read for transmitting the data written in the cache memory array to the bit line decoder in units of one page or less.

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