WO2024057519A1

WO2024057519A1 - Storage device

Info

Publication number: WO2024057519A1
Application number: PCT/JP2022/034724
Authority: WO
Inventors: 泰宏内山
Original assignee: キオクシア株式会社
Priority date: 2022-09-16
Filing date: 2022-09-16
Publication date: 2024-03-21

Abstract

In the present invention, a first string includes a first memory cell transistor, one end of the first string being connected to a first wire, the other end being connected to a second wire. A second string includes a second memory cell transistor, one end of the second string being connected to the first wire, the other end being connected to the second wire. A first power supply line is connected to the gate of the first memory cell transistor via a first transistor and is connected to the gate of the second memory cell transistor via a second transistor. A third string includes a third memory cell transistor, one end of the third string being connected to the first wire, the other end being connected to the second wire. A second power supply line is connected to the gate of the third memory cell transistor and applies a voltage different from that of the first power supply line during data erase.

Description

Storage device

Embodiments generally relate to storage devices.

A memory device in which memory cells are arranged three-dimensionally is known. Storage devices are required to have smaller areas.

US Patent No. 11011237

The aim is to provide a storage device with a smaller area.

A storage device according to one embodiment includes a first wiring, a second wiring, a first string, a second string, a first power line, a third string, and a second power line.

The first string has one end connected to the first wiring, the other end connected to the second wiring, and includes a first memory cell transistor. The second string has one end connected to the first wiring, the other end connected to the second wiring, and includes a second memory cell transistor. The first power supply line is connected to the gate of the first memory cell transistor via a first transistor, and is connected to the gate of the second memory cell transistor via a second transistor. The third string has one end connected to the first wiring, the other end connected to the second wiring, and includes a third memory cell transistor. The second power supply line is connected to the gate of the third memory cell transistor, and applies a different voltage to the first power supply line during data erasing.

FIG. 3 is a diagram illustrating an example of components and connections of the components of the storage device according to the first embodiment. FIG. 3 is a diagram showing types of blocks in the first embodiment. FIG. 3 is a diagram showing the components of one block of the storage device according to the first embodiment and the connections between the components. FIG. 3 is a diagram showing voltages output from the voltage generation circuit of the first embodiment. FIG. 3 is a diagram showing components of a driver according to the first embodiment and connections between the components. FIG. 3 is a diagram showing the components and connections of the components of the row decoder according to the first embodiment. FIG. 2 is a diagram illustrating a cross-sectional structure of a part of the memory cell array of the memory device of the first embodiment, showing the structure along the yz plane. FIG. 3 is a diagram showing a concentration distribution of some impurities in the storage device of the first embodiment. FIG. 3 is a diagram showing a concentration distribution of some impurities in the storage device of the first embodiment. FIG. 3 is a diagram showing voltages applied to some wirings during data erasing in the memory device of the first embodiment. FIG. 3 is a diagram showing voltages applied to some wirings over time during data erasing in the memory device of the first embodiment. FIG. 3 is a diagram showing voltages applied to some wirings during data writing in the memory device of the first embodiment. FIG. 3 is a diagram showing voltages applied to some wirings during data read in the memory device of the first embodiment. FIG. 7 is a diagram showing voltages applied to some wirings during data erasing in a storage device according to a modification of the first embodiment. FIG. 7 is a diagram showing voltages applied to some wirings during data writing in the storage device of the modification of the first embodiment. 6 shows voltages applied to some wirings during data read in a storage device according to a modification of the first embodiment.

Embodiments will be described below with reference to the drawings. Multiple components having substantially the same function and configuration in one embodiment or different embodiments may be distinguished from each other by an additional number or letter appended to the end of the reference numeral. In embodiments that follow a certain described embodiment, differences from the previously described embodiment are mainly described. All descriptions of one embodiment also apply as descriptions of other embodiments, unless explicitly or trivially excluded.

The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc. may differ from the actual one. Therefore, the specific thickness and dimensions should be determined with reference to the following explanation. Furthermore, the drawings may include portions with different dimensional relationships and ratios.

As used herein and in the claims, a first element is "connected" to another second element, whether directly or through an element that is permanently or selectively conductive. and connected to the second element.

Hereinafter, embodiments will be described using an xyz orthogonal coordinate system. In the following description, the description "lower" and its derivatives and related words refer to a position with smaller coordinates on the z-axis, and the description "above" and its derivatives and related words refer to a position with smaller coordinates on the z-axis. Points to the location with larger coordinates.

1. First embodiment 1.1. Composition (structure)
1.1.1. Storage Device FIG. 1 shows an example of components and connections of the components of a storage device 1 according to the first embodiment. The storage device 1 is a device that stores data using memory cells. The storage device 1 is controlled by an external memory controller. The storage device 1 operates based on command CMD and address information ADD received from a memory controller, for example. The storage device 1 receives the data DAT to be written and outputs the data stored in the storage device 1.

As shown in FIG. 1, the storage device 1 includes a plurality of planes PLN, for example, four planes PLN_0, PLN_1, PLN_2, and PLN_3, a register 12, a sequencer 13, a voltage generation circuit 14, a driver 15, etc. Contains components.

Each plane PLN is a set of multiple components. The plane PLN is a unit (memory area) for data writing and data reading. Planes PLN_0 to PLN_3 can operate independently of each other. Each plane PLN includes the same set of components, including a memory cell array 10, a row decoder 11, and a sense amplifier 17.

The register 12 is a circuit that holds the command CMD and address information ADD received by the storage device 1. Command CMD instructs the sequencer 13 to perform various operations including data reading, data writing, and data erasing. Address information ADD specifies an access target in memory cell array 10.

The sequencer 13 is a circuit that controls the overall operation of the storage device 1. Based on the command CMD received from the register 12, the sequencer 13 controls the row decoder 11, driver 15, and sense amplifier 17 to execute various operations including data read, data write, and data erase.

The voltage generation circuit 14 is a circuit that generates a plurality of voltages of different magnitudes. The voltage generation circuit 14 receives a power supply voltage from outside the storage device 1 and generates a plurality of voltages from the power supply voltage. The generated voltage is supplied to components such as the memory cell array 10 and the driver 15.

The driver 15 is a circuit that applies various voltages necessary for the operation of the storage device 1 to several components. The driver 15 receives a plurality of voltages from the voltage generation circuit 14 and supplies a selected one of the plurality of voltages to one or more row decoders 11.

The memory cell array 10 is a collection of arranged memory cells. The memory cell array 10 includes a plurality of memory blocks (blocks) BLK. Each block BLK includes a plurality of memory cell transistors MT (not shown). Wiring lines such as word lines WL (not shown) and bit lines BL (not shown) are also located in the memory cell array 10.

The row decoder 11 is a circuit for selecting a block BLK. The row decoder 11 transfers the voltage supplied from the driver 15 to one block BLK selected based on the block address received from the register 12.

The sense amplifier 17 is a circuit that outputs a signal based on data stored in the memory cell array 10. Sense amplifier 17 senses the state of memory cell transistor MT, and generates read data or transfers write data to memory cell transistor MT based on the sensed state. The sense amplifier 17 also applies a voltage of a magnitude based on the operation to the bit line BL during data reading and data writing.

1.1.2. Block Types FIG. 2 shows the block types of the first embodiment. FIG. 2 shows the memory cell array 10 of one plane PLN. The following description applies to the memory cell array 10 of each plane PLN.

As shown in FIG. 2, the blocks BLK in the memory cell array 10 in one plane PLN include a normal type block BLK and at least one bias block BLKB. A normal block BLK is used for storing data, and may be referred to as a normal block BLKO hereinafter.

As described later, the bias block BLKB has the same configuration as the normal block BLK, that is, the components and the connections of the components. On the other hand, the bias block BLKB is not used to store data, but applies and/or transfers voltage to certain elements.

1.1.3. Circuit Configuration of Memory Cell Array FIG. 3 shows the components and connections of the components of one block BLK of the memory device of the first embodiment. A plurality of blocks BLK, for example all blocks BLK, include the components and connections shown in FIG. Both the regular block BLK and the bias block BLKB include the components and connections shown in FIG.

Block BLK includes multiple string units SU. FIG. 3 shows an example of five string units SU_0 to SU_4.

As shown in FIG. 3, each of the m bit lines BL_0 to BL_m-1 is connected to one NAND string NS from each of the string units SU_0 to SU_4 of each block BLK. m is a positive integer. Each bit line BL is shared by all blocks BLK in each plane PLN, that is, it is common to all blocks BLK in each plane PLN.

Each NAND string NS includes one selection gate transistor ST, n-1 memory cell transistors MT, and one selection gate transistor DT (DT0, DT1, DT2, DT3, or DT4). n is a positive integer. The memory cell transistor MT is an element that includes a control gate electrode and a charge storage film insulated from the surroundings, and stores data in a non-volatile manner based on the amount of charge in the charge storage film. The selection gate transistor ST, the memory cell transistor MT, and the selection gate transistor DT are connected in series between the source line SL and one bit line BL in this order. The source line SL is shared by all blocks BLK in each plane PLN, that is, it is common to all blocks BLK in each plane PLN.

A plurality of NAND strings NS each connected to a plurality of different bit lines BL constitute one string unit SU. In each string unit SU, control gate electrodes of memory cell transistors MT_0 to MT_n-1 are connected to word lines WL_0 to WL_n-1, respectively. A set of memory cell transistors MT that share a word line WL in one string unit SU is called a cell unit CU.

Selection gate transistors DT0 to DT4 belong to string units SU_0 to SU_4, respectively. In FIG. 3, selection gate transistors DT2, DT3, and DT4 are not shown. The gate of the selection gate transistor DT0 of each of the plurality of NAND strings NS of the string unit SU_0 is connected to the selection gate line SGDL_0. Similarly, the gates of the selection gate transistors DT1, DT2, DT3, and DT4 of each of the plurality of NAND strings NS of the string units SU_1, SU_2, SU_3, and SU_4 are connected to the selection gate lines SGDL_1, SGDL_2, SGDL_3, and SGDL_4. It is connected.

The gate of the selection gate transistor ST is connected to the selection gate line SGSL.

1.1.4. Voltage Generation Circuit FIG. 4 shows the voltage output from the voltage generation circuit of the first embodiment. As shown in FIG. 4, the voltage generation circuit 14 generates a ground voltage VSS, a power supply voltage VDDSA, a program selection voltage VSGD, a program selection voltage VSGS, a program voltage VPGM, and a program path from the voltage supplied to the storage device 1. Generates voltage VPASS, read selection voltage VSG, read voltage VCG, read pass voltage VREAD, read bias voltage VCELSRC, read bias voltage VBL, erase voltage VERA, erase voltage transfer voltage VERAH, erase selection voltage VSGE, and erase bias voltage VWLE. Output.

The ground voltage VSS is, for example, 0V. Power supply voltage VDDSA is higher than 0V.

The program selection voltage VSGD is higher than 0V. When the program selection voltage VSGD is applied to the gate of the selection gate transistor DT connected to the bit line BL receiving a certain low voltage and high voltage used in data writing, the selection gate transistor DT is , are kept off and on, respectively.

The program selection voltage VSGS is higher than 0V. When the program selection voltage VSGS is applied to the gate of the selection gate transistor ST, it turns off the selection gate transistor ST even if a voltage exceeding 0V used in data writing is applied to the source line SL. maintain.

The program voltage VPGM is higher than 0V and has a variable magnitude. Program voltage VPGM has a magnitude that causes electrons to be taken into the charge storage film of memory cell transistor MT when it is applied to the gate electrode of memory cell transistor MT.

The program pass voltage VPASS is lower than the program voltage VPGM. The program pass voltage VPASS has a magnitude that turns on the memory cell transistor MT to which no data has been written and suppresses the capture of electrons by the charge storage film of the memory cell transistor MT to which no data has been written.

Read selection voltage VSG is higher than 0V. The read selection voltage VSG has a magnitude that, when applied to the gates of the selection gate transistors DT and ST, allows a current used in data reading to flow through the selection gate transistors DT and ST.

The read voltage VCG is higher than 0V and has a variable magnitude determined based on the type of data read.

When the read pass voltage VREAD is applied to the gate of the memory cell transistor MT, it has a magnitude that keeps the memory cell transistor MT on regardless of its state, and is higher than the read voltage VCG.

Read bias voltage VCELSRC is higher than 0V. Read bias voltage VBL is higher than read bias voltage VCELSRC.

The erase voltage VERA is higher than 0V and higher than the program voltage VPGM and the read pass voltage VREAD. The erase voltage VERA has a magnitude that allows holes to be supplied to the semiconductor in the NAND string NS when applied to the source line SL and/or bit line BL.

The erase voltage transfer voltage VERAH is higher than the erase voltage VERA. The erase voltage transfer voltage VERAH has a magnitude that allows the memory cell transistor MT and the selection gate transistors DT and ST receiving the erase voltage transfer voltage VERAH at their gates to transfer the erase voltage VERA.

The erase selection voltage VSGE is higher than 0V. When the erase selection voltage VSGE is applied to the selection gate transistors ST and (or) DT while being applied to the source line SL and/or the bit line BL, It has a size that allows GIDL (Gate Induced Drain Leakage) to occur.

When the erase bias voltage VWLE is applied to the gate of the memory cell transistor MT, it has a magnitude that causes holes to be taken into the charge storage film of the memory cell transistor MT. Erasing bias voltage VWLE has, for example, the same magnitude as ground voltage VSS, and is, for example, 0V. Erase bias voltage VWLE may be less than 0V.

1.1.5. Driver FIG. 5 shows the components and connections of the components of the driver of the first embodiment.

As shown in FIG. 5, the driver 15 includes the same number of driver circuits SGDdr (SGDdr_0 to SGDdr_4) as the number of string units SU included in one block BLK, the driver circuit SGSdr, and the driver 15 includes one NAND The string NS includes the same number of driver circuits CGdr (CGdr_0 to CGdr_n-1) and driver circuits BLKBdr as word lines WL included in the string NS.

The driver circuits SGDdr_0 to SGDdr_4 receive the ground voltage VSS, program selection voltage VSGD, read selection voltage VSG, and erase selection voltage VSGE from the voltage generation circuit 14. The driver circuits SGDdr_0 to SGDdr_4 supply one of the received voltages instructed by the sequencer 13 to the wirings SGD_0 to SGD_4, respectively.

The driver circuits CGdr_0 to CGdr_n-1 receive a program voltage VPGM, a program pass voltage VPASS, a read voltage VCG, a read pass voltage VREAD, and an erase bias voltage VWLE from the voltage generation circuit 14. The driver circuits CGdr_0 to CGdr_n-1 supply one of the received voltages as instructed by the sequencer 13 to the wirings CG_0 to CG_n-1, respectively.

The driver circuit SGSdr receives a program selection voltage VSGS, a read selection voltage VSG, and an erase selection voltage VSGE from the voltage generation circuit 14. The driver circuit SGSdr supplies one of the received voltages instructed by the sequencer 13 to the wiring SGS.

The driver circuit BLKBdr receives the erase voltage transfer voltage VERAH from the voltage generation circuit 14. The driver circuit BLKBdr supplies the erase voltage transfer voltage VERAH to the wiring BLKBI based on instructions from the sequencer 13.

1.1.6. Block Decoder FIG. 6 shows the components and connections of the components of the row decoder of the first embodiment. FIG. 6 also shows block BLK.

The row decoder 11 includes the same number of block decoders 111 as the number of normal blocks BLKO, and the same number of transfer switch sets 112 as the number of normal blocks BLKO.

The block decoder 111 is a circuit that decodes the address information ADD and outputs a block selection signal BSS on the wiring BSSL and a signal ￣BSS on the wiring BSSL based on the decoding result. The signal |BSS has a logic that is the inverse of the logic of the block selection signal BSS.

Each block decoder 111 is associated with one normal block BLKO. Each block decoder 111 performs control to bring the associated normal block BLKO into a selected state. The block decoder 111 outputs an asserted block selection signal BSS when the address information ADD specifies the normal block BLKO with which it is associated.

Each transfer switch set 112 is a set of multiple transfer switches XS and multiple transfer switches XSB. Each transfer switch set 112 is associated with one normal block BLKO. Each transfer switch set 112 puts the normal block BLKO associated with itself in a selected state based on the block selection signal BSS. Each transfer switch XS is, for example, an n-type MOSFET. The four transfer switches XS are connected between the wirings SGD_0 to SGD_4 and the selection gate lines SGDL_0 to SGDL_4, respectively. The n transfer switches XS are connected between the wirings CG_0 to CG_n-1 and the word lines WL_0 to WL_n-1, respectively. One transfer switch XS is connected between the wiring SGS and the selection gate line SGSL. Each transfer switch XS receives a block selection signal BSS at its gate.

Each transfer switch XSB is, for example, an n-type MOSFET. The four transfer switches XSB are connected between the wirings SGDU_0 to SGDU_4 and the selection gate lines SGDL_0 to SGDL_4, respectively. The wirings SGDU_0 to SGDU_4 receive the ground voltage Vss from the voltage generation circuit 14 or from the voltage generation circuit 14 via the driver 15. Each transfer switch XSB receives the signal BSS at its gate.

When a certain block selection signal BSS is asserted, the transfer switch XS that receives this block selection signal BSS is turned on. Thereby, the voltages of the wirings SGD, CG, and SGS are transferred to the selection gate line SGDL, word line WL, and selection gate line SGSL of the selected block BLK, respectively. On the other hand, while the block BLK is not selected, the signal |BSS for this block BLK is asserted. Therefore, in this unselected block BLK, the transfer switch XSB is turned on. Therefore, the selection gate lines SGDL_0 to SGDL_4 receive the ground voltage VSS via the wirings SGDU_0 to SGDU_4, respectively.

In this way, the normal block BLKO is connected to the driver 15 via the row decoder 11. On the other hand, bias block BLKB is connected to driver 15 without going through row decoder 11. That is, a set of the selection gate line SGDL, word line WL, and selection gate line SGSL of the bias block BLKB is connected to the wiring BLKBI connected to the driver 15.

1.1.5. Memory Cell Array FIG. 7 shows a cross-sectional structure of a part of the memory cell array of the memory device of the first embodiment, showing the structure along the yz plane.

As shown in FIG. 7, the memory cell array 10 includes

conductors

21 and 22, n conductors 23,

conductors

24 and 27, and insulators 33 to 36. The insulators 33 to 36 contain, for example, silicon oxide or are made of silicon oxide.

The conductor 21 spreads along the xy plane and has a plate-like shape. The conductor 21 functions as at least a portion of the source line SL. The conductor 21 includes, for example, silicon doped with phosphorus or is made of silicon doped with phosphorus, and has an n-type conductivity type.

The insulator 33 is located on the upper surface of the conductor 21.

The conductor 22 is located on the upper surface of the insulator 33. The conductor 22 extends along the xy plane and has a plate-like shape. The conductor 22 functions as at least a portion of the selection gate line SGSL. The conductor 22 contains or is made of tungsten, for example.

The plurality of insulators 34 and the plurality of conductors 23 are alternately located on the upper surface of the conductor 22 along the z-axis. Therefore, the conductors 23 are arranged along the z-axis with intervals between them. The insulator 34 and the conductor 23 extend along the xy plane and have a plate-like shape. The plurality of conductors 23 each function as at least a part of the word lines WL_0 to WL_n-1 in order from the conductor 21 side. The conductor 23 contains or is made of tungsten, for example.

The insulator 35 is located on the top surface of the uppermost conductor 23.

The conductor 24 is located on the upper surface of the insulator 35. The conductor 24 functions as at least a portion of one of the selection gate lines SGDL_0 to SGDL_4. The conductor 24 contains or is made of tungsten.

The insulator 36 is located on the top surface of the conductor 24.

The conductor 26 is located on the top surface of the insulator 36. The conductor 26 has a linear shape and extends along the y-axis. The conductor 26 functions as at least a part of one bit line BL. Conductors 26 are also provided in the yz plane, which is different from the yz plane shown in FIG. 7, and therefore, the conductors 26 are arranged at intervals along the x-axis. The conductor 26 contains or is made of copper, for example.

The memory pillar MP extends along the z-axis and has a columnar shape. The memory pillar MP is located in a laminated structure consisting of insulators 33 to 36 and conductors 22 to 24, and penetrates or passes through the insulators 33 to 36 and conductors 22 to 24. The upper surface of the memory pillar MP is located above the uppermost conductor 24. The lower surface of the memory pillar MP is in contact with the conductor 21. A portion where the memory pillar MP and the conductor 22 are in contact functions as a selection gate transistor ST. A portion where memory pillar MP and one conductor 23 are in contact functions as one memory cell transistor MT. A portion where the memory pillar MP and the conductor 24 are in contact functions as one selection gate transistor DT.

The memory pillar MP includes, for example, a core 50, a semiconductor 51, a tunnel insulator 53, a charge storage film 54, a block insulator 55, and a conductor 27. The core 50 extends along the z-axis and has the shape of a column. The core 50 is made of an insulator, for example, contains silicon oxide or is made of silicon oxide.

The semiconductor 51 covers the surface of the core 50. The semiconductor 51 is in contact with the conductor 21 on the lower surface. The semiconductor 51 functions as a channel (current path) of the memory cell transistor MT and the selection gate transistors DT and ST. The semiconductor 51 includes, for example, silicon or is made of silicon.

The tunnel insulator 53 surrounds the side surface of the semiconductor 51. Tunnel insulator 53 includes, for example, silicon oxide or is made of silicon oxide.

The charge storage film 54 surrounds the side surface of the tunnel insulator 53. The charge storage film 54 includes, for example, silicon nitride or is made of silicon nitride.

The block insulator 55 surrounds the side surface of the charge storage film 54. The side surfaces of the block insulator 55 are surrounded by the conductor 23. Block insulator 55 includes, for example, silicon oxide or is made of silicon oxide.

The structure of the memory pillar MP is not limited to the example shown in FIG. 7. For example, a region including the bottom surface of the memory pillar MP may be located in the conductor 21. In this case, the tunnel insulator 53, the charge storage film 54, and the set of the charge storage film 54 are partially opened in the conductor 21. By locating the material of the conductor 21 in this opening, the conductor 21 comes into contact with the semiconductor 51 .

The conductor 25 is located on the upper surface of the core 50 and the semiconductor 51. The conductor 25 includes, for example, silicon doped with phosphorus or is made of silicon doped with phosphorus.

One memory pillar MP and one conductor 25 are connected by a conductor 27.

The structure surrounding the structure shown in FIG. 7 may be of any kind. For example, the conductor 21 is located above the substrate, and circuits such as the row decoder 11, the driver 15, and/or the sense amplifier 17 are formed in a region including the upper surface of the substrate. The circuit may be provided below the upper surface of the substrate where the memory pillar MP, which will be described later, is provided, or may be provided in an area of the upper surface of the substrate that is different from the area below the area where the memory pillar MP is provided. may be provided.

Alternatively, the storage device 1 may include, above the substrate, an upper structure in which the structure shown in FIG. 7 is reversed along the xy plane. That is, the storage device 1 includes a substrate and a lower structure including a circuit formed in a region including the upper surface of the substrate. The structure shown in FIG. 7 is formed on another substrate, and a structure obtained by inverting the formed structure with respect to the xy plane is bonded to the lower structure as an upper structure. The substrate used to form the upper structure is then removed.

FIG. 8 shows the concentration distribution of some impurities in the memory device of the first embodiment. FIG. 8 shows an enlarged view of the area RA shown in FIG. 7 in part (a). FIG. 8 shows, in part (b), the concentration distribution of impurities contained in the part of the semiconductor 51 shown in part (a).

As shown in part (b), the region including the end of semiconductor 51 on the side of conductor 21 is doped with, for example, phosphorus as an impurity. By containing phosphorus, the region including the end of semiconductor 51 on the side of conductor 21 has n-type conductivity. The doped impurity is not limited to phosphorus. For example, arsenic may be doped.

For example, phosphorus is distributed as follows. That is, a portion of the semiconductor 51 that is within a distance D or less from the interface with the conductor 21 to the conductor 22 contains, for example, phosphorus at a concentration of 1×10 ¹⁹ atoms/cm ³ or more. A portion of the semiconductor 51 that extends beyond the distance D from the interface with the conductor 21 toward the conductor 22 contains phosphorus at a concentration lower than, for example, 1×10 ¹⁹ atoms/cm ³ . The distance D is larger than the distance from the interface between the semiconductor 51 and the conductor 21 to the lower surface of the conductor 22 and smaller than the distance from the interface between the semiconductor 51 and the conductor 21 to the upper surface of the conductor 22.

Due to such impurity concentration distribution, the channel of the selection gate transistor ST includes a portion where the phosphorus concentration is 1×10 ¹⁹ atoms/cm ³ or more. Thereby, the selection gate transistor ST can generate a GIDL current in the semiconductor 51. GIDL current generates electron-hole pairs. The holes of the generated electron-hole pairs are injected into the charge storage film 54, so that they can recombine with the electrons taken into the charge storage film 54. Due to the recombination, negative charges disappear from the charge storage film 54. Due to the disappearance of negative charges, the threshold voltage of memory cell transistor MT decreases. That is, the data stored in memory cell transistor MT is erased. Hereinafter, the GIDL current flowing from the source line SL toward the selection gate transistor DT may be referred to as an SL-side GIDL current.

Further, the channel of the selection gate transistor ST includes a portion where the phosphorus concentration is less than 1×10 ¹⁹ atoms/cm ³ . Thereby, the selection gate transistor ST also functions as a switch that controls connection and disconnection between the source line SL (conductor 21) and the memory cell transistor MT_0 during data writing and data reading.

The semiconductor 51 also contains impurities such as phosphorus in the selection gate transistor DT portion as well as in the selection gate transistor ST portion. FIG. 9 shows the concentration distribution of some impurities in the memory device of the first embodiment. FIG. 9 shows an enlarged view of the region RB shown in FIG. 7 in part (a). FIG. 9 shows, in part (b), the concentration distribution of impurities contained in the part of the semiconductor 51 and conductor 25 shown in part (a).

As shown in part (b), the region including the end of the pair of semiconductor 51 and conductor 25 on the side (upper side) of conductor 27 (not shown) is doped with phosphorus as an impurity, for example. There is. By containing phosphorus, the region including the end of the pair of semiconductor 51 and conductor 25 on the conductor 27 side has n-type conductivity. The impurity to be doped is not limited to phosphorus. For example, it may be doped with arsenic.

For example, phosphorus is distributed as follows. That is, a portion of the set of the semiconductor 51 and the conductor 25 that is within a distance D or less from the upper surface of the conductor 25 toward the conductor 24 has a concentration of, for example, 1×10 ¹⁹ atoms/cm ³ or more. Contains phosphorus. A portion of the set of the semiconductor 51 and the conductor 25 that exceeds the distance D from the upper surface of the conductor 25 toward the conductor 24 contains phosphorus at a concentration lower than, for example, 1×10 ¹⁹ atoms/cm ³ . The distance D is larger than the distance from the top surface of the conductor 25 to the top surface of the conductor 24 and smaller than the distance from the top surface of the conductor 25 to the bottom surface of the conductor 24.

Due to such impurity concentration distribution, the channel of the selection gate transistor DT includes a portion where the phosphorus concentration is 1×10 ¹⁹ atoms/cm ³ or more. Thereby, the selection gate transistor DT can generate a GIDL current in the semiconductor 51 and the conductor 25. The GIDL current allows holes to be generated. Hereinafter, the GIDL current from the bit line BL toward the selection gate transistor DT may be referred to as the BL side GIDL current.

Further, the channel of the selection gate transistor DT includes a portion where the phosphorus concentration is less than 1×10 ¹⁹ atoms/cm ³ . Thereby, the selection gate transistor DT also functions as a switch that controls connection and disconnection between the bit line BL (conductor 26) and the memory cell transistor MT_n-1 during data writing and data reading.

1.2. Operation 1.2.1. Data Erase FIG. 10 shows the voltages applied to some wiring during data erase (data erase operation) in the memory device of the first embodiment. FIG. 10 shows a bias block BLKB, a non-selected block BLKns, and a selected block BLKs. The selected block BLKs is a data erasure target block BLK of the normal block BLKO. The non-selected block BLKns is a block BLK other than the selected block BLKs among the normal blocks BLKO.

The block decoder 111 connected to the selected block BLKs is activated, that is, the all transfer switch XS in the activated block decoder 111 is turned on, while the block decoder 111 connected to the non-selected block BLKns is activated. The block decoders 111 in the deactivated block decoders 111 are deactivated, that is, all transfer switches XS in the deactivated block decoders 111 are turned off.

The source line SL receives the erase voltage VERA by the voltage generation circuit 14 and driver 15. As described above with reference to FIG. 3, the source line SL is connected to each block BLK, namely the bias block BLKB, the unselected block BLKns, and the selected block BLKs. Therefore, the source line SL has the potential VERA in any of the bias block BLKB, the unselected block BLKns, and the selected block BLKs.

All selection gate lines SGDL (SGDL_0 to SGDL_4), all word lines WL (WL_0 to WL_n-1), and selection gate line SGSL of bias block BLKB receive erase voltage transfer voltage VERAH from driver 15. Therefore, all the selection gate transistors DT, all the memory cell transistors MT, and the selection gate transistors ST of the bias block BLKB are turned on and in a state where the erase voltage VERA can be transferred.

All selection gate transistors DT, all memory cell transistors MT, and all selection gate transistors ST of bias block BLKB are on and in a state where erase voltage VERA can be transferred. Therefore, each bit line BL is connected to the source via the NAND string NS including the selection gate transistors DT and ST and the memory cell transistor MT, which are connected to the bit line BL and are in a state where the erase voltage VERA can be transferred. It is electrically connected to line SL. The source line SL receives the erase voltage VERA. Therefore, each bit line BL receives the erase voltage VERA via the NAND string NS connected to this bit line BL, and is charged by the erase voltage VERA. During data erasing, each bit line BL does not receive voltage from the sense amplifier 17 and is not connected to any other node via the transistor that is turned on.

The block decoder 111 connected to any non-selected block BLKns is also in an inactive state. Therefore, in each non-selected block BLKns, all selection gate lines SGDL, all word lines WL, and selection gate lines SGSL are electrically floating. Therefore, the selection gate transistors DT and ST and the memory cell transistor MT of the non-selected block BLKns are off.

Since the block decoder 111 connected to the selected block BLKs is in the active state, the selected block BLKs is in a state of receiving voltage from each driver circuit SGDdr (SGDdr_0 to SGDdr_4). Each driver circuit SGDdr outputs an erase selection voltage VSGE. Therefore, each selection gate line SGDL receives the erase selection voltage VSGE.

Since the block decoder 111 connected to the selected block BLKs is in the active state, the selected block BLKs is in a state of receiving voltage from each driver circuit CGdr (CGdr_0 to CGdr_n-1). Each driver circuit CGdr outputs an erase bias voltage VWLE. Therefore, each word line WL receives erase bias voltage VWLE.

Since the block decoder 111 connected to the selected block BLKs is in an active state, the selected block BLKs is in a state of receiving voltage from the driver circuit SGSdr. Then, the driver circuit SGSdr outputs the erase selection voltage VSGE. Therefore, the selection gate line SGSL receives the erase selection voltage VSGE.

FIG. 11 shows voltages applied to some wirings over time during data erasing in the memory device of the first embodiment. FIG. 11 shows the bias block BLKB and the selected block BLKs among the bias block BLKB, the non-selected block BLKns, and the selected block BLKs.

As shown in FIG. 11, at the beginning of the range shown in FIG. 11, the ground voltage VSS is applied to all wirings.

From time t1, the erase voltage transfer voltage VERAH is applied to the selection gate line SGDL, word line WL, and selection gate line SGSL of the bias block BLKB. Furthermore, from time t1, erase voltage VERA is applied to the source line SL. The erase voltage VERA may be applied before the erase voltage transfer voltage VERAH is applied. By applying the erase voltage VERA and the erase voltage transfer voltage VERAH, the voltage of the source line SL is transferred through the bias block BLKB, so that the erase voltage VERA is applied to the bit line BL from time t1.

From time t2, the erase selection voltage VSGE is applied to the selection gate line SGSL of the selected block BLKs. As a result, from time t2, a state is formed in which the erase voltage VERA is applied to the source line SL and the erase selection voltage VSGE is applied to the selection gate line SGSL. By applying such a voltage, the SL side GIDL current flows from the selection gate transistor ST toward the inside of the NAND string NS. Electron-hole pairs are generated by the SL side GIDL current.

Furthermore, from time t2, a state is formed in which the erase voltage VERA is applied to each bit line BL and the erase selection voltage VSGE is applied to each selection gate line SGDL. By applying such a voltage, the BL side GIDL current flows from the selection gate transistor DT toward the inside of the NAND string NS. Electron-hole pairs are generated by the BL side GIDL current.

Holes generated by the BL side GIDL current and the SL side GIDL current move in the semiconductor 51 toward the inner side of the memory cell transistors MT connected in series (the center of the NAND string NS). The word line WL of the selected block BLKs continues to receive the erase bias voltage VWLE. Therefore, holes in the semiconductor 51 are attracted by the erase bias voltage VWLE applied to the word line WL and enter the charge storage film 54. The intruding holes recombine with electrons in the charge storage film 54. Due to the recombination, electrons in the charge storage film 54 disappear, and the amount of electrons in the charge storage film 54 decreases. This lowers the threshold voltage of the memory cell transistor MT of the selected block BLKs, and as a result, data is erased.

From time t3, ground voltage VSS is applied to selection gate lines SGDL and SGSL and word line WL of bias block BLKB and selection gate lines SGDL and SGSL of selection block BLKs.

1.2.2. Data Writing FIG. 12 shows voltages applied to some wiring during data writing (data write operation) in the memory device of the first embodiment.

During data writing, the driver circuits SGDdr_0 to SGDdr_4 output the program selection voltage VSGD or the ground voltage VSS. Among the five string units SU included in each block BLK, the string unit SU that includes the cell unit CU to be accessed by data writing or data reading in the selected block BLKs is referred to as the selected string unit SUs. There is. String units SU other than the selected string units SUs may be referred to as unselected string units SU. A driver circuit SGDdr connected to the selected string unit SUs outputs a program selection voltage VSGD. The driver circuit SGDdr connected to the unselected string unit SU outputs the ground voltage VSS.

During data writing, the driver circuit CGdrv outputs the program voltage VPGM or the program pass voltage VPASS. Data writing includes multiple program loops, and program voltage VPGM has different magnitudes in different program loops.

During data writing, the driver circuit SGSdr outputs the program selection voltage VSGS.

Each bit line BL receives ground voltage VSS or power supply voltage VDDSA by sense amplifier 17. The bit line BL connected to the NAND string (selected NAND string) NS including the memory cell transistor MT whose threshold voltage can be raised by data writing receives the ground voltage VSS. The bit line BL connected to the NAND string (unselected NAND string) NS including the memory cell transistor MT whose threshold voltage cannot be raised by data writing receives the power supply voltage VDDSA.

Source line SL receives power supply voltage VDDSA by driver 15.

The bias block BLKB is required not to participate in data writing and not to inhibit data writing in the selected block BLKs. For this purpose, during data reading, each selection gate line SGDL, each word line WL, and selection gate line SGSL of bias block BLKB is electrically floating. This can be done, for example, by electrically disconnecting a node in the driver circuit BLKBdr from the wiring BLKBI. Since the selection gate lines SGDL and SGSL and the word line WL of the bias block BLKB are electrically floating, the selection gate transistors DT and ST and the memory cell transistor MT of the bias block BLKB are off.

The block decoder 111 connected to any non-selected block BLKns is also in an inactive state. Therefore, in each non-selected block BLKns, each selection gate line SGDL receives the ground voltage VSS, and each word line WL and selection gate line SGSL are electrically floating. Therefore, the selection gate transistors DT and ST and the memory cell transistors MT of the non-selected block BLKns are turned off.

On the other hand, the selected block BLKs receives voltages from the driver circuits SGDdr, CGdr, and SGSdr via the block decoder 111 connected to the selected block BLKs. Therefore, the selection gate line SGDL of the selection block BLKs receives the program selection voltage VSGD or the ground voltage VSS. Further, the word line WL of the selected block BLKs receives the program voltage VPGM or the program pass voltage VPASS. Further, the selection gate line SGSL of the selection block BLKs receives the program selection voltage VSGS.

By applying the voltages as described above, data is written to the cell unit CU to which data is written in the selected block BLKs. The selection gate transistor DT of the selected NAND string NS is turned on, and electrons are supplied from the bit line BL to the semiconductor 51 of the selected NAND string NS. These electrons are drawn by the program voltage VPGM and injected into the charge storage film 54 of the memory cell transistor MT in the selected NAND string NS and in the data writing target cell unit CU. On the other hand, the selection gate transistor DT of the non-selected NAND string NS is not turned on. Therefore, the supply of electrons from the bit line BL to the semiconductor 51 of the non-selected NAND string NS is suppressed. Therefore, injection of electrons into the charge storage film 54 of the memory cell transistor MT in the selected NAND string NS and in the data writing target cell unit CU is suppressed.

1.2.2. Data Read FIG. 13 shows the voltages applied to some wiring during data read (data read operation) in the memory device of the first embodiment.

During data reading, the driver circuit SGDdr connected to the selected string unit SUs outputs the read selection voltage VSG. The driver circuit SGDdr connected to the unselected string unit SU outputs the ground voltage VSS.

During data reading, the driver circuit CGdrv outputs the read voltage VCG or the read pass voltage VREAD.

During data reading, the driver circuit SGSdr outputs the program selection voltage VSGS.

The source line SL receives a read bias voltage VCELSRC by the driver 15. Each bit line BL receives read bias voltage VBL by sense amplifier 17.

The bias block BLKB is required not to participate in data reading and not to inhibit data reading in the selected block BLKs. For this purpose, during data reading, each selection gate line SGDL, each word line WL, and selection gate line SGSL of bias block BLKB is electrically floating. Since the selection gate lines SGDL and SGSL and the word line WL of the bias block BLKB are electrically floating, the selection gate transistors DT and ST and the memory cell transistor MT of the bias block BLKB are off.

On the other hand, the selected block BLKs receives voltages from the driver circuits SGDdr, CGdr, and SGSdr via the block decoder 111 connected to the selected block BLKs. Therefore, the selection gate line SGDL of the selected block BLKs receives the ground voltage VSS or the read selection voltage VSG, and the selection gate line SGSL of the selected block BLKs receives the read selection voltage VSG. Furthermore, the word line WL of the selected block BLKs receives the read voltage VCG or the read pass voltage VREAD.

By applying the voltages as described above, data reading is performed on the cell unit CU from which data is to be read in the selected block BLKs. By receiving the read selection voltage VSG, the selection gate transistors DT and ST of the selected NAND string NS of the selected block BLKs are turned on. Further, by receiving the read pass voltage VREAD, the memory cell transistors MT of the cell units CU other than the data read target cell unit CU are turned on. By receiving the read voltage VCG, the memory cell transistor MT having a threshold voltage less than the read voltage VCG in the data read target cell unit CU is turned on. As a result, a current flows from the bit line BL to the source line SL in the NAND string NS including the memory cell transistor MT having a threshold voltage less than the read voltage VCG. On the other hand, even when receiving the read voltage VCG, the memory cell transistor MT having a threshold voltage greater than the read voltage VCG in the data read target cell unit CU continues to be turned off. As a result, in the NAND string NS including the memory cell transistor MT having a threshold voltage greater than or equal to the read voltage VCG, the flow of current from the bit line BL to the source line SL is suppressed or prevented. Based on whether this current flows, the sense amplifier determines the data stored in the cell unit CU from which data is to be read.

1.3. Advantages (effects)
According to the first embodiment, a storage device with a smaller area can be provided, as described below.

For data erasing, it is necessary to inject holes into each semiconductor of the NAND string. For that purpose, it is necessary to increase the voltage at one end and/or the other end of the NAND string. One end of the NAND string is connected to a source line, and the other end of the NAND string is connected to a bit line. The source line is commonly connected to multiple NAND strings. Therefore, increasing the voltage at one end of multiple NAND strings can be performed by increasing the voltage at one source line. Therefore, it is relatively easy to generate holes by increasing the voltage of the source line.

In order to inject holes more efficiently, hole injection using a voltage increase at the other end of the NAND string can be performed. For that purpose, the voltage on the bit line needs to be increased. In a storage device, a plurality of independent bit lines are provided. Therefore, in order to charge the bit lines, it is necessary to provide a driver circuit for charging the bit lines for each bit line. However, since so many bit lines are provided, providing a driver circuit for each bit line can increase the area of the memory device.

According to the first embodiment, a bias block BLKB is provided. Bias block BLKB is not used for storing data. Instead, during data erasing, the selection gate lines SGDL and SGSL and the word line WL of bias block BLKB receive the erase voltage transfer voltage VERAH. Accordingly, during data erasing, the NAND string NS of the bias block BLKB is in a state where the erase voltage VERA can be transferred. During data erasure, the source line SL receives the erase voltage VERA. The erase voltage VERA of the source line SL is transferred through the NAND string NS of the bias block BLKB which is in a state where the erase voltage VERA can be transferred. As a result, each bit line BL is charged by the erase voltage VERA via the bias block BLKB. Therefore, it is not necessary to provide a driver circuit for charging the erase voltage VERA for each bit line BL. Therefore, efficient hole injection using the bit line BL can be performed, and a memory device having a small area can be provided.

1.4. Modifications Although an example is described in which both the BL side GIDL current and the SL side GIDL current are used, only the BL side GIDL current may be used. Also, only the SL side GIDL current may be used. In this case, a region including the end of the pair of semiconductor 51 and conductor 25 on the conductor 27 side (upper side) is not doped with phosphorus as an impurity.

With reference to FIGS. 9, 11, and 12, an example is described in which selection gate lines SGDL and SGSL and word line WL of bias block BLKB are made floating during data erasing, data writing, and data reading. . During one or more of data erasing, data writing, and data reading, one or more of the selection gate lines SGDL and SGSL and the word line WL of the bias block BLKB may receive the ground voltage VSS.

An example is described in which the GIDL current is used to erase data. Data erasure is not limited to the use of GIDL current. In this case, the conductor 21 has a p-type conductivity type, and includes, for example, boron-doped silicon or is made of boron-doped silicon. Thereby, by applying the voltage described above with reference to FIG. 9, holes are injected into the semiconductor 51 of the selected block BLKs without depending on the GIDL current. Further, holes are injected into the semiconductor 51 of the selected block BLKs from the bit line BL receiving the erase voltage VERA via the bias block BLKB without depending on the GIDL current.

In each NAND string NS, a plurality of selection gate transistors ST may be provided between the source line SL and the memory cell transistor MT_0. In this case, a plurality of conductors 22 are provided. The distance D of the range containing high concentration impurities in the semiconductor 51 is larger than the distance from the interface with the conductor 21 to the upper surface of the lowest conductor 22. Thereby, the bottom selection gate transistor ST exclusively contributes to the generation of the GIDL current, and the other selection gate transistors ST function as switches.

In each NAND string NS, a plurality of selection gate transistors DT may be provided between the source line SL and the memory cell transistor MT_n-1. In this case, a plurality of conductors 24 are provided. The distance D of the range containing high concentration impurities in the semiconductor 51 is larger than the distance from the upper surface of the conductor 25 to the lower surface of the uppermost conductor 24. Thereby, the top select gate transistor DT exclusively contributes to the generation of the GIDL current, and the other select gate transistors DT function as switches.

Referring to FIG. 5, an example has been described above in which one driver circuit BLKBdr is provided and one driver circuit BLKBdr drives all selection gate lines SGDL, all word lines WL, and selection gate lines SGSL of bias block BLKB. There is. The selection gate line SGDL, word line WL, and selection gate line SGSL of bias block BLKB may be driven by a plurality of driver circuits BLKBdr. In this case, the set of selection gate line SGDL, word line WL, and selection gate line SGSL of bias block BLKB is divided into a plurality of groups, and each group is connected to one driver circuit BLKBdr. Then, all the driver circuits BLKBdr output the erase voltage transfer voltage VERAH during data erase.

The selection gate transistors DT and ST and the memory cell transistor MT of the bias block BLKB may be normally-on type. Examples of voltage application in such cases are shown in FIGS. 14, 15, and 16. FIG. 14 shows voltages applied to some wiring during data erasing in a storage device according to a modification of the first embodiment. FIG. 15 shows voltages applied to some wiring during data writing in a storage device of a modification of the first embodiment. FIG. 16 shows voltages applied to some wiring during data read in a storage device of a modification of the first embodiment. Hereinafter, the differences from the embodiments described above will be mainly described with reference to FIGS. 10, 12, and 13.

As shown in FIG. 14, during data erasing, all selection gate lines SGDL, all word lines WL, and selection gate lines SGSL of bias block BLKB receive erase voltage VERA from driver circuit BLKdr. Since the selection gate transistors DT and ST and the memory cell transistor MT of the bias block BLKB are normally on type, they are in a state where the erase voltage VERA can be transferred by applying the erase voltage VERA.

As shown in FIG. 15, during data writing, the selection gate line SGDL of the bias block BLKB receives the voltage VNG. Voltage VNG has a negative magnitude, and since it is applied to normally-on type selection gate transistor DT, it has a magnitude that can keep this selection gate transistor DT off. Voltage VNG is generated by voltage generation circuit 14 and supplied by driver circuit SGDdr. By receiving voltage VNG at its gate, selection gate transistor DT is turned off during data writing. Therefore, the flow of current through the selection gate transistor DT is suppressed or prevented, and in turn, the bias block BLKB is suppressed or prevented from inhibiting data writing.

As shown in FIG. 16, during data reading, the selection gate line SGDL of the bias block BLKB receives the voltage VNG. By receiving voltage VNG at its gate, selection gate transistor DT is turned off during data reading. Therefore, the flow of current through the selection gate transistor DT is suppressed or prevented, and in turn, the bias block BLKB is suppressed or prevented from interfering with data reading.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included within the scope and gist of the invention as well as within the scope of the invention described in the claims and its equivalents.

BLKO...Normal block BLKB...Bias block SGDdr...Driver circuit SGSdr...Driver circuit CGdr...Driver circuit BLKBdr...Driver circuit SGD...Wiring CG...Wiring SGS...Wiring BLKBI...Wiring 111...Block decoder 112...Transfer switch set XS...Transfer switch

Claims

first wiring;
a second wiring;
a first string having one end connected to the first wiring, the other end connected to the second wiring, and including a first memory cell transistor;
a second string having one end connected to the first wiring, the other end connected to the second wiring, and including a second memory cell transistor;
a first power supply line connected to the gate of the first memory cell transistor via a first transistor and connected to the gate of the second memory cell transistor via a second transistor;
a third string having one end connected to the first wiring, the other end connected to the second wiring, and including a third memory cell transistor;
a second power line connected to the gate of the third memory cell transistor and applying a voltage different from that of the first power line during data erasing;
A storage device comprising:
The first string further includes a first selection transistor between the first memory cell transistor and the first wiring, and a second selection transistor between the first memory cell transistor and the second wiring. ,
A first voltage is applied to the second wiring,
A second voltage higher than the first voltage is applied to the second power line,
A third voltage lower than the first voltage is applied to the gate of the first selection transistor and the gate of the second selection transistor,
a fourth voltage lower than the first voltage is applied to the gate of the first memory cell transistor;
It is configured as follows.
The storage device according to claim 1.
A fifth voltage lower than the first voltage, the second voltage, and the third voltage is applied to the first wiring,
A sixth voltage higher than the fifth voltage is applied to the second wiring,
A seventh voltage higher than the fifth voltage is applied to the gate of the first selection transistor,
an eighth voltage higher than the fifth voltage and lower than the second voltage is applied to the gate of the first memory cell transistor;
the second power line is electrically floating or is applied with the fifth voltage;
It is configured as follows.
The storage device according to claim 2.
A ninth voltage is applied to the first wiring,
A tenth voltage lower than the ninth voltage is applied to the second wiring,
an eleventh voltage is applied to the gate of the first selection transistor and the gate of the second selection transistor;
a twelfth voltage is applied to the gate of the first memory cell transistor;
The second power line is electrically floating or is applied with a fifth voltage lower than the tenth voltage.
It is configured as follows.
The storage device according to claim 2.
The third string further includes a third selection transistor between the third memory cell transistor and the first wiring, and a fourth selection transistor between the third memory cell transistor and the second wiring,
a gate of the third selection transistor and a gate of the fourth selection transistor are connected to the second power supply line;
The storage device according to claim 1.
The first string further includes a first selection transistor between the first memory cell transistor and the first wiring, and a second selection transistor between the first memory cell transistor and the second wiring. ,
A first voltage is applied to the second wiring,
A second voltage higher than the first voltage is applied to the second power line,
A third voltage lower than the first voltage is applied to the gate of the first selection transistor and the gate of the second selection transistor,
a fourth voltage lower than the first voltage is applied to the gate of the first memory cell transistor;
It is configured as follows.
The storage device according to claim 5.
A fifth voltage lower than the first voltage, the second voltage, and the third voltage is applied to the first wiring,
A sixth voltage higher than the fifth voltage is applied to the second wiring,
A seventh voltage higher than the fifth voltage is applied to the gate of the first selection transistor,
an eighth voltage higher than the fifth voltage and lower than the second voltage is applied to the gate of the first memory cell transistor;
the second power line is electrically floating or is applied with the fifth voltage;
It is configured as follows.
The storage device according to claim 6.
A ninth voltage is applied to the first wiring,
A tenth voltage lower than the ninth voltage is applied to the second wiring,
an eleventh voltage is applied to the gate of the first selection transistor and the gate of the second selection transistor;
a twelfth voltage is applied to the gate of the first memory cell transistor;
The second power line is electrically floating or is applied with a fifth voltage lower than the tenth voltage.
It is configured as follows.
The storage device according to claim 6.
The third string further includes a plurality of third memory cell transistors that include the third memory cell transistor and are connected in series,
a gate of each of the plurality of third memory cell transistors is connected to the second power supply line;
The storage device according to claim 1.
The first string further includes a first selection transistor between the first memory cell transistor and the first wiring, and a second selection transistor between the first memory cell transistor and the second wiring. ,
A first voltage is applied to the second wiring,
A second voltage higher than the first voltage is applied to the second power line,
A third voltage lower than the first voltage is applied to the gate of the first selection transistor and the gate of the second selection transistor,
a fourth voltage lower than the first voltage is applied to the gate of the first memory cell transistor;
It is configured as follows.
The storage device according to claim 9.
A fifth voltage lower than the first voltage, the second voltage, and the third voltage is applied to the first wiring,
A sixth voltage higher than the fifth voltage is applied to the second wiring,
A seventh voltage higher than the fifth voltage is applied to the gate of the first selection transistor,
an eighth voltage higher than the fifth voltage and lower than the second voltage is applied to the gate of the first memory cell transistor;
the second power line is electrically floating or is applied with the fifth voltage;
It is configured as follows.
The storage device according to claim 10.
A ninth voltage is applied to the first wiring,
A tenth voltage lower than the ninth voltage is applied to the second wiring,
an eleventh voltage is applied to the gate of the first selection transistor and the gate of the second selection transistor;
a twelfth voltage is applied to the gate of the first memory cell transistor;
The second power line is electrically floating or is applied with a fifth voltage lower than the tenth voltage.
It is configured as follows.
The storage device according to claim 10.
first wiring;
a second wiring;
a first selection transistor connected to the first wiring;
a second selection transistor connected to the second wiring;
a first memory cell transistor between the first selection transistor and the second selection transistor;
a first driver connected to one of the gate of the first selection transistor, the gate of the second selection transistor, and the gate of the first memory cell transistor via a first transistor;
a third selection transistor connected to the first wiring;
a fourth selection transistor connected to the second wiring;
a second memory cell transistor between the third selection transistor and the fourth selection transistor;
a second driver connected to one of the gate of the third selection transistor, the gate of the fourth selection transistor, and the gate of the second memory cell transistor without a transistor;
A storage device comprising: