WO2014059617A1

WO2014059617A1 - Port configuration method and device for high-speed peripheral component interconnect express

Info

Publication number: WO2014059617A1
Application number: PCT/CN2012/083072
Authority: WO
Inventors: 杨安林; 刘华伟
Original assignee: 华为技术有限公司
Priority date: 2012-10-17
Filing date: 2012-10-17
Publication date: 2014-04-24
Also published as: CN103098039A; CN103098039B

Abstract

Disclosed are a port configuration method and device for a high-speed peripheral component interconnect express. The method comprises: reading a pull-up and/or pull-down level value of a PCIE auxiliary signal line on a PCIE master device, identifying the type of a PCIE board card in accordance with the read pull-up and/or pull-down level value, the PCIE board card being connected to the PCIE auxiliary signal line, and performing pull-up and/or pull-down processing on the PCIE auxiliary signal line by a pull-up and/or pull-down device (101); and configuring the PCIE bus line on the PCIE master device to be a PCIE port matching with the type of the PCIE board card (102). The solution reduces the overhead for identifying the type of the PCIE board card while achieving the purpose of configuring the port type of the PCIE master device in accordance with the PCIE board card type.

Description

High-speed peripheral device interconnection bus port configuration method and device

Technical field

The present invention relates to circuit technology, and more particularly to a high speed peripheral device interconnect bus port configuration method and apparatus. Background technique

In the processor system, a high-speed Peripheral Component Interconnect Express (PCIE) master device and one or more board PCIE boards are connected through a PCIE bus, and a PCIE host to a PCIE board PCIE bus can According to the number of PCIE slaves on the PCIE board configured as one or more PCIE ports, for example, 16 lanes (lane) PCIE bus support is configured as one xl6 channel PCIE port, or two x8 channel PCIE ports or four x4 channels PCIE port, etc. The PCIE slave device on the PCIE board may have different PCIE port types on the PCIE master device. Therefore, the PCIE master device needs to identify the type of the PCIE card in advance, and then the PCIE bus can be correctly installed. Configured as a PCIE port type that matches the PCIE board.

In the prior art, the PCIE board type is identified by performing a pull-up indication on the PCIE board through a dedicated General Purpose Input/Output (GPIO) signal line, for example, if the GPIO signal line is pulled down. The PCIE board is a type corresponding to one xl6 channel PCIE port. If the GPIO signal line indicates that the PCIE board is the type corresponding to two x8 channel PCIE ports, based on this, the PCIE master reads the up and down of the GPIO signal line. Level combination, you can determine the type of PCIE board. It can be seen that in order to identify the type of PCIE board, the prior art needs to add an additional GPIO signal line as a PCIE board type indication, which adds additional signal line resource overhead. Summary of the invention

Embodiments of the present invention provide a high-speed peripheral device interconnection bus port configuration method and device, which are used to reduce the overhead of identifying a PCIE board type.

A first aspect of the embodiments of the present invention provides a high speed peripheral device interconnect bus PCIE port Method, including:

Reading the pull-up and/or pull-down level values of the PCIE auxiliary signal line on the PCIE master device, and identifying the type of the PCIE board according to the read pull-up and/or pull-down level values, wherein the PCIE board is The PCIE auxiliary signal line is connected, and the PCIE auxiliary signal line is pulled up and/or pulled down by a pull-up and/or pull-down device;

The PCIE bus on the PCIE master is configured as a PCIE port that matches the type of the PCIE board.

In a first possible implementation manner of the first aspect, the reading the pull-up and/or pull-down level values of the PCIE auxiliary signal line on the PCIE master device, according to the read pull-up and/or pull-down levels The types of values that identify PCIE boards include:

When the PCIE master device is started or reset, setting the PCIE auxiliary signal line to an input state, and reading a pull-up and/or pull-down level value of the PCIE auxiliary signal line;

The preset level value and the type mapping relationship are queried, and the type corresponding to the read pull-up and/or pull-down level value is determined as the type of the PCIE board.

In conjunction with the first possible implementation of the first aspect, in a second possible implementation manner of the first aspect, the PCIE bus on the PCIE host device is configured to be the type of the PCIE card After matching PCIE ports, include:

The PCIE auxiliary signal line is set to a state in which the original function is implemented.

With reference to the first aspect or the first possible implementation of the first aspect, or the second possible implementation of the first aspect, in a third possible implementation manner of the first aspect, the PCIE auxiliary signal line is a PCIE reset signal line;

The value of the pull-up and/or pull-down level of the PCIE auxiliary signal line on the PCIE master device is read, and the type of the PCIE card is identified according to the read pull-up and/or pull-down level values:

The pull-up or pull-down level value of the PCIE reset signal line is read, and the type of the PCIE board is identified according to the pull-up or pull-down level value of the read PCIE reset signal line.

With reference to the first aspect, or the first possible implementation of the first aspect, or the second possible implementation of the first aspect, in a fourth possible implementation manner of the first aspect, the PCIE auxiliary signal line is Two ^ ^ 艮 or two ^ ^ 艮 above the PCIE reset signal line;

The pull-up and/or pull-down level values of the PCIE auxiliary signal lines on the PCIE master device are read, and the types of PCIE boards are identified based on the read pull-up and/or pull-down level values, including: The pull-up or pull-down level value of each PCIE reset signal line is read, and the type of the PCIE board is identified according to the pull-up or pull-down level value of the read PCIE reset signal line.

With reference to the first aspect, or the first possible implementation of the first aspect, or the second possible implementation of the first aspect, in a fifth possible implementation manner of the first aspect, the PCIE auxiliary signal line is The PCIE multiplexes the reserved signal line and/or the PCIE wake-up signal line.

A second aspect of the embodiments of the present invention provides a high-speed peripheral device interconnection bus PCIE port configuration device, including:

a reading unit, configured to read a pull-up and/or pull-down level value of the PCIE auxiliary signal line on the PCIE master device, and identify a type of the PCIE card according to the read pull-up and/or pull-down level value, where The PCIE board is connected to the PCIE auxiliary signal line, and performs pull-up and/or pull-down processing on the PCIE auxiliary signal line by using a pull-up and/or pull-down device;

And a configuration unit, configured to configure a PCIE bus on the PCIE master device to be a PCIE port that matches a type of the PCIE board.

In a first possible implementation manner of the second aspect, the reading unit is specifically configured to: when the PCIE master device is started or reset, set the PCIE auxiliary signal line to an input state, and read the PCIE assist Pull-up and/or pull-down level values of the signal line, query the preset level value and type mapping relationship, and determine the type corresponding to the read pull-up and/or pull-down level value as the type of the PCIE board .

With reference to the first possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, the configuration unit is further configured to configure the PCIE bus on the PCIE host device to be After the type of the PCIE board matches the PCIE port, the PCIE auxiliary signal line is set to implement the original function state.

With reference to the second aspect or the first possible implementation manner of the second aspect, or the second possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, the PCIE auxiliary signal line is a PCIE reset signal line;

The reading unit is specifically configured to read a pull-up or pull-down level value of the PCIE reset signal line, and identify the type of the PCIE board according to a pull-up or pull-down level value of the read PCIE reset signal line.

In conjunction with the second aspect or the first possible implementation of the second aspect, or the second possible implementation of the second aspect, in a fourth possible implementation of the second aspect, the PCIE auxiliary The number line is a PCIE reset signal line of two ^ ^ 艮 or two ^ ^ ; or more;

The reading unit is specifically configured to read a pull-up or pull-down level value of each PCIE reset signal line, and identify the type of the PCIE board according to a pull-up or pull-down level value of the read PCIE reset signal line.

With reference to the second aspect or the first possible implementation manner of the second aspect, or the second possible implementation manner of the second aspect, in a fifth possible implementation manner of the second aspect, the PCIE auxiliary signal line is The PCIE multiplexes the reserved signal line and/or the PCIE wake-up signal line.

A third aspect of the embodiments of the present invention provides a high speed peripheral device interconnect bus PCIE board, the PCIE board being connected to a PCIE auxiliary signal line on a PCIE master device, and being connected by a pull-up and/or pull-down device The PCIE auxiliary signal line is pulled up and/or pulled down.

The high-speed peripheral device interconnection bus port configuration method and device provided by the embodiments of the present invention perform type identification on the PCIE board by multiplexing the auxiliary signal lines already existing in the PCIE master device, and then configuring the PCIE bus on the PCIE master device to be The PCIE board type matches the port, and does not require an additional GPIO indicator signal line, which reduces the overhead of identifying the PCIE board type compared to the prior art. BRIEF DESCRIPTION OF THE DRAWINGS In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description of the drawings used in the embodiments or the prior art description will be briefly described below. The drawings are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive labor. FIG. 1 is a flowchart of a method for configuring a PCIE port according to an embodiment of the present invention;

2 is a schematic structural diagram of a PCIE port configuration device according to an embodiment of the present invention; and FIG. 3 is a schematic diagram of a connection between a PCIE card and a PCIE host device and a PCIE port configuration device according to an embodiment of the present invention. The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. The embodiments are a part of the embodiments of the invention, and not all of the embodiments. Based on the embodiments of the present invention, those of ordinary skill in the art obtain the following without creative efforts. All other embodiments obtained are within the scope of the invention.

FIG. 1 is a flowchart of a method for configuring a PCIE port according to an embodiment of the present invention. As shown in FIG. 1, the method in this embodiment includes:

Step 101: Read a pull-up and/or pull-down level value of the PCIE auxiliary signal line on the PCIE master device, and identify a PCIE board type according to the read pull-up and/or pull-down level values, where the PCIE board The PCIE auxiliary signal line is connected to the above, and the PCIE auxiliary signal line is pulled up and/or pulled down by a pull-up and/or pull-down device.

Step 102: Configure the PCIE bus on the PCIE host device to be a PCIE port that matches the type of the PCIE board.

In a processor system, the PCIE bus of the PCIE master device is typically interconnected with the PCIE board through a gusset connector or a backplane connector. The Central Processing Unit (CPU) in the processor system configures the PCIE master's PCIE bus as one or more PCIE ports and needs to match the PCIE board type. Among them, the PCIE bus can be configured as PCIE port types including but not limited to: x4 channel PCIE port, x8 channel PCIE port, xl6 channel PCIE port. The type of PCIE board is mainly determined by the number and type of PCIE slaves on the PCIE board. For example, if there are two PCIE slaves on a PCIE board, the PCIE master needs to configure two PCIE ports for the PCIE board. For establishing a communication connection with two PCIE slaves on the PCIE board, the PCIE board corresponds to two PCIE ports. If the two PCIE ports are x8 channel PCIE ports, the PCIE board is Corresponds to the type of 2 x8 channel PCIE ports. For different boards, the PCIE ports that correspond to the same number and the same type (mainly including the same number of channels) belong to the same type of board. For example, if two PCIE boards correspond to two x8-channel PCIE ports, the two PCIE boards are the same type.

In order to meet the needs of different types of boards for PCIE ports, the CPU needs to identify the type of PCIE board first, and then configure the PCIE bus to be a PCIE port that is compatible with the type of PCIE board. The adaptation here mainly refers to the number and type of PCIE ports configured to meet the requirements of the PCIE board.

In order to be able to identify the type of the PCIE board and ensure the lowest possible overhead, the embodiment uses the PCIE auxiliary signal line to multiplex the PCIE auxiliary signal line to perform type identification on the PCIE board. The multiplexed PCIE auxiliary signal line is connected to the PCIE board. In addition, through the PCIE board and the PCIE master device, the PCIE auxiliary signal line is pulled up and/or pulled down by the pull-up and/or pull-down devices on the PCIE board, and then the CPU reads the PCIE auxiliary signal line. The pull-up and/or pull-down level values identify the type of PCIE board based on the read pull-up and/or pull-down level values. After identifying the type of PCIE board, the CPU configures the PCIE bus as a PCIE port that matches the PCIE board type. The pull-up device used for the PCIE auxiliary signal line to be pulled up by the PCIE board may be a pull-up resistor, or may be a pull-up current source and other pull-up devices; correspondingly, the PCIE board performs the PCIE auxiliary signal line. The pull-down device used for the pull-down processing can be a pull-down resistor or other pull-down device such as a pull-down current source.

For example, taking a 16-lane PCIE bus as an example, it can be defined that the PCIE auxiliary signal line is pulled high to indicate that the PCIE board is corresponding to one xl6 channel PCIE port type, and the PCIE auxiliary signal line is pulled down to indicate low level. The PCIE board is a type that corresponds to two x8 lane PCIE ports. Assume that the PCIE board is of the type corresponding to one xl6 channel PCIE port, and the PCIE auxiliary signal line is pre-pulled on the PCIE board. In this way, the CPU reads the pull-up level value from the PCIE auxiliary signal line, that is, the high level. According to the pre-defined, the PCIE board is identified as a type corresponding to one xl6 channel PCIE port, and then the PCIE bus is configured as One xl6 channel PCIE port meets the requirements of PCIE boards.

The reusable PCIE auxiliary signal line may be, but not limited to, any one of the following signal lines or a combination thereof: a PCIE reset (PERST) signal line, a PCIE multiplexed reserved signal line, and a PCIE wake-up (wake) signal line.

As can be seen from the above, in the embodiment, the CPU identifies the type of the PCIE card by multiplexing the auxiliary signal line already existing on the PCIE master device, and then configures the PCIE bus on the PCIE master device to match the PCIE board type. The port, which does not require an additional GPIO indicator signal line, reduces the overhead of identifying the PCIE board type compared to the prior art.

In an optional implementation, the CPU reads the pull-up and/or pull-down level values of the PCIE auxiliary signal lines on the PCIE master device, and identifies the type of the PCIE board based on the read pull-up and/or pull-down level values. The process includes: setting, when the PCIE master device is started or reset, the PCIE auxiliary signal line as an input state, and reading the pull-up and/or pull-down level values of the PCIE auxiliary signal line; then, the CPU queries the preset level. The value-to-type mapping relationship determines the type of the PCIE board corresponding to the type of pull-up and/or pull-down level values read. In this embodiment, the mapping relationship between the level value of the PCIE auxiliary signal line and the PCIE board type is pre-stored on the processor system, so that the CPU reads After the pull-up and/or pull-down level values of the PCIE auxiliary signal line, the above-mentioned level value and type mapping relationship can be directly searched to determine the type of the PCIE board, which has the advantages of simple implementation and high efficiency.

Since the PCIE auxiliary signal line is multiplexed in this embodiment, the multiplexed PCIE auxiliary signal line has its original function. For example, the original function of the PCIE reset signal line is reset, and the original function of the PCIE wake-up signal line is wake-up. Based on this, after the PCIE auxiliary signal line is multiplexed to identify the PCIE board type, the CPU can set the PCIE auxiliary signal line to achieve the original function status. For example, for the PCIE reset signal, the CPU will set it to the input state when it uses the PCIE board type identification, but the state of the reset function should be the output state, so the identification of the PCIE board type is completed. After that, the CPU sets the state of the PCIE reset signal line to the output state, so that the PCIE reset signal line completes the reset function.

Optionally, if the PCIE auxiliary signal line used is also in the input state when the original function is completed, the CPU may not need to reset the state of the PCIE auxiliary signal line.

The following uses the multiplexed PCIE auxiliary signal line as the PCIE reset signal line as an example to explain how the CPU multiplexes the PCIE auxiliary signal line to identify the PCIE board type and configure the port.

The first case: The PCIE bus of the PCIE master device is connected to the PCIE bus through the gusset connector or the backplane connector.

The PCIE board is interconnected. The PCIE auxiliary signal line used in this embodiment is a PCIE reset signal line. In this case, two PCIE board types can be indicated by pull-up or pull-down. Specifically, the CPU reads the pull-up or pull-down level of the PCIE reset signal line, and identifies the type of the PCIE board according to the pull-up or pull-down level of the read PCIE reset signal line. For the root PCIE reset signal line, the same PCIE board is either pulled up or pulled down.

Assume that the PCIE bus is a 16-lane PCIE bus, which can be configured as one x16-channel PCIE port and two x8-channel PCIE ports, while the PCIE board is compatible with one PCIE slave device and supports one xl6 channel. The PCIE port, or two PCIE slaves, supports two x8-channel PCIE ports. The PCIE master provides a PCIE reset signal line to reset the PCIE slaves on the PCIE board. If the PCIE board compatible design includes one PCIE slave device and supports one xl6 channel PCIE port, the CPU resets the unique PCIE slave device through the PCIE reset signal line; if the PCIE board is compatible, the design includes 2 The PCIE slaves support two x8-channel PCIE ports, and the CPU resets the two PCIE slaves through the PCIE reset signal line. In this embodiment, the one PCIE reset signal line is defined as being pulled down in the PCIE board to indicate that the PCIE board corresponds to one xl6 channel PCIE port, and The above PCIE reset signal line is pulled up in the PCIE board to indicate that the PCIE board corresponds to two x8 channel PCIE ports; correspondingly, the PCIE board is pulled up according to its own design for the PCIE reset signal line. Or pull down processing. Based on this, when the PCIE master device is started or reset, the CPU sets the PCIE reset signal line to the input state, and reads the level value of the PCIE reset signal line. If the pull-down level value is read, the CPU can recognize The PCIE board is a type corresponding to one xl6 channel PCIE port. If the value of the pull-up level is read, it can be recognized that the PCIE board is of the type corresponding to two x8-channel PCIE ports. Then, if the CPU recognizes that the PCIE board is of a type corresponding to one xl6 channel PCIE port, the PCIE bus is set to one xl6 channel PCIE port; if the CPU recognizes that the PCIE board is a type corresponding to two x8 channel PCIE ports , set the PCIE bus to two x8 lane PCIE ports.

Optionally, after the port configuration is completed, the CPU sets the PCIE reset signal line to an output state to implement its original function.

When the PCIE auxiliary signal line used is only one auxiliary signal line, the CPU either reads the pull-up level value or reads the pull-down level value.

In the second case, the PCIE bus of the PCIE master device passes through the gusset connector or the backplane connector.

The PCIE board is interconnected. The PCIE auxiliary signal line used in this embodiment is two PCIE reset signal lines. In this case, four PCIE board types can be indicated by pull-up and pull-down combinations. The upper and lower pull-down combinations of the two PCIE reset signal lines are: all pull-ups, all pull-downs, one pull-up and another pull-down, and one pull-down and another pull-up. However, for each PCIE reset signal line, the same PCIE board should be pulled up or pulled down. Specifically, the CPU reads the pull-up or pull-down level of each PCIE reset signal line, and identifies the type of the PCIE board according to the pull-up or pull-down level of the read PCIE reset signal line.

Assume that the PCIE bus is a 16-lane PCIE bus, which can be configured as one x16-channel PCIE port and two x8-channel PCIE ports, while the PCIE board is compatible with one PCIE slave device and supports one xl6 channel. The PCIE port, or two PCIE slaves, supports two x8-channel PCIE ports. The PCIE master provides two PCIE reset signal lines to reset the PCIE slaves on the PCIE board. The two types of up-and-down combinations can be used to indicate that the PCIE board corresponds to one xl6 channel PCIE port and the PCIE board corresponds to two x8 channel PCIE ports. In this embodiment, 殳 defining that the two PCIE reset signal lines are pulled down in the PCIE board, indicating that the PCIE board corresponds to one xl6 channel PCIE port. The above two PCIE reset signal lines are pulled up in the PCIE board to indicate that the PCIE board corresponds to two x8 channel PCIE ports; correspondingly, the PCIE board is based on its own design for the two PCIE reset signal lines. Pull up or pull down processing. Based on this, when the PCIE master device is started or reset, the CPU sets two PCIE reset signal lines to the input state, and reads the level values of the two PCIE reset signal lines. If the read-down values are all the pull-down level values, It is recognized that the PCIE board is of the type corresponding to one xl6 channel PCIE port. If the value of the pull-up level is read, it can be recognized that the PCIE board is of the type corresponding to two x8-channel PCIE ports. Then, if the CPU recognizes that the PCIE board is of a type corresponding to one xl6 channel PCIE port, the PCIE bus is set to one xl6 channel PCIE port; if the CPU recognizes that the PCIE board is a type corresponding to two x8 channel PCIE ports , set the PCIE bus to two x8 lane PCIE ports.

Optionally, after completing the port configuration, the CPU sets two PCIE reset signal lines to be output states, so that they can implement their original functions.

When the PCIE auxiliary signal line used is two auxiliary signal lines, the CPU may have to read two pull-up level values, or need to read two pull-down levels, or need to read one pull-up level and one pull-down level.

The multiplexed PCIE auxiliary signal line is taken as an example of the PCIE reset signal line, but is not limited thereto. The way to multiplex other PCIE auxiliary signal lines is similar to the way the PCIE reset signal lines are described above. For example, if the multiplexed PCIE auxiliary signal line is a PCIE multiplexed reserved signal line, it can be pulled up, pulled down, or pulled up and down on the PCIE board, and can also be used as a PCIE board type indication signal line. If the multiplexed PCIE auxiliary signal line is other auxiliary signal lines such as the PCIE wake-up signal line, it can also be used as a PCIE board type indication signal line by pulling up, pulling down or up-down combinations on the PCIE board. . The usage method is also as follows: The CPU in the processor system first sets the multiplexed PCIE auxiliary signal line to the input state when the PCIE master device in the processor system is powered on or reset, and then reads the multiplexed PCIE auxiliary signal line. Pull-up and/or pull-down level values, identify the type of PCIE board based on the read pull-up and/or pull-down level values, and then configure the PCIE bus to match the port type of the PCIE board type, then If the PCIE master device is required, then the state of the multiplexed PCIE auxiliary signal line is set to a state suitable for its original function (for example, an output state).

Herein, in the above example, the multiplexed PCIE auxiliary signal line is a PCIE reset signal line representing a case of multiplexing one PCIE auxiliary signal line, and the multiplexed PCIE auxiliary signal line is represented by two PCIE reset signal lines. Multiple multiplexed PCIE auxiliary signal lines. Where multiple reuse The case of the PCIE auxiliary signal line includes not only the case of multiplexing the same type of multiple auxiliary signal lines, but also the case of multiplexing different types of auxiliary signal lines. For example, one PCIE reset signal line and one PCIE wake-up signal line can be multiplexed at the same time, or two PCIE reset signal lines and one PCIE wake-up signal line can be multiplexed. The more PCIE auxiliary signal lines are multiplexed, the more PCIE card types can be indicated. The number of PCIE auxiliary signal lines to be multiplexed depends on the actual application requirements. No matter how many PCIE auxiliary signal lines are multiplexed, the principle is the same, no longer - repeat.

FIG. 2 is a schematic structural diagram of a PCIE port configuration device according to an embodiment of the present invention. As shown in FIG. 2, the PCIE port configuration device of this embodiment includes: a reading unit 21 and a configuration unit 22.

The reading unit 21 is configured to read the pull-up and/or pull-down level values of the PCIE auxiliary signal line on the PCIE master device, and identify the type of the PCIE board according to the read pull-up and/or pull-down level values. The PCIE board is connected to the PCIE auxiliary signal line, and the PCIE auxiliary signal line is pulled up and/or pulled down by a pull-up and/or pull-down device.

The configuration unit 22 is connected to the reading unit 21 for configuring the PCIE bus on the PCIE host device to be a PCIE port matching the type of the PCIE board identified by the reading unit 21.

In an optional implementation, the reading unit 21 is specifically configured to set the PCIE auxiliary signal line to an input state when the PCIE master device is started or reset, and read the pull-up and/or pull-down levels of the PCIE auxiliary signal line. The value is used to query the preset level value and the type mapping relationship, and determine the type corresponding to the read pull-up and/or pull-down level value as the type of the PCIE board.

Based on the foregoing embodiment, optionally, the configuration unit 22 of the embodiment is further configured to: after configuring the PCIE bus on the PCIE host device to be a PCIE port matching the type of the PCIE board, setting the PCIE auxiliary signal line. To achieve the state of the original function.

In an optional implementation manner, the PCIE auxiliary signal line is a PCIE reset signal line. Based on the reading unit 21, the reading unit 21 is configured to read the pull-up or pull-down level of the PCIE reset signal line, according to the reading. The pull-up or pull-down level value of the PCIE reset signal line identifies the type of PCIE board described above.

In an optional implementation manner, the PCIE auxiliary signal line is two or more PCIEs. Resetting the signal line; based on this, the reading unit 21 is specifically configured to read the pull-up or pull-down level value of each PCIE reset signal line, and identify the PCIE according to the pull-up or pull-down level value of the read PCIE reset signal line. The type of board.

In an optional implementation, the PCIE auxiliary signal line may also be a PCIE multiplexed reserved signal line and/or a PCIE wake-up signal line.

In an optional implementation, the PCIE auxiliary signal lines may be one or more. The plurality of PCIE auxiliary signal lines may be multiple PCIE auxiliary signal lines of the same type, or may be different types of multiple-to-PCIE auxiliary signal lines.

The PCIE port configuration device provided in this embodiment may be a CPU in the processor system, but is not limited thereto. The PCIE port configuration device of this embodiment, together with the PCIE master device and the PCIE card, can constitute a processor system.

The functional units of the PCIE port configuration device provided in this embodiment may be used to perform the corresponding process in the foregoing embodiment of the method for configuring the PCIE port. For the specific working principle, refer to the description of the foregoing method embodiment, and details are not described herein.

The PCIE port configuration device provided in this embodiment performs type identification on the PCIE board by multiplexing the auxiliary signal lines already existing in the PCIE master device, and then configures the PCIE bus on the PCIE master device to match the PCIE board type. No additional GPIO indicator signal lines are required, which reduces the overhead of identifying PCIE board types compared to the prior art.

An embodiment of the present invention provides a PCIE board, which is connected to a PCIE auxiliary signal line on a PCIE host device, and pulls up and/or pulls the PCIE auxiliary signal line through a pull-up and/or pull-down device. Pull down processing.

Optionally, the PCIE board of this embodiment may be connected to a PCIE auxiliary signal line on the PCIE host device through a gusset connector or a backplane connector. The PCIE board of this embodiment may include one or more PCIE slaves. Based on the above, the connection relationship between the PCIE board and the PCIE master device in this embodiment is shown in Figure 3. As shown in Figure 3, the PCIE master device is also connected to the PCIE port configuration device. The PCIE port configuration device can be a CPU, and the processor system formed by the CPU, the PCIE host device, and the PCIE board can be shown in FIG.

Optionally, the pull-up device may be a pull-up resistor, and the pull-down device may be a pull-down resistor, but is not limited thereto.

The PCIE board and the PCIE main device provided by this embodiment and the PCIE provided by the foregoing embodiment The port configuration device cooperates with the PCIE port configuration device to identify the type of the PCIE card by multiplexing the existing auxiliary signal lines of the PCIE master device, and then configuring the PCIE bus on the PCIE master device to match the PCIE card type. The port does not require an additional GPIO indicator signal line, which provides a condition for reducing the overhead of identifying PCIE board types.

A person skilled in the art can understand that all or part of the steps of implementing the above method embodiments may be completed by using hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed. The method includes the steps of the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

Finally, it should be noted that the above embodiments are only for explaining the technical solutions of the present invention, and are not intended to be limiting thereof; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; and the modifications or substitutions do not deviate from the technical solutions of the embodiments of the present invention. range.

Claims

claims

1. A high-speed peripheral device interconnect bus PCIE port configuration method, characterized by: reading the pull-up and/or pull-down level values of the PCIE auxiliary signal line on the PCIE master device, and based on the read pull-up and /or the pull-down level value identifies the type of the PCIE board, wherein the PCIE board is connected to the PCIE auxiliary signal line, and pulls up and down the PCIE auxiliary signal line # through a pull-up and/or pull-down device /or pull-down processing;

The PCIE bus on the PCIE master device is configured as a PCIE port that matches the type of the PCIE board card.

2. The PCIE port configuration method according to claim 1, wherein the reading of the pull-up and/or pull-down level values of the PCIE auxiliary signal line on the PCIE master device is based on the read pull-up and/or pull-down level values. Or the pull-down level value identifies the type of PCIE board including:

When the PCIE master device is started or reset, the PCIE auxiliary signal line is set to the input state, and the pull-up and/or pull-down level values of the PCIE auxiliary signal line are read;

Query the preset mapping relationship between level values and types, and determine that the type corresponding to the read pull-up and/or pull-down level values is the type of the PCIE board card.

3. The PCIE port configuration method according to claim 2, wherein configuring the PCIE bus on the PCIE master device as a PCIE port matching the type of the PCIE board card includes:

Set the PCIE auxiliary signal line to the state of realizing the original function.

4. The PCIE port configuration method according to any one of claims 1 to 3, characterized in that the PCIE auxiliary signal line is a PCIE reset signal line;

Reading the pull-up and/or pull-down level values of the PCIE auxiliary signal line on the PCIE master device, and identifying the type of PCIE board card based on the read pull-up and/or pull-down level values include:

Read the pull-up or pull-down level value of the PCIE reset signal line, and identify the type of the PCIE board card according to the read pull-up or pull-down level value of the PCIE reset signal line.

5. The PCIE port configuration method according to any one of claims 1-3, characterized in that the PCIE auxiliary signal lines are two or more PCIE reset signal lines;

Read the pull-up and/or pull-down level values of the PCIE auxiliary signal line on the PCIE master device, and identify the type of PCIE board card based on the read pull-up and/or pull-down level values, including:

Read the pull-up or pull-down level value of each PCIE reset signal line, based on the read PCIE reset The pull-up or pull-down level value of the signal line identifies the type of the PCIE board.

6. The PCIE port configuration method according to any one of claims 1-3, wherein the PCIE auxiliary signal line is a PCIE multiplexing reserved signal line and/or a PCIE wake-up signal line.

7. The PCIE port configuration method according to claim 1, 2, 3 or 6, characterized in that there are one or more PCIE auxiliary signal lines.

8. The PCIE port configuration method according to any one of claims 1 to 7, characterized in that the pull-up device is a pull-up resistor, and the pull-down device is a pull-down resistor.

9. A high-speed peripheral device interconnection bus PCIE port configuration device, characterized by including: a reading unit for reading the pull-up and/or pull-down level values of the PCIE auxiliary signal line on the PCIE master device, according to The read pull-up and/or pull-down level values identify the type of PCIE board card, wherein the PCIE board card is connected to the PCIE auxiliary signal line, and the PCIE auxiliary signal is controlled by a pull-up and/or pull-down device. The line is pulled up and/or pulled down;

A configuration unit configured to configure the PCIE bus on the PCIE master device as a PCIE port that matches the type of the PCIE board card.

10. The PCIE port configuration device according to claim 9, wherein the reading unit is specifically configured to set the PCIE auxiliary signal line to an input state when the PCIE main device is started or reset, and read For the pull-up and/or pull-down level values of the PCIE auxiliary signal line, query the preset level value and type mapping relationship, and determine that the type corresponding to the read pull-up and/or pull-down level value is the PCIE The type of board.

11. The PCIE port configuration device according to claim 10, wherein the configuration unit is further configured to configure the PCIE bus on the PCIE master device as a PCIE bus that matches the type of the PCIE board card. After the port, set the PCIE auxiliary signal line to a state to realize the original function.

12. The PCIE port configuration device according to any one of claims 9-11, characterized in that the PCIE auxiliary signal line is a PCIE reset signal line;

The reading unit is specifically configured to read the pull-up or pull-down level value of the PCIE reset signal line, and identify the type of the PCIE board card according to the read pull-up or pull-down level value of the PCIE reset signal line.

13. The PCIE port configuration device according to any one of claims 9 to 11, characterized in that the PCIE auxiliary signal lines are two or more PCIE reset signal lines; The reading unit is specifically used to read the pull-up or pull-down level value of each PCIE reset signal line, and identify the type of the PCIE board card according to the read pull-up or pull-down level value of the PCIE reset signal line.

14. The PCIE port configuration device according to any one of claims 9 to 11, characterized in that the PCIE auxiliary signal line is a PCIE multiplexing reserved signal line and/or a PCIE wake-up signal line.

15. The PCIE port configuration device according to claim 9, 10, 11 or 14, characterized in that there are one or more PCIE auxiliary signal lines.

16. A high-speed peripheral device interconnection bus PCIE board, characterized in that the PCIE board is connected to the PCIE auxiliary signal line on the PCIE main device, and the PCIE auxiliary signal is connected to the PCIE auxiliary signal through a pull-up and/or pull-down device. The line is pulled up and/or pulled down.

17. The PCIE board card according to claim 16, wherein the pull-up device is a pull-up resistor, and the pull-down device is a pull-down resistor.